5962R9583403VXA [AEROFLEX]
Quad Receiver; 四通道接收机
| 型号： | 5962R9583403VXA |
| 厂家： | 
AEROFLEX CIRCUIT TECHNOLOGY |
| 描述： | Quad Receiver |
| 文件： | 总11页 (文件大小：81K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Standard Products
UT54LVDS032 Quad Receiver
Data Sheet
May 22, 2003
FEATURES
INTRODUCTION
The UT54LVDS032 Quad Receiver is a quad CMOS
differential line receiver designed for applications requiring
ultra low power dissipation and high data rates. The device
is designed to support data rates in excess of 155.5 Mbps
(77.7 MHz) utilizing Low Voltage Differential Signaling
(LVDS) technology.
q
q
q
q
q
q
q
q
>155.5 Mbps (77.7 MHz) switching rates
+340mV differential signaling
5 V power supply
TTL compatible outputs
Ultra low power CMOS technology
8.0ns maximum propagation delay
3.0ns maximum differential skew
The UT54LVDS032 accepts low voltage (340mV)
differential input signals and translates them to 5V TTL
output levels. The receiver supports a three-state function
that may be used to multiplex outputs. The receiver also
supports OPEN, shorted and terminated (100W) input fail-
safe. Receiver output will be HIGH for all fail-safe
conditions.
Radiation-hardened design; total dose irradiation testing to
MIL-STD-883 Method 1019
- Total-dose: 300 krad(Si)and 1Mrad(Si)
- Latchup immune (LET > 111 M eV-cm2/mg)
The UT54LVDS032 and companion quad line driver
UT54LVDS031 provides new alternatives to high power
pseudo-ECL devices for high speed point-to-point interface
applications.
q
q
Packaging options:
- 16-lead flatpack (dual in-line)
Standard Microcircuit Drawing5962-95834
- QML Q and V compliant part
q
q
Compatible with IEEE 1596.3SCI LVDS
Compatible with ANSI/TIA/EIA 644-1996 LVDS Standard
RIN1+
RIN1-
+
-
ROUT1
R1
RIN2+
RIN2-
+
ROUT2
R2
-
RIN3+
RIN3-
+
-
ROUT3
R3
RIN4+
RIN4-
+
-
ROUT4
R4
EN
EN
Figure 1. UT54LVDS032 Quad Receiver Block Diagram
APPLICATIONS INFORMATION
The UT54LVDS032 receiver’s intended use is primarily in an
uncomplicated point-to-point configuration as is shown in
Figure 3. This configuration provides a clean signaling
environment for quick edge rates of the drivers. The receiver is
connected to the driver through a balanced media which may be
a standard twisted pair cable, a parallel pair cable, or simply
PCB traces. Typically, the characteristic impedance of the media
is in the range of 100W. A termination resistor of 100W should
be selected to match the media and is located as close to the
receiver input pins as possible. The termination resistor converts
the current sourced by the driver into voltages that are detected
by the receiver. Other configurations are possible such as a
multi-receiver configuration, but the effects of a mid-stream
connector(s), cable stub(s), and other impedance discontinuities,
as well as ground shifting, noise margin limits, and total
termination loading must be taken into account.
1
R
16
V
DD
IN1-
2
3
R
15
14
R
R
IN1+
IN4-
R
OUT1
IN4+
UT54LVDS032
Receiver
EN
4
5
6
13
12
11
R
OUT4
R
EN
OUT2
R
R
R
IN2+
OUT3
IN3+
7
8
R
10
9
IN2-
V
SS
R
IN3-
Figure 2. UT54LVDS032 Pinout
TRUTH TABLE
ENABLE
1/4 UT54LVDS032
DATA
+
-
Enables
Input
RIN+ - RIN-
X
Output
RT 100W
INPUT
1/4 UT54LVDS031
DATA
OUTPUT
EN
L
EN
ROUT
H
Z
H
L
All other combinations
of ENABLE inputs
VID > 0.1V
VID < -0.1V
Figure 3. Point-to-Point Application
Full Fail-safe
OPEN/SHORT or
Terminated
H
The UT54LVDS032 differential line receiver is capable of
detecting signals as low as 100mV, over a + 1V common-mode
range centered around +1.2V. This is related to the driver offset
voltage which is typically +1.2V. The driven signal is centered
around this voltage and may shift+1V around this center point.
The +1V shifting may be the result of a ground potential
difference between the driver’s ground reference and the
receiver’s ground reference, the common-mode effects of
coupled noise or a combination of the two. Both receiver input
pins should honor their specified operating input voltage range
of 0V to +2.4V (measured from each pin to ground).
PIN DESCRIPTION
Pin No.
Name
Description
2, 6, 10, 14
RIN+
Non-inverting receiver input pin
Inverting receiver input pin
Receiver output pin
1, 7, 9, 15
3, 5, 11, 13
4
RIN-
ROUT
EN
Active high enable pin, OR-ed
with EN
12
EN
Active low enable pin, OR-ed
with EN
16
8
VDD
VSS
Power supply pin, +5V + 10%
Ground pin
2
Receiver Fail-Safe
2. Terminated Input. If the driver is disconnected (cable
unplugged), or if the driver is in a three-state condition,
the receiver output will again be in a HIGH state, even
with the end of cable 100W termination resistor across
the input pins. The unplugged cable can become a
floating antenna which can pick up noise. If the cable
picks up more than 10mV of differential noise, the
receiver may see the noise as a valid signal and switch.
To insure that any noise is seen as common-mode and
not differential, a balanced interconnect should be used.
Twisted pair cable offers better balance than flat ribbon
cable.
The UT54LVDS032 receiver is a high gain, high speed device
that amplifies a small differential signal (20mV) toTTL logic
levels. Due to the high gain and tight threshold of the receiver,
care should be taken to prevent noise from appearing as a valid
signal.
The receiver’s internal fail-safe circuitry is designed to source/
sink a small amount of current, providing fail-safe protection (a
stable known state of HIGH output voltage) for floating,
terminated or shorted receiver inputs.
1. Open Input Pins. The UT54LVDS032 is a quad
receiver device, and if an application requires only 1, 2
or 3 receivers, the unused channel(s) inputs should be
left OPEN. Do not tie unused receiver inputs to ground
or any other voltages. The input is biased by internal high
value pull up and pull down resistors to set the output to
a HIGH state. This internal circuitry will guarantee a
HIGH, stable output state for open inputs.
3. Shorted Inputs. If a fault condition occurs that shorts
the receiver inputs together, thus resulting in a 0V
differential input voltage, the receiver output remains in
a HIGH state. Shorted input fail-safe is not supported
across the common-mode range of the device (VSS to
2.4V). It is only supported with inputs shorted and no
external common-mode voltage applied.
3
1
ABSOLUTE MAXIMUM RATINGS
(Referenced to VSS
)
SYMBOL
VDD
PARAMETER
DC supply voltage
LIMITS
-0.3 to 6.0V
VI/O
Voltage on any pin
-0.3 to (VDD + 0.3V)
TSTG
PD
Storage temperature
-65 to +150°C
1.25 W
Maximum power dissipation
Maximum junction temperature2
TJ
+150°C
Thermal resistance, junction-to-case3
DC input current
QJC
10°C/W
II
±10mA
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.
2. Maximum junction temperature may be increased to +175°C during burn-in and steady-static life.
3. Test per MIL-STD-883, Method 1012.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
VDD
PARAMETER
Positive supply voltage
LIMITS
4.5 to 5.5V
-55 to +125°C
TC
Case temperature range
VIN
DC input voltage, receiver inputs
DC input voltage, logic inputs
2.4V
0 to VDD for EN, EN
4
DC ELECTRICAL CHARACTERISTICS 1
(VDD = 5.0V +10%; -55°C < TC < +125°C)
SYMBOL
PARAMETER
CONDITION
MIN
MAX
UNIT
VIH
High-level input voltage
(TTL)
(TTL)
2.0
V
VIL
VOL
VOH
IIN
Low-level input voltage
Low-level output voltage
High-level output voltage
Logic input leakage current
0.8
0.3
V
V
IOL = 2mA, VDD = 4.5V
IOH = -0.4mA, VDD = 4.5V
Inputs, VIN = 0 and 2.4V, V CC = 5.5
4.0
V
-10
-10
+10
+10
mA
Enables = EN/EN= 0 and 5.5V,
VCC = 5.5
3
Differential Input High Threshold
Differential Input Low Threshold
VCM = +1.2V
VCM = +1.2V
+100
mV
mV
VTH
3
-100
VTL
II
Receiver input Current
VIN = 2.4V
-10
-10
+10
+10
mA
mA
4
Output Three-State Current
Disabled, VOUT = 0 V or VDD
IOZ
VCL
Input clamp voltage
ICL = +/-18mA
-1.5
-15
1.5
V
3
IOS
Enabled, VOUT = 0 V2
Output Short Circuit Current
-130
mA
4
Loaded supply current receivers
enabled
EN, EN = VDD or VSS
Inputs Open
11
11
mA
mA
ICC
4
Loaded supply current receivers
disabled
EN = VSS, EN = VDD
Inputs Open
ICCZ
Notes:
1. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground.
2. Output short circuit current (I ) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not exceed
OS
maximum junction temperature specification.
3. Guaranteed by characterization.
4. Device tested at V = 5.5V only.
CC
5
AC SWITCHING CHARACTERISTICS1, 2, 3, 4
(VDD = +5.0V + 10%, TA = -55 °C to +125°C)
SYMBOL
PARAMETER
MIN
MAX
UNIT
tPHLD
Differential Propagation Delay High to Low
CL = 20pf (figures 4 and 5)
1.0
8.0
ns
tPLHD
Differential Propagation Delay Low to High
CL = 20pf (figures 4 and 5)
1.0
8.0
ns
tSKD
Differential Skew (tPHLD - tPLHD) (figures 4 and 5)
Channel-to-Channel Skew1 (figures 4 and 5)
0
0
3.0
3.0
ns
ns
4
tSK1
4
7.0
2.0
2.0
20
ns
ns
ns
ns
ns
ns
ns
tSK2
Chip-to-Chip Skew5 (figures 4 and 5)
Rise Time (figures 4 and 5)
4
tTLH
4
Fall Time (figures 4 and 5)
tTHL
4
Disable Time High to Z (figures 6 and 7)
Disable Time Low to Z (figures 6 and 7)
Enable Time Z to High (figures 6 and 7)
Enable Time Z to Low (figures 6 and 7)
tPHZ
4
20
tPLZ
4
20
tPZH
4
20
tPZL
Notes:
1. Channel-to-Channel Skew is defined as the difference between the propagation delay of the channel and the other channels in the same chip with an event on the inputs.
2. Generator waveform for all tests unless otherwise specified: f = 1 MHz, Z = 50W, t and t (0% - 100%) < 1ns for R and t and t < 6ns for EN or EN.
0
r
f
IN
r
f
3. C includes probe and jig capacitance.
L
4. Guaranteed by characterization.
5. Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays.
6
R
IN+
R
R
Generator
OUT
R
IN-
C
L
50W
50W
Receiver Enabled
Figure 4. Receiver Propagation Delay and Transition Time Test Circuit or Equivalent Circuit
R
+1.3V
+1.1V
IN-
+1.2V
V
= 200mV
0V Differential
ID
R
IN+
t
PHLD
t
PLHD
V
OH
80%
80%
1.25V
1.25V
20%
R
OUT
20%
V
OL
t
t
THL
TLH
Figure 5. Receiver Propagation Delay and Transition Time Waveforms
7
EN
V
DD
2K
R
IN+
IN-
R
20pf
2K
Figure 6. Receiver Three-State Delay Test Circuit or Equivalent Circuit
EN when EN = VDD
VDD
1.25V
1.25V
1.25V
0V
VDD
1.25V
tPLZ
EN when EN = VSS
0V
tPZL
VDD
50%
50%
0.5V
Output when
VID = -100mV
VOL
VOH
tPHZ
tPZH
Output when
VID = +100mV
0.5V
VSS
Figure 7. Receiver Three-State Delay Waveform
8
PACKAGING
Notes:
1. All exposed metalized areas are gold plated over electroplated nickel per MIL-PRF-38535.
2. The lid is electrically connected to VSS.
3. Lead finishes are in accordance to MIL-PRF-38535.
4. Package dimensions and symbols are similar to MIL-STD-1835 variation F-5A.
5. Lead position and coplanarity are not measured.
6. ID mark symbol is vendor option.
7. With solder, increase maximum by 0.003.
Figure 8. 16-pin Ceramic Flatpack
9
ORDERING INFORMATION
UT54LVDS032 QUAD RECEIVER:
UT 54LVDS032- * * * * *
Lead Finish:
(A)
(C)
(X)
=
=
=
Hot solder dipped
Gold
Factory option (gold or solder)
Screening:
(C)
(P)
=
=
Military Temperature Range flow
Prototype flow
Package Type:
(U) 16-lead Flatpack (dual-in-line)
=
Access Time:
Not applicable
Device Type:
UT54LVDS032 LVDS Receiver
Notes:
1. Lead finish (A,C, or X) must be specified.
2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Prototype flow per UTMC Manufacturing Flows Document. Tested at 25°C only. Lead finish is GOLD ONLY. Radiation neither
tested nor guaranteed.
4. Military Temperature Range flow per UTMC Manufacturing Flows Document. Devices are tested at -55°C, room temp, and 125°C.
Radiation neither tested nor guaranteed.
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UT54LVDS032 QUAD RECEIVER: SMD
95834
5962 -
**
* * *
Lead Finish:
(A)
(C)
(X)
=
=
=
Hot solder dipped
Gold
Factory Option (gold or solder)
Case Outline:
(X) 16 lead Flatpack (dual-in-line)
=
Class Designator:
(Q)
(V)
=
=
QML Class Q
QML Class V
Device Type
02 = LVDS Receiver
Drawing Number: 95834
Total Dose
(R) = 1E5 rad(Si)
(F) = 3E5 rad(Si)
(G) = 5E5 rad(Si)
(H) = 1E6 rad(Si)
Federal Stock Class Designator: No Options
Notes:
1.Lead finish (A,C, or X) must be specified.
2.If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3.Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening.
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