OP196GP [ADI]
Micropower, Rail-to-Rail Input and Output Operational Amplifiers; 微功耗，轨到轨输入和输出运算放大器
| 型号： | OP196GP |
| 厂家： | 
ADI |
| 描述： | Micropower, Rail-to-Rail Input and Output Operational Amplifiers |
| 文件： | 总16页 (文件大小：340K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Micropower, Rail-to-Rail Input and Output
Operational Amplifiers
a
OP196/OP296/OP496
FEATURES
P IN CO NFIGURATIO NS
Rail-to-Rail Input and Output Sw ing
Low Pow er: 60 A/ Am plifier
Gain Bandw idth Product: 450 kHz
Single-Supply Operation: +3 V to +12 V
Low Offset Voltage: 300 V m ax
High Open-Loop Gain: 500 V/ m V
Unity-Gain Stable
8-Lead Narrow-Body SO
8-Lead P lastic D IP
NULL
–IN A
+IN A
V–
1
2
3
4
8
7
6
5
NC
NC
1
2
3
4
8
7
6
5
NULL
–IN A
+IN A
V–
OP196
V+
OP196
V+
OUT A
NULL
OUT A
NULL
NC = NO CONNECT
No Phase Reversal
NC = NO CONNECT
APPLICATIONS
Battery Monitoring
Sensor Conditioners
Portable Pow er Supply Control
Portable Instrum entation
8-Lead Narrow-Body SO
8-Lead P lastic D IP
1
2
3
4
8
7
6
5
V+
OUT A
–IN A
+IN A
V–
V+
1
2
3
4
8
7
6
5
OUT A
–IN A
+IN A
V–
OP296
OUT B
–IN B
+IN B
OP296
OUT B
–IN B
+IN B
GENERAL D ESCRIP TIO N
T he OP196 family of CBCMOS operational amplifiers features
micropower operation and rail-to-rail input and output ranges.
T he extremely low power requirements and guaranteed opera-
tion from +3 V to +12 V make these amplifiers perfectly suited
to monitor battery usage and to control battery charging. T heir
dynamic performance, including 26 nV/√Hz voltage noise
density, recommends them for battery-powered audio applica-
tions. Capacitive loads to 200 pF are handled without oscillation.
8-Lead TSSO P
1
8
V+
OUT A
–IN A
+IN A
V–
OUT B
–IN B
+IN B
OP296
4
5
T he OP196/OP296/OP496 are specified over the HOT extended
industrial (–40°C to +125°C) temperature range. +3 V opera-
tion is specified over the 0°C to +125°C temperature range.
14-Lead Narrow-Body SO
14-Lead P lastic D IP
T he single OP196 and the dual OP296 are available in 8-lead
plastic DIP and SO-8 surface mount packages. T he quad
OP496 is available in 14-lead plastic DIP and narrow SO-14
surface mount packages.
OUT A
–IN A
+IN A
+V
1
2
3
4
5
6
7
14
OUT D
1
2
3
4
5
6
7
14
13
12
OUT A
–IN A
+IN A
+V
OUT D
13 –IN D
12 +IN D
11 V–
–IN D
+IN D
OP496
10
9
+IN B
–IN B
OUT B
+IN C
–IN C
OUT C
11 V–
OP496
10 +IN C
+IN B
–IN B
OUT B
8
9
8
–IN C
OUT C
14-Lead TSSO P
(RU Suffix)
1
14
OUT A
–IN A
+IN A
V+
+IN B
–IN B
OUT B
OUT D
–IN D
+IN D
V–
+IN C
–IN C
OUT C
OP496
7
8
REV. B
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 781/ 329-4700
Fax: 781/ 326-8703
World Wide Web Site: http:/ / w w w .analog.com
© Analog Devices, Inc., 1998
OP196/OP296/OP496–SPECIFICATIONS
ELECTRICAL SPECIFICATIONS (@ V = +5.0 V, V = +2.5 V, T = +25؇C unless otherwise noted)
S
CM
A
P aram eter
Sym bol
Conditions
Min
Typ
Max
Units
INPUT CHARACT ERIST ICS
Offset Voltage
VOS
OP196G, OP296G, OP496G
–40°C ≤ TA ≤ +125°C
OP296H, OP496H
–40°C ≤ TA ≤ +125°C
–40°C ≤ TA ≤ +125°C
35
300
650
800
1.2
±50
±8
µV
µV
µV
mV
nA
nA
nA
V
Input Bias Current
Input Offset Current
IB
IOS
±10
±1.5
–40°C ≤ TA ≤ +125°C
±20
+5.0
Input Voltage Range
VCM
0
Common-Mode Rejection Ratio
CMRR
0 V ≤ VCM ≤ 5.0 V,
–40°C ≤ TA ≤ +125°C
RL = 100 kΩ,
65
dB
Large Signal Voltage Gain
AVO
0.30 V ≤ VOUT ≤ 4.7 V,
–40°C ≤ TA ≤ +125°C
G Grade, Note 1
H Grade, Note 1
G Grade, Note 2
150
200
V/mV
µV
mV
µV/°C
µV/°C
Long-T erm Offset Voltage
Offset Voltage Drift
VOS
550
1
∆VOS/∆T
1.5
2
H Grade, Note 2
OUT PUT CHARACT ERIST ICS
Output Voltage Swing High
VOH
VOL
IOUT
IL = –100 µA
IL = 1 mA
IL = 2 mA
IL = –1 mA
IL = –1 mA
IL = –2 mA
4.85
4.30
4.92
4.56
4.1
V
V
V
mV
mV
mV
mA
Output Voltage Swing Low
Output Current
36
70
550
350
750
±4
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
ISY
±2.5 V ≤ VS ≤ ±6 V,
–40°C ≤ TA ≤ +125°C
85
dB
µA
µA
Supply Current per Amplifier
VOUT = 2.5 V, RL
=
∞
60
80
–40°C ≤ TA ≤ +125°C
45
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Phase Margin
SR
GBP
øm
RL = 100 kΩ
0.3
350
47
V/µs
kHz
Degrees
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
en p-p
en
in
0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
0.8
26
0.19
µV p-p
nV/√Hz
pA/√Hz
NOT ES
1Long-term offset voltage is guaranteed by a 1000 hour life test performed on three independent lots at +125 °C, with an LT PD of 1.3.
2Offset voltage drift is the average of the –40°C to +25°C delta and the +25°C to +125°C delta.
Specifications subject to change without notice.
REV. B
–2–
OP196/OP296/OP496
ELECTRICAL SPECIFICATIONS (@ V = +3.0 V, V = +1.5 V, T = +25؇C unless otherwise noted)
S
CM
A
P aram eter
Sym bol
Conditions
Min
Typ
Max
Units
INPUT CHARACT ERIST ICS
Offset Voltage
VOS
OP196G, OP296G, OP496G
0°C ≤ T A ≤ +125°C
OP296H, OP496H
35
300
650
800
1.2
±50
±8
µV
µV
µV
mV
nA
nA
V
0°C ≤ T A ≤ +125°C
Input Bias Current
Input Offset Current
Input Voltage Range
Common-Mode Rejection Ratio
IB
IOS
VCM
CMRR
±10
±1
0
+3.0
0 V ≤ VCM ≤ 3.0 V,
0°C ≤ T A ≤ +125°C
RL = 100 kΩ
G Grade, Note 1
H Grade, Note 1
G Grade, Note 2
H Grade, Note 2
60
80
dB
V/mV
µV
mV
µV/°C
µV/°C
Large Signal Voltage Gain
Long-T erm Offset Voltage
AVO
VOS
200
550
1
Offset Voltage Drift
∆VOS/∆T
1.5
2
OUT PUT CHARACT ERIST ICS
Output Voltage Swing High
Output Voltage Swing Low
VOH
VOL
IL = 100 µA
IL = –100 µA
2.85
V
mV
70
POWER SUPPLY
Supply Current per Amplifier
ISY
VOUT = 1.5 V, RL
0°C ≤ T A ≤ +125°C
=
∞
40
60
80
µA
µA
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Phase Margin
SR
GBP
øm
RL = 100 kΩ
0.25
350
45
V/µs
kHz
Degrees
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
en p-p
en
in
0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
0.8
26
0.19
µV p-p
nV/√Hz
pA/√Hz
NOT ES
1Long-term offset voltage is guaranteed by a 1000 hour life test performed on three independent lots at +125 °C, with an LT PD of 1.3.
2Offset voltage drift is the average of the 0°C to +25°C delta and the +25°C to +125°C delta.
Specifications subject to change without notice.
REV. B
–3–
OP196/OP296/OP496
(@ V = +12.0 V, V = +6 V, T = +25؇C unless otherwise noted)
ELECTRICAL SPECIFICATIONS
S
CM
A
P aram eter
Sym bol
Conditions
Min
Typ
Max
Units
INPUT CHARACT ERIST ICS
Offset Voltage
VOS
OP196G, OP296G, OP496G
0°C ≤ T A ≤ +125°C
OP296H, OP496H
0°C ≤ T A ≤ +125°C
–40°C ≤ TA ≤ +125°C
35
300
650
800
1.2
±50
±8
µV
µV
µV
mV
nA
nA
nA
V
Input Bias Current
Input Offset Current
IB
IOS
±10
±1
–40°C ≤ TA ≤ +125°C
±15
+12
Input Voltage Range
VCM
0
Common-Mode Rejection Ratio
CMRR
0 V ≤ VCM ≤ +12 V,
–40°C ≤ TA ≤ +125°C
RL = 100 kΩ
G Grade, Note 1
H Grade, Note 1
G Grade, Note 2
H Grade, Note 2
65
dB
Large Signal Voltage Gain
Long-T erm Offset Voltage
AVO
VOS
300
1000
V/mV
µV
mV
550
1
Offset Voltage Drift
∆VOS/∆T
1.5
2
µV/°C
µV/°C
OUT PUT CHARACT ERIST ICS
Output Voltage Swing High
VOH
VOL
IOUT
IL = 100 µA
IL = 1 mA
IL = –1 mA
IL = –1 mA
11.85
11.30
V
V
mV
mV
mA
Output Voltage Swing Low
Output Current
70
550
±4
POWER SUPPLY
Supply Current per Amplifier
ISY
VS
VOUT = 6 V, RL
–40°C ≤ TA ≤ +125°C
=
∞
60
80
+12
µA
µA
V
Supply Voltage Range
+3
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Phase Margin
SR
GBP
øm
RL = 100 kΩ
0.3
450
50
V/µs
kHz
Degrees
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
en p-p
en
in
0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
0.8
26
0.19
µV p-p
nV/√Hz
pA/√Hz
NOT ES
1Long-term offset voltage is guaranteed by a 1000 hour life test performed on three independent lots at +125 °C, with an LT PD of 1.3.
2Offset voltage drift is the average of the –40°C to +25°C delta and the +25°C to +125°C delta.
Specifications subject to change without notice.
–4–
REV. B
OP196/OP296/OP496
ABSO LUTE MAXIMUM RATINGS1
O RD ERING GUID E
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+15 V
Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15 V
Differential Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . +15 V
Output Short Circuit Duration . . . . . . . . . . . . . . . . . Indefinite
Storage T emperature Range
P, S, RU Package . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating T emperature Range
OP196G, OP296G, OP496G, H . . . . . . . –40°C to +125°C
Junction T emperature Range
Tem perature
Range
P ackage
D escription
P ackage
O ption
Model
OP196GP
OP196GS
–40°C to +125°C
–40°C to +125°C
8-Lead Plastic DIP N-8
8-Lead SOIC SO-8
OP296GP
OP296GS
–40°C to +125°C
–40°C to +125°C
OP296HRU –40°C to +125°C
8-Lead Plastic DIP N-8
8-Lead SOIC
8-Lead T SSOP
SO-8
RU-8
P, S, RU Package . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead T emperature Range (Soldering, 60 sec) . . . . . . . +300°C
OP496GP
OP496GS
OP496HRU –40°C to +125°C
–40°C to +125°C
–40°C to +125°C
14-Lead Plastic DIP N-14
14-Lead SOIC
SO-14
RU-14
14-Lead T SSOP
3
P ackage Type
Units
JA
JC
8-Lead Plastic DIP
8-Lead SOIC
8-Lead T SSOP
14-Lead Plastic DIP
14-Lead SOIC
103
158
240
83
120
180
43
43
43
39
36
35
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
14-Lead T SSOP
NOT ES
1Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
2For supply voltages less than +15 V, the absolute maximum input voltage is
equal to the supply voltage.
3θJA is specified for the worst case conditions, i.e., θJA is specified for device in
socket for P-DIP package; θJA is specified for device soldered in circuit board
for SOIC and T SSOP packages.
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the OP196/OP296/OP496 feature proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. T herefore, pro per
ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
–5–
OP196/OP296/OP496–Typical Performance Characteristics
25
20
15
10
5
250
200
150
V
V
= ؉5V
S
= ؉2.5V
CM
V
T
= ؉3V
S
T
= –40؇C TO ؉125؇C
A
= ؉25؇C
A
COUNT = 400
100
50
0
0
–4.0 –3.5 –3.0 –2.5 –2.0 –1.5 –1.0 –0.5
0
0.5 1.0
–250 –200 –150 –100 –50
0
50
100 150 200 250
INPUT OFFSET DRIFT, TCV – V/؇C
INPUT OFFSET VOLTAGE – V
OS
Figure 1. Input Offset Voltage Distribution
Figure 4. Input Offset Voltage Distribution (TCVOS )
25
250
200
150
100
50
V
V
= ؉12V
S
= ؉6V
V
T
= ؉5V
CM
S
T
= –40؇C TO ؉125؇C
A
20
15
10
5
= ؉25؇C
A
COUNT = 400
0
0
–4.0 –3.5 –3.0 –2.5 –2.0 –1.5 –1.0 –0.5
0
0.5 1.0 1.5
–250 –200 –150 –100 –50
0
50
100 150 200 250
INPUT OFFSET DRIFT, TCV – V/؇C
INPUT OFFSET VOLTAGE – V
OS
Figure 2. Input Offset Voltage Distribution
Figure 5. Input Offset Voltage Distribution (TCVOS
)
250
200
150
100
50
600
V
T
= ؉12V
S
؉3V
V
؉12V
S
= ؉25؇C
400
200
0
A
V
S
COUNT = 400
V
=
CM
2
–200
0
–400
–250 –200 –150 –100 –50
0
50
100 150 200 250
–75
–50
–25
0
25
50
75
100
125
150
INPUT OFFSET VOLTAGE – V
TEMPERATURE – ؇C
Figure 3. Input Offset Voltage Distribution
Figure 6. Input Offset Voltage vs. Tem perature
REV. B
–6–
OP196/OP296/OP496
25
20
15
10
5
1000
100
10
V
V
= ؉5V
S
= ؉2.5V
CM
V
= ؎1.5V
S
SOURCE
SINK
0
1
–75
–50
–25
0
25
50
75
100
125 150
0.001
0.01
0.1
LOAD CURRENT – mA
1
10
TEMPERATURE – ؇C
Figure 7. Input Bias Current vs. Tem perature
Figure 10. Output Voltage to Supply Rail vs. Load Current
16
1000
V
= ؎2.5V
S
12
100
10
1
SOURCE
SINK
8
4
2
3
5
12
14
0.001
0.01
0.1
LOAD CURRENT – mA
1
10
SUPPLY VOLTAGE – Volts
Figure 8. Input Bias Current vs. Supply Voltage
Figure 11. Output Voltage to Supply Rail vs. Load Current
40
1000
V
= ؎2.5V
= ؉25؇C
S
30
20
T
A
V
= ؎6V
S
100
SOURCE
10
0
SINK
–10
–20
–30
–40
10
1
0.001
0.01
0.1
LOAD CURRENT – mA
1
10
–2.5 –2.0 –1.5 –1.0 –0.5
0
0.5
1.0 1.5
2.0 2.5
COMMON-MODE VOLTAGE – Volts
Figure 9. Input Bias Current vs. Com m on-Mode Voltage
Figure 12. Output Voltage to Supply Rail vs. Load Current
REV. B
–7–
OP196/OP296/OP496–Typical Performance Characteristics
4.95
4.70
4.45
4.2
90
80
70
60
50
40
30
20
10
0
I
= 100A
L
V
= ؎2.5V
= –40؇C
S
T
A
I
= 1mA
L
GAIN
0
I
= 2mA
45
L
90
V
= ؉5V
S
PHASE
3.85
3.7
135
180
225
–10
–75
–50
–25
0
25
50
75
100 125
150
10
100
1k
10k
100k
1M
TEMPERATURE – ؇C
FREQUENCY – Hz
Figure 13. Output Voltage Swing vs. Tem perature
Figure 16. Open-Loop Gain and Phase vs. Frequency
(No Load)
0.80
90
V
= ؉5V
S
V
T
= ؎2.5V
= ؉125؇C
S
A
80
70
60
50
40
30
20
10
0
0.60
0.50
0.30
0.10
I
= –1mA
L
GAIN
0
45
90
PHASE
135
180
225
I
= –100A
L
–10
–75 –50
–25
0
25
50
75
100
125
150
10
100
1k
10k
100k
1M
TEMPERATURE – ؇C
FREQUENCY – Hz
Figure 14. Output Voltage Swing vs. Tem perature
Figure 17. Open-Loop Gain and Phase vs. Frequency
(No Load)
90
950
V
= ؉5V
V
T
= ؎2.5V
= ؉25؇C
S
S
80
70
60
50
40
30
20
10
0
0.3V < VO < 4.7V
= 100k⍀
A
800
650
500
350
200
R
L
GAIN
0
45
90
PHASE
135
180
225
–10
10
100
1k
10k
100k
1M
–75
–50
–25
0
25
50
75
100
125 150
FREQUENCY – Hz
TEMPERATURE – ؇C
Figure 15. Open-Loop Gain and Phase vs. Frequency
(No Load)
Figure 18. Open-Loop Gain vs. Tem perature
–8–
REV. B
OP196/OP296/OP496
600
500
400
300
200
100
0
160
140
120
100
80
V
T
= ؎2.5V
= ؉25؇C
S
V
T
= ؉5V
S
A
= ؉25؇C
A
ALL CHANNELS
60
40
20
0
–20
–40
150
100
50
10
2
1
100
1k
10k
100k
1M
10M
LOAD – k⍀
FREQUENCY – Hz
Figure 19. Open Loop Gain vs. Resistive Load
Figure 22. CMRR vs. Frequency
70
160
140
120
100
80
V
T
= ؉5V
V
= ؎2.5V
= 10k⍀
= ؉25؇C
S
S
60
50
= ؉25؇C
R
T
A
L
A
40
30
+PSRR
20
60
10
40
–PSRR
0
20
–10
–20
–30
0
–20
–40
10
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
10M
FREQUENCY – Hz
FREQUENCY – Hz
Figure 20. Closed-Loop Gain vs. Frequency
Figure 23. PSRR vs. Frequency
1000
6
5
4
3
2
V
V
= ؎2.5V
900
800
700
600
500
400
300
200
100
0
S
= ؉5V p-p
= ؉1
IN
V
= ؎2.5V
= ؉25؇C
S
A
R
V
L
T
A
= 100k⍀
A
= 10
CL
A
= 1
CL
1
0
1k
100
1k
10k
FREQUENCY – Hz
100k
1M
10k
100k
FREQUENCY – Hz
1M
Figure 21. Output Im pedance vs. Frequency
Figure 24. Maxim um Output Swing vs. Frequency
REV. B
–9–
OP196/OP296/OP496–Typical Performance Characteristics
90
0.6
V
= ؎2.5V
= ؉25؇C
= 0V
S
80
T
A
0.5
V
CM
70
0.4
V
= ؉12V
S
60
50
40
30
20
0.3
0.2
0.1
0
V
= ؉5V
S
V
= ؉3V
S
–75 –50 –40 –25
0
25 50
85 75
100 125 150
1
10
100
FREQUENCY – Hz
1k
TEMPERATURE – ؇C
Figure 25. Supply Current/Am plifier vs. Tem perature
Figure 28. Input Bias Current Noise Density vs. Frequency
55
10
T
= ؉25؇C
V
= ؎6V
8
6
A
S
T
= ؉25؇C
A
TO 0.1%
؉OUTPUT SWING
50
45
40
35
4
2
0
–2
–4
–6
–8
–10
– OUTPUT SWING
1
3
5
7
9
11
12
13
0
5
10
15
20
25
30
SUPPLY VOLTAGE – Volts
SETTLING TIME – s
Figure 26. Supply Current/Am plifier vs. Supply Voltage
Figure 29. Settling Tim e to 0.1% vs. Step Size
80
V
= ؎2.5V
= ؉25؇C
S
70
60
50
40
30
20
10
0
T
A
V
= 0V
CM
2mV
1s
100
90
10
V
= ؎2.5V
S
0%
A
= 10k
V
e
= 0.8V p-p
n
1
10
100
FREQUENCY – Hz
1k
Figure 27. Voltage Noise Density vs. Frequency
Figure 30. 0.1 Hz to 10 Hz Noise
REV. B
–10–
OP196/OP296/OP496
V
R
= ؎2.5V
= 10k⍀
L
S
100
90
100mV
100
90
V
=
2.5V
S
A
R
C
= 1
V
L
10
= 10k⍀
= 100pF
= ؉25؇C
10
0%
0V
0%
L
T
A
20mV
2s
1V
10s
Figure 31. Sm all Signal Transient Response
Figure 33. Large Signal Transient Response
V
= ؎2.5V
= 100k⍀
S
R
100
90
L
100
100mV
90
V
= ؎2.5V
= 1
S
A
R
C
T
V
L
L
10
10
= 100k⍀
= 100pF
= ؉25؇C
0%
0%
0V
1V
10s
20mV
A
2s
Figure 32. Sm all Signal Transient Response
Figure 34. Large Signal Transient Response
CH A: 40.0V FS
MKR: 36.8V/ Hz
5.00V/DIV
10Hz
0Hz
MKR: 1.00Hz
BW: 145mHz
Figure 35. 1/f Noise Corner, VS = ±5 V, AV = 1,000
V
CC
R2
R1
R8
R7
I1
R6
I4
I5
D3
Q22
D9
QL1
Q11
Q12
Q6
Q5
Q7
D4
Q17
D8
Q21
2x
2x
Q4
QC1
Q3
CC2
OUT
1x
1x
CF1
1x
1x
CF2
Q13
Q14
Q8
2x
D5
D6
2x
Q10
Q18
Q19
1x
Q9
2x
+IN
–IN
Q1
Q2
QC2
Q23
R5
CC1
R9
R3A
R3B
R4A
R4B
Q20
1.5x
I3
I2
Q16
Q15
D7
D10
1x
V
EE
1*
5*
*OP196 ONLY
Figure 36. Sim plified Schem atic
–11–
REV. B
OP196/OP296/OP496
AP P LICATIO NS INFO RMATIO N
Functional D escr iption
input current must be limited if the inputs are driven beyond the
supply rails. In the circuit of Figure 38, the source amplitude is
±15 V, while the supply voltage is only ±5 V. In this case, a
2 kΩ source resistor limits the input current to 5 mA.
The OP196 family of operational amplifiers is comprised of single-
supply, micropower, rail-to-rail input and output amplifiers. Input
offset voltage (VOS) is only 300 µV maximum, while the output
will deliver ±5 mA to a load. Supply current is only 50 µA, while
bandwidth is over 450 kHz and slew rate is 0.3 V/µs. Figure 36
is a simplified schematic of the OP196—it displays the novel
circuit design techniques used to achieve this performance.
5V
V
5V
S
A
= 1
V
100
90
V
IN
0
Input O ver voltage P r otection
T he OPx96 family of op amps uses a composite PNP/NPN
input stage. T ransistor Q1 in Figure 36 has a collector-base
voltage of 0 V if +IN = VEE. If +IN then exceeds VEE, the junc-
tion will be forward biased and large diode currents will flow,
which may damage the device. T he same situation applies to
+IN on the base of transistor Q5 being driven above VCC . There-
fore, the inverting and noninverting inputs must not be driven
above or below either supply rail unless the input current is
limited.
V
OUT
10
0
0%
5V
1ms
TIME – 1ns/DIV
Figure 38. Output Voltage Phase Reversal Behavior
Input O ffset Voltage Nulling
Figure 37 shows the input characteristics for the OPx96 family.
T his photograph was generated with the power supply pins
connected to ground and a curve tracer’s collector output drive
connected to the input. As shown in the figure, when the input
voltage exceeds either supply by more than 0.6 V, internal pn-
junctions energize and permit current flow from the inputs to
the supplies. If the current is not limited, the amplifier may be
damaged. T o prevent damage, the input current should be
limited to no more than 5 mA.
T he OP196 provides two offset adjust terminals that can be
used to null the amplifier’s internal VOS. In general, operational
amplifier terminals should never be used to adjust system offset
voltages. A 100 kΩ potentiometer, connected as shown in Fig-
ure 39, is recommended to null the OP196’s offset voltage.
Offset nulling does not adversely affect T CVOS performance,
providing that the trimming potentiometer temperature coeffi-
cient does not exceed ±100 ppm/°C.
V+
8
7
2
6
100
OP196
6
90
4
4
3
5
2
0
1
100k⍀
V–
–2
10
–4
0%
–6
Figure 39. Offset Nulling Circuit
D r iving Capacitive Loads
–8
–1.5 –1 –0.5
0
0.5
1
1.5
OP196 family amplifiers are unconditionally stable with capaci-
tive loads less than 170 pF. When driving large capacitive loads
in unity-gain configurations, an in-the-loop compensation
technique is recommended, as illustrated in Figure 40.
INPUT VOLTAGE – Volts
Figure 37. Input Overvoltage I-V Characteristics of the
OPx96 Fam ily
R
R
O utput P hase Rever sal
G
F
V
IN
Some other operational amplifiers designed for single-supply
operation exhibit an output voltage phase reversal when their
inputs are driven beyond their useful common-mode range.
T ypically for single-supply bipolar op amps, the negative supply
determines the lower limit of their common-mode range. With
these common-mode limited devices, external clamping diodes
are required to prevent input signal excursions from exceeding
the device’s negative supply rail (i.e., GND) and triggering
output phase reversal.
C
F
R
X
V
OP296
OUT
C
L
R
R
G
O
R
=
WHERE R = OPEN-LOOP OUTPUT RESISTANCE
O
X
R
F
(R
|
)
C R
L O
+ R
I
F
G
I +
(
|A
R
CL
F
T he OPx96 family of op amps is free from output phase reversal
effects due to its novel input structure. Figure 38 illustrates the
performance of the OPx96 op amps when the input is driven
beyond the supply rails. As previously mentioned, amplifier
Figure 40. In-the-Loop Com pensation Technique for
Driving Capacitive Loads
–12–
REV. B
OP196/OP296/OP496
A Micr opower False-Gr ound Gener ator
same potential. T he result is that both terminals of R1 are at the
same potential and no current flows in R1. Since there is no
current flow in R1, the same condition must exist in R2; thus,
the output of the circuit tracks the input signal. When the input
signal is below 0 V, the output voltage of A1 is forced to 0 V.
T his condition now forces A2 to operate as an inverting voltage
follower because the noninverting terminal of A2 is also at 0 V.
T he output voltage of VOUT A is then a full-wave rectified
version of the input signal. A resistor in series with A1’s
noninverting input protects the ESD diodes when the input
signal goes below ground.
Some single supply circuits work best when inputs are biased
above ground, typically at 1/2 of the supply voltage. In these
cases, a false-ground can be created by using a voltage divider
buffered by an amplifier. One such circuit is shown in Figure 41.
T his circuit will generate a false-ground reference at 1/2 of the
supply voltage, while drawing only about 55 µA from a 5 V
supply. T he circuit includes compensation to allow for a 1 µF
bypass capacitor at the false-ground output. T he benefit of a
large capacitor is that not only does the false-ground present a
very low dc resistance to the load, but its ac impedance is low
as well.
Squar e Wave O scillator
T he oscillator circuit in Figure 43 demonstrates how a rail-to-
rail output swing can reduce the effects of power supply varia-
tions on the oscillator’s frequency. T his feature is especially
valuable in battery powered applications, where voltage regula-
tion may not be available. T he output frequency remains stable
as the supply voltage changes because the RC charging current,
which is derived from the rail-to-rail output, is proportional to
the supply voltage. Since the Schmitt trigger threshold level is
also proportional to supply voltage, the frequency remains rela-
tively independent of supply voltage. For a supply voltage
change from 9 V to 5 V, the output frequency only changes
about 4 Hz. T he slew rate of the amplifier limits the oscillation
frequency to a maximum of about 200 Hz at a supply voltage
of +5 V.
+5V OR +12V
10k⍀
0.022F
240k⍀
2
3
7
100⍀
+2.5V OR +6V
6
OP196
1F
4
240k⍀
1F
Figure 41. A Micropower False-Ground Generator
Single-Supply H alf-Wave and Full-Wave Rectifier s
An OP296, configured as a voltage follower operating from a
single supply, can be used as a simple half-wave rectifier in low
frequency (<400 Hz) applications. A full-wave rectifier can be
configured with a pair of OP296s as illustrated in Figure 42.
V+
100k⍀
59k⍀
R2
100k⍀
R1
100k⍀
8
4
3
2
1
FREQ OUT
1
100k⍀
1/2
OP296/
OP496
+5V
8
f
=
< 200Hz @ V+ = +5V
OSC
V
A
6
5
OUT
2k⍀
RC
+2Vp-p
<500Hz
FULL-WAVE
RECTIFIED
OUTPUT
A2
7
3
2
R
1
A1
1/2
OP296
C
4
1/2
OP296
V
B
OUT
HALF-WAVE
RECTIFIED
OUTPUT
Figure 43. Square Wave Oscillator Has Stable Frequency
Regardless of Supply Voltage Changes
A 3 V Low D r opout, Linear Voltage Regulator
1V
500mV
500µs
Figure 44 shows a simple +3 V voltage regulator design. T he
regulator can deliver 50 mA load current while allowing a 0.2 V
dropout voltage. T he OP296’s rail-to-rail output swing easily
drives the MJE350 pass transistor without requiring special
drive circuitry. With no load, its output can swing to less than
the pass transistor’s base-emitter voltage, turning the device
nearly off. At full load, and at low emitter-collector voltages, the
transistor beta tends to decrease. T he additional base current is
easily handled by the OP296 output.
100
90
INPUT
V
B
OUT
(HALF-WAVE
OUTPUT)
f = 500Hz
10
V
A
0%
OUT
(FULL-WAVE
OUTPUT)
500mV
T he AD589 provides a 1.235 V reference voltage for the regula-
tor. T he OP296, operating with a noninverting gain of 2.43,
drives the base of the MJE350 to produce an output voltage of
3.0 V. Since the MJE350 operates in an inverting (common-
emitter) mode, the output feedback is applied to the OP296’s
noninverting input.
Figure 42. Single-Supply Half-Wave and Full-Wave
Rectifiers Using an OP296
T he circuit works as follows: When the input signal is above
0 V, the output of amplifier A1 follows the input signal. Since
the noninverting input of amplifier A2 is connected to A1’s
output, op amp loop control forces A2’s inverting input to the
REV. B
–13–
OP196/OP296/OP496
T he next two DACs, B and C, sum their outputs into the other
OP296 amplifier. In this circuit DAC C provides the coarse
output voltage setting and DAC B is used for fine adjustment.
T he insertion of R1 in series with DAC B attenuates its contri-
bution to the voltage sum node at the DAC C output.
I
L < 50mA
MJE 350
V
O
V
IN
44.2k⍀
1%
100F
5V TO 3.2V
8
3
2
30.9k⍀
1%
1/2
OP296
1
A H igh-Side Cur r ent Monitor
4
In the design of power supply control circuits, a great deal of
design effort is focused on ensuring a pass transistor’s long-term
reliability over a wide range of load current conditions. As a
result, monitoring and limiting device power dissipation is of
prime importance in these designs. T he circuit illustrated in
Figure 47 is an example of a +5 V, single-supply high-side cur-
rent monitor that can be incorporated into the design of a volt-
age regulator with fold-back current limiting or a high current
power supply with crowbar protection. T his design uses an
OP296’s rail-to-rail input voltage range to sense the voltage
drop across a 0.1 Ω current shunt. A p-channel MOSFET is
used as the feedback element in the circuit to convert the op
amp’s differential input voltage into a current. T his current is
then applied to R2 to generate a voltage that is a linear represen-
tation of the load current. T he transfer equation for the current
monitor is given by:
1000pF
1.235V
43k⍀
AD589
Figure 44. 3 V Low Dropout Voltage Regulator
Figure 45 shows the regulator’s recovery characteristics when its
output underwent a 20 mA to 50 mA step current change.
2V
50mA
STEP
CURRENT
CONTROL
100
90
WAVEFORM
30mA
10
OUTPUT
RSENSE
0%
Monitor Output = R2 ×
× IL
10mV
50µs
R1
For the element values shown, the Monitor Output’s transfer
characteristic is 2.5 V/A.
Figure 45. Output Step Load Current Recovery
Buffer ing a D AC O utput
Multichannel T rimDACs such as the AD8801/AD8803, are
R
SENSE
I
L
®
0.1⍀
+5V
+5V
widely used for digital nulling and similar applications. T hese
DACs have rail-to-rail output swings, with a nominal output
resistance of 5 kΩ. If a lower output impedance is required, an
OP296 amplifier can be added. T wo examples are shown in
Figure 45. One amplifier of an OP296 is used as a simple buffer
to reduce the output resistance of DAC A. T he OP296 provides
rail-to-rail output drive while operating down to a 3 V supply
and requiring only 50 µA of supply current.
+5V
R1
100⍀
3
2
8
1/2
OP296
4
1
S
D
G
M1
3N163
MONITOR
OUTPUT
R2
2.49k⍀
+5V
Figure 47. A High-Side Load Current Monitor
V
V
REFH DD
OP296
V
H
A Single-Supply RTD Am plifier
SIMPLE BUFFER
0V TO +5V
+4.983V
V
L
T he circuit in Figure 48 uses three op amps on the OP496 to
produce a bridge driver for an RT D amplifier while operating
from a single +5 V supply. T he circuit takes advantage of the
OP496’s wide output swing to generate a bridge excitation
voltage of 3.9 V. An AD589 provides a 1.235 V reference for
the bridge current. Op amp A1 drives the bridge to maintain
1.235 V across the parallel combination of the 6.19 kΩ and
2.55 MΩ resistors, which generates a 200 µA current source.
T his current divides evenly and flows through both halves of
the bridge. T hus, 100 µA flows through the RT D to generate
an output voltage which is proportional to its resistance. For
improved accuracy, a 3-wire RT D is recommended to balance
the line resistance in both 100 Ω legs of the bridge.
V
H
+1.1mV
V
L
R1
100k⍀
V
H
SUMMER CIRCUIT
WITH FINE TRIM
ADJUSTMENT
V
L
AD8801/
AD8803
V
GND
REFL
DIGITAL INTERFACING
OMITTED FOR CLARITY
Figure 46. Buffering a Trim DAC Output
T rimDAC is a registered trademark of Analog Devices Inc.
–14–
REV. B
OP196/OP296/OP496
Amplifiers A2 and A3 are configured in a two op amp instru-
mentation amplifier configuration. For ease of measurement,
the IA resistors are chosen to produce a gain of 259, so that
each 1°C increase in temperature results in a 10 mV increase in
the output voltage. T o reduce measurement noise, the band-
width of the amplifier is limited. A 0.1 µF capacitor, connected
in parallel with the 100 kΩ resistor on amplifier A3, creates a pole
at 16 Hz.
GAIN = 259
+5V
200⍀
10-TURNS
26.7k⍀
26.7k⍀
1/4
OP496
1/4
OP496
A3
V
100⍀
RTD
OUT
A2
100⍀
2.55M⍀
392⍀
100k⍀
0.1F
392⍀
1/4
OP496
6.17k⍀
20k⍀
100k⍀
A1
NOTE:
AD589
37.4k⍀
ALL RESISTORS 1% OR BETTER
+5V
Figure 48. A Single Supply RTD Am plifier
CIN
*
* GAIN ST AGE
*
1
2
1P
* OP496 SPICE Macro-model
*
REV. B, 5/95
ARG / ADSC
*
* Copyright 1995 by Analog Devices
*
EREF 98
0
POLY(2)
POLY(2)
251.641MEG
8P
DX
DX
(99,0) (50,0) 0 0.5 0.5
(6,5) (13,12) 0 10U 10U
G1
R10
CC
D1
D2
*
98
15
15
15
50
15
98
49
99
15
* Refer to “README.DOC” file for License Statement.
* Use of this model indicates your acceptance of the
* terms and provisions in the License Statement.
*
* Node assignments
*
*
Noninverting input
Inverting input
* COMMON MODE ST AGE
*
ECM 16
R11
R12
*
* OUT PUT ST AGE
*
ISY
EIN
Q24
QD4 37
Q27
R5
R6
Q26
QD5 40
Q28 41
QL1 37
R7
I4
QD7 42
QD6 43
Q29
Q30
QD10 45
R9
Q31
QD8 47
QD9 48
R8
I5
Q32
Q33
.MODEL
.MODEL
.MODEL
.ENDS
*
*
*
*
Positive supply
98
17
98
POLY(2)
1MEG
10
(1,98) (2,98)
0
0.5 0.5
Negative supply
Output
16
17
*
.SUBCKT OP496
*
1
2
99
50
49
99
35
37
50
50
35
37
37
39
38
42
40
40
41
41
43
42
43
43
45
46
46
47
47
48
51
46
48
44
20U
POLY(1)
* INPUT ST AGE
*
(15,98) 1.42735
1
36
38
38
50
99
99
QN
QP
QP
1
1
1
IREF 21
QB1 21
QB2 22
50
21
21
21
22
22
4
4
4
4
1
3
2
1
3
11
11
11
11
5
1U
99
99
99
50
50
7
8
7
8
7
40
36
99
39
99
99
99
50
50
50
50
50
50
99
99
QP
QP
QP
QN
QN
QN
QN
QN
QN
QP
QP
1
1
1.5
150K
45K
50
QB3
4
50
50
50
99
QN
QN
QN
QP
3
1
1
1
QB4 22
QB5 11
2
3
2
2
1
1
2
2
39
44
99
Q1
Q2
5
6
99
99
10.7K
2U
50
Q3
Q4
4
4
50
50
50
50
50
QN
QN
QN
QN
QN
2
2
1
1.5
1
Q5
Q6
EOS
Q7
Q8
50
50
3
42
44
50
50
8
47
44
POLY(1)
9
10
9
10
9
10
50K
50K
50K
50K
0.75N
3.183P
3.183P
(17,98) 35U
1
99
99
12
13
11
11
99
99
12
13
1
50
QN
QN
QP
QP
QP
QP
2
2
2
2
1
1
50
99
99
99
99
45
46
175
48
Q9
99
99
99
QP
QP
QP
1
1
5
Q10
Q11
Q12
R1
R2
R3
48
51
99
99
49
49
2.9K
1U
99
6
99
50
QP
QN
10
4
50
50
2
6
13
50
R4
DX D()
QN NPN(BF=120VAF=100)
QP PNP(BF=80 VAF=60)
IOS
C10
C11
5
12
REV. B
–15–
OP196/OP296/OP496
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
8-Lead P lastic D IP
14-Lead P lastic D IP
(N-14)
(N-8)
0.430 (10.92)
0.348 (8.84)
0.795 (20.19)
0.725 (18.42)
14
1
8
7
8
5
4
0.280 (7.11)
0.240 (6.10)
0.280 (7.11)
0.240 (6.10)
1
0.325 (8.25)
0.300 (7.62)
0.325 (8.25)
0.300 (7.62)
0.195 (4.95)
0.115 (2.93)
0.060 (1.52)
0.015 (0.38)
0.060 (1.52)
0.015 (0.38)
PIN 1
PIN 1
0.195 (4.95)
0.210 (5.33)
0.210 (5.33)
MAX
0.115 (2.93)
MAX
0.130
0.130
(3.30)
MIN
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.160 (4.06)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
SEATING
PLANE
0.022 (0.558)
0.014 (0.356)
0.070 (1.77)
0.045 (1.15)
0.100 0.070 (1.77)
0.022 (0.558)
0.014 (0.356)
0.100
(2.54)
BSC
(2.54)
0.045 (1.15)
BSC
14-Lead Nar r ow-Body SO IC
(SO -14)
8-Lead Nar r ow Body SO IC
(SO -8)
0.1968 (5.00)
0.1890 (4.80)
0.3444 (8.75)
0.3367 (8.55)
8
1
5
4
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
14
1
8
7
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.0688 (1.75)
0.0532 (1.35)
0.0196 (0.50)
0.0099 (0.25)
0.0688 (1.75)
0.0532 (1.35)
x 45°
PIN 1
0.0196 (0.50)
0.0098 (0.25)
0.0040 (0.10)
x 45°
0.0098 (0.25)
0.0040 (0.10)
0.0099 (0.25)
8°
0°
8°
0°
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
SEATING
PLANE
0.0098 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
SEATING
PLANE
0.0500 (1.27)
0.0160 (0.41)
0.0099 (0.25)
0.0075 (0.19)
8-Lead TSSO P
(RU-8)
14-Lead TSSO P
(RU-14)
0.122 (3.10)
0.114 (2.90)
0.201 (5.10)
0.193 (4.90)
8
5
14
8
7
1
4
1
PIN 1
0.0256 (0.65)
BSC
0.006 (0.15)
0.002 (0.05)
PIN 1
0.0433
(1.10)
MAX
0.006 (0.15)
0.002 (0.05)
0.0433
(1.10)
MAX
0.028 (0.70)
0.020 (0.50)
8°
0°
0.0118 (0.30)
0.0075 (0.19)
SEATING
PLANE
0.0079 (0.20)
0.0035 (0.090)
0.028 (0.70)
0.020 (0.50)
8°
0°
0.0118 (0.30)
0.0075 (0.19)
0.0256
(0.65)
BSC
SEATING
PLANE
0.0079 (0.20)
0.0035 (0.090)
–16–
REV. B
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