ADUM3401ARWZ-RL [ADI]
Quad-Channel, Digital Isolators, hanced System-Level ESD Reliability; 四通道数字隔离器， hanced系统级ESD可靠性
| 型号： | ADUM3401ARWZ-RL |
| 厂家： | 
ADI |
| 描述： | Quad-Channel, Digital Isolators, hanced System-Level ESD Reliability |
| 文件： | 总24页 (文件大小：423K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quad-Channel, Digital Isolators,
Enhanced System-Level ESD Reliability
Data Sheet
ADuM3400/ADuM3401/ADuM3402
FEATURES
GENERAL DESCRIPTION
Enhanced system-level ESD performance per IEC 61000-4-x
Low power operation
5 V operation
The ADuM340x1 are 4-channel digital isolators based on the
Analog Devices, Inc., iCoupler® technology. Combining high
speed CMOS and monolithic air core transformer technology,
these isolation components provide outstanding performance
characteristics superior to alternatives such as optocoupler devices.
1.4 mA per channel maximum @ 0 Mbps to 2 Mbps
4.3 mA per channel maximum @ 10 Mbps
34 mA per channel maximum @ 90 Mbps
3 V operation
0.9 mA per channel maximum @ 0 Mbps to 2 Mbps
2.4 mA per channel maximum @ 10 Mbps
20 mA per channel maximum @ 90 Mbps
Bidirectional communication
iCoupler devices remove the design difficulties commonly
associated with optocouplers. Typical optocoupler concerns
regarding uncertain current transfer ratios, nonlinear transfer
functions, and temperature and lifetime effects are eliminated
with the simple iCoupler digital interfaces and stable performance
characteristics. The need for external drivers and other discrete
components is eliminated with these iCoupler products. Further-
more, iCoupler devices consume one-tenth to one-sixth the
power of optocouplers at comparable signal data rates.
3 V/5 V level translation
High temperature operation: 105°C
High data rate: dc to 90 Mbps (NRZ)
Precise timing characteristics
2 ns maximum pulse width distortion
2 ns maximum channel-to-channel matching
High common-mode transient immunity: >25 kV/μs
Output enable function
16-lead SOIC wide body, RoHS-compliant package
Safety and regulatory approvals
UL recognition: 2500 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice #5A
VDE Certificate of Conformity
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12
VIORM = 560 V peak
The ADuM340x isolators provide four independent isolation
channels in a variety of channel configurations and data rates
(see the Ordering Guide). All models operate with the supply
voltage on either side ranging from 2.7 V to 5.5 V, providing
compatibility with lower voltage systems as well as enabling a
voltage translation functionality across the isolation barrier. The
ADuM340x isolators have a patented refresh feature that ensures dc
correctness in the absence of input logic transitions and during
power-up/power-down conditions.
In comparison to the ADuM140x isolators, the ADuM340x
isolators contain various circuit and layout changes to provide
increased capability relative to system-level IEC 61000-4-x testing
(ESD/burst/surge). The precise capability in these tests for either
the ADuM140x or ADuM340x products is strongly determined
by the design and layout of the user’s board or module. For more
information, see the AN-793 Application Note, ESD/Latch-Up
Considerations with iCoupler Isolation Products.
APPLICATIONS
General-purpose multichannel isolation
SPI/data converter isolation
RS-232/RS-422/RS-485 transceivers
Industrial field bus isolation
1 Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329.
FUNCTIONAL BLOCK DIAGRAMS
1
2
3
16
1
2
3
16
V
1
2
3
16
15
14
V
V
V
V
V
DD2
DD1
DD2
DD1
DD2
DD1
15 GND
15 GND
2
GND
V
GND
V
GND
V
GND
1
2
1
1
2
14
V
14
V
ENCODE
ENCODE
ENCODE
DECODE
DECODE
DECODE
DECODE
ENCODE
ENCODE
ENCODE
DECODE
DECODE
DECODE
DECODE
ENCODE
ENCODE
ENCODE
ENCODE
ENCODE
ENCODE
DECODE
DECODE
DECODE
DECODE
V
IA
IB
OA
IA
IB
OA
IA
IB
OA
V
V
V
4
5
13
V
4
5
13
V
4
5
13
12
V
OB
OB
OB
12
12
V
V
V
V
V
V
V
V
IC
OC
OC
IC
IC
OC
6
7
8
11
10
9
6
7
8
11
10
9
6
7
8
11
10
9
V
V
V
V
V
V
OD
ID
OD
ID
ID
OD
V
V
NC
GND
V
E1
E2
E1
E2
E2
GND
GND
GND
GND
2
GND
1
2
1
1
2
Figure 1. ADuM3400 Functional Block Diagram
Figure 2. ADuM3401 Functional Block Diagram
Figure 3. ADuM3402 Functional Block Diagram
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2006–2012 Analog Devices, Inc. All rights reserved.
ADuM3400/ADuM3401/ADuM3402
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ......................................................... 14
ESD Caution................................................................................ 14
Pin Configurations and Function Descriptions......................... 15
Typical Performance Characteristics ........................................... 18
Application Information................................................................ 20
PC Board Layout ........................................................................ 20
System-Level ESD Considerations and Enhancements ........ 20
Propagation Delay-Related Parameters................................... 20
DC Correctness and Magnetic Field Immunity........................... 20
Power Consumption .................................................................. 21
Insulation Lifetime..................................................................... 22
Outline Dimensions....................................................................... 23
Ordering Guide .......................................................................... 23
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics—5 V Operation................................ 3
Electrical Characteristics—3 V Operation................................ 6
Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V
Operation....................................................................................... 8
Package Characteristics ............................................................. 12
Regulatory Information............................................................. 12
Insulation and Safety-Related Specifications.......................... 12
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics ............................................................................ 13
Recommended Operating Conditions .................................... 13
REVISION HISTORY
2/12—Rev. A to Rev. B
Created Hyperlink for Safety and Regulatory Approvals
Entry in Features Section................................................................. 1
Change to PC Board Layout Section............................................ 20
6/07—Rev. 0 to Rev. A
Updated VDE Certification Throughout ...................................... 1
Changes to Features, General Description, Note 1, Figure 1,
Figure 2, and Figure 3....................................................................... 1
Changes to Regulatory Information Section .............................. 12
Changes to Table 7 and Figure 4 Caption.................................... 13
Added Table 10; Renumbered Sequentially ................................ 14
Added Insulation Lifetime Section .............................................. 22
Inserted Figure 21, Figure 22, and Figure 23 .............................. 22
Changes to Ordering Guide .......................................................... 23
3/06—Revision 0: Initial Version
Rev. B | Page 2 of 24
Data Sheet
ADuM3400/ADuM3401/ADuM3402
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION
All voltages are relative to their respective ground. 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply
over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V.
Table 1.
Parameter
Symbol
Min
Typ Max Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
IDDI (Q)
0.57 0.83 mA
0.29 0.35 mA
Output Supply Current per Channel, Quiescent IDDO (Q)
ADuM3400, Total Supply Current, Four Channels1
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
IDD1 (Q)
IDD2 (Q)
2.9
1.2
3.5 mA
1.9 mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (10)
IDD2 (10)
9.0
3.0
11.6 mA
5.5 mA
5 MHz logic signal freq.
5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current
VDD2 Supply Current
ADuM3401, Total Supply Current, Four Channels1
DC to 2 Mbps
IDD1 (90)
IDD2 (90)
72
19
100 mA
45 MHz logic signal freq.
45 MHz logic signal freq.
36
mA
VDD1 Supply Current
VDD2 Supply Current
IDD1 (Q)
IDD2 (Q)
2.5
1.6
3.2 mA
2.4 mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (10)
IDD2 (10)
7.4
4.4
10.6 mA
6.5 mA
5 MHz logic signal freq.
5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current
VDD2 Supply Current
ADuM3402, Total Supply Current, Four Channels1
DC to 2 Mbps
IDD1 (90)
IDD2 (90)
59
32
82
46
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
VDD1 or VDD2 Supply Current
10 Mbps (BRW and CRW Grades Only)
VDD1 or VDD2 Supply Current
90 Mbps (CRW Grade Only)
VDD1 or VDD2 Supply Current
For All Models
IDD1 (Q), IDD2 (Q)
IDD1 (10), IDD2 (10)
IDD1 (90), IDD2 (90)
2.0
6.0
51
2.8 mA
7.5 mA
DC to 1 MHz logic signal freq.
5 MHz logic signal freq.
62
mA
45 MHz logic signal freq.
Input Currents
IIA, IIB, IIC,
IID, IE1, IE2
VIH, VEH
VIL, VEL
VOAH, VOBH
VOCH, VODH
VOAL, VOBL
VOCL, VODL
−10
2.0
+0.01 +10 µA
V
0V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2
0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
,
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
0.8
V
V
V
V
V
V
,
(VDD1 or VDD2) − 0.1 5.0
(VDD1 or VDD2) − 0.4 4.8
0.0
IOx = −20 µA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 µA, VIx = VIxL
IOx = 400 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
Logic Low Output Voltages
,
0.1
0.04 0.1
0.2 0.4
Rev. B | Page 3 of 24
ADuM3400/ADuM3401/ADuM3402
Data Sheet
Parameter
Symbol
Min
Typ Max Unit
Test Conditions
SWITCHING SPECIFICATIONS
ADuM340xARW
Minimum Pulse Width2
Maximum Data Rate3
Propagation Delay4
Pulse Width Distortion, |tPLH − tPHL
Propagation Delay Skew5
Channel-to-Channel Matching6
ADuM340xBRW
Minimum Pulse Width2
Maximum Data Rate3
Propagation Delay4
Pulse Width Distortion, |tPLH − tPHL
Change vs. Temperature
Propagation Delay Skew5
PW
1000 ns
Mbps
100 ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
1
50
tPHL, tPLH
PWD
tPSK
65
4
|
|
40
50
50
ns
ns
ns
tPSKCD/OD
PW
100 ns
Mbps
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
10
20
tPHL, tPLH
PWD
32
5
50
3
4
ns
ps/°C
ns
ns
tPSK
tPSKCD
15
3
Channel-to-Channel Matching,
Codirectional Channels6
Channel-to-Channel Matching,
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels
Opposing-Directional Channels6
ADuM340xCRW
Minimum Pulse Width2
Maximum Data Rate3
PW
8.3
120
27
0.5
3
11.1 ns
Mbps
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
90
18
Propagation Delay4
tPHL, tPLH
PWD
32
2
4
Pulse Width Distortion, |tPLH − tPHL
Change vs. Temperature
Propagation Delay Skew5
Channel-to-Channel Matching,
Codirectional Channels6
|
ns
ps/°C
ns
ns
tPSK
tPSKCD
10
2
Channel-to-Channel Matching,
tPSKOD
5
ns
CL = 15 pF, CMOS signal levels
Opposing-Directional Channels6
For All Models
Output Disable Propagation Delay
(High/Low-to-High Impedance)
Output Enable Propagation Delay
(High Impedance-to-High/Low)
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity
at Logic High Output7
tPHZ, tPLH
tPZH, tPZL
6
6
8
8
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
VIx = VDD1/VDD2, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
tR/tF
|CMH|
2.5
35
ns
kV/µs
25
25
Common-Mode Transient Immunity
at Logic Low Output7
|CML|
35
kV/µs
transient magnitude = 800 V
Refresh Rate
fr
1.2
0.20
0.05
Mbps
mA/Mbps
mA/Mbps
Input Dynamic Supply Current per Channel8
IDDI (D)
Output Dynamic Supply Current per Channel8 IDDO (D)
Rev. B | Page 4 of 24
Data Sheet
ADuM3400/ADuM3401/ADuM3402
1 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM3400/ADuM3401/ADuM3402 channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Rev. B | Page 5 of 24
ADuM3400/ADuM3401/ADuM3402
Data Sheet
ELECTRICAL CHARACTERISTICS—3 V OPERATION
All voltages are relative to their respective ground. 2.7 V ≤ VDD1 ≤ 3.6 V, 2.7 V ≤ VDD2 ≤ 3.6 V; all minimum/maximum specifications apply
over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V.
Table 2.
Parameter
Symbol
Min
Typ Max Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
Output Supply Current per Channel, Quiescent
ADuM3400, Total Supply Current, Four Channels1
DC to 2 Mbps
IDDI (Q)
IDDO (Q)
0.31 0.49 mA
0.19 0.27 mA
VDD1 Supply Current
VDD2 Supply Current
IDD1 (Q)
IDD2 (Q)
1.6
0.7
2.1 mA
1.2 mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (10)
IDD2 (10)
4.8
1.8
7.1 mA
2.3 mA
5 MHz logic signal freq.
5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current
VDD2 Supply Current
ADuM3401, Total Supply Current, Four Channels1
DC to 2 Mbps
IDD1 (90)
IDD2 (90)
37
11
54
15
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
VDD1 Supply Current
VDD2 Supply Current
IDD1 (Q)
IDD2 (Q)
1.4
0.9
1.9 mA
1.5 mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (10)
IDD2 (10)
4.1
2.5
5.6 mA
3.3 mA
5 MHz logic signal freq.
5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current
VDD2 Supply Current
ADuM3402, Total Supply Current, Four Channels1
DC to 2 Mbps
IDD1 (90)
IDD2 (90)
31
17
44
24
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
VDD1 or VDD2 Supply Current
10 Mbps (BRW and CRW Grades Only)
VDD1 or VDD2 Supply Current
90 Mbps (CRW Grade Only)
VDD1 or VDD2 Supply Current
For All Models
IDD1 (Q), IDD2 (Q)
IDD1 (10), IDD2 (10)
IDD1 (90), IDD2 (90)
1.2
3.3
24
1.7 mA
4.4 mA
DC to 1 MHz logic signal freq.
5 MHz logic signal freq.
39
mA
45 MHz logic signal freq.
Input Currents
IIA, IIB, IIC,
IID, IE1, IE2
VIH, VEH
VIL, VEL
VOAH, VOBH
VOCH, VODH
VOAL, VOBL
−10
1.6
+0.01 +10 µA
V
0V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2
0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
,
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
0.4
V
V
V
V
V
V
,
(VDD1 or VDD2) − 0.1 3.0
(VDD1 or VDD2) − 0.4 2.8
0.0
IOx = −20 µA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 µA, VIx = VIxL
IOx = 400 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
Logic Low Output Voltages
,
0.1
0.04 0.1
VOCL, VODL
0.2
0.4
SWITCHING SPECIFICATIONS
ADuM340xARW
Minimum Pulse Width2
Maximum Data Rate3
Propagation Delay4
PW
1000 ns
Mbps
100 ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
1
50
tPHL, tPLH
75
Rev. B | Page 6 of 24
Data Sheet
ADuM3400/ADuM3401/ADuM3402
Parameter
Symbol
PWD
tPSK
Min
Typ Max Unit
Test Conditions
4
Pulse Width Distortion, |tPLH − tPHL
|
|
40
50
50
ns
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
Channel-to-Channel Matching6
ADuM340xBRW
tPSKCD/OD
Minimum Pulse Width2
Maximum Data Rate3
Propagation Delay4
Pulse Width Distortion, |tPLH − tPHL
Change vs. Temperature
Propagation Delay Skew5
Channel-to-Channel Matching,
Codirectional Channels6
PW
100 ns
Mbps
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
10
20
tPHL, tPLH
PWD
38
5
50
3
4
ns
ps/°C
ns
ns
tPSK
tPSKCD
22
3
Channel-to-Channel Matching,
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels
Opposing-Directional Channels6
ADuM340xCRW
Minimum Pulse Width2
Maximum Data Rate3
PW
8.3
120
34
0.5
3
11.1 ns
Mbps
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
90
20
Propagation Delay4
tPHL, tPLH
PWD
45
2
4
Pulse Width Distortion, |tPLH − tPHL
Change vs. Temperature
Propagation Delay Skew5
Channel-to-Channel Matching,
Codirectional Channels6
|
ns
ps/°C
ns
ns
tPSK
tPSKCD
16
2
Channel-to-Channel Matching,
tPSKOD
5
ns
CL = 15 pF, CMOS signal levels
Opposing-Directional Channels6
For All Models
Output Disable Propagation Delay
(High/Low-to-High Impedance)
Output Enable Propagation Delay
(High Impedance-to-High/Low)
tPHZ, tPLH
tPZH, tPZL
6
6
8
8
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%)
tR/tF
3
ns
Common-Mode Transient Immunity
at Logic High Output7
Common-Mode Transient Immunity
at Logic Low Output7
|CMH|
25
25
35
kV/µs
VIx = VDD1/VDD2, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
|CML|
fr
35
kV/µs
transient magnitude = 800 V
Refresh Rate
1.1
0.10
0.03
Mbps
mA/Mbps
mA/Mbps
Input Dynamic Supply Current per Channel8 IDDI (D)
Output Dynamic Supply Current per Channel8 IDDO (D)
1 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM3400/ADuM3401/ADuM3402 channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Rev. B | Page 7 of 24
ADuM3400/ADuM3401/ADuM3402
Data Sheet
ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION
All voltages are relative to their respective ground. 5 V/3 V operation: 4.5 V ≤ VDD1 ≤ 5.5 V, 2.7 V ≤ VDD2 ≤ 3.6 V; 3 V/5 V operation:
2.7 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted; all typical specifications are at TA = 25°C; VDD1 = 3.0 V, VDD2 = 5 V or VDD1 = 5 V, VDD2 = 3.0 V.
Table 3.
Parameter
Symbol Min
Typ
Max Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent IDDI (Q)
5 V/3 V Operation
3 V/5 V Operation
0.57
0.31
0.83 mA
0.49 mA
Output Supply Current per Channel, Quiescent
5 V/3 V Operation
IDDO (Q)
0.29
0.19
0.27 mA
0.35 mA
3 V/5 V Operation
ADuM3400, Total Supply Current, Four Channels1
DC to 2 Mbps
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD1 (Q)
2.9
1.6
3.5
2.1
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD2 (Q)
0.7
1.2
1.2
1.9
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
5 V/3 V Operation
IDD1 (10)
9.0
4.8
11.6 mA
5 MHz logic signal freq.
5 MHz logic signal freq.
3 V/5 V Operation
7.1
mA
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD2 (10)
1.8
3.0
2.3
5.5
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current
5 V/3 V Operation
IDD1 (90)
72
37
100 mA
45 MHz logic signal freq.
45 MHz logic signal freq.
3 V/5 V Operation
54
mA
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD2 (90)
11
19
15
36
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
ADuM3401, Total Supply Current, Four Channels1
DC to 2 Mbps
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD1 (Q)
2.5
1.4
3.2
1.9
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD2 (Q)
0.9
1.6
1.5
2.4
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
5 V/3 V Operation
IDD1 (10)
7.4
4.1
10.6 mA
5 MHz logic signal freq.
5 MHz logic signal freq.
3 V/5 V Operation
5.6
mA
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD2 (10)
2.5
4.4
3.3
6.5
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
Rev. B | Page 8 of 24
Data Sheet
ADuM3400/ADuM3401/ADuM3402
Parameter
Symbol Min
Typ
Max Unit
Test Conditions
90 Mbps (CRW Grade Only)
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD1 (90)
59
31
82
44
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD2 (90)
17
32
24
46
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
ADuM3402, Total Supply Current, Four Channels1
DC to 2 Mbps
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD1 (Q)
2.0
1.2
2.8
1.7
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD2 (Q)
1.2
2.0
1.7
2.8
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
5 V/3 V Operation
IDD1 (10)
6.0
3.3
7.5
4.4
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD2 (10)
3.3
6.0
4.4
7.5
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current
5 V/3 V Operation
IDD1 (90)
46
24
62
39
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD2 (90)
24
46
39
62
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
For All Models
Input Currents
IIA, IIB, IIC, −10
IID, IE1, IE2
+0.01
+10 μA
0 V ≤ VIA,VIB, VIC,VID ≤ VDD1 or VDD2
0 V ≤ VE1,VE2 ≤ VDD1 or VDD2
,
Logic High Input Threshold
5 V/3 V Operation
3 V/5 V Operation
VIH, VEH
2.0
1.6
V
V
Logic Low Input Threshold
5 V/3 V Operation
3 V/5 V Operation
VIL, VEL
0.8
0.4
V
V
V
Logic High Output Voltages
VOAH, VOBH, (VDD1 or VDD2) − (VDD1 or VDD2
)
IOx = −20 μA, VIx = VIxH
0.1
VOCH, VODH (VDD1 or VDD2) − (VDD1 or VDD2) −
V
IOx = −4 mA, VIx = VIxH
0.4
0.2
Logic Low Output Voltages
VOAL, VOBL
VOCL, VODL
,
0.0
0.04
0.2
0.1
0.1
0.4
V
V
V
IOx = 20 μA, VIx = VIxL
IOx = 400 μA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM340xARW
Minimum Pulse Width2
Maximum Data Rate3
PW
1000 ns
Mbps
100 ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
1
50
Propagation Delay4
tPHL, tPLH
PWD
tPSK
70
4
Pulse Width Distortion, |tPLH − tPHL
|
40
50
50
ns
ns
ns
Propagation Delay Skew5
Channel-to-Channel Matching6
tPSKCD/OD
Rev. B | Page 9 of 24
ADuM3400/ADuM3401/ADuM3402
Data Sheet
Parameter
Symbol Min
Typ
Max Unit
Test Conditions
ADuM340xBRW
Minimum Pulse Width2
PW
100 ns
Mbps
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
10
15
Propagation Delay4
tPHL, tPLH
PWD
35
5
50
3
ns
ns
4
Pulse Width Distortion, |tPLH − tPHL
Change vs. Temperature
Propagation Delay Skew5
Channel-to-Channel Matching,
Codirectional Channels6
|
ps/°C
ns
ns
tPSK
tPSKCD
22
3
Channel-to-Channel Matching,
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels
Opposing-Directional Channels6
ADuM340xCRW
Minimum Pulse Width2
Maximum Data Rate3
PW
8.3
120
30
0.5
3
11.1 ns
Mbps
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
90
20
Propagation Delay4
tPHL, tPLH
PWD
40
2
4
Pulse Width Distortion, |tPLH − tPHL
Change vs. Temperature
Propagation Delay Skew5
Channel-to-Channel Matching,
Codirectional Channels6
|
ns
ps/°C
ns
ns
tPSK
tPSKCD
14
2
Channel-to-Channel Matching,
tPSKOD
5
ns
CL = 15 pF, CMOS signal levels
Opposing-Directional Channels6
For All Models
Output Disable Propagation Delay
(High/Low-to-High Impedance)
Output Enable Propagation Delay
(High Impedance-to-High/Low)
Output Rise/Fall Time (10% to 90%)
5 V/3 V Operation
3 V/5 V Operation
Common-Mode Transient Immunity
at Logic High Output7
Common-Mode Transient Immunity
at Logic Low Output7
tPHZ, tPLH
tPZH, tPZL
tR/tF
6
6
8
8
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
3.0
2.5
35
ns
ns
kV/µs
|CMH|
|CML|
fr
25
25
VIx = VDD1/VDD2, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
35
kV/µs
transient magnitude = 800 V
Refresh Rate
5 V/3 V Operation
3 V/5 V Operation
Input Dynamic Supply Current per Channel8
5 V/3 V Operation
1.2
1.1
Mbps
Mbps
IDDI (D)
0.20
0.10
mA/Mbps
mA/Mbps
3 V/5 V Operation
Output Dynamic Supply Current per Channel8 IDDO (D)
5 V/3 V Operation
0.03
0.05
mA/Mbps
mA/Mbps
3 V/5 V Operation
Rev. B | Page 10 of 24
Data Sheet
ADuM3400/ADuM3401/ADuM3402
1 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM3400/ADuM3401/ADuM3402 channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Rev. B | Page 11 of 24
ADuM3400/ADuM3401/ADuM3402
Data Sheet
PACKAGE CHARACTERISTICS
Table 4.
Parameter
Symbol
RI-O
CI-O
CI
θJCI
Min
Typ
1012
2.2
4.0
33
Max
Unit
Ω
pF
pF
°C/W
°C/W
Test Conditions
Resistance (Input-to-Output)1
Capacitance (Input-to-Output)1
Input Capacitance2
f = 1 MHz
IC Junction-to-Case Thermal Resistance, Side 1
IC Junction-to-Case Thermal Resistance, Side 2
Thermocouple located at
center of package underside
θJCO
28
1 Device considered a 2-terminal device; Pin 1 to Pin 8 are shorted together and Pin 9 to Pin 16 are shorted together.
2 Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
The ADuM340x is approved by the organizations listed in Table 5. Refer to Table 10 and the Insulation Lifetime section for details
regarding recommended maximum working voltages for specific crossisolation waveforms and insulation levels.
Table 5.
UL
CSA
VDE
Recognized under
Approved under
CSA Component Acceptance Notice #5A
Certified according to DIN V VDE V 0884-10
(VDE V 0884-10): 2006-122
1577 component recognition program1
Double/reinforced insulation,
2500 V rms isolation voltage
Basic insulation per CSA 60950-1-03 and
IEC 60950-1, 800 V rms (1131 V peak)
maximum working voltage
Reinforced insulation, 560 V peak
Reinforced insulation per CSA 60950-1-03
and IEC 60950-1, 400 V rms (566 V peak)
maximum working voltage
File E214100
File 205078
File 2471900-4880-0001
1 In accordance with UL 1577, each ADuM340x is proof tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage detection limit = 5 µA).
2 In accordance with DIN V VDE V 0884-10, each ADuM340x is proof tested by applying an insulation test voltage ≥1050 V peak for 1 sec (partial discharge detection
limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval.
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 6.
Parameter
Symbol Value
Unit Conditions
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
2500
7.7 min
V rms 1-minute duration
L(I01)
L(I02)
mm
Measured from input terminals to output terminals,
shortest distance through air
Minimum External Tracking (Creepage)
8.1 min
mm
Measured from input terminals to output terminals,
shortest distance path along body
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Isolation Group
0.017 min mm
Insulation distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
CTI
>175
IIIa
V
Rev. B | Page 12 of 24
Data Sheet
ADuM3400/ADuM3401/ADuM3402
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
protective circuits. The * marking on packages denotes DIN V VDE V 0884-10 approval.
Table 7.
Description
Conditions
Symbol Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 400 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Input-to-Output Test Voltage, Method B1
I to IV
I to III
I to II
40/105/21
2
VIORM
VPR
560
1050
V peak
V peak
VIORM × 1.875 = VPR, 100% production test,
tm = 1 sec, partial discharge < 5 pC
Input-to-Output Test Voltage, Method A
VIORM × 1.6 = VPR, tm = 60 sec,
partial discharge < 5 pC
VPR
After Environmental Tests Subgroup 1
After Input and/or Safety Test Subgroup 2 and Subgroup 3
896
672
V peak
V peak
VIORM × 1.2 = VPR, tm = 60 sec,
partial discharge < 5 pC
Highest Allowable Overvoltage
Safety-Limiting Values
Transient overvoltage, tTR = 10 seconds
Maximum value allowed in the
event of a failure (see Figure 4)
VTR
4000
V peak
Case Temperature
Side 1 Current
Side 2 Current
TS
IS1
IS2
RS
150
265
335
>109
°C
mA
mA
Ω
Insulation Resistance at TS
VIO = 500 V
350
300
RECOMMENDED OPERATING CONDITIONS
Table 8.
Parameter
Rating
250
SIDE #2
Operating Temperature Range (TA)
−40°C to +105°C
2.7 V to 5.5 V
1.0 ms
1
200
Supply Voltages (VDD1, VDD2
)
Input Signal Rise and Fall Times
150
1 All voltages are relative to their respective ground. See the DC Correctness
and Magnetic Field Immunity section for information on immunity to
external magnetic fields.
SIDE #1
100
50
0
0
50
100
150
200
CASE TEMPERATURE (°C)
Figure 4. Thermal Derating Curve, Dependence of Safety-Limiting Values
with Case Temperature per DIN V VDE V 0884-10
Rev. B | Page 13 of 24
ADuM3400/ADuM3401/ADuM3402
ABSOLUTE MAXIMUM RATINGS
Data Sheet
Ambient temperature = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 9.
Parameter
Rating
Storage Temperature Range (TST)
−65°C to +150°C
Ambient Operating Temperature Range (TA) −40°C to +105°C
1
Supply Voltages (VDD1, VDD2
)
−0.5 V to +7.0 V
Input Voltage (VIA, VIB, VIC, VID, VE1, VE2)1, 2
Output Voltage (VOA, VOB, VOC, VOD)1, 2
Average Output Current per Pin3
Side 1 (IO1)
Side 2 (IO2)
Common-Mode Transients (CMH, CML)4
−0.5 V to VDD1 + 0.5 V
−0.5 V to VDDO + 0.5 V
ESD CAUTION
−18 mA to +18 mA
−22 mA to +22 mA
−100 kV/µs to
+100 kV/µs
1 All voltages are relative to their respective ground.
2 VDDI and VDDO refer to the supply voltages on the input and output sides of a
given channel, respectively. See the PC Board Layout section.
3 See Figure 4 for maximum rated current values for various temperatures.
4 Refers to common-mode transients across the insulation barrier. Common-
mode transients exceeding the Absolute Maximum Ratings can cause latch-
up or permanent damage.
Table 10. Maximum Continuous Working Voltage1
Parameter
Max
Unit
Constraint
AC Voltage, Bipolar Waveform
AC Voltage, Unipolar Waveform
Basic Insulation
Reinforced Insulation
DC Voltage
565
V peak
50-year minimum lifetime
1131
560
V peak
V peak
Maximum approved working voltage per IEC 60950-1
Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
Basic Insulation
Reinforced Insulation
1131
560
V peak
V peak
Maximum approved working voltage per IEC 60950-1
Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
1 Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.
Table 11. Truth Table (Positive Logic)
VIx Input1 VEx Input2 VDDI State1 VDDO State1 VOX Output1
Notes
H
L
x
x
x
x
H or NC
H or NC
L
H or NC
L
x
Powered
Powered
Powered
Unpowered Powered
Unpowered Powered
Powered
Powered
Powered
H
L
Z
H
Z
Outputs return to the input state within 1 µs of VDDI power restoration.
Powered
Unpowered Indeterminate Outputs return to the input state within 1 µs of VDDO power restoration
if VEx state is H or NC. Outputs return to high impedance state within
8 ns of VDDO power restoration if VEx state is L.
1 VIx and VOx refer to the input and output signals of a given channel (A, B, C, or D). VEx refers to the output enable signal on the same side as the VOx outputs. VDDI and
VDDO refer to the supply voltages on the input and output sides of the given channel, respectively.
2 In noisy environments, connecting VEx to an external logic high or low is recommended.
Rev. B | Page 14 of 24
Data Sheet
ADuM3400/ADuM3401/ADuM3402
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
1
2
3
4
5
6
7
8
16
V
DD2
DD1
*GND
15 GND *
1
IA
IB
IC
ID
2
V
V
V
V
14
13
12
11
10
9
V
V
V
V
V
OA
OB
OC
OD
E2
ADuM3400
TOP VIEW
(Not to Scale)
NC
*GND
GND *
1
2
NC = NO CONNECT
*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED AND CONNECTING BOTH TO
GND IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED AND
1
CONNECTING BOTH TO GND IS RECOMMENDED. IN NOISY ENVIRONMENTS,
2
CONNECTING OUTPUT ENABLES (PIN 7 FOR ADuM3401/ADuM3402 AND PIN 10
FOR ALL MODELS) TO AN EXTERNAL LOGIC HIGH OR LOW IS RECOMMENDED.
Figure 5. ADuM3400 Pin Configuration
Table 12. ADuM3400 Pin Function Descriptions
Pin No. Mnemonic Description
1
2, 8
3
VDD1
GND1
VIA
Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V.
Ground 1. Ground reference for Isolator Side 1.
Logic Input A.
4
VIB
Logic Input B.
5
VIC
Logic Input C.
6
VID
Logic Input D.
7
NC
No Connect.
9, 15
10
GND2
VE2
Ground 2. Ground reference for Isolator Side 2.
Output Enable 2. Active high logic input. VOA, VOB, VOC, and VOD outputs are enabled when VE2 is high or disconnected.
VOA, VOB, VOC, and VOD outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic
high or low is recommended.
11
12
13
14
16
VOD
VOC
VOB
VOA
VDD2
Logic Output D.
Logic Output C.
Logic Output B.
Logic Output A.
Supply Voltage for Isolator Side 2, 2.7 V to 5.5 V.
Rev. B | Page 15 of 24
ADuM3400/ADuM3401/ADuM3402
Data Sheet
V
1
2
3
4
5
6
7
8
16
V
DD2
DD1
*GND
15 GND *
1
IA
IB
IC
2
V
V
V
14
13
12
11
10
9
V
V
V
V
V
OA
OB
OC
ID
ADuM3401
TOP VIEW
(Not to Scale)
V
OD
V
E1
E2
*GND
GND *
1
2
*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED AND CONNECTING BOTH TO
GND IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED AND
1
CONNECTING BOTH TO GND IS RECOMMENDED. IN NOISY ENVIRONMENTS,
2
CONNECTING OUTPUT ENABLES (PIN 7 FOR ADuM3401/ADuM3402 AND PIN 10
FOR ALL MODELS) TO AN EXTERNAL LOGIC HIGH OR LOW IS RECOMMENDED.
Figure 6. ADuM3401 Pin Configuration
Table 13. ADuM3401 Pin Function Descriptions
Pin No. Mnemonic Description
1
2, 8
3
VDD1
GND1
VIA
Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V.
Ground 1. Ground reference for Isolator Side 1.
Logic Input A.
4
VIB
Logic Input B.
5
VIC
Logic Input C.
6
7
VOD
VE1
Logic Output D.
Output Enable 1. Active high logic input. VOD output is enabled when VE1 is high or disconnected. VOD is disabled when
VE1 is low. In noisy environments, connecting VE1 to an external logic high or low is recommended.
9, 15
10
GND2
VE2
Ground 2. Ground reference for Isolator Side 2.
Output Enable 2. Active high logic input. VOA, VOB, and VOC outputs are enabled when VE2 is high or disconnected.
VOA, VOB, and VOC outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic high
or low is recommended.
11
12
13
14
16
VID
Logic Input D.
Logic Output C.
Logic Output B.
Logic Output A.
VOC
VOB
VOA
VDD2
Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V.
Rev. B | Page 16 of 24
Data Sheet
ADuM3400/ADuM3401/ADuM3402
V
1
2
3
4
5
6
7
8
16
V
DD2
DD1
*GND
15 GND *
1
IA
IB
2
V
V
14
13
12
11
10
9
V
V
V
V
V
OA
OB
IC
ADuM3402
TOP VIEW
(Not to Scale)
V
V
OC
OD
ID
V
E1
E2
*GND
GND *
1
2
*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED AND CONNECTING BOTH TO
GND IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED AND
1
CONNECTING BOTH TO GND IS RECOMMENDED. IN NOISY ENVIRONMENTS,
2
CONNECTING OUTPUT ENABLES (PIN 7 FOR ADuM3401/ADuM3402 AND PIN 10
FOR ALL MODELS) TO AN EXTERNAL LOGIC HIGH OR LOW IS RECOMMENDED.
Figure 7. ADuM3402 Pin Configuration
Table 14. ADuM3402 Pin Function Descriptions
Pin No. Mnemonic Description
1
2, 8
3
VDD1
GND1
VIA
Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V.
Ground 1. Ground reference for Isolator Side 1.
Logic Input A.
4
VIB
Logic Input B.
5
6
7
VOC
VOD
VE1
Logic Output C.
Logic Output D.
Output Enable 1. Active high logic input. VOC and VOD outputs are enabled when VE1 is high or disconnected.
V
OC and VOD outputs are disabled when VE1 is low. In noisy environments, connecting VE1 to an external logic high or
low is recommended.
9, 15
10
GND2
VE2
Ground 2. Ground reference for Isolator Side 2.
Output Enable 2. Active high logic input. VOA and VOB outputs are enabled when VE2 is high or disconnected.
V
OA and VOB outputs are disabled when VE2 is low. In noisy environments, connecting VE2 to an external logic high or
low is recommended.
11
12
13
14
16
VID
VIC
VOB
VOA
VDD2
Logic Input D.
Logic Input C.
Logic Output B.
Logic Output A.
Supply Voltage for Isolator Side 2, 2.7 V to 5.5 V.
Rev. B | Page 17 of 24
ADuM3400/ADuM3401/ADuM3402
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
20
80
60
40
15
5V
10
5V
3V
3V
5
20
0
0
0
20
40
60
80
100
0
20
40
60
80
100
DATA RATE (Mbps)
DATA RATE (Mbps)
Figure 8. Typical Input Supply Current per Channel vs. Data Rate (No Load)
Figure 11. Typical ADuM3400 VDD1 Supply Current vs. Data Rate
for 5 V and 3 V Operation
20
80
60
40
15
10
5
20
5V
5V
3V
3V
0
0
0
20
40
60
80
100
0
20
40
60
80
100
DATA RATE (Mbps)
DATA RATE (Mbps)
Figure 9. Typical Output Supply Current per Channel vs. Data Rate (No Load)
Figure 12. Typical ADuM3400 VDD2 Supply Current vs. Data Rate
for 5 V and 3 V Operation
20
80
15
60
10
40
5V
5V
5
20
3V
3V
0
0
0
20
40
60
80
100
0
20
40
60
80
100
DATA RATE (Mbps)
DATA RATE (Mbps)
Figure 10. Typical Output Supply Current per Channel vs. Data Rate
(15 pF Output Load)
Figure 13. Typical ADuM3401 VDD1 Supply Current vs. Data Rate
for 5 V and 3 V Operation
Rev. B | Page 18 of 24
Data Sheet
ADuM3400/ADuM3401/ADuM3402
40
35
30
25
80
60
40
20
3V
5V
5V
3V
0
0
–50
–25
0
25
50
75
100
20
40
60
80
100
TEMPERATURE (°C)
DATA RATE (Mbps)
Figure 14. Typical ADuM3401 VDD2 Supply Current vs. Data Rate
for 5 V and 3 V Operation
Figure 16. Propagation Delay vs. Temperature, C Grade
80
60
40
5V
20
3V
0
0
20
40
60
80
100
DATA RATE (Mbps)
Figure 15. Typical ADuM3402 VDD1 or VDD2 Supply Current vs. Data Rate
for 5 V and 3 V Operation
Rev. B | Page 19 of 24
ADuM3400/ADuM3401/ADuM3402
Data Sheet
APPLICATION INFORMATION
PC BOARD LAYOUT
While the ADuM340x improve system-level ESD reliability,
they are no substitute for a robust system-level design. See the
AN-793 application note, ESD/Latch-Up Considerations with
iCoupler Isolation Products for detailed recommendations on
board layout and system-level design.
The ADuM340x digital isolator requires no external interface
circuitry for the logic interfaces. Power supply bypassing is
strongly recommended at the input and output supply pins (see
Figure 17). Bypass capacitors are most conveniently connected
between Pin 1 and Pin 2 for VDD1 and between Pin 15 and
Pin 16 for VDD2. The capacitor value should be between 0.01 μF
and 0.1 μF. The total lead length between both ends of the
capacitor and the input power supply pin should not exceed
20 mm. Bypassing between Pin 1 and Pin 8 and between Pin 9
and Pin 16 should also be considered unless the ground pair on
each package side is connected close to the package.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propagation
delay to a logic low output can differ from the propagation
delay to a logic high.
INPUT (V
)
50%
Ix
V
GND
V
DD1
DD2
GND
tPLH
tPHL
1
IA
IB
2
V
V
V
V
V
V
V
OA
OB
OUTPUT (V
)
50%
Ox
V
V
IC/OC
ID/OD
OC/IC
OD/ID
E2
Figure 18. Propagation Delay Parameters
V
E1
GND
GND
1
2
Pulse width distortion is the maximum difference between
these two propagation delay values and is an indication of how
accurately the input signal’s timing is preserved.
Figure 17. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, care
should be taken to ensure that board coupling across the isolation
barrier is minimized. Furthermore, the board layout should be
designed such that any coupling that does occur equally affects
all pins on a given component side. Failure to ensure this could
cause voltage differentials between pins exceeding the Absolute
Maximum Ratings of the device, thereby leading to latch-up or
permanent damage.
Channel-to-channel matching refers to the maximum amount
the propagation delay differs between channels within a single
ADuM340x component.
Propagation delay skew refers to the maximum amount the
propagation delay differs between multiple ADuM340x
components operating under the same conditions.
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
See the AN-1109 Application Note for board layout guidelines.
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent to the decoder via the transformer.
The decoder is bistable and is, therefore, either set or reset by
the pulses, indicating input logic transitions. In the absence of
logic transitions at the input for more than ~1 μs, a periodic set
of refresh pulses indicative of the correct input state are sent to
ensure dc correctness at the output. If the decoder receives no
internal pulses of more than about 5 μs, the input side is
assumed to be unpowered or nonfunctional, in which case the
isolator output is forced to a default state (see Table 11) by the
watchdog timer circuit.
SYSTEM-LEVEL ESD CONSIDERATIONS AND
ENHANCEMENTS
System-level ESD reliability (for example, per IEC 61000-4-x) is
highly dependent on system design, which varies widely by
application. The ADuM340x incorporate many enhancements
to make ESD reliability less dependent on system design. The
enhancements include:
ESD protection cells added to all input/output interfaces.
Key metal trace resistances reduced using wider geometry
and paralleling of lines with vias.
The limitation on the magnetic field immunity of the ADuM340x
is set by the condition in which induced voltage in the receiving
coil of the transformer is sufficiently large to either falsely set or
reset the decoder. The following analysis defines the conditions
under which this can occur. The 3 V operating condition of the
ADuM340x is examined because it represents the most
susceptible mode of operation.
The SCR effect inherent in CMOS devices minimized by
use of guarding and isolation technique between PMOS
and NMOS devices.
Areas of high electric field concentration eliminated using
45° corners on metal traces.
Supply pin overvoltage prevented with larger ESD clamps
between each supply pin and its respective ground.
Rev. B | Page 20 of 24
Data Sheet
ADuM3400/ADuM3401/ADuM3402
1000
100
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus
establishing a 0.5 V margin in which induced voltages can be
tolerated. The voltage induced across the receiving coil is given by
DISTANCE = 1m
2
10
1
V = (−dβ/dt)∑∏rn ; N = 1, 2, … , N
DISTANCE = 100mm
DISTANCE = 5mm
where:
β is magnetic flux density (gauss).
N is the number of turns in the receiving coil.
rn is the radius of the nth turn in the receiving coil (cm).
0.1
0.01
Given the geometry of the receiving coil in the ADuM340x and
an imposed requirement that the induced voltage be at most
50% of the 0.5 V margin at the decoder, a maximum allowable
magnetic field is calculated as shown in Figure 19.
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 20. Maximum Allowable Current
for Various Current-to-ADuM340x Spacings
100
Note that at combinations of strong magnetic field and high
frequency, any loops formed by printed circuit board traces
could induce error voltages sufficiently large enough to trigger
the thresholds of succeeding circuitry. Care should be taken in
the layout of such traces to avoid this possibility.
10
1
POWER CONSUMPTION
0.1
The supply current at a given channel of the ADuM340x
isolator is a function of the supply voltage, the channel’s data
rate, and the channel’s output load.
0.01
0.001
For each input channel, the supply current is given by
1k
10k
100k
1M
10M
100M
I
DDI = IDDI (Q)
f ≤ 0.5 fr
f > 0.5 fr
MAGNETIC FIELD FREQUENCY (Hz)
IDDI = IDDI (D) × (2f − fr) + IDDI (Q)
Figure 19. Maximum Allowable External Magnetic Flux Density
For each output channel, the supply current is given by
IDDO = IDDO (Q) f ≤ 0.5 fr
DDO = (IDDO (D) + (0.5 × 10−3) × CL × VDDO) × (2f − fr) + IDDO (Q)
f > 0.5 fr
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kgauss induces a
voltage of 0.25 V at the receiving coil, which is about 50% of the
sensing threshold and does not cause a faulty output transition.
Similarly, if such an event were to occur during a transmitted
pulse (and was of the worst-case polarity), it would reduce the
received pulse from >1.0 V to 0.75 V—still well above the 0.5 V
sensing threshold of the decoder.
I
where:
DDI (D), IDDO (D) are the input and output dynamic supply currents
I
per channel (mA/Mbps).
CL is the output load capacitance (pF).
The preceding magnetic flux density values correspond to
specific current magnitudes at given distances from the
ADuM340x transformers. Figure 20 expresses these allowable
current magnitudes as a function of frequency for selected
distances. As shown, the ADuM340x is extremely immune and
can be affected only by extremely large currents operated at
high frequency very close to the component. For the 1 MHz
example noted, one would have to place a 0.5 kA current 5 mm
away from the ADuM340x to affect the operation of the
component.
VDDO is the output supply voltage (V).
f is the input logic signal frequency (MHz); it is half of the input
data rate expressed in units of Mbps.
fr is the input stage refresh rate (Mbps).
I
DDI (Q), IDDO (Q) are the specified input and output quiescent
supply currents (mA).
Rev. B | Page 21 of 24
ADuM3400/ADuM3401/ADuM3402
Data Sheet
To calculate the total IDD1 and IDD2 supply current, the supply
currents for each input and output channel corresponding to
In the case of unipolar ac or dc voltage, the stress on the
insulation is significantly lower, which allows operation at
higher working voltages while still achieving a 50-year service
life. The working voltages listed in Table 10 can be applied while
maintaining the 50-year minimum lifetime provided the voltage
conforms to either the unipolar ac or dc voltage cases. Any cross
insulation voltage waveform that does not conform to Figure 22 or
Figure 23 should be treated as a bipolar ac waveform and its
peak voltage should be limited to the 50-year lifetime voltage
value listed in Table 10.
V
DD1 and VDD2 are calculated and totaled. Figure 8 provides the
per-channel input supply current as a function of the data rate.
Figure 9 and Figure 10 provide the per-channel supply output
current as a function of the data rate for an unloaded output
condition and for a 15 pF output condition, respectively. Figure 11
through Figure 15 provide the total VDD1 and VDD2 supply current
as a function of the data rate for ADuM3400/ADuM3401/
ADuM3402 channel configurations.
Note that the voltage presented in Figure 22 is shown as
sinusoidal for illustration purposes only. It is meant to represent
any voltage waveform varying between 0 V and some limiting
value. The limiting value can be positive or negative, but the
voltage cannot cross 0 V.
INSULATION LIFETIME
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of
the voltage waveform applied across the insulation. In addition
to the testing performed by the regulatory agencies, Analog
Devices carries out an extensive set of evaluations to determine
the lifetime of the insulation structure within the ADuM340x.
RATED PEAK VOLTAGE
0V
Figure 21. Bipolar AC Waveform
Analog Devices performs accelerated life testing using voltage
levels higher than the rated continuous working voltage.
Acceleration factors for several operating conditions are
determined. These factors allow calculation of the time to
failure at the actual working voltage. The values shown in
Figure 21 summarize the peak voltage for 50 years of service life
for a bipolar ac operating condition, and the maximum
CSA/VDE approved working voltages. In many cases, the
approved working voltage is higher than the 50-year service life
voltage. Operation at these high working voltages can lead to
shortened insulation life in some cases.
RATED PEAK VOLTAGE
0V
Figure 22. Unipolar AC Waveform
RATED PEAK VOLTAGE
The insulation lifetime of the ADuM340x depends on the
voltage waveform type imposed across the isolation barrier. The
iCoupler insulation structure degrades at different rates
depending on whether the waveform is bipolar ac, unipolar ac,
or dc. Figure 21, Figure 22, and Figure 23 illustrate these
different isolation voltage waveforms.
0V
Figure 23. DC Waveform
Bipolar ac voltage is the most stringent environment. The goal
of a 50-year operating lifetime under the ac bipolar condition
determines the recommended maximum working voltage of
Analog Devices.
Rev. B | Page 22 of 24
Data Sheet
ADuM3400/ADuM3401/ADuM3402
OUTLINE DIMENSIONS
10.50 (0.4134)
10.10 (0.3976)
16
1
9
8
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
10.00 (0.3937)
0.75 (0.0295)
45°
1.27 (0.0500)
BSC
2.65 (0.1043)
0.25 (0.0098)
2.35 (0.0925)
0.30 (0.0118)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 24. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body (RW-16)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Number Number Maximum Maximum
of Inputs, of Inputs, Data Rate Propagation Pulse Width
VDD1 Side VDD2 Side (Mbps) Delay, 5 V (ns) Distortion (ns) Range
Maximum
Temperature
Package
Package Description Option
Model1, 2
ADuM3400ARWZ
ADuM3400BRWZ
ADuM3400CRWZ
ADuM3401ARWZ
ADuM3401BRWZ
ADuM3401CRWZ
ADuM3402ARWZ
ADuM3402BRWZ
ADuM3402CRWZ
4
4
4
3
3
3
2
2
2
0
0
0
1
1
1
2
2
2
1
100
50
32
40
3
2
−40°C to +105°C 16-Lead SOIC_W
−40°C to +105°C 16-Lead SOIC_W
−40°C to +105°C 16-Lead SOIC_W
−40°C to +105°C 16-Lead SOIC_W
−40°C to +105°C 16-Lead SOIC_W
−40°C to +105°C 16-Lead SOIC_W
−40°C to +105°C 16-Lead SOIC_W
−40°C to +105°C 16-Lead SOIC_W
−40°C to +105°C 16-Lead SOIC_W
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
10
90
1
10
90
1
100
50
32
40
3
2
100
50
32
40
3
2
10
90
1 Z = RoHS Compliant Part.
2 Tape and reel are available. The addition of an -RL suffix designates a 13” (1,000 units) tape-and-reel option.
Rev. B | Page 23 of 24
ADuM3400/ADuM3401/ADuM3402
NOTES
Data Sheet
©2006–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05985-0-2/12(B)
Rev. B | Page 24 of 24
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