ADSP-2185L_技术文档

a

DSP Microcomputer

ADSP-2185L

FEATURES

FUNCTIONAL BLOCK DIAGRAM

PERFORMANCE

19 ns Instruction Cycle Time @ 3.3 Volts, 52 MIPS

Sustained Performance

Single-Cycle Instruction Execution

Single-Cycle Context Switch

POWER-DOWN

CONTROL

FULL MEMORY

MODE

MEMORY

DATA ADDRESS

GENERATORS

PROGRAMMABLE

EXTERNAL

ADDRESS

BUS

PROGRAM

SEQUENCER

16K

؋

24 PM

8K

؋

24 OVERLAY 1

16K

؋

16 DM

I/O

AND

FLAGS

8K

؋

16 OVERLAY 1

8K

؋

16 OVERLAY 2

(

)

(

8K

؋

24 OVERLAY 2

DAG 2

DAG 1

)

EXTERNAL

DATA

3-Bus Architecture Allows Dual Operand Fetches in

Every Instruction Cycle

Multifunction Instructions

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

BUS

BYTE DMA

CONTROLLER

PROGRAM MEMORY DATA

DATA MEMORY DATA

Power-Down Mode Featuring Low CMOS Standby

Power Dissipation with 400 Cycle Recovery from

Power-Down Condition

OR

EXTERNAL

DATA

BUS

Low Power Dissipation in Idle Mode

SERIAL PORTS

SPORT 0 SPORT 1

ARITHMETIC UNITS

ALU SHIFTER

TIMER

INTERNAL

DMA

PORT

MAC

INTEGRATION

ADSP-2100 Family Code Compatible, with Instruction

Set Extensions

ADSP-2100 BASE

ARCHITECTURE

HOST MODE

80K Bytes of On-Chip RAM, Configured as 16K Words

Program Memory RAM and 16K Words

Data Memory RAM

Dual Purpose Program Memory for Instruction and Data

Storage

Independent ALU, Multiplier/Accumulator and Barrel

Shifter Computational Units

Two Independent Data Address Generators

Powerful Program Sequencer Provides Zero Overhead

Looping Conditional Instruction Execution

Programmable 16-Bit Interval Timer with Prescaler

100-Lead LQFP

GENERAL NOTE

This data sheet represents specifications for the ADSP-2185L

3.3 V processor.

GENERAL DESCRIPTION

The ADSP-2185L is a single-chip microcomputer optimized for

digital signal processing (DSP) and other high speed numeric

processing applications.

SYSTEM INTERFACE

The ADSP-2185L combines the ADSP-2100 family base archi-

tecture (three computational units, data address generators and

a program sequencer) with two serial ports, a 16-bit internal

DMA port, a byte DMA port, a programmable timer, Flag I/O,

extensive interrupt capabilities and on-chip program and data

memory.

16-Bit Internal DMA Port for High Speed Access to

On-Chip Memory (Mode Selectable)

4 MByte Memory Interface for Storage of Data Tables

and Program Overlays (Mode Selectable)

8-Bit DMA to Byte Memory for Transparent Program

and Data Memory Transfers (Mode Selectable)

I/O Memory Interface with 2048 Locations Supports

Parallel Peripherals (Mode Selectable)

Programmable Memory Strobe and Separate I/O Memory

Space Permits “Glueless” System Design

Programmable Wait State Generation

Two Double-Buffered Serial Ports with Companding

Hardware and Automatic Data Buffering

Automatic Booting of On-Chip Program Memory from

Byte-Wide External Memory, e.g., EPROM, or

Through Internal DMA Port

Six External Interrupts

13 Programmable Flag Pins Provide Flexible System

Signaling

UART Emulation through Software SPORT Reconfiguration

ICE-Port™ Emulator Interface Supports Debugging in

Final Systems

The ADSP-2185L integrates 80K bytes of on-chip memory

configured as 16K words (24-bit) of program RAM, and 16K

words (16-bit) of data RAM. Power-down circuitry is also pro-

vided to meet the low power needs of battery operated portable

equipment. The ADSP-2185L is available in 100-lead LQFP

package.

In addition, the ADSP-2185L supports instructions which

include bit manipulations—bit set, bit clear, bit toggle, bit test—

ALU constants, multiplication instruction (x squared), biased

rounding, result free ALU operations, I/O memory transfers and

global interrupt masking, for increased flexibility.

Fabricated in a high speed, low power, CMOS process, the

ADSP-2185L operates with a 19 ns instruction cycle time. Ev-

ery instruction can execute in a single processor cycle.

ICE-Port is a trademark of Analog Devices, Inc.

REV. A

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

ADSP-2185L

The ADSP-2185L’s flexible architecture and comprehensive in-

struction set allow the processor to perform multiple operations

in parallel. In one processor cycle the ADSP-2185L can:

• Registers and memory values can be examined and altered

• PC upload and download functions

• Instruction-level emulation of program booting and execution

• Complete assembly and disassembly of instructions

• C source-level debugging

• Generate the next program address

• Fetch the next instruction

• Perform one or two data moves

• Update one or two data address pointers

• Perform a computational operation

See “Designing An EZ-ICE-Compatible Target System” in the

ADSP-2100 Family EZ-Tools Manual (ADSP-2181 sections) as

well as the Designing an EZ-ICE Compatible System section of

this data sheet for the exact specifications of the EZ-ICE target

board connector.

This takes place while the processor continues to:

• Receive and transmit data through the two serial ports

• Receive or transmit data through the internal DMA port

• Receive or transmit data through the byte DMA port

• Decrement timer

Additional Information

This data sheet provides a general overview of ADSP-2185L

functionality. For additional information on the architecture and

instruction set of the processor, see the ADSP-2100 Family

User’s Manual, Third Edition. For more information about the

development tools, refer to the ADSP-2100 Family Develop-

ment Tools Data Sheet.

DEVELOPMENT SYSTEM

The ADSP-2100 Family Development Software, a complete set

of tools for software and hardware system development, sup-

ports the ADSP-2185L. The System Builder provides a high

level method for defining the architecture of systems under de-

velopment. The Assembler has an algebraic syntax that is easy

to program and debug. The Linker combines object files into an

executable file. The Simulator provides an interactive instruc-

tion-level simulation with a reconfigurable user interface to dis-

play different portions of the hardware environment.

ARCHITECTURE OVERVIEW

The ADSP-2185L instruction set provides flexible data moves

and multifunction (one or two data moves with a computation)

instructions. Every instruction can be executed in a single pro-

cessor cycle. The ADSP-2185L assembly language uses an alge-

braic syntax for ease of coding and readability. A comprehensive

set of development tools supports program development.

A PROM Splitter generates PROM programmer compatible

files. The C Compiler, based on the Free Software Foundation’s

GNU C Compiler, generates ADSP-2185L assembly source

code. The source code debugger allows programs to be cor-

rected in the C environment. The Runtime Library includes over

100 ANSI-standard mathematical and DSP-specific functions.

POWER-DOWN

CONTROL

FULL MEMORY

MODE

MEMORY

DATA ADDRESS

PROGRAMMABLE

EXTERNAL

ADDRESS

BUS

PROGRAM

SEQUENCER

GENERATORS

16K

؋

24 PM

16K

؋

16 DM

I/O

AND

8K

؋

24 OVERLAY 1

8K

؋

16 OVERLAY 1

8K

؋

16 OVERLAY 2

FLAGS

(

)

(

8K

؋

24 OVERLAY 2

DAG 2

DAG 1

)

EXTERNAL

DATA

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

The EZ-KIT Lite is a hardware/software kit offering a complete

development environment for the entire ADSP-21xx family: an

ADSP-218x based evaluation board with PC monitor software

plus Assembler, Linker, Simulator, and PROM Splitter soft-

ware. The ADSP-218x EZ-KIT Lite is a low cost, easy to use

hardware platform on which you can quickly get started with

your DSP software design. The EZ-KIT Lite includes the fol-

lowing features:

BUS

BYTE DMA

CONTROLLER

PROGRAM MEMORY DATA

DATA MEMORY DATA

OR

EXTERNAL

DATA

BUS

SERIAL PORTS

SPORT 0 SPORT 1

ARITHMETIC UNITS

ALU SHIFTER

TIMER

INTERNAL

DMA

PORT

MAC

ADSP-2100 BASE

ARCHITECTURE

HOST MODE

• 33 MHz ADSP-218x

• Full 16-bit Stereo Audio I/O with AD1847 SoundPort^®Codec

• RS-232 Interface to PC with Windows 3.1 Control Software

• EZ-ICE^®Connector for Emulator Control

• DSP Demo Programs

Figure 1. Functional Block Diagram

Figure 1 is an overall block diagram of the ADSP-2185L. The

processor contains three independent computational units: the

ALU, the multiplier/accumulator (MAC) and the shifter. The

computational units process 16-bit data directly and have provi-

sions to support multiprecision computations. The ALU per-

forms a standard set of arithmetic and logic operations; division

primitives are also supported. The MAC performs single-cycle

multiply, multiply/add and multiply/subtract operations with

40 bits of accumulation. The shifter performs logical and arith-

metic shifts, normalization, denormalization and derive expo-

nent operations.

The ADSP-218x EZ-ICE Emulator aids in the hardware debug-

ging of ADSP-2185L system. The emulator consists of hard-

ware, host computer resident software and the target board

connector. The ADSP-2185L integrates on-chip emulation sup-

port with a 14-pin ICE-Port interface. This interface provides a

simpler target board connection requiring fewer mechanical

clearance considerations than other ADSP-2100 Family

EZ-ICEs. The ADSP-2185L device need not be removed from

the target system when using the EZ-ICE, nor are any adapters

needed. Due to the small footprint of the EZ-ICE connector, emu-

lation can be supported in final board designs.

The shifter can be used to efficiently implement numeric for-

mat control including multiword and block floating-point

representations.

The EZ-ICE performs a full range of functions, including:

The internal result (R) bus connects the computational units so

that the output of any unit may be the input of any unit on the

next cycle.

• In-target operation

• Up to 20 breakpoints

• Single-step or full-speed operation

EZ-ICE and SoundPort are registered trademarks of Analog Devices, Inc.

REV. A

–2–

ADSP-2185L

A powerful program sequencer and two dedicated data address

generators ensure efficient delivery of operands to these computa-

tional units. The sequencer supports conditional jumps, subroutine

calls and returns in a single cycle. With internal loop counters and

loop stacks, the ADSP-2185L executes looped code with zero over-

head; no explicit jump instructions are required to maintain loops.

The ADSP-2185L provides up to 13 general-purpose flag pins.

The data input and output pins on SPORT1 can be alternatively

configured as an input flag and an output flag. In addition, there

are eight flags that are programmable as inputs or outputs and

three flags that are always outputs.

A programmable interval timer generates periodic interrupts. A

16-bit count register (TCOUNT) is decremented every n pro-

cessor cycle, where n is a scaling value stored in an 8-bit register

(TSCALE). When the value of the count register reaches zero,

an interrupt is generated and the count register is reloaded from

a 16-bit period register (TPERIOD).

Two data address generators (DAGs) provide addresses for

simultaneous dual operand fetches (from data memory and pro-

gram memory). Each DAG maintains and updates four address

pointers. Whenever the pointer is used to access data (indirect

addressing), it is post-modified by the value of one of four pos-

sible modify registers. A length value may be associated with

each pointer to implement automatic modulo addressing for

circular buffers.

Serial Ports

The ADSP-2185L incorporates two complete synchronous se-

rial ports (SPORT0 and SPORT1) for serial communications

and multiprocessor communication.

Efficient data transfer is achieved with the use of five internal

buses:

Here is a brief list of the capabilities of the ADSP-2185L

SPORTs. For additional information on Serial Ports, refer to

the ADSP-2100 Family User’s Manual, Third Edition.

• Program Memory Address (PMA) Bus

• Program Memory Data (PMD) Bus

• Data Memory Address (DMA) Bus

• Data Memory Data (DMD) Bus

• Result (R) Bus

• SPORTs are bidirectional and have a separate, double-

buffered transmit and receive section.

• SPORTs can use an external serial clock or generate their

own serial clock internally.

The two address buses (PMA and DMA) share a single external

address bus, allowing memory to be expanded off-chip, and the

two data buses (PMD and DMD) share a single external data

bus. Byte memory space and I/O memory space also share the

external buses.

• SPORTs have independent framing for the receive and trans-

mit sections. Sections run in a frameless mode or with frame

synchronization signals internally or externally generated.

Frame sync signals are active high or inverted, with either of

two pulsewidths and timings.

Program memory can store both instructions and data, permit-

ting the ADSP-2185L to fetch two operands in a single cycle,

one from program memory and one from data memory. The

ADSP-2185L can fetch an operand from program memory and

the next instruction in the same cycle.

• SPORTs support serial data word lengths from 3 to 16 bits

and provide optional A-law and µ-law companding according

to CCITT recommendation G.711.

In lieu of the address and data bus for external memory connec-

tion, the ADSP-2185L may be configured for 16-bit Internal

DMA port (IDMA port) connection to external systems. The

IDMA port is made up of 16 data/address pins and five control

pins. The IDMA port provides transparent, direct access to the

DSPs on-chip program and data RAM.

• SPORT receive and transmit sections can generate unique in-

terrupts on completing a data word transfer.

• SPORTs can receive and transmit an entire circular buffer of

data with only one overhead cycle per data word. An interrupt

is generated after a data buffer transfer.

• SPORT0 has a multichannel interface to selectively receive

and transmit a 24- or 32-word, time-division multiplexed,

serial bitstream.

An interface to low cost byte-wide memory is provided by the

Byte DMA port (BDMA port). The BDMA port is bidirectional

and can directly address up to four megabytes of external RAM

or ROM for off-chip storage of program overlays or data tables.

• SPORT1 can be configured to have two external interrupts

(IRQ0 and IRQ1) and the Flag In and Flag Out signals. The

internally generated serial clock may still be used in this

configuration.

The byte memory and I/O memory space interface supports slow

memories and I/O memory-mapped peripherals with program-

mable wait state generation. External devices can gain control of

external buses with bus request/grant signals (BR, BGH, and BG).

One execution mode (Go Mode) allows the ADSP-2185L to con-

tinue running from on-chip memory. Normal execution mode re-

quires the processor to halt while buses are granted.

PIN DESCRIPTIONS

The ADSP-2185L is available in a 100-lead LQFP package. In

order to maintain maximum functionality and reduce package

size and pin count, some serial port, programmable flag, inter-

rupt and external bus pins have dual, multiplexed functionality.

The external bus pins are configured during RESET only,

while serial port pins are software configurable during program

execution. Flag and interrupt functionality is retained concur-

rently on multiplexed pins. In cases where pin functionality is

reconfigurable, the default state is shown in plain text; alternate

functionality is shown in italics. See Common-Mode Pin

Descriptions.

The ADSP-2185L can respond to eleven interrupts. There can

be up to six external interrupts (one edge-sensitive, two level-

sensitive and three configurable) and seven internal interrupts

generated by the timer, the serial ports (SPORTs), the Byte

DMA port and the power-down circuitry. There is also a master

RESET signal. The two serial ports provide a complete synchro-

nous serial interface with optional companding in hardware and a

wide variety of framed or frameless data transmit and receive

modes of operation.

Each port can generate an internal programmable serial clock or

accept an external serial clock.

REV. A

–3–

ADSP-2185L

Memory Interface Pins

Common-Mode Pin Descriptions

The ADSP-2185L processor can be used in one of two modes,

Full Memory Mode, which allows BDMA operation with full

external overlay memory and I/O capability, or Host Mode,

which allows IDMA operation with limited external addressing

capabilities. The operating mode is determined by the state of

the Mode C pin during RESET and cannot be changed while

the processor is running. See tables for Full Memory Mode Pins

and Host Mode Pins for descriptions.

# of Input/

Name(s) Pins Output Function

RESET

BR

BG

BGH

DMS

PMS

IOMS

BMS

CMS

RD

WR

IRQ2/

PF7

IRQL1/

PF6

1

I

Processor Reset Input

Bus Request Input

Bus Grant Output

O

Bus Grant Hung Output

Data Memory Select Output

Program Memory Select Output

Memory Select Output

Byte Memory Select Output

Combined Memory Select Output

Memory Read Enable Output

Memory Write Enable Output

Full Memory Mode Pins (Mode C = 0)

# of Input/

Name(s) Pins Output Function

A13:0

D23:0

14

24

O

Address Output Pins for Program,

Data, Byte and I/O Spaces

I/O

Data I/O Pins for Program, Data,

Byte and I/O Spaces (8 MSBs are

also used as Byte Memory addresses)

I

Edge- or Level-Sensitive Interrupt

I/O

Request.¹Programmable I/O Pin

1

I

I/O

I

I/O

I

Level-Sensitive Interrupt Requests¹

Programmable I/O Pin

Host Mode Pins (Mode C = 1)

IRQL0/

PF5

IRQE/

PF4

Level-Sensitive Interrupt Requests¹

Programmable I/O Pin

# of Input/

Edge-Sensitive Interrupt Requests¹

Programmable I/O Pin

Name(s) Pins Output Function

I/O

IAD15:0 16

I/O

O

IDMA Port Address/Data Bus

PF3

Programmable I/O Pin During

Normal Operation

A0

1

Address Pin for External I/O, Pro-

gram, Data or Byte access

Mode C/

PF2

1

I

Mode Select Input—Checked

Only During RESET

Programmable I/O Pin During

Normal Operation

Mode Select Input—Checked

Only During RESET

Programmable I/O Pin During

Normal Operation

Mode Select Input—Checked

Only During RESET

Programmable I/O Pin During

Normal Operation

D23:8

16

I/O

Data I/O Pins for Program, Data

Byte and I/O spaces

I/O

I

IWR

IRD

IAL

IS

1

I

IDMA Write Enable

IDMA Read Enable

IDMA Address Latch Pin

IDMA Select

I

Mode B/

I

PF1

I/O

I

IACK

O

IDMA Port Acknowledge

Mode A/

PF0

1

In Host Mode, external peripheral addresses can be decoded using the A0,

CMS, PMS, DMS and IOMS signals

I/O

Terminating Unused Pin

The following table shows the recommendations for terminating

unused pins.

CLKIN,

XTAL

CLKOUT

SPORT0

SPORT1

IRQ1:0

FI, FO

PWD

PWDACK

FL0, FL1,

FL2

2

1

5

I

O

I/O

Clock or Quartz Crystal Input

Processor Clock Output

Serial Port I/O Pins

Edge- or Level-Sensitive Interrupts,

Flag In, Flag Out²

Pin Terminations

I/O

Hi-Z*

Name

3-State Reset Caused

(Z)

Unused

State

By

Configuration

XTAL

CLKOUT

A13:1 or

IAD12:0

A0

D23:8

D7 or

IWR

D6 or

IRD

D5 or

IAL

I

O

I

O

Hi-Z

Float

BR, EBR Float

IS Float

BR, EBR Float

1

I

O

Power-Down Control Input

Power-Down Control Output

O (Z)

I/O (Z) Hi-Z

O (Z) Hi-Z

I/O (Z) Hi-Z

I

I/O (Z) Hi-Z

I

I/O (Z) Hi-Z

I

3

O

Output Flags

VDD and

GND

16

9

I

Power and Ground

For Emulation Use

I

High (Inactive)

BR, EBR Float

BR, EBR High (Inactive)

Float

EZ-Port

I/O

I

N

OTES

¹Interrupt/Flag Pins retain both functions concurrently. If IMASK is set to enable the

corresponding interrupts, then the DSP will vector to the appropriate interrupt vec-

tor address when the pin is asserted, either by external devices, or set as a program-

mable flag.

I

Low (Inactive)

²SPORT configuration determined by the DSP System Control Register. Software

configurable.

REV. A

–4–

ADSP-2185L

Pin Terminations (Continued)

Interrupts

The interrupt controller allows the processor to respond to the

eleven possible interrupts and reset with minimum overhead.

The ADSP-2185L provides four dedicated external interrupt

input pins, IRQ2, IRQL0, IRQL1 and IRQE. In addition,

SPORT1 may be reconfigured for IRQ0, IRQ1, FLAG_IN and

FLAG_OUT, for a total of six external interrupts. The ADSP-

2185L also supports internal interrupts from the timer, the byte

DMA port, the two serial ports, software and the power-down

control circuit. The interrupt levels are internally prioritized and

individually maskable (except power down and reset). The

IRQ2, IRQ0 and IRQ1 input pins can be programmed to be

either level- or edge-sensitive. IRQL0 and IRQL1 are level-

sensitive and IRQE is edge sensitive. The priorities and vector

addresses of all interrupts are shown in Table I.

I/O

Hi-Z*

Caused

By

Name

3-State Reset

(Z)

Unused

Configuration

State

D4 or

IS

I/O (Z)

I

I/O (Z)

Hi-Z

I

Hi-Z

BR, EBR Float

High (Inactive)

BR, EBR Float

Float

BR, EBR Float

IS

BR, EBR Float

D3 or

IACK

D2:0 or

IAD15:13

PMS

DMS

BMS

IOMS

CMS

RD

WR

BR

BG

BGH

IRQ2/PF7

I/O (Z)

O (Z)

I

Hi-Z

O

I

O

I

Float

Table I. Interrupt Priority and Interrupt Vector Addresses

Interrupt Vector

High (Inactive)

Float

O (Z)

O

I/O (Z)

EE

Source of Interrupt

Address (Hex)

Input = High (Inactive)

or Program as Output,

Set to 1, Let Float

Input = High (Inactive)

or Program as Output,

Set to 1, Let Float

Input = High (Inactive)

or Program as Output,

Set to 1, Let Float

Input = High (Inactive)

or Program as Output,

Set to 1, Let Float

Input = High or Low,

Output = Float

RESET (or Power-Up with PUCR = 1) 0000 (Highest Priority)

Power-Down (Nonmaskable)

IRQ2

002C

0004

IRQL1/PF6 I/O (Z)

IRQL0/PF5 I/O (Z)

IRQE/PF4 I/O (Z)

I

IRQL1

0008

IRQL0

000C

SPORT0 Transmit

SPORT0 Receive

IRQE

0010

0014

0018

BDMA Interrupt

SPORT1 Transmit or IRQ1

SPORT1 Receive or IRQ0

Timer

001C

0020

0024

0028 (Lowest Priority)

SCLK0

I/O

Interrupt routines can either be nested with higher priority inter-

rupts taking precedence or processed sequentially. Interrupts

can be masked or unmasked with the IMASK register. Indi-

vidual interrupt requests are logically ANDed with the bits in

IMASK; the highest priority unmasked interrupt is then se-

lected. The power-down interrupt is nonmaskable.

RFS0

DR0

TFS0

DT0

I/O

I

I/O

O

I

O

I

High or Low

Float

Input = High or Low,

Output = Float

High or Low

SCLK1

I/O

RFS1/RQ0 I/O

DR1/FI

TFS1/RQ1 I/O

DT1/FO

EE

I

O

I

The ADSP-2185L masks all interrupts for one instruction cycle

following the execution of an instruction that modifies the

IMASK register. This does not affect serial port auto-

buffering or DMA transfers.

I

O

I

Float

EBR

EBG

I

O

I

O

I

O

I

O

I

The interrupt control register, ICNTL, controls interrupt nest-

ing and defines the IRQ0, IRQ1 and IRQ2 external interrupts to

be either edge- or level-sensitive. The IRQE pin is an external

edge-sensitive interrupt and can be forced and cleared. The

IRQL0 and IRQL1 pins are external level-sensitive interrupts.

ERESET

EMS

EINT

ECLK

ELIN

ELOUT

The IFC register is a write-only register used to force and clear

interrupts. On-chip stacks preserve the processor status and are

automatically maintained during interrupt handling. The stacks are

twelve levels deep to allow interrupt, loop and subroutine nest-

ing. The following instructions allow global enable or disable

servicing of the interrupts (including power down), regardless of

the state of IMASK. Disabling the interrupts does not affect se-

rial port autobuffering or DMA.

I

O

I

O

NOTES

**Hi-Z = High Impedance.

1.If the CLKOUT pin is not used, turn it OFF.

2.If the Interrupt/Programmable Flag pins are not used, there are two options:

Option 1: When these pins are configured as INPUTS at reset and function as

interrupts and input flag pins, pull the pins High (inactive).

Option 2: Program the unused pins as OUTPUTS, set them to 1, and let

them float.

3.All bidirectional pins have three-stated outputs. When the pins is configured

as an output, the output is Hi-Z (high impedance) when inactive.

4.CLKIN, RESET, and PF3:0 are not included in the table because these pins

must be used.

ENA INTS;

DIS INTS;

When the processor is reset, interrupt servicing is enabled.

REV. A

–5–

ADSP-2185L

LOW POWER OPERATION

When the IDLE (n) instruction is used, it effectively slows down

the processor’s internal clock and thus its response time to in-

coming interrupts. The one-cycle response time of the standard

idle state is increased by n, the clock divisor. When an enabled

interrupt is received, the ADSP-2185L will remain in the idle

state for up to a maximum of n processor cycles (n = 16, 32, 64

or 128) before resuming normal operation.

The ADSP-2185L has three low power modes that significantly

reduce the power dissipation when the device operates under

standby conditions. These modes are:

• Power-Down

• Idle

• Slow Idle

When the IDLE (n) instruction is used in systems that have an

externally generated serial clock (SCLK), the serial clock rate

may be faster than the processor’s reduced internal clock rate.

Under these conditions, interrupts must not be generated at a

faster rate than can be serviced, due to the additional time the

processor takes to come out of the idle state (a maximum of n

processor cycles).

The CLKOUT pin may also be disabled to reduce external

power dissipation.

Power-Down

The ADSP-2185L processor has a low power feature that lets

the processor enter a very low power dormant state through

hardware or software control. Here is a brief list of power-down

features. Refer to the ADSP-2100 Family User’s Manual, Third

Edition, “System Interface” chapter, for detailed information

about the power-down feature.

SYSTEM INTERFACE

Figure 2 shows a typical basic system configuration with the

ADSP-2185L, two serial devices, a byte-wide EPROM, and

optional external program and data overlay memories (mode se-

lectable). Programmable wait state generation allows the proces-

sor to connect easily to slow peripheral devices. The ADSP-2185L

also provides four external interrupts and two serial ports or six

external interrupts and one serial port. Host Memory Mode al-

lows access to the full external data bus, but limits addressing to

a single address bit (A0). Additional system peripherals can be

added in this mode through the use of external hardware to gen-

erate and latch address signals.

• Quick recovery from power-down. The processor begins ex-

ecuting instructions in as few as 400 CLKIN cycles.

• Support for an externally generated TTL or CMOS processor

clock. The external clock can continue running during power-

down without affecting the 400 CLKIN cycle recovery.

• Support for crystal operation includes disabling the oscillator

to save power (the processor automatically waits 4096 CLKIN

cycles for the crystal oscillator to start and stabilize), and let-

ting the oscillator run to allow 400 CLKIN cycle start up.

• Power-down is initiated by either the power-down pin (PWD)

or the software power-down force bit Interrupt support allows

an unlimited number of instructions to be executed before op-

tionally powering down. The power-down interrupt also can

be used as a non-maskable, edge-sensitive interrupt.

Clock Signals

The ADSP-2185L can be clocked by either a crystal or a TTL-

compatible clock signal.

The CLKIN input cannot be halted, changed during operation

or operated below the specified frequency during normal opera-

tion. The only exception is while the processor is in the power-

down state. For additional information, refer to Chapter 9,

ADSP-2100 Family User’s Manual, Third Edition, for detailed in-

formation on this power-down feature.

• Context clear/save control allows the processor to continue

where it left off or start with a clean context when leaving the

power-down state.

• The RESET pin also can be used to terminate power-down.

• Power-down acknowledge pin indicates when the processor

has entered power-down.

If an external clock is used, it should be a TTL-compatible sig-

nal running at half the instruction rate. The signal is connected

to the processor’s CLKIN input. When an external clock is

used, the XTAL input must be left unconnected.

Idle

When the ADSP-2185L is in the Idle Mode, the processor waits

indefinitely in a low power state until an interrupt occurs. When

an unmasked interrupt occurs, it is serviced; execution then con-

tinues with the instruction following the IDLE instruction. In

Idle Mode IDMA, BDMA and autobuffer cycle steals still occur.

The ADSP-2185L uses an input clock with a frequency equal to

half the instruction rate; a 26.00 MHz input clock yields a 19 ns

processor cycle (which is equivalent to 52 MHz). Normally, in-

structions are executed in a single processor cycle. All device

timing is relative to the internal instruction clock rate, which is

indicated by the CLKOUT signal when enabled.

Slow Idle

The IDLE instruction on the ADSP-2185L slows the processor’s

internal clock signal, further reducing power consumption. The

reduced clock frequency, a programmable fraction of the nor-

mal clock rate, is specified by a selectable divisor given in the

IDLE instruction. The format of the instruction is

Because the ADSP-2185L includes an on-chip oscillator circuit,

an external crystal may be used. The crystal should be connected

across the CLKIN and XTAL pins, with two capacitors connected

as shown in Figure 3. Capacitor values are dependent on crystal

type and should be specified by the crystal manufacturer. A

parallel-resonant, fundamental frequency, microprocessor-grade

crystal should be used.

IDLE (n);

where n = 16, 32, 64 or 128. This instruction keeps the proces-

sor fully functional, but operating at the slower clock rate. While

it is in this state, the processor’s other internal clock signals,

such as SCLK, CLKOUT and timer clock, are reduced by the

same ratio. The default form of the instruction, when no clock

divisor is given, is the standard IDLE instruction.

A clock output (CLKOUT) signal is generated by the processor

at the processor’s cycle rate. This can be enabled and disabled

by the CLK0DIS bit in the SPORT0 Autobuffer Control Register.

REV. A

–6–

ADSP-2185L

Reset

FULL MEMORY MODE

The RESET signal initiates a master reset of the ADSP-2185L.

The RESET signal must be asserted during the power-up se-

quence to assure proper initialization. RESET during initial

power-up must be held long enough to allow the internal clock

to stabilize. If RESET is activated any time after power-up, the

clock continues to run and does not require stabilization time.

ADSP-2185L

14

A

1/2x CLOCK

OR

13-0

CLKIN

ADDR13-0

XTAL

CRYSTAL

D

A0-A21

23-16

FL0-2

BYTE

MEMORY

24

D

15-8

PF3

DATA

DATA23-0

IRQ2/PF7

IRQE/PF4

IRQL0/PF5

BMS

CS

A

10-0

IRQL1/PF6

WR

The power-up sequence is defined as the total time required for

the crystal oscillator circuit to stabilize after a valid V_DDis ap-

plied to the processor, and for the internal phase-locked loop

(PLL) to lock onto the specific crystal frequency. A minimum

of 2000 CLKIN cycles ensures that the PLL has locked, but

does not include the crystal oscillator start-up time. During this

power-up sequence the RESET signal should be held low. On

any subsequent resets, the RESET signal must meet the mini-

ADDR

DATA

PF2 [MODE C]

PF1 [MODE B]

PF0 [MODE A]

D

23-8

I/O SPACE

RD

(PERIPHERALS)

2048 LOCATIONS

CS

IOMS

A

13-0

ADDR

DATA

SPORT1

SCLK1

RFS1 OR IRQ0

OVERLAY

MEMORY

D

23-0

SERIAL

DEVICE

TFS1 OR IRQ1

DT1 OR FL0

DR1 OR FL1

TWO 8K

PMS

DMS

CMS

PM SEGMENTS

TWO 8K

DM SEGMENTS

SPORT0

SCLK0

RFS0

TFS0

DT0

DR0

mum pulsewidth specification, t_RSP

.

BR

BG

SERIAL

DEVICE

BGH

The RESET input contains some hysteresis; however, if an

RC circuit is used to generate the RESET signal, an external

Schmidt trigger is recommended.

PWD

PWDACK

HOST MEMORY MODE

The master reset sets all internal stack pointers to the empty

stack condition, masks all interrupts and clears the MSTAT

register. When RESET is released, if there is no pending bus

request and the chip is configured for booting, the boot-loading

sequence is performed. The first instruction is fetched from

on-chip program memory location 0x0000 once boot loading

completes.

ADSP-2185L

CLKIN

1/2x CLOCK

OR

CRYSTAL

1

A0

XTAL

FL0-2

PF3

16

DATA23-8

IRQ2/PF7

IRQE/PF4

IRQL0/PF5

BMS

IRQL1/PF6

WR

PF2 [MODE C]

PF1 [MODE B]

PF0 [MODE A]

RD

MODES OF OPERATION

Table II summarizes the ADSP-2185L memory modes.

IOMS

SPORT1

SCLK1

RFS1 OR IRQ0

TFS1 OR IRQ1

Setting Memory Mode

SERIAL

DEVICE

Memory Mode selection for the ADSP-2185L is made during

chip reset through the use of the Mode C pin. This pin is multi-

plexed with the DSP’s PF2 pin, so care must be taken in how

the mode selection is made. The two methods for selecting the

value of Mode C are active and passive.

DT1 OR FO

DR1 OR FI

PMS

DMS

CMS

SPORT0

SCLK0

RFS0

TFS0

DT0

SERIAL

DEVICE

BR

BG

BGH

DR0

IDMA PORT

IRD/D6

IWR/D7

IS/D4

IAL/D5

IACK/D3

IAD15-0

Passive configuration involves the use a pull-up or pull-down

resistor connected to the Mode C pin. To minimize power con-

sumption, or if the PF2 pin is to be used as an output in the

DSP application, a weak pull-up or pull-down, on the order of

100 kΩ, can be used. This value should be sufficient to pull the

pin to the desired level and still allow the pin to operate as

a programmable flag output without undue strain on the

processor’s output driver. For minimum power consumption

during power-down, reconfigure PF2 to be an input, as the

pull-up or pull-down will hold the pin in a known state, and will

not switch.

PWD

PWDACK

SYSTEM

INTERFACE

OR

␮CONTROLLER

16

Figure 2. ADSP-2185L Basic System Configuration

XTAL

CLKIN

CLKOUT

DSP

Active configuration involves the use of a three-statable exter-

nal driver connected to the Mode C pin. A driver’s output en-

able should be connected to the DSP’s RESET signal such that

it only drives the PF2 pin when RESET is active (low). When

RESET is deasserted, the driver should three-state, thus allow-

ing full use of the PF2 pin as either an input or output. To

minimize power consumption during power-down, configure

the programmable flag as an output when connected to a three-

stated buffer. This ensures that the pin will be held at a con-

stant level and not oscillate should the three-state driver’s level

hover around the logic switching point.

Figure 3. External Crystal Connections

REV. A

–7–

ADSP-2185L

Table II. Modes of Operations¹

MODE C²MODE B³MODE A⁴Booting Method

0

1

0

1

0

1

BDMA feature is used to load the first 32 program memory words from the byte memory

space. Program execution is held off until all 32 words have been loaded. Chip is configured

in Full Memory Mode.⁵

No Automatic boot operations occur. Program execution starts at external memory location

0. Chip is configured in Full Memory Mode. BDMA can still be used, but the processor does

not automatically use or wait for these operations.

BDMA feature is used to load the first 32 program memory words from the byte memory

space. Program execution is held off until all 32 words have been loaded. Chip is config-

ured in Host Mode. (REQUIRES ADDITIONAL HARDWARE.)

IDMA feature is used to load any internal memory as desired. Program execution is held off

until internal program memory location 0 is written to. Chip is configured in Host Mode.⁵

1

NOTES

¹All mode pins are recognized while RESET is active (low).

²When Mode C = 0, Full Memory enabled. When Mode C = 1, Host Memory Mode enabled.

³When Mode B = 0, Auto Booting enabled. When Mode B = 1, no Auto Booting.

⁴When Mode A = 0, BDMA enabled. When Mode A = 1, IDMA enabled.

⁵Considered as standard operating settings. Using these configurations allows for easier design and better memory management.

Program Memory (Host Mode) allows access to all internal

MEMORY ARCHITECTURE

memory. External overlay access is limited by a single external

address line (A0). External program execution is not available in

host mode due to a restricted data bus that is 16-bits wide only.

The ADSP-2185L provides a variety of memory and peripheral

interface options. The key functional groups are Program

Memory, Data Memory, Byte Memory, and I/O. Refer to the

following figures and tables for PM and DM memory alloca-

tions in the ADSP-2185L.

Table III. PMOVLAY Bits

PMOVLAY Memory A13

A12:0

PROGRAM MEMORY

0

1

Internal

Not Applicable Not Applicable

Program Memory (Full Memory Mode) is a 24-bit-wide

space for storing both instruction opcodes and data. The

ADSP-2185L has 16K words of Program Memory RAM on

chip, and the capability of accessing up to two 8K external

memory overlay spaces using the external data bus.

External

Overlay 1

0

1

13 LSBs of Address

Between 0x2000

and 0x3FFF

2

External

13 LSBs of Address

Between 0x2000

and 0x3FFF

Overlay 2

1

PM (MODE B = 0)

PM (MODE B = 1)

ALWAYS

RESERVED

ACCESSIBLE

AT ADDRESS

0x2000–

0x3FFF

INTERNAL

MEMORY

0x0000 – 0x1FFF

INTERNAL

MEMORY

ACCESSIBLE WHEN

PMOVLAY = 0

0x2000–

0x3FFF

0x0000–

0x1FFF

ACCESSIBLE WHEN

PMOVLAY = 0

2

0x2000–

0x3FFF

ACCESSIBLE WHEN

PMOVLAY = 0

2

ACCESSIBLE WHEN

PMOVLAY = 1

0x2000–

0x3FFF

EXTERNAL

MEMORY

RESERVED

2

EXTERNAL

MEMORY

ACCESSIBLE WHEN

PMOVLAY = 2

1

WHEN MODE B = 1, PMOVLAY MUST BE SET TO 0

2

SEE TABLE III FOR PMOVLAY BITS

PROGRAM MEMORY

MODE B = 0

MODE B = 1

ADDRESS

0x3FFF

8K INTERNAL

PMOVLAY = 0

OR

8K EXTERNAL

PMOVLAY = 1 OR 2

8K INTERNAL

PMOVLAY = 0

0x2000

0x1FFF

0x2000

0x1FFF

8K EXTERNAL

8K INTERNAL

0x0000

Figure 4. Program Memory

–8–

REV. A

ADSP-2185L

DATA MEMORY

Composite Memory Select (CMS)

Data Memory (Full Memory Mode) is a 16-bit-wide space

used for the storage of data variables and for memory-mapped

control registers. The ADSP-2185L has 16K words on Data

Memory RAM on chip, consisting of 16,352 user-accessible lo-

cations and 32 memory-mapped registers. Support also exists

for up to two 8K external memory overlay spaces through the

external data bus. All internal accesses complete in one cycle.

Accesses to external memory are timed using the wait states

specified by the DWAIT register.

The ADSP-2185L has a programmable memory select signal

that is useful for generating memory select signals for memories

mapped to more than one space. The CMS signal is generated

to have the same timing as each of the individual memory select

signals (PMS, DMS, BMS, IOMS) but can combine their

functionality.

Each bit in the CMSSEL register, when set, causes the CMS

signal to be asserted when the selected memory select is as-

serted. For example, to use a 32K word memory to act as both

program and data memory, set the PMS and DMS bits in the

CMSSEL register and use the CMS pin to drive the chip select

of the memory; use either DMS or PMS as the additional

address bit.

DATA MEMORY

ADDRESS

3FFF

DATA MEMORY

32 MEMORY

MAPPED

REGISTERS

0x

ALWAYS

ACCESSIBLE

AT ADDRESS

0x3FE0

0x3FDF

0x2000 – 0x3FFF

INTERNAL

8160

WORDS

INTERNAL

MEMORY

0x0000–

0x1FFF

0x2000

The CMS pin functions like the other memory select signals,

with the same timing and bus request logic. A 1 in the enable bit

causes the assertion of the CMS signal at the same time as the

selected memory select signal. All enable bits default to 1 at re-

set, except the BMS bit.

ACCESSIBLE WHEN

DMOVLAY = 0

0x1FFF

0x0000–

0x1FFF

8K INTERNAL

DMOVLAY = 0

OR

EXTERNAL 8K

DMOVLAY = 1, 2

ACCESSIBLE WHEN

DMOVLAY = 1

0x0000–

0x1FFF

EXTERNAL

MEMORY

0x0000

ACCESSIBLE WHEN

DMOVLAY = 2

Boot Memory Select (BMS) Disable

Figure 5. Data Memory Map

The ADSP-2185L also lets you boot the processor from one ex-

ternal memory space while using a different external memory

space for BDMA transfers during normal operation. You can

use the CMS to select the first external memory space for

BDMA transfers and BMS to select the second external memory

space for booting. The BMS signal can be disabled by setting

Bit 3 of the System Control Register to 1. The System Control

Register is illustrated in Figure 6.

Data Memory (Host Mode) allows access to all internal memory.

External overlay access is limited by a single external address

line (A0). The DMOVLAY bits are defined in Table IV.

Table IV. DMOVLAY Bits

DMOVLAY Memory A13

A12:0

0

1

Internal

Not Applicable Not Applicable

SYSTEM CONTROL REGISTER

15 14 13 12 11 10

9

8

7

6

5

4

3

0

2

1

0

1

External

Overlay 1

0

1

13 LSBs of Address

Between 0x2000

and 0x3FFF

DM (0

؋

3FFF)

0

1

0

PWAIT

PROGRAM MEMORY

WAIT STATES

SPORT0 ENABLE

1 = ENABLED, 0 = DISABLED

SPORT1 ENABLE

1 = ENABLED, 0 = DISABLED

2

External

Overlay 2

13 LSBs of Address

Between 0x2000

and 0x3FFF

BMS ENABLE

0 = ENABLED, 1 = DISABLED

SPORT1 CONFIGURE

1 = SERIAL PORT

0 = FI, FO, IRQ0, IRQ1, SCLK

Figure 6. System Control Register

Byte Memory

The byte memory space is a bidirectional, 8-bit-wide, external

memory space used to store programs and data. Byte memory is

accessed using the BDMA feature. The BDMA Control Register is

shown in Figure 7. The byte memory space consists of 256 pages,

each of which is 16K × 8.

I/O Space (Full Memory Mode)

The ADSP-2185L supports an additional external memory

space called I/O space. This space is designed to support simple

connections to peripherals (such as data converters and external

registers) or to bus interface ASIC data registers. I/O space sup-

ports 2048 locations of 16-bit wide data. The lower eleven bits

of the external address bus are used; the upper three bits are un-

defined. Two instructions were added to the core ADSP-2100

Family instruction set to read from and write to I/O memory

space. The I/O space also has four dedicated 3-bit wait state

registers, IOWAIT0-3, that specify up to seven wait states to be

automatically generated for each of four regions. The wait states

act on address ranges as shown in Table V.

BDMA CONTROL

15 14 13 12 11 10

9

8

7

6

5

0

4

0

3

1

2

0

1

0

DM (0

؋

3FE3)

BTYPE

BDIR

BMPAGE

0 = LOAD FROM BM

1 = STORE TO BM

Table V. Wait States

BCR

0 = RUN DURING BDMA

1 = HALT DURING BDMA

Address Range

Wait State Register

Figure 7. BDMA Control Register

0x000–0x1FF

0x200–0x3FF

0x400–0x5FF

0x600–0x7FF

IOWAIT0

IOWAIT1

IOWAIT2

IOWAIT3

The byte memory space on the ADSP-2185L supports read and

write operations as well as four different data formats. The byte

memory uses data bits 15:8 for data. The byte memory uses

data bits 23:16 and address bits 13:0 to create a 22-bit address.

This allows up to a 4 meg × 8 (32 megabit) ROM or RAM to be

used without glue logic. All byte memory accesses are timed by

the BMWAIT register.

REV. A

–9–

ADSP-2185L

Byte Memory DMA (BDMA, Full Memory Mode)

Internal Memory DMA Port (IDMA Port; Host Memory

Mode)

The Byte memory DMA controller allows loading and storing of

program instructions and data using the byte memory space.

The BDMA circuit is able to access the byte memory space

while the processor is operating normally, and steals only one

DSP cycle per 8-, 16- or 24-bit word transferred.

The IDMA Port provides an efficient means of communication

between a host system and the ADSP-2185L. The port is used

to access the on-chip program memory and data memory of the

DSP with only one DSP cycle per word overhead. The IDMA

port cannot be used, however, to write to the DSP’s memory-

mapped control registers. A typical IDMA transfer process is

described as follows:

The BDMA circuit supports four different data formats that are

selected by the BTYPE register field. The appropriate number

of 8-bit accesses are done from the byte memory space to build

the word size selected. Table VI shows the data formats sup-

ported by the BDMA circuit.

1. Host starts IDMA transfer.

2. Host checks IACK control line to see if the DSP is busy.

Table VI. Data Formats

3. Host uses IS and IAL control lines to latch the DMA starting

address (IDMAA) into the DSP’s IDMA control registers.

IAD[15] must be set = 0.

Internal

BTYPE

Memory Space

Word Size

Alignment

4. Host uses IS and IRD (or IWR) to read (or write) DSP inter-

00

01

10

11

Program Memory

Data Memory

24

16

8

Full Word

MSBs

nal memory (PM or DM).

5. Host checks IACK line to see if the DSP has completed the

previous IDMA operation.

8

LSBs

6. Host ends IDMA transfer.

Unused bits in the 8-bit data memory formats are filled with 0s.

The BIAD register field is used to specify the starting address

for the on-chip memory involved with the transfer. The 14-bit

BEAD register specifies the starting address for the external

byte memory space. The 8-bit BMPAGE register specifies the

starting page for the external byte memory space. The BDIR

register field selects the direction of the transfer. Finally the 14-

bit BWCOUNT register specifies the number of DSP words to

transfer and initiates the BDMA circuit transfers.

The IDMA port has a 16-bit multiplexed address and data bus

and supports 24-bit program memory. The IDMA port is

completely asynchronous and can be written to while the

ADSP-2185L is operating at full speed.

The DSP memory address is latched and then automatically in-

cremented after each IDMA transaction. An external device can

therefore access a block of sequentially addressed memory by

specifying only the starting address of the block. This increases

throughput as the address does not have to be sent for each

memory access.

BDMA accesses can cross page boundaries during sequential

addressing. A BDMA interrupt is generated on the completion

of the number of transfers specified by the BWCOUNT

register.

IDMA Port access occurs in two phases. The first is the IDMA

Address Latch cycle. When the acknowledge is asserted, a

14-bit address and 1-bit destination type can be driven onto the

bus by an external device. The address specifies an on-chip

memory location; the destination type specifies whether it is a

DM or PM access. The falling edge of the address latch signal

latches this value into the IDMAA register.

The BWCOUNT register is updated after each transfer so it can

be used to check the status of the transfers. When it reaches

zero, the transfers have finished and a BDMA interrupt is gener-

ated. The BMPAGE and BEAD registers must not be accessed

by the DSP during BDMA operations.

Once the address is stored, data can either be read from or

written to the ADSP-2185L’s on-chip memory. Asserting the

select line (IS) and the appropriate read or write line (IRD and

IWR respectively) signals the ADSP-2185L that a particular

transaction is required. In either case, there is a one-processor-

cycle delay for synchronization. The memory access consumes

one additional processor cycle.

The source or destination of a BDMA transfer will always be

on-chip program or data memory.

When the BWCOUNT register is written with a nonzero value,

the BDMA circuit starts executing byte memory accesses with

wait states set by BMWAIT. These accesses continue until the

count reaches zero. When enough accesses have occurred to

create a destination word, it is transferred to or from on-chip

memory. The transfer takes one DSP cycle. DSP accesses to ex-

ternal memory have priority over BDMA byte memory accesses.

Once an access has occurred, the latched address is automati-

cally incremented and another access can occur.

Through the IDMAA register, the DSP can also specify the

starting address and data format for DMA operation. Asserting

the IDMA port select (IS) and address latch enable (IAL) di-

rects the ADSP-2185L to write the address onto the IAD0–14

bus into the IDMA Control Register. The IDMAA register,

shown below, is memory mapped at address DM (0x3FE0).

Note that the latched address (IDMAA) cannot be read back by

the host. See Figure 8 for more information on IDMA and

DMA memory maps.

The BDMA Context Reset bit (BCR) controls whether or not

the processor is held off while the BDMA accesses are occur-

ring. Setting the BCR bit to 0 allows the processor to continue

operations. Setting the BCR bit to 1 causes the processor to

stop execution while the BDMA accesses are occurring, to clear

the context of the processor and start execution at address 0

when the BDMA accesses have completed.

REV. A

–10–

ADSP-2185L

IDMA CONTROL (U = UNDEFINED AT RESET)

If the ADSP-2185L is performing an external memory access

when the external device asserts the BR signal, it will not three-

state the memory interfaces or assert the BG signal until the

processor cycle after the access completes. The instruction does

not need to be completed when the bus is granted. If a single in-

struction requires two external memory accesses, the bus will be

granted between the two accesses.

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

U

DM(0

؋

3FE0)

IDMAA

ADDRESS

IDMAD

DESTINATION MEMORY TYPE:

0 = PM

1 = DM

When the BR signal is released, the processor releases the BG

signal, reenables the output drivers and continues program ex-

ecution from the point at which it stopped.

Figure 8. IDMA Control/OVLAY Registers

Bootstrap Loading (Booting)

The bus request feature operates at all times, including when

the processor is booting and when RESET is active.

The ADSP-2185L has two mechanisms to allow automatic

loading of the internal program memory after reset. The method

for booting after reset is controlled by the Mode A, B and C

configuration bits.

The BGH pin is asserted when the ADSP-2185L is ready to ex-

ecute an instruction, but is stopped because the external bus is

already granted to another device. The other device can release

the bus by deasserting bus request. Once the bus is released, the

ADSP-2185L deasserts BG and BGH and executes the external

memory access.

When the mode pins specify BDMA booting, the ADSP-2185L

initiates a BDMA boot sequence when reset is released.

The BDMA interface is set up during reset to the following de-

faults when BDMA booting is specified: the BDIR, BMPAGE,

BIAD and BEAD registers are set to 0, the BTYPE register is

set to 0 to specify program memory 24-bit words, and the

BWCOUNT register is set to 32. This causes 32 words of on-

chip program memory to be loaded from byte memory. These

32 words are used to set up the BDMA to load in the remaining

program code. The BCR bit is also set to 1, which causes pro-

gram execution to be held off until all 32 words are loaded into

on-chip program memory. Execution then begins at address 0.

Flag I/O Pins

The ADSP-2185L has eight general purpose programmable

input/output flag pins. They are controlled by two memory

mapped registers. The PFTYPE register determines the direc-

tion, 1 = output and 0 = input. The PFDATA register is used to

read and write the values on the pins. Data being read from a

pin configured as an input is synchronized to the ADSP-2185L’s

clock. Bits that are programmed as outputs will read the value

being output. The PF pins default to input during reset.

The ADSP-2100 Family Development Software (Revision 5.02

and later) fully supports the BDMA booting feature and can

generate byte memory space compatible boot code.

In addition to the programmable flags, the ADSP-2185L has

five fixed-mode flags, FLAG_IN, FLAG_OUT, FL0, FL1 and

FL2. FL0-FL2 are dedicated output flags. FLAG_IN and

FLAG_OUT are available as an alternate configuration of

SPORT1.

The IDLE instruction can also be used to allow the processor to

hold off execution while booting continues through the BDMA

interface. For BDMA accesses while in Host Mode, the ad-

dresses to boot memory must be constructed externally to the

ADSP-2185L. The only memory address bit provided by the

processor is A0.

Note: Pins PF0, PF1, PF2 and PF3 are also used for device

configuration during reset.

INSTRUCTION SET DESCRIPTION

The ADSP-2185L assembly language instruction set has an

algebraic syntax that was designed for ease of coding and read-

ability. The assembly language, which takes full advantage of

the processor’s unique architecture, offers the following benefits:

IDMA Port Booting

The ADSP-2185L can also boot programs through its Internal

DMA port. If Mode C = 1, Mode B = 0 and Mode A = 1, the

ADSP-2185L boots from the IDMA port. IDMA feature can

load as much on-chip memory as desired. Program execution is

held off until on-chip program memory location 0 is written to.

• The algebraic syntax eliminates the need to remember cryptic

assembler mnemonics. For example, a typical arithmetic add

instruction, such as AR = AX0 + AY0, resembles a simple

equation.

Bus Request and Bus Grant (Full Memory Mode)

The ADSP-2185L can relinquish control of the data and ad-

dress buses to an external device. When the external device re-

quires access to memory, it asserts the bus request (BR) signal.

If the ADSP-2185L is not performing an external memory ac-

cess, it responds to the active BR input in the following proces-

sor cycle by:

• Every instruction assembles into a single, 24-bit word that can

execute in a single instruction cycle.

• The syntax is a superset ADSP-2100 Family assembly lan-

guage and is completely source and object code compatible

with other family members. Programs may need to be relo-

cated to utilize on-chip memory and conform to the ADSP-

2185L’s interrupt vector and reset vector map.

• three-stating the data and address buses and the PMS, DMS,

BMS, CMS, IOMS, RD, WR output drivers,

• asserting the bus grant (BG) signal, and

• Sixteen condition codes are available. For conditional jump,

call, return or arithmetic instructions, the condition can be

checked and the operation executed in the same instruction

cycle.

• halting program execution.

If Go Mode is enabled, the ADSP-2185L will not halt program

execution until it encounters an instruction that requires an ex-

ternal memory access.

• Multifunction instructions allow parallel execution of an

arithmetic instruction with up to two fetches or one write to

processor memory space during a single instruction cycle.

REV. A

–11–

ADSP-2185L

DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM

The ADSP-2185L has on-chip emulation support and an ICE-

Port, a special set of pins that interface to the EZ-ICE. These

features allow in-circuit emulation without replacing the target

system processor by using only a 14-pin connection from the

target system to the EZ-ICE. Target systems must have a 14-pin

connector to accept the EZ-ICE’s in-circuit probe, a 14-pin plug.

See the ADSP-2100 Family EZ-Tools data sheet for complete in-

formation on ICE products.

The EZ-ICE connects to your target system via a ribbon cable

and a 14-pin female plug. The ribbon cable is 10 inches in

length with one end fixed to the EZ-ICE. The female plug is

plugged onto the 14-pin connector (a pin strip header) on the

target board.

Target Board Connector for EZ-ICE Probe

The EZ-ICE connector (a standard pin strip header) is shown in

Figure 10. You must add this connector to your target board

design if you intend to use the EZ-ICE. Be sure to allow enough

room in your system to fit the EZ-ICE probe onto the 14-pin

connector.

Issuing the chip reset command during emulation causes the

DSP to perform a full chip reset, including a reset of its memory

mode. Therefore, it is vital that the mode pins are set correctly

PRIOR to issuing a chip reset command from the emulator user

interface. If you are using a passive method of maintaining

mode information (as discussed in Setting Memory Modes)

then it does not matter that the mode information is latched by

an emulator reset. However, if you are using the RESET pin as

a method of setting the value of the mode pins, then you have to

take into consideration the effects of an emulator reset.

1

3

5

2

4

GND

BG

EBG

BR

6

EBR

KEY (NO PIN)

ELOUT

EINT

ELIN

7

8

؋

One method of ensuring that the values located on the mode

pins are those desired is to construct a circuit like the one shown

in Figure 9. This circuit forces the value located on the Mode A

pin to logic high; regardless if it latched via the RESET or

ERESET pin.

10

12

14

9

ECLK

11

13

EE

EMS

RESET

ERESET

RESET

TOP VIEW

ADSP-2185L

Figure 10. Target Board Connector for EZ-ICE

1k⍀

The 14-pin, 2-row pin strip header is keyed at the Pin 7 loca-

tion—you must remove Pin 7 from the header. The pins must

be 0.025 inch square and at least 0.20 inch in length. Pin spac-

ing should be 0.1 × 0.1 inches. The pin strip header must have

at least 0.15 inch clearance on all sides to accept the EZ-ICE

probe plug.

MODE A/PFO

PROGRAMMABLE I/O

Figure 9. Mode A Pin/EZ-ICE Circuit

The ICE-Port interface consists of the following ADSP-2185L

pins:

Pin strip headers are available from vendors such as 3M,

McKenzie and Samtec.

EBR

EMS

ELIN

EBG

EINT

ELOUT

ERESET

ECLK

EE

Target Memory Interface

For your target system to be compatible with the EZ-ICEemu-

lator, it must comply with the memory interface guidelines listed

below.

These ADSP-2185L pins must be connected only to the EZ-ICE

connector in the target system. These pins have no function ex-

cept during emulation, and do not require pull-up or pull-down

resistors. The traces for these signals between the ADSP-2185L

and the connector must be kept as short as possible, no longer

than three inches.

PM, DM, BM, IOM and CM

Design your Program Memory (PM), Data Memory (DM),

Byte Memory (BM), I/O Memory (IOM) and Composite

Memory (CM) external interfaces to comply with worst case

device timing requirements and switching characteristics as

specified in the DSP’s data sheet. The performance of the

EZ-ICE may approach published worst case specification for

some memory access timing requirements and switching

characteristics.

The following pins are also used by the EZ-ICE:

BR

RESET

BG

GND

The EZ-ICE uses the EE (emulator enable) signal to take con-

trol of the ADSP-2185L in the target system. This causes the

processor to use its ERESET, EBR and EBG pins instead of the

RESET, BR and BG pins. The BG output is three-stated. These

signals do not need to be jumper-isolated in your system.

Note: If your target does not meet the worst case chip specifica-

tion for memory access parameters, you may not be able to

emulate your circuitry at the desired CLKIN frequency. De-

pending on the severity of the specification violation, you may

have trouble manufacturing your system as DSP components

statistically vary in switching characteristic and timing require-

ments within published limits.

REV. A

–12–

ADSP-2185L

Restriction: All memory strobe signals on the ADSP-2185L

(RD, WR, PMS, DMS, BMS, CMS and IOMS) used in your

target system must have 10 kΩ pull-up resistors connected when

the EZ-ICE is being used. The pull-up resistors are necessary

because there are no internal pull-ups to guarantee their state

during prolonged three-state conditions resulting from typical

EZ-ICE debugging sessions. These resistors may be removed at

your option when the EZ-ICE is not being used.

Target System Interface Signals

When the EZ-ICE board is installed, the performance on some

system signals changes. Design your system to be compatible

with the following system interface signal changes introduced by

the EZ-ICE board:

• EZ-ICE emulation introduces an 8 ns propagation delay be-

tween your target circuitry and the DSP on the RESET

signal.

• EZ-ICE emulation introduces an 8 ns propagation delay be-

tween your target circuitry and the DSP on the BR signal.

• EZ-ICE emulation ignores RESET and BR when single-

stepping.

• EZ-ICE emulation ignores RESET and BR when in Emulator

Space (DSP halted).

• EZ-ICE emulation ignores the state of target BR in certain

modes. As a result, the target system may take control of the

DSP’s external memory bus only if bus grant (BG) is asserted

by the EZ-ICE board’s DSP.

REV. A

–13–

ADSP-2185L–SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

K Grade

B Grade

Parameter

Min

Max

Min

Max

Unit

V_DD

T_AMB

Supply Voltage

Ambient Operating Temperature

3.0

0

3.6

+70

3.0

–40

3.6

+85

V

°C

ELECTRICAL CHARACTERISTICS

K/B Grades

Typ

Parameter

Test Conditions

Min

Max

Unit

V_IH

V_IL

Hi-Level Input Voltage^{1, 2}

Hi-Level CLKIN Voltage

Lo-Level Input Voltage^{1, 3}

Hi-Level Output Voltage^{1, 4, 5}

@ V_DD= max

@ V_DD= min

I_OH= –0.5 mA

@ V_DD= min

2.0

2.2

V

0.8

V_OH

2.4

V

I

_OH= –100 µA⁶

@ V_DD= min

_OL= 2 mA

V_DD– 0.3

V

V_OL

I_IH

Lo-Level Output Voltage^{1, 4, 5}

Hi-Level Input Current³

I

0.4

10

V

@ V_DD= max

V_IN= V_DDmax

@ V_DD= max

µA

I_IL

Lo-Level Input Current³

Three-State Leakage Current⁷

Supply Current (Idle)⁹

V

_IN= 0 V

@ V_DD= max

_IN= V_DDmax⁸

I_OZH

I_OZL

I_DD

V

@ V_DD= max

V_IN= 0 V⁸

@ V_DD= 3.3

t

_CK= 19 ns¹⁰

8.6

7

6

mA

t_CK= 25 ns¹⁰

_CK= 30 ns¹⁰

t

I_DD

Supply Current (Dynamic)¹¹

@ V_DD= 3.3

T_AMB= +25°C

t

_CK= 19 ns¹⁰

_CK= 25 ns¹⁰

49

38

31.5

mA

t_CK= 30 ns¹⁰

C_I

Input Pin Capacitance^{3, 6, 12}

@ V_IN= 2.5 V

f_IN= 1.0 MHz

T_AMB= +25°C

@ V_IN= 2.5 V

f_IN= 1.0 MHz

T_AMB= +25°C

8

pF

C_O

Output Pin Capacitance^{6, 7, 12, 13}

NOTES

¹¹Bidirectional pins: D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1–A13, PF0–PF7.

¹²Input only pins: RESET, BR, DR0, DR1, PWD.

¹³Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD.

¹⁴Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2–0, BGH.

¹⁵Although specified for TTL outputs, all ADSP-2185L outputs are CMOS-compatible and will drive to V _DDand GND, assuming no dc loads.

¹⁶Guaranteed but not tested.

¹⁷Three-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF0–PF7.

¹⁸0 V on BR.

¹⁹Idle refers to ADSP-2185L state of operation during execution of IDLE instruction. Deasserted pins are driven to either V_DDor GND.

10

V

= 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section.

measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2

IN

11

I

DD

and type 6, and 20% are idle instructions.

¹²Applies to LQFP package type.

¹³Output pin capacitance is the capacitive load for any three-stated output pin.

Specifications subject to change without notice.

REV. A

–14–

ADSP-2185L

ABSOLUTE MAXIMUM RATINGS^*

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.6 V

Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.5 V to V_DD+ 0.5 V

Output Voltage Swing . . . . . . . . . . . . . . –0.5 V to V_DD+ 0.5 V

Operating Temperature Range (Ambient) . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (5 sec) LQFP . . . . . . . . . . . . . . . . . +280°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. These are stress ratings only; functional operation of

the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

ESD SENSITIVITY

The ADSP-2185L is an ESD (electrostatic discharge) sensitive device. Electrostatic charges readily

accumulate on the human body and equipment and can discharge without detection. Permanent

damage may occur to devices subjected to high energy electrostatic discharges.

WARNING!

The ADSP-2185L features proprietary ESD protection circuitry to dissipate high energy discharges

(Human Body Model). Per method 3015 of MIL-STD-883, the ADSP-2185L has been classified

as a Class 1 device.

ESD SENSITIVE DEVICE

Proper ESD precautions are recommended to avoid performance degradation or loss of function-

ality. Unused devices must be stored in conductive foam or shunts, and the foam should be

discharged to the destination before devices are removed.

MEMORY TIMING SPECIFICATIONS

TIMING PARAMETERS

The table below shows common memory device specifications

and the corresponding ADSP-2185L timing parameters, for

your convenience.

GENERAL NOTES

Use the exact timing information given. Do not attempt to de-

rive parameters from the addition or subtraction of others.

While addition or subtraction would yield meaningful results for

an individual device, the values given in this data sheet reflect

statistical variations and worst cases. Consequently, you cannot

meaningfully add up parameters to derive longer times.

Memory

ADSP-2185L Timing

Device

Timing

Parameter

Specification

Parameter

Definition

Address Setup to

Write Start

Address Setup to

Write End

t_ASW

t_AW

A0–A13, xMS Setup before

WR Low

A0–A13, xMS Setup before

WR Deasserted

TIMING NOTES

Switching Characteristics specify how the processor changes its

signals. You have no control over this timing—circuitry external

to the processor must be designed for compatibility with these

signal characteristics. Switching characteristics tell you what the

processor will do in a given circumstance. You can also use switch-

ing characteristics to ensure that any timing requirement of a

device connected to the processor (such as memory) is satisfied.

Address Hold Time t_WRA

A0–A13, xMS Hold before

WR Low

Data Setup Time

Data Hold Time

OE to Data Valid

t_DW

t_DH

t_RDD

Data Setup before WR High

Data Hold after WR High

RD Low to Data Valid

Address Access Time t_AA

A0–A13, xMS to Data Valid

Timing Requirements apply to signals that are controlled by cir-

cuitry external to the processor, such as the data input for a read

operation. Timing requirements guarantee that the processor

operates correctly with other devices.

xMS = PMS, DMS, BMS, CMS, IOMS.

FREQUENCY DEPENDENCY FOR TIMING

SPECIFICATIONS

t_CK= Instruction Clock Period. t_CKI= External Clock Period.

t

_CKis defined as 0.5t_CKI. The ADSP-2185L uses an input clock

with a frequency equal to half the instruction rate: a 26 MHz

input clock (which is equivalent to 38 ns) yields a 19 ns processor

cycle (equivalent to 52 MHz). t_CKvalues within the range of

0.5t_CKIperiod should be substituted for all relevant timing

parameters to obtain the specification value.

Example: t_CKH= 0.5t_CK– 7 ns = 0.5 (19 ns) – 7 ns = 2.5 ns

REV. A

–15–

ADSP-2185L

OUTPUT DRIVE CURRENTS

2

Total Power Dissipation = P_INT+ (C × V_DD× f )

Figure 11 shows typical I-V characteristics for the output drivers

of the ADSP-2185L. The curves represent the current drive

capability of the output drivers as a function of output voltage.

P_INT= internal power dissipation from Power vs. Frequency

graph, see Figure 13.

(C × V_DD²× f ) is calculated for each output:

80

# of

Pins × C

3.6V, –40؇C

2

× V_DD

× f

60

40

3.3V, +25؇C

Address, DMS

Data Output, WR

RD

8

9

1

× 10 pF × 3.3²

V

× 33.3 MHz

× 16.67 MHz = 16.3 mW

× 16.67 MHz =

× 33.3 MHz

=

29.0 mW

1.8 mW

3.6 mW

20

CLKOUT

=

3.0V, +85؇C

50.7 mW

0

3.0V, +85؇C

Total power dissipation for this example is P_INT+ 50.7 mW.

–20

–40

–60

–80

3.3V, +25؇C

1, 3, 4

2185L POWER, INTERNAL

250

3.6V, –40

؇C

197mW

200

V

= 3.6V

= 3.3V

DD

161mW

130mW

0

0.5

1

1.5

2

2.5

3

3.5

4

SOURCE VOLTAGE – Volts

150

100

50

128mW

104mW

DD

Figure 11. Typical Drive Currents

V

= 3.0V

Figure 12 shows the typical power-down supply current.

DD

84mW

1000

0

52

33.3

FREQUENCY – MHz

1, 2, 3

V

= 3.6V

= 3.3V

DD

100

10

1

POWER, IDLE

45

40

V

DD

35mW

35

30

V

= 3.6V

DD

28mW

22mW

25mW

V

= 3.3V

= 3.0V

DD

25

20

20mW

16mW

V

DD

15

10

0

25

55

85

TEMPERATURE – ؇C

5

0

NOTES:

1. REFLECTS ADSP-2187L OPERATION IN LOWEST POWER MODE.

(SEE "SYSTEM INTERFACE" CHAPTER OF THE ADSP-2100 FAMILY

USER'S MANUAL FOR DETAILS.)

33.33

52

FREQUENCY – MHz

2. CURRENT REFLECTS DEVICE OPERATING WITH NO INPUT LOADS.

3

POWER, IDLE n MODES

45

40

35

30

25

20

15

10

Figure 12. Power-Down Supply Current (Typical)

POWER DISSIPATION

To determine total power dissipation in a specific application,

the following equation should be applied for each output:

28mW

C × V_DD²× f

20mW

C = load capacitance, f = output switching frequency.

13mW

12mW

IDLE (16)

IDLE (128)

10mW

9mW

Example:

In an application where external data memory is used and no other

outputs are active, power dissipation is calculated as follows:

5

8

33.33

52

Assumptions:

FREQUENCY – MHz

•

External data memory is accessed every cycle with 50% of the

address pins switching.

VALID FOR ALL TEMPERATURE GRADES.

1

POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.

2

IDLE REFERS TO ADSP-2187L STATE OF OPERATION DURING EXECUTION OF IDLE

INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER V OR GND.

DD

External data memory writes occur every other cycle with

50% of the data pins switching.

3

4

TYPICAL POWER DISSIPATION AT 3.3V V AND 25؇C EXCEPT WHERE SPECIFIED.

DD

I

MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM INTERNAL

DD

MEMORY. 50% OF THE INSTRUCTIONS ARE MULTIFUNCTION (TYPES 1, 4, 5, 12, 13, 14),

30% ARE TYPE 2 AND TYPE 6, AND 20% ARE IDLE INSTRUCTIONS.

•

Each address and data pin has a 10 pF total load at the pin.

The application operates at V_DD= 3.3 V and t_CK= 34.7 ns.

Figure 13. Power vs. Frequency

REV. A

–16–

ADSP-2185L

CAPACITIVE LOADING

Figures 14 and 15 show the capacitive loading characteristics of

the ADSP-2185L.

INPUT

OR

OUTPUT

1.5V

Figure 16. Voltage Reference Levels for AC Measure-

ments (Except Output Enable/Disable)

18

T = +85؇C

16

V

= 3.0V

DD

Output Enable Time

14

12

10

8

Output pins are considered to be enabled when they have made

a transition from a high-impedance state to when they start

driving. The output enable time (t_ENA) is the interval from when

a reference signal reaches a high or low voltage level to when

the output has reached a specified high or low trip point, see

Figure 17. If multiple pins (such as the data bus) are enabled,

the measurement value is that of the first pin to start driving.

6

4

2

REFERENCE

SIGNAL

0

50

100

150

– pF

200

250

t_MEASURED

t_DIS

C

t_ENA

L

V

OH

(MEASURED)

Figure 14. Typical Output Rise Time vs. Load Capacitance,

C_L(at Maximum Ambient Operating Temperature)

V

(MEASURED) – 0.5V

(MEASURED) +0.5V

2.0V

1.0V

OH

OUTPUT

OL

V

OL

10

9

8

7

6

5

4

3

2

1

t_DECAY

(MEASURED)

OUTPUT STARTS

DRIVING

OUTPUT STOPS

DRIVING

HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE

THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.

Figure 17. Output Enable/Disable

I

OL

NOMINAL

–1

–2

–3

–4

TO

OUTPUT

+1.5V

0

20

40

60

80 100 120 140 160 180 200

– pF

C

L

50pF

Figure 15. Typical Output Valid Delay or Hold vs. Load

Capacitance, C_L(at Maximum Ambient Operating

Temperature)

I

OH

Figure 18. Equivalent Device Loading for AC Measure-

ments (Including All Fixtures)

TEST CONDITIONS

Output Disable Time

ENVIRONMENTAL CONDITIONS

Ambient Temperature Rating is shown below:

Output pins are considered to be disabled when they have

stopped driving and started a transition from the measured out-

put high or low voltage to a high impedance state, see Figure

16. The output disable time (t_DIS) is the difference between

t_MEASUREDand t_DECAY, see Figure 17. The time is the interval

from when a reference signal reaches a high or low voltage level

to when the output voltages have changed by 0.5 V from the

measured output high or low voltage. The decay time, t_DECAY, is

dependent on the capacitive load, C_L, and the current load, i_L,

on the output pin. It can be approximated by the following

equation:

T

_AMB= T_CASE– (PD × θ_CA

)

T_CASE= Case Temperature in °C

PD = Power Dissipation in W

θ_CA= Thermal Resistance (Case-to-Ambient)

θ_JA= Thermal Resistance (Junction-to-Ambient)

θ_JC= Thermal Resistance (Junction-to-Case)

Package

θ_JA

θ_JC

θ_CA

LQFP

50°C/W

2°C/W

48°C/W

C_L• 0.5V

t_DECAY

=

i_L

from which

t_DIS= t_MEASURED– t_DECAY

is calculated. If multiple pins (such as the data bus) are disabled,

the measurement value is that of the last pin to stop driving.

REV. A

–17–

ADSP-2185L

TIMING PARAMETERS (See page 15, Frequency Depending for Timing Specifications, for timing definitions.)

Parameter

Min

Max

Unit

Clock Signals and Reset

Timing Requirements:

t_CKI

t_CKIL

t_CKIH

CLKIN External Clock Period

CLKIN Width Low

CLKIN Width High

38

15

100

ns

Switching Characteristics:

t_CKL

t_CKH

t_CKOH

CLKOUT Width Low

CLKOUT Width High

CLKIN High to CLKOUT High

0.5t_CK– 7

0

ns

20

Control Signals

Timing Requirement:

1

t_RSP

t_MS

t_MH

RESET Width Low

Mode Setup before RESET High

Mode Hold after RESET High

5t_CK

2

5

ns

NOTE

¹Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal

oscillator start-up time).

t_CKI

t_CKIH

CLKIN

t_CKIL

t_CKOH

t_CKH

CLKOUT

t_CKL

PF(3:0)*

t_MH

t_MS

RESET

*PF3 IS MODE D, PF2 IS MODE C, PF1 IS MODE B, PF0 IS MODE A

Figure 19. Clock Signals

REV. A

–18–

ADSP-2185L

Parameter

Min

Max

Unit

Interrupts and Flag

Timing Requirements:

t_IFS

t_IFH

IRQx, FI, or PFx Setup before CLKOUT Low^{1, 2, 3, 4}

IRQx, FI, or PFx Hold after CLKOUT High^{1, 2, 3, 4}

0.25t_CK+ 15

0.25t_CK

ns

Switching Characteristics:

t_FOH

Flag Output Hold after CLKOUT Low⁵

t_FOD

Flag Output Delay from CLKOUT Low⁵

0.25t_CK– 7

ns

0.5t_CK+ 6

NOTES

¹If IRQx and FI inputs meet t_IFSand t_IFHsetup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on

the following cycle. (Refer to Interrupt Controller Operation in the Program Control chapter of the User’s Manual for further information on interrupt servicing.)

²Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced.

³IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQE.

⁴PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.

⁵Flag outputs = PFx, FL0, FL1, FL2, Flag_out.

t_FOD

CLKOUT

t_FOH

FLAG

OUTPUTS

t_IFH

IRQx

FI

PFx

t_IFS

Figure 20. Interrupts and Flags

REV. A

–19–

ADSP-2185L

Parameter

Min

Max

Unit

Bus Request–Bus Grant

Timing Requirements:

t_BH

t_BS

BR Hold after CLKOUT High¹

BR Setup before CLKOUT Low¹

0.25t_CK+ 2

0.25t_CK+ 17

ns

Switching Characteristics:

t_SD

t_SDB

t_SE

t_SEC

t_SDBH

t_SEH

CLKOUT High to xMS, RD, WR Disable

0.25t_CK+ 10

ns

xMS, RD, WR Disable to BG Low

BG High to xMS, RD, WR Enable

xMS, RD, WR Enable to CLKOUT High

xMS, RD, WR Disable to BGH Low²

BGH High to xMS, RD, WR Enable²

0

0.25t_CK– 7

0

NOTES

xMS = PMS, DMS, CMS, IOMS, BMS.

¹BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on

the following cycle. Refer to the ADSP-2100 Family User’s Manual, Third Edition for BR/BG cycle relationships.

²BGH is asserted when the bus is granted and the processor requires control of the bus to continue.

t_BH

CLKOUT

BR

t_BS

CLKOUT

PMS, DMS

BMS, RD

t_SD

t_SEC

WR

BG

t_SDB

t_SE

BGH

t_SDBH

t_SEH

Figure 21. Bus Request–Bus Grant

REV. A

–20–

ADSP-2185L

Parameter

Min

Max

Unit

Memory Read

Timing Requirements:

t_RDD

t_AA

t_RDH

RD Low to Data Valid

A0–A13, xMS to Data Valid

Data Hold from RD High

0.5t_CK– 9 + w

0.75t_CK– 12.5 + w

ns

1

Switching Characteristics:

t_RP

RD Pulsewidth

CLKOUT High to RD Low

A0–A13, xMS Setup before RD Low

A0–A13, xMS Hold after RD Deasserted

RD High to RD or WR Low

0.5t_CK– 5 + w

0.25t_CK– 5

0.25t_CK– 6

0.25t_CK– 3

0.5t_CK– 5

ns

t_CRD

t_ASR

t_RDA

t_RWR

0.25t_CK+ 7

w = wait states x t_CK

xMS = PMS, DMS, CMS, IOMS, BMS.

CLKOUT

A0–A13

DMS, PMS,

BMS, IOMS,

CMS

t_RDA

RD

D

t_ASR

t_CRD

t_RP

t_RWR

t_RDD

t_RDH

t_AA

WR

Figure 22. Memory Read

REV. A

–21–

ADSP-2185L

Parameter

Min

Max

Unit

Memory Write

Switching Characteristics:

t_DW

t_DH

t_WP

t_WDE

t_ASW

t_DDR

t_CWR

t_AW

Data Setup before WR High

Data Hold after WR High

WR Pulsewidth

WR Low to Data Enabled

A0–A13, xMS Setup before WR Low

Data Disable before WR or RD Low

CLKOUT High to WR Low

A0–A13, xMS, Setup before Deasserted

A0–A13, xMS Hold after WR Deasserted

WR High to RD or WR Low

0.5t_CK– 7 + w

0.25t_CK– 2

0.5t_CK– 5 + w

0

0.25t_CK– 6

0.25t_CK– 7

0.25t_CK– 5

0.75t_CK– 9 + w

0.25t_CK– 3

0.5t_CK– 5

ns

0.25 t_CK+ 7

t_WRA

t_WWR

w = wait states x t_CK

.

xMS = PMS, DMS, CMS, IOMS, BMS.

CLKOUT

A0–A13

DMS, PMS,

BMS, CMS,

IOMS

t_WRA

WR

t_WWR

t_ASW

t_WP

t_AW

t_DH

t_DDR

t_CWR

D

t_DW

t_WDE

RD

Figure 23. Memory Write

REV. A

–22–

ADSP-2185L

Parameter

Min

Max

Unit

Serial Ports

Timing Requirements:

t_SCK

t_SCS

t_SCH

t_SCP

SCLK Period

50

4

8

ns

DR/TFS/RFS Setup before SCLK Low

DR/TFS/RFS Hold after SCLK Low

SCLK_INWidth

15

Switching Characteristics:

t_CC

CLKOUT High to SCLK_OUT

SCLK High to DT Enable

SCLK High to DT Valid

TFS/RFS_OUTHold after SCLK High

TFS/RFS_OUTDelay from SCLK High

DT Hold after SCLK High

TFS (Alt) to DT Enable

TFS (Alt) to DT Valid

0.25t_CK

0

0.25t_CK+ 10

ns

t_SCDE

t_SCDV

t_RH

15

0

t_RD

t_SCDH

t_TDE

t_TDV

t_SCDD

t_RDV

0

14

15

SCLK High to DT Disable

RFS (Multichannel, Frame Delay Zero) to DT Valid

CLKOUT

t_CC

t_SCK

SCLK

t_SCP

t_SCS

t_SCH

DR

TFS

IN

RFS

IN

t_RD

t_RH

RFS

TFS

OUT

t_SCDD

t_SCDV

t_SCDH

t_SCDE

DT

t_TDE

t_TDV

TFS

OUT

ALTERNATE

FRAME MODE

t_RDV

RFS

OUT

MULTICHANNEL MODE,

FRAME DELAY 0

(MFD = 0)

t_TDE

t_TDV

TFS

IN

ALTERNATE

FRAME MODE

t_RDV

RFS

IN

MULTICHANNEL MODE,

FRAME DELAY 0

(MFD = 0)

Figure 24. Serial Ports

REV. A

–23–

ADSP-2185L

Parameter

Min

Max

Unit

IDMA Address Latch

Timing Requirements:

t_IALP

t_IASU

t_IAH

t_IKA

t_IALS

t_IALD

Duration of Address Latch^{1, 2}

10

5

3

0

3

ns

IAD15–0 Address Setup before Address Latch End²

IAD15–0 Address Hold after Address Latch End²

IACK Low before Start of Address Latch^{2, 3}

Start of Write or Read after Address Latch End^{2, 3}

Address Latch Start after Address Latch End^{1, 2}

2

NOTES

¹Start of Address Latch = IS Low and IAL High.

²End of Address Latch = IS High or IAL Low.

³Start of Write or Read = IS Low and IWR Low or IRD Low.

IACK

t_IKA

t_IALD

IAL

t_IALP

IS

IAD15–0

t_IASU

t_IAH

t_IALS

RD OR WR

Figure 25. IDMA Address Latch

REV. A

–24–

ADSP-2185L

Parameter

Min

Max

Unit

IDMA Write, Short Write Cycle

Timing Requirements:

t_IKW

t_IWP

t_IDSU

t_IDH

IACK Low before Start of Write¹

0

15

5

ns

Duration of Write^{1, 2}

IAD15–0 Data Setup before End of Write^{2, 3, 4}

IAD15–0 Data Hold after End of Write^{2, 3, 4}

2

Switching Characteristic:

t_IKHW

Start of Write to IACK High

4

15

ns

NOTES

¹Start of Write = IS Low and IWR Low.

²End of Write = IS High or IWR High.

³If Write Pulse ends before IACK Low, use specifications t_IDSU, t_IDH

.

⁴If Write Pulse ends after IACK Low, use specifications t_IKSU, t_IKH

.

t_IKW

IACK

t_IKHW

IS

t_IWP

IWR

t_IDH

t_IDSU

DATA

IAD15–0

Figure 26. IDMA Write, Short Write Cycle

REV. A

–25–

ADSP-2185L

Parameter

Min

Max

Unit

IDMA Write, Long Write Cycle

Timing Requirements:

t_IKW

t_IKSU

t_IKH

IACK Low before Start of Write¹

0

ns

IAD15–0 Data Setup before IACK Low^{2, 3, 4}

IAD15–0 Data Hold after IACK Low^{2, 3, 4}

0.5t_CK+ 10

2

Switching Characteristics:

t_IKLW

Start of Write to IACK Low⁴

t_IKHWStart of Write to IACK High

1.5t_CK

4

ns

15

NOTES

¹Start of Write = IS Low and IWR Low.

²If Write Pulse ends before IACK Low, use specifications t_IDSU, t_IDH

.

³If Write Pulse ends after IACK Low, use specifications t_IKSU, t_IKH

.

⁴This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User’s Manual, Third Edition.

t_IKW

IACK

t_IKHW

t_IKLW

IS

IWR

t_IKSU

t_IKH

DATA

IAD15–0

Figure 27. IDMA Write, Long Write Cycle

REV. A

–26–

ADSP-2185L

Parameter

Min

Max

Unit

IDMA Read, Long Read Cycle

Timing Requirements:

t_IKR

t_IRK

IACK Low before Start of Read¹

0

2

ns

End of Read after IACK Low²

Switching Characteristics:

t_IKHR

t_IKDS

t_IKDH

t_IKDD

t_IRDE

t_IRDV

t_IRDH1

t_IRDH2

IACK High after Start of Read¹

4

15

ns

IAD15–0 Data Setup before IACK Low

0.5t_CK– 7

0

IAD15–0 Data Hold after End of Read²

IAD15–0 Data Disabled after End of Read²

10

15

IAD15–0 Previous Data Enabled after Start of Read

IAD15–0 Previous Data Valid after Start of Read

IAD15–0 Previous Data Hold after Start of Read (DM/PM1)³

IAD15–0 Previous Data Hold after Start of Read (PM2)⁴

0

2t_CK– 5

t_CK– 5

NOTES

¹Start of Read = IS Low and IRD Low.

²End of Read = IS High or IRD High.

³DM read or first half of PM read.

⁴Second half of PM read.

IACK

IS

t_IKHR

t_IKR

t_IRK

IRD

t_IKDH

t_IKDS

t_IRDE

READ

DATA

IAD15–0

t_IRDV

t_IKDD

t_IRDH

Figure 28. IDMA Read, Long Read Cycle

REV. A

–27–

ADSP-2185L

Parameter

Min

Max

Unit

IDMA Read, Short Read Cycle

Timing Requirements:

t_IKR

t_IRP

IACK Low before Start of Read¹

Duration of Read

0

15

ns

Switching Characteristics:

t_IKHR

t_IKDH

t_IKDD

t_IRDE

t_IRDV

IACK High after Start of Read¹

4

0

15

10

15

ns

IAD15–0 Data Hold after End of Read²

IAD15–0 Data Disabled after End of Read²

IAD15–0 Previous Data Enabled after Start of Read

IAD15–0 Previous Data Valid after Start of Read

0

NOTES

¹Start of Read = IS Low and IRD Low.

²End of Read = IS High or IRD High.

IACK

IS

t_IKR

t_IKHR

t_IRP

IRD

t_IRDE

t_IKDH

IAD15–0

t_IKDD

t_IRDV

Figure 29. IDMA Read, Short Read Cycle

REV. A

–28–

ADSP-2185L

100-Lead LQFP Package Pinout

75

74

A4/IAD3

A5/IAD4

1

2

D15

D14

PIN 1

IDENTIFIER

73

GND

3

D13

72

71

A6/IAD5

A7/IAD6

4

5

D12

GND

70

69

6

7

A8/IAD7

A9/IAD8

D11

D10

68

8

9

A10/IAD9

D9

67

66

A11/IAD10

VDD

GND

A12/IAD11 10

65

A13/IAD12 11

GND 12

D8

64 D7/IWR

ADSP-2185L

D6/IRD

63

CLKIN 13

TOP VIEW

(Not to Scale)

D5/IAL

D4/IS

62

61

XTAL 14

VDD 15

60

59

CLKOUT 16

GND 17

GND

VDD

D3/IACK

58

57

VDD 18

WR

D2/IAD15

19

RD

56 D1/IAD14

55

20

BMS

D0/IAD13

54 BG

21

DMS

PMS

22

23

EBG

53

BR

IOMS

CMS

52

51

24

25

EBR

REV. A

–29–

ADSP-2185L

The ADSP-2185L package pinout is shown in the table below. Pin names in bold text replace the plain text named functions when

Mode C = 1. A + sign separates two functions when either function can be active for either major I/O mode. Signals enclosed in

brackets [ ] are state bits latched from the value of the pin at the deassertion of RESET.

LQFP Pin Configurations

LQFP

Number

Name

LQFP

Number

Name

LQFP

Number

Name

LQFP

Number

Name

1

2

3

4

5

6

7

8

A4/IAD3

A5/IAD4

GND

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

IRQE + PF4

IRQL0 + PF5

GND

IRQL1 + PF6

IRQ2 + PF7

DT0

TFS0

RFS0

DR0

SCLK0

VDD

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

EBR

BR

EBG

BG

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

D16

D17

D18

D19

GND

D20

D21

D22

D23

FL2

FL1

FL0

PF3

PF2 [Mode C]

VDD

PWD

GND

PF1 [Mode B]

PF0 [Mode A]

BGH

PWDACK

A0

A1/IAD0

A2/IAD1

A3/IAD2

A6/IAD5

A7/IAD6

A8/IAD7

A9/IAD8

A10/IAD9

A11/IAD10

A12/IAD11

A13/IAD12

GND

CLKIN

XTAL

VDD

CLKOUT

GND

VDD

WR

RD

BMS

DMS

PMS

IOMS

CMS

D0/IAD13

D1/IAD14

D2/IAD15

D3/IACK

VDD

GND

D4/IS

D5/IAL

D6/IRD

D7/IWR

D8

GND

VDD

D9

D10

D11

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

DT1

TFS1

RFS1

DR1

GND

SCLK1

ERESET

RESET

EMS

EE

GND

D12

D13

D14

D15

ECLK

ELOUT

ELIN

EINT

REV. A

–30–

ADSP-2185L

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

100-Lead Metric Thin Plastic Quad Flatpack (LQFP)

(ST-100)

0.640 (16.25)

TYP SQ

0.630 (16.00)

0.620 (15.75)

0.553 (14.05)

0.551 (14.00)

0.549 (13.95)

0.063 (1.60) MAX

0.472 (12.00) BSC

0.030 (0.75)

0.024 (0.60) TYP

0.020 (0.50)

100

1

76

75

12°

TYP

SEATING

PLANE

TOP VIEW

(PINS DOWN)

0.004

(0.102)

MAX LEAD

COPLANARITY

25

26

51

50

6° ± 4°

0° – 7°

0.020 (0.50)

BSC

0.007 (0.177)

0.011 (0.27)

0.005 (0.127) TYP

0.003 (0.077)

0.009 (0.22) TYP

0.007 (0.17)

LEAD PITCH

LEAD WIDTH

NOTE:

THE ACTUAL POSITION OF EACH LEAD IS WITHIN (0.08)

0.0032 FROM ITS IDEAL POSITION WHEN MEASURED IN THE

LATERAL DIRECTION.

CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED

ORDERING GUIDE

Instruction

Ambient

Temperature

Range

Rate

(MHz)

Package

Description

Package

Option*

Part Number

ADSP-2185LKST-115

ADSP-2185LBST-115

ADSP-2185LKST-133

ADSP-2185LBST-133

ADSP-2185LBST-160

ADSP-2185LKST-210

ADSP-2185LBST-210

0°C to +70°C

–40°C to +85°C

0°C to +70°C

–40°C to +85°C

0°C to +70°C

–40°C to +85°C

28.8

33.3

40

100-Lead LQFP

ST-100

52

*ST = Plastic Thin Quad Flatpack (LQFP).

REV. A

–31–


型号：	ADSP-2185L
厂家：	ADI
描述：	DSP Microcomputer 微电脑DSP 电脑
文件：	总31页 (文件大小：224K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADSP-2185L [ADI]

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