ADP2370ACPZ-1.5-R7 [ADI]
High Voltage, 1.2 MHz/600 kHz, 800 mA; 高电压， 1.2 MHz的/ 600千赫， 800毫安
| 型号： | ADP2370ACPZ-1.5-R7 |
| 厂家： | 
ADI |
| 描述： | High Voltage, 1.2 MHz/600 kHz, 800 mA |
| 文件： | 总32页 (文件大小：2227K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Voltage, 1.2 MHz/600 kHz, 800 mA,
Low Quiescent Current Buck Regulator
Data Sheet
ADP2370/ADP2371
FEATURES
TYPICAL APPLICATION CIRCUIT
V
= 6V
IN
Input voltage range: 3.2 V to 15 V, output current: 800 mA
Quiescent current < 14 µA in power saving mode (PSM)
>90% efficiency
C
IN
10µF
POWER GOOD
Force PWM pin (SYNC), 600 kHz/1.2 MHz frequency pin
(FSEL)
Fixed outputs: 0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.0 V, 3.3 V, 5 V,
and adjustable option
100% duty cycle capability
Initial accuracy: 1%
ADP2370/
ADP2371
VIN
PGND
1
2
3
4
8
7
6
5
1.2MHz
V
= 3.3V
OUT
SW
PG
FSEL
EN
600kHz
C
OUT
ON
10µF
OFF
Low shutdown current: <1.2 µA
AGND
(EXPOSED PAD)
Quick output discharge (QOD) option
Synchronizable to an external clock
8-lead, 0.75 mm × 3 mm × 3 mm LFCSP (QFN) package
Supported by ADIsimPower design tool
SYNC
FB
Figure 1.
APPLICATIONS
Portable and battery-powered equipment
Automatic meter readers (WSN)
Point of sales and transaction processing instruments
Medical instruments
Medium format display tablets and pads
GENERAL DESCRIPTION
The ADP2370/ADP2371 are high efficiency, low quiescent current,
800 mA buck (step-down) dc-to-dc converters in small 8-lead,
3 mm × 3 mm LFCSP (QFN) packages. The total solution requires
only three tiny external components.
A power-good output is available to indicate when the output
voltage is below 92% of its nominal value.
The ADP2371 is identical to the ADP2370 except that the
ADP2371 includes the addition of an integrated switched
resistor, quick output discharge function (QOD) that auto-
matically discharges the output when the device is disabled.
The buck regulator uses a proprietary high speed current mode,
constant frequency PWM control scheme for excellent stability
and transient response. The need for an external rectifier is elimi-
nated by using a high efficiency synchronous rectifier architecture.
Both devices include an internal power switch and a synchronous
rectifier for minimal external part count and high efficiency.
The ADP2370/ADP2371 also include internal soft start and
internal compensation for ease of use.
To ensure the longest battery life in portable applications, the
ADP2370/ADP2371 employ a power saving variable frequency
mode that reduces the switching frequency under light load
conditions. The ADP2370/ADP2371 operate from input voltages
of 3.2 V to 15 V allowing the use of multiple alkaline/NiMH,
lithium cells, or other standard power sources.
During a logic controlled shutdown, the input is disconnected
from the output and the regulator draws less than 1.2 μA from
the input source. Other key features include undervoltage lockout
to prevent deep battery discharge and soft start to prevent input
overcurrent at startup. Short-circuit protection and thermal over-
load protection circuits prevent damage under adverse conditions.
The ADP2370/ADP2371 offer multiple options for setting the
operational frequency. The ADP2370/ADP2371 can be synchro-
nized to a 600 kHz to 1.2 MHz external clock or it can be forced
to operate at 600 kHz or 1.2 MHz via the FSEL pin. The ADP2370/
ADP2371 can be forced to operate in PWM mode (FPWM)
when noise considerations are more important than efficiency.
The ADP2370/ADP2371 each use one 0805 capacitor, one 1206
capacitor, and one 4 mm × 4 mm inductor. The total solution
size is about 53 mm2 resulting in a very small footprint solution
to meet a variety of portable applications.
Rev. A
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rightsof third parties that may result fromits use. Specifications subject to change without notice. No
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Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2012 Analog Devices, Inc. All rights reserved.
ADP2370/ADP2371
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Undervoltage Lockout ............................................................... 22
Thermal Protection.................................................................... 22
Soft Start ...................................................................................... 22
Current Limit.............................................................................. 22
100% Duty Cycle ........................................................................ 23
Synchronizing ............................................................................. 23
Power Good ................................................................................ 24
Applications Information.............................................................. 25
ADIsimPower Design Tool ....................................................... 25
External Component Selection ................................................ 25
Selecting the Inductor................................................................ 25
Output Capacitor........................................................................ 25
Input Capacitor........................................................................... 25
Adjustable Output Voltage Programming .............................. 25
Efficiency..................................................................................... 26
Recommended Buck External Components .......................... 26
Capacitor Selection .................................................................... 28
Thermal Considerations................................................................ 29
PCB Layout Considerations...................................................... 30
Packaging and Ordering Information ......................................... 32
Outline Dimensions................................................................... 32
Ordering Guide .......................................................................... 32
Applications....................................................................................... 1
Typical Application Circuit ............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Recommended Specifications: Capacitors................................ 5
Absolute Maximum Ratings ....................................................... 6
Thermal Data................................................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Buck Output.................................................................................. 8
Theory of Operation ...................................................................... 20
PWM Operation......................................................................... 20
PSM Operation ........................................................................... 21
Features Descriptions..................................................................... 22
Precision Enable ......................................................................... 22
Forced PWM or PWM/PSM Selection.................................... 22
Quick Output Discharge (QOD) Function............................. 22
Short-Circuit Protection............................................................ 22
REVISION HISTORY
5/12—Rev. 0 to Rev. A
Changed Voltage Range for SW to PGND and Ground Plane
from −0.3 V to VIN + 0.3 V to −0.7 V to VIN + 0.3 V ............... 6
Changes to Ordering Guide .......................................................... 32
4/12—Revision 0: Initial Version
Rev. A | Page 2 of 32
Data Sheet
ADP2370/ADP2371
SPECIFICATIONS
VIN = VOUT + 1 V or 3.2 V, whichever is greater, EN = VIN, IOUT = 100 mA, CIN = 10 μF, COUT = 10 µF, TA = 25°C for typical specifications,
TJ = −40°C to +125°C for minimum/maximum specifications, unless otherwise noted.
Table 1.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
SUPPLY
Input Voltage Range
Quiescent Current
VIN
IQ-PSM
3.2
15
V
μA
FSEL = VIN, SYNC = 0 V, no load, device not
switching
FSEL = VIN, SYNC = VIN, no load, device not
switching
13.5
725
IQ-PWM
μA
ISW-PWM
ISHUT
FSEL = VIN, SYNC = VIN, no load, device switching
EN = GND, TJ = −40°C to +85°C
5.7
1.2
mA
μA
Shutdown Current
FIXED OUTPUT
3.5
Output Current
Fixed Output Accuracy
IOUT
VOUT
800
−1
−1.5
−3
mA
%
%
Initial set point, IOUT = 250 mA, TJ = 25°C
IOUT = 250 mA
No load to full load, PWM mode
+1
+1.5
+3
%
ADJUSTABLE OUTPUT
Feedback Voltage
Feedback Voltage Accuracy
Output Voltage Range
FIXED AND ADJUSTABLE OUTPUT
Load Regulation
VFB
VFB-TOL
VOUT-ADJ
0.8
V
%
V
Initial set point, IOUT = 250 mA, TJ = 25°C
No load to full load
−1
0.8
+1
14
∆VOUT/∆IOUT
∆VOUT/∆VIN
EFF
No load to full load
IOUT = 250 mA
IOUT = 250 mA, VIN = 7.2 V, VOUT = 3.3 V
0.125
0.01
92
%/A
%/V
%
Line Regulation
Efficiency
Overcurrent Frequency Foldback Threshold
Rising
Falling
OCFOLDBACK-RISE % of VOUT, VOUT rising
OCFOLDBACK-FALL % of VOUT, VOUT falling
PSMTHRESHOLD VIN = 7.2 V, VOUT = 3.3 V
50
37.5
170
%
%
mA
PSM Threshold
Feedback Pin Input Current
Fixed
Adjustable
IFB-FIXED
IFB-ADJUST
ON-TIMEMIN
Fixed output voltage model
Adjustable output voltage model
VIN < 5.5 V
2.5
10
65
40
350
260
μA
nA
ns
ns
μs
Ω
Minimum On Time
100
60
VIN > 5.5 V
Soft Start Time
Active Pull-Down Resistance
(ADP2371)
SSTIME
RPULL-DOWN
When EN rises from 0 V to VIN, and VOUT = 0.9 × VOUT
400
POWER SWITCH
P-Channel On Resistance
RDSON-P
RDSON-N
VIN > 5.5 V, IOUT = 400 mA
VIN < 5.5 V, IOUT = 400 mA
VIN > 5.5 V, IOUT = 400 mA
VIN < 5.5 V, IOUT = 400 mA
400
500
280
400
mΩ
mΩ
mΩ
mΩ
N-Channel On Resistance
Current Limit
P-Channel
N-Channel
ILIM-P
ILIM-N
Peak inductor current
Peak inductor current
1200 1300 mA
500
550
mA
Leakage Current
P-Channel
N-Channel
ILEAK-SW
0.01
0.01
1
1
μA
μA
OSCILLATOR
Oscillator Frequency
fOSC
FSEL = VIN, 3.2 V ≤ VIN ≤ 15 V
FSEL = 0 V, 3.2 V ≤ VIN ≤ 15 V
1.0
500
1.2
600
1.4
700
MHz
kHz
Rev. A | Page 3 of 32
ADP2370/ADP2371
Data Sheet
Parameter
Symbol
Test Conditions/Comments
FSEL = 0 V, 3.2 V ≤ VIN ≤ 15 V
FSEL = VIN, 3.2 V ≤ VIN ≤ 15 V
Min
400
0.8
Typ
Max
800
1.6
Unit
kHz
MHz
Frequency Synchronization Range
fSYNC_RANGE
Synchronization Threshold
High
Low
SYNCHIGH
SYNCLOW
SYNCHYS
SYNCDUTY
3.2 V ≤ VIN ≤ 15 V
3.2 V ≤ VIN ≤ 15 V
3.2 V ≤ VIN ≤ 15 V
VIN (1.2 MHz), 3.2 V ≤ VIN ≤ 5 V, FSEL = VIN
VIN (1.2 MHz), 5 V ≤ VIN ≤ 15 V, FSEL = VIN
SYNC = 0 V or SYNC = VIN
3.2 V ≤ VIN ≤ 15 V
1.2
V
V
mV
%
%
0.4
Hysteresis
Typical Sync Duty Cycle Range
200
20
20
55
70
1
SYNC Pin Leakage Current
FSEL Threshold
High
Low
Hysteresis
FSEL Pin Leakage Current
POWER GOOD (PG PIN)
PG Threshold
Rising
Falling
Hysteresis
PG Output Low
PG Delay
SYNCLKG
0.05
μA
FESLHIGH
FSELLOW
FSELHYS
FSELLKG
1
V
V
mV
μA
0.4
1
125
0.04
FSEL = 0 V or FSEL = VIN
3.2 V ≤ VIN ≤ 15 V
PGRISE
PGFALL
PGHYS
PGLOW
92
87
5
95
%
%
%
V
82.5
Pull-up current < 1 mA
0.3
Rising
PGDELAYRISE
PGDELAYFALL
PGLKG
VOUT crossing PG rising threshold, pull-up
current < 1 mA
VOUT crossing PG falling threshold, pull-up
current < 1 mA
20
μs
μs
μA
Falling
0.5
0.04
PG Leakage
1
UNDERVOLTAGE LOCKOUT (UVLO)
Input Voltage Rising
Input Voltage Falling
Hysteresis
UVLORISE
UVLOFALL
UVLOHYS
3.19
V
V
mV
2.80
1
190
125
ENABLE INPUT STANDBY (EN PIN)
EN Input Logic
3.2 V ≤ VIN ≤ 15 V
3.2 V ≤ VIN ≤ 15 V
EN = VIN or GND
V
High
Low
Hysteresis
ENSTBY-HIGH
ENSTBY-LOW
ENSTBY-HYS
0.4
V
mV
ENABLE INPUT PRECISION (EN PIN)
EN Input Logic
High
Low
ENHIGH
ENLOW
ENHYS
IEN-LKG
TIEN-DLY
1.135 1.2
1.045 1.1
100
1.26
1.155
V
V
mV
µA
μs
Hysteresis
EN Input Leakage Current
EN Input Delay Time
0.05
70
1
For VOUT = 0 V to 0.1 × VOUT when EN rises from
0 V to VIN
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
3.2 V ≤ VIN ≤ 15 V
TJ rising
TSSD
TSSD-HYS
150
15
°C
°C
Rev. A | Page 4 of 32
Data Sheet
ADP2370/ADP2371
RECOMMENDED SPECIFICATIONS: CAPACITORS
Table 2.
Parameter
MINIMUM INPUT and OUTPUT CAPACITANCE1
Symbol
Test Conditions/Comments
TA = −40°C to +125°C
Min
6.5
1
Typ
Max
Unit
µF
CMIN
RESR
10
TA = −40°C to +125°C
CAPACITOR ESR
10
mΩ
1 The minimum input and output capacitance should be greater than 7 μF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R- and X5R-type capacitors are recommended;
Y5V and Z5U capacitors are not recommended for use with any buck.
Rev. A | Page 5 of 32
ADP2370/ADP2371
Data Sheet
ABSOLUTE MAXIMUM RATINGS
attention to thermal board design is required. The value of θJA can
vary, depending on PCB material, layout, and environmental con-
ditions.
Table 3.
Parameter
Rating
VIN to PGND and Ground Plane
SW to PGND and Ground Plane
FB to PGND and Ground Plane
EN to PGND and Ground Plane
PG to PGND and Ground Plane
SYNC to PGND and Ground Plane
FSEL to PGND and Ground Plane
Temperature Range
−0.3 V to +17 V
−0.7 V to VIN + 0.3 V
−0.3 V to +6 V
−0.3 V to +17 V
−0.3 V to +17 V
−0.3 V to +17 V
−0.3 V to +17 V
The specified values of θJA are based on a 4-layer, 4 in. × 3 in.
circuit board. See JESD 51-7, High Effective Thermal Conduc-
tivity Test Board for Leaded Surface Mount Packages, for detailed
information on board construction. For more information, see
Application Note AN-772, A Design and Manufacturing Guide for
the Lead Frame Chip Scale Package (LFCSP).
ΨJB is the junction to board thermal characterization parameter
with units of °C/W. The ΨJB of the package is based on modeling
and calculation using a 4-layer board. The JESD51-12, Guidelines
for Reporting and Using Electronic Package Thermal Information,
states that thermal characterization parameters are not the same
as thermal resistances. ΨJB measures the component power flowing
through multiple thermal paths rather than a single path as in
thermal resistance, θJB. Therefore, ΨJB thermal paths include
convection from the top of the package as well as radiation
from the package, factors that make ΨJB more useful in real-
world applications. Maximum junction temperature (TJ) is
calculated from the board temperature (TB) and power
dissipation (PD) using the formula
Storage
Operating Ambient
Operating Junction
Soldering Conditions
−65°C to +150°C
−40°C to +85°C
−40°C to +125°C
JEDEC J-STD-020
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
TJ = TB + (PD × ΨJB)
Absolute maximum ratings apply individually only, not in com-
bination. Exceeding the junction temperature (TJ) limit can
cause damage to the ADP2370/ADP2371. Monitoring ambient
temperature does not guarantee that TJ is within the specified
temperature limits. The maximum ambient temperature may
require derating in applications with high power dissipation and
poor thermal resistance.
For more detailed information regarding ΨJB, see JESD51-12
and JESD51-8, Integrated Circuit Thermal Test Method Envi-
ronmental Conditions—Junction-to-Board.
THERMAL RESISTANCE
θJA and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
In applications with moderate power dissipation and low
printed circuit board (PCB) thermal resistance, the maximum
ambient temperature can exceed the maximum limit as long
as the junction temperature is within specification limits. The
junction temperature of the device is dependent on the ambient
temperature, the power dissipation of the device, and the junction
to ambient thermal resistance of the package (θJA).
θ
JC is a parameter for surface-mount packages with top mounted
heat sinks.
Table 4. Thermal Resistance
Package Type
θJA
θJC
ΨJB
Unit
8-Lead 3 mm × 3 mm LFCSP
36.7
23.5 17.2 °C/W
Maximum junction temperature (TJ) is calculated from the
ambient temperature (TA) and power dissipation (PD) using
the formula
ESD CAUTION
TJ = TA + (PD × θJA)
Junction-to-ambient thermal resistance (θJA) of the package is
based on modeling and calculation using a 4-layer board. θJA is
highly dependent on the application and board layout. In applica-
tions where high maximum power dissipation exists, close
Rev. A | Page 6 of 32
Data Sheet
ADP2370/ADP2371
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADP2370/ADP2371
VIN
FSEL
EN
1
2
3
4
8
7
6
5
PGND
SW
TOP VIEW
(Not to
Scale)
PG
FB
SYNC
NOTES
1. THE EXPOSED PAD ON THE BOTTOM OF THE PACKAGE ENHANCES
THE THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED
TO GROUND INSIDE THE PACKAGE. THE EXPOSED PAD MUST BE
CONNECTED TO THE GROUND PLANE ON THE CIRCUIT BOARD
FOR PROPER OPERATION.
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
3
4
VIN
FSEL
EN
SYNC
Power Input.
Frequency Select. High = 1.2 MHz, low = 600 kHz.
Enable. Enable input with precision thresholds.
Synchronize. This pin is used to synchronize the device to an external 600 kHz to 1.2 MHz clock or forces
PWM mode when it is held high. SYNC held low forces automatic PWM/PSM operation.
5
6
7
8
FB
PG
SW
PGND
EPAD
Feedback. This pin provides feedback from the output.
Power Good. PG is an open-drain output.
Switch. This pin serves as the connection from the power MOSFETs to the inductor.
Power Ground.
Exposed Pad. The exposed pad on the bottom of the package enhances the thermal performance and is
electrically connected to ground inside the package. The exposed pad must be connected to the ground
plane on the circuit board for proper operation.
Rev. A | Page 7 of 32
ADP2370/ADP2371
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
BUCK OUTPUT
Using recommended inductor values, IOUT = 10 mA, CIN = COUT = 10 µF, automatic PSM/PWM mode, TA = 25°C, unless otherwise noted.
1.30
1.28
1.26
1.24
1.22
1.20
1.18
1.16
1.14
1.12
1.10
0.65
0.63
0.61
0.59
0.57
0.55
25
20
15
10
5
600kHz
1.2MHz
+125°C
+85°C
+25°C
–5°C
–40°C
0
3
5
7
9
11
13
15
3
4
5
6
7
8
9
10 11 12 13 14 15 16
TEMPERATURE (°C)
INPUT VOLTAGE (V)
Figure 3. Quiescent Supply Current vs. Input Voltage, Nonswitching,
Different Temperatures
Figure 6. Switching Frequency vs. Input Voltage, FPWM Mode
800
3.40
3.35
3.30
+125°C
+85°C
+25°C
–5°C
–40°C
750
700
650
600
550
500
3.25
0.1mA
3.20
3.15
3.10
1mA
5mA
10mA
50mA
100mA
300mA
800mA
3
4
5
6
7
8
9
10 11 12 13 14 15
–40
–5
25
85
125
INPUT VOLTAGE (V)
TEMPERATURE (°C)
Figure 4. FPWM Quiescent Supply Current vs. Input Voltage, Nonswitching,
Different Temperatures
Figure 7. Output Voltage vs. Temperature, VOUT = 3.3 V, VIN = 7.3 V,
Different Loads
1.30
1.28
1.26
1.24
1.22
1.20
1.18
1.16
1.14
1.12
1.10
0.65
0.63
0.61
0.59
0.57
0.55
5.20
5.15
5.10
5.05
600kHz
1.2MHz
5.00
0.1mA
1mA
4.95
4.90
4.85
5mA
10mA
50mA
100mA
300mA
800mA
4.80
–40
–45
–25
–5
15
35
55
75
95
115
135
–5
25
85
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 5. Switching Frequency vs. Temperature, FPWM Mode, VIN = 8 V
Figure 8. Output Voltage vs. Temperature, VOUT = 5 V, VIN = 7.2 V,
Different Loads
Rev. A | Page 8 of 32
Data Sheet
ADP2370/ADP2371
1.25
1.23
1.21
1.19
3.40
3.35
3.30
3.25
3.20
3.15
3.10
3.8V
4.55V
6.05V
7.30V
10.55V
12.05V
15.05V
0.1mA
1mA
5mA
10mA
50mA
100mA
300mA
800mA
1.17
1.15
–40
–5
25
85
125
0.1
1
10
100
1000
TEMPERATURE (°C)
LOAD (mA)
Figure 12. Load Regulation, VOUT = 3.3 V
Figure 9. Output Voltage vs. Temperature, VOUT = 1.2 V, VIN = 4 V,
Different Loads
1.90
3.40
3.35
3.30
3.25
3.20
3.15
3.10
1.85
1.80
0.1mA
1mA
5mA
10mA
50mA
100mA
300mA
800mA
0.1mA
1m
A
5mA
1.75
10mA
50mA
100mA
300mA
800mA
1.70
3
5
7
9
11
13
15
–40
–5
25
85
125
INPUT VOLTAGE (V)
TEMPERATURE (°C)
Figure 10. Output Voltage vs. Temperature, VOUT = 1.8 V, VIN = 7.2 V,
Different Loads
Figure 13. Line Regulation, VOUT = 5.0 V, Different Loads
3.40
3.35
3.30
5.20
5.15
5.10
5.05
5.00
4.95
4.90
4.85
4.80
3.25
0.1mA
5.40V
3.20
3.15
3.10
1mA
6.00V
5mA
7.20V
10mA
50mA
100mA
300mA
800mA
9.00V
10.80V
12.00V
15.05V
3
5
7
9
11
13
15
0.1
1
10
100
1000
INPUT VOLTAGE (V)
LOAD (mA)
Figure 11. Line Regulation, VOUT = 3.3 V, Different Loads
Figure 14. Load Regulation, VOUT = 5.0 V
Rev. A | Page 9 of 32
ADP2370/ADP2371
Data Sheet
1.25
1.24
1.23
1.22
1.21
1.20
1.90
1.85
1.80
1.75
1.70
3.20V
3.95V
5.45V
7.20V
9.95V
11.95V
15.20V
1.19
0.1mA
1mA
1.18
1.17
1.16
1.15
5mA
10mA
50mA
100mA
300mA
800mA
3
5
7
9
11
13
15
0.1
1
10
100
1000
INPUT VOLTAGE (V)
LOAD (mA)
Figure 15. Line Regulation, VOUT = 1.2 V, Different Loads
Figure 18. Load Regulation, VOUT = 1.8 V
1.25
1.24
1.23
1.22
1.21
1.20
1.19
1.18
1.17
1.16
1.15
100
90
80
70
60
50
40
30
20
10
0
3.80V
4.55V
6.05V
7.30V
10.55V
12.05V
15.05V
3.20V
3.95V
5.45V
7.20V
9.95V
11.95V
15.20V
0.01
0.10
1.0
10
100
1000
0.1
1
10
100
1000
LOAD (mA)
LOAD (mA)
Figure 19. Efficiency vs. Load Current, VOUT = 3.3 V, Different Input Voltages
Figure 16. Load Regulation, VOUT = 1.2 V
1.90
1.85
1.80
1.75
1.70
100
90
80
70
60
50
–40°C
–5°C
+25°C
+85°C
+125°C
40
0.1mA
1mA
30
20
10
0
5mA
10mA
50mA
100mA
300mA
800mA
0.01
0.10
1.0
10
100
1000
3
5
7
9
11
13
15
LOAD (mA)
INPUT VOLTAGE (V)
Figure 20. Efficiency vs. Load Current, VOUT = 3.3 V, Different Temperatures,
IN = 7.3 V
Figure 17. Line Regulation, VOUT = 1.8 V, Different Loads
V
Rev. A | Page 10 of 32
Data Sheet
ADP2370/ADP2371
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
5.4V
–40°C
–5°C
+25°C
+85°C
+125°C
6.0V
7.2V
9.0V
10.8V
12.8V
15.0V
0.01
0.10
1.0
10
100
1000
0.01
0.10
1.0
10
100
1000
LOAD (mA)
LOAD (mA)
Figure 21. Efficiency vs. Load Current, VOUT = 5.0 V, Different Input Voltages
Figure 24. Efficiency vs. Load Current, VOUT = 1.2 V, Different Temperatures,
VIN = 4 V
100
90
80
70
60
100
90
80
70
60
50
40
30
20
10
0
50
–40°C
–5°C
+25°C
+85°C
+125°C
40
3.20V
3.95V
5.50V
7.20V
9.95V
12.45V
15.20V
30
20
10
0
0.01
0.10
1.0
10
100
1000
0.01
0.10
1.0
10
100
1000
LOAD (mA)
LOAD (mA)
Figure 22. Efficiency vs. Load Current, VOUT = 5.0 V, Different Temperatures
Figure 25. Efficiency vs. Load Current, VOUT = 1.8 V, Different Input Voltages
100
90
80
70
60
50
100
90
80
70
60
50
–40°C
–5°C
+25°C
+85°C
+125°C
40
40
3.20V
30
20
10
0
3.95V
5.50V
7.20V
9.95V
12.45V
15.20V
30
20
10
0
0.01
0.10
1.0
10
100
1000
0.01
0.10
1.0
10
100
1000
LOAD (mA)
LOAD (mA)
Figure 23. Efficiency vs. Load Current, VOUT = 1.2 V, Different Input Voltages
Figure 26. Efficiency vs. Load Current, VOUT = 1.8 V, Different Temperatures,
IN = 4 V
V
Rev. A | Page 11 of 32
ADP2370/ADP2371
Data Sheet
90
85
V
IN
80
600kHz
75
INDUCTOR CURRENT
1.2MHz
70
65
60
55
50
45
40
1
V
OUT
2
3
B
B
W
CH1 500mA Ω
CH2 20.0mV
M10.0µs A CH3 4.56V
W
0.01
0.1
1
10
100
1000
B
CH3 1.00V
W
T
11.0%
LOAD (mA)
Figure 30. Line Transient, VOUT = 1.2 V, PSM Mode, 100 mA, VIN1 = 4 V to 5 V,
2 μs Rise Time, CIN = 3.3 μF
Figure 27. Efficiency vs. Load Current, Different Switching Frequency,
OUT = 1.8 V, VIN = 9 V
V
V
IN
V
IN
INDUCTOR CURRENT
1
INDUCTOR CURRENT
1
2
V
OUT
V
OUT
2
3
3
B
B
W
B
B
W
CH1 500mA Ω
B
CH3 1.00V
W
CH2 10.0mV
M10.0µs A CH3 5.44V
10.80%
CH1 500mA Ω
B
CH3 1.00V
W
CH2 20.0mV
M10.0µs A CH3 4.56V
11.00%
W
W
T
T
Figure 31. Line Transient, VOUT = 1.2 V, PWM Mode, 800 mA, VIN1 = 4 V to 5 V,
2 μs Rise Time, CIN = 3.3 μF
Figure 28. Line Transient, VOUT = 1.8 V, PSM Mode, 100 mA, VIN1 = 4 V to 5 V,
2 μs Rise Time, CIN = 3.3 μF
V
IN
V
IN
1
INDUCTOR CURRENT
INDUCTOR CURRENT
1
2
3
V
OUT
V
OUT
B
B
W
B
B
W
CH1 200mA Ω
B
CH3 1.00V
W
CH2 20.0mV
M10.0µs A CH3 6.78V
11.40%
CH1 200mA Ω
B
CH3 1.00V
W
CH2 20.0mV
M10.0µs A CH3 4.64V
11.20%
W
W
T
T
Figure 32. Line Transient, VOUT = 3.3 V, PSM Mode, 100 mA, VIN1 = 6 V to 7 V,
2 μs Rise Time, CIN = 3.3 μF
Figure 29. Line Transient, VOUT = 1.8 V, PWM Mode, 800 mA, VIN1 = 4 V to 5 V,
2 μs Rise Time, CIN = 3.3 μF
Rev. A | Page 12 of 32
Data Sheet
ADP2370/ADP2371
LOAD CURRENT
V
IN
1
2
INDUCTOR CURRENT
V
OUT
V
OUT
INDUCTOR CURRENT
2
1
3
B
B
B
B
CH1 200mA Ω
CH2 10.0mV
M10.0µs A CH3 6.78V
11.40%
CH1 500mA Ω
CH2 50.0mV
M20.0µs A CH1 560mA
W
W
W
W
W
B
B
CH3 1.00V
CH3 500mA Ω
W
T
T
10.40%
Figure 33. Line Transient, VOUT = 3.3 V, PWM Mode, 800 mA, VIN1 = 6 V to 7 V,
2 μs Rise Time, CIN = 3.3 μF
Figure 36. Load Transient, VOUT = 1.8 V, 300 mA to 800 mA,
Load Current Rise Time = 200 ns
V
IN
LOAD CURRENT
1
2
INDUCTOR CURRENT
V
OUT
1
2
3
V
OUT
INDUCTOR CURRENT
3
B
B
B
B
W
CH1 200mA Ω
CH2 50.0mV
M10.0µs A CH3 6.74V
10.60%
CH1 500mA Ω
CH2 100mV
M40.0µs A CH1 320mA
W
W
W
W
B
B
CH3 1.00V
CH3 500mA Ω
W
T
T
72.00%
Figure 34. Line Transient, VOUT = 5 V, PSM Mode, 100 mA, VIN1 = 6 V to 7 V,
2 μs Rise Time, CIN = 3.3 μF
Figure 37. Load Transient, VOUT = 1.8 V, 10 mA to 800 mA,
Load Current Rise Time = 200 ns
V
IN
LOAD CURRENT
1
2
V
INDUCTOR CURRENT
OUT
V
OUT
INDUCTOR CURRENT
2
1
3
B
B
B
B
W
CH1 200mA Ω
CH2 10.0mV
M10.0µs A CH3 6.52V
11.00%
CH1 100mA Ω
CH2 20.0mV
M10.0µs A CH1 76.0mA
W
W
W
W
B
B
CH3 1.00V
CH3 200mA Ω
W
T
T
50.40%
Figure 35. Line Transient, VOUT = 5 V, PWM Mode, 800 mA, VIN1 = 6 V to 7 V,
2 μs Rise Time, CIN = 3.3 μF
Figure 38. Load Transient, VOUT = 1.8 V,10 mA to 110 mA,
Load Current Rise Time = 200 ns
Rev. A | Page 13 of 32
ADP2370/ADP2371
Data Sheet
LOAD CURRENT
LOAD CURRENT
1
1
2
V
V
OUT
OUT
2
INDUCTOR CURRENT
INDUCTOR CURRENT
3
3
B
B
B
B
W
CH1 200mA Ω
CH2 50.0mV
M20.0µs A CH1 208mA
CH1 100mA Ω
CH2 50.0mV
M20.0µs A CH1 46.0mA
W
W
W
W
W
B
B
CH3 200mA Ω
CH3 200mA Ω
T
50.40%
T
50.40%
Figure 39. Load Transient, VOUT = 1.8 V,100 mA to 300 mA,
Load Current Rise Time = 200 ns
Figure 42. Load Transient, VOUT = 3.3 V, 10 mA to 110 mA,
Load Current Rise Time = 200 ns
LOAD CURRENT
LOAD CURRENT
1
2
1
2
V
OUT
V
OUT
INDUCTOR CURRENT
INDUCTOR CURRENT
3
3
B
B
B
B
W
CH1 500mA Ω
CH2 50.0mV
M40.0µs A CH1 580mA
CH1 200mA Ω
CH2 50.0mV
M20.0µs A CH1 184mA
W
W
W
W
W
B
B
CH3 500mA Ω
CH3 200mA Ω
T
10.20%
T
29.80%
Figure 40. Load Transient, VOUT = 3.3 V, 300 mA to 800 mA,
Load Current Rise Time = 200 ns
Figure 43. Load Transient, VOUT = 3.3 V, 100 mA to 300 mA,
Load Current Rise Time = 200 ns
LOAD CURRENT
LOAD CURRENT
1
2
1
2
V
OUT
V
OUT
INDUCTOR CURRENT
INDUCTOR CURRENT
3
3
B
B
B
B
W
CH1 500mA Ω
CH2 200mV
M40.0µs A CH1 530mA
CH1 500mA Ω
CH3 500mA Ω
CH2 50.0mV
M10.0µs A CH1 560mA
W
W
W
W
W
B
B
CH3 500mA Ω
T
71.80%
T
10.40%
Figure 41. Load Transient, VOUT = 3.3 V, 10 mA to 800 mA,
Load Current Rise Time = 200 ns
Figure 44. Load Transient, VOUT = 1.2 V, 300 mA to 800 mA,
Load Current Rise Time = 200 ns, VIN = 5 V
Rev. A | Page 14 of 32
Data Sheet
ADP2370/ADP2371
LOAD CURRENT
LOAD CURRENT
1
2
1
2
V
OUT
V
OUT
INDUCTOR CURRENT
INDUCTOR CURRENT
3
3
B
B
B
B
W
CH1 500mA Ω
CH2 100mV
M40.0µs A CH1 320mA
72.00%
CH1 500mA Ω
CH2 100mV
M20.0µs A CH1 530mA
T 10.00%
W
W
W
W
W
B
B
CH3 500mA Ω
CH3 500mA Ω
T
Figure 45. Load Transient, VOUT = 1.2 V, 10 mA to 800 mA, Load Current Rise
Time = 200 ns, VIN = 5 V
Figure 48. Load Transient, VOUT = 5 V, 300 mA to 800 mA, Load Current Rise
Time = 200 ns, VIN = 8 V
LOAD CURRENT
1
LOAD CURRENT
1
V
V
OUT
OUT
2
2
INDUCTOR CURRENT
INDUCTOR CURRENT
3
3
B
B
B
B
W
CH1 100mA Ω
CH3 500mA Ω
CH2 20.0mV
M10.0µs A CH1 112mA
CH1 500mA Ω
CH2 200mV
M40.0µs A CH1 320mA
T 72.00%
W
W
W
W
W
B
B
CH3 500mA Ω
T
50.40%
Figure 46. Load Transient, VOUT = 1.2 V,10 mA to 110 mA, Load Current Rise
Time = 200 ns, VIN = 5 V
Figure 49. Load Transient, VOUT = 5 V, 1 mA to 800 mA, Load Current Rise
Time = 200 ns, VIN = 8 V
LOAD CURRENT
1
LOAD CURRENT
1
V
V
OUT
OUT
2
2
INDUCTOR CURRENT
INDUCTOR CURRENT
3
3
B
B
B
B
W
CH1 100mA Ω
CH2 50.0mV
M20.0µs A CH1 220mA
CH1 100mA Ω
CH2 50.0mV
M20.0µs A CH1 80.0mA
W
W
W
W
W
B
B
CH3 200mA Ω
CH3 200mA Ω
T
50.40%
T
50.40%
Figure 47. Load Transient, VOUT = 1.2 V,100 mA to 300 mA, Load Current Rise
Time = 200 ns, VIN = 5 V
Figure 50. Load Transient, VOUT = 5 V,10 mA to 110 mA, Load Current Rise
Time = 200 ns, VIN = 8 V
Rev. A | Page 15 of 32
ADP2370/ADP2371
Data Sheet
V
V
IN
LOAD CURRENT
1
1
2
V
OUT
OUT
2
INDUCTOR CURRENT
INDUCTOR CURRENT
3
3
B
B
W
B
B
W
CH1 200mA Ω
CH2 100mV
M20.0µs A CH1 208mA
30.40%
CH1 5.00V
CH3 200mA Ω
CH2 2.00V
M100µs A CH1 2.50V
10.00%
W
W
W
B
B
CH3 200mA Ω
W
T
T
Figure 51. Load Transient, VOUT = 5 V, 100 mA to 300 mA, Load Current Rise
Time = 200 ns, VIN = 8 V
Figure 54. Startup, VOUT = 3.3 V, 10 mA
V
V
V
IN
IN
1
1
2
OUT
V
OUT
2
INDUCTOR CURRENT
INDUCTOR CURRENT
3
3
B
B
B
B
CH2 2.00V
W
CH1 5.00V
CH3 200mA Ω
CH2 1.00V
M100µs A CH1 2.50V
10.00%
CH1 5.00V
CH3 500mA Ω
M100µs A CH1 2.50V
T 10.00%
W
W
W
B
B
W
W
T
Figure 52. Startup, VOUT = 1.8 V, 10 mA
Figure 55. Startup, VOUT = 3.3 V, 800 mA
V
V
IN
IN
1
2
1
2
V
V
OUT
OUT
INDUCTOR CURRENT
INDUCTOR CURRENT
3
3
B
B
B
B
CH2 1.00V
W
CH1 5.00V
CH3 500mA Ω
CH2 1.00V
M100µs A CH1 2.50V
10.00%
CH1 5.00V
CH3 200mA Ω
M100µs A CH1 2.50V
T 10.00%
W
W
W
B
B
W
W
T
Figure 53. Startup, VOUT = 1.8 V, 800 mA
Figure 56. Startup, VOUT = 1.2 V, 10 mA, VIN = 5 V
Rev. A | Page 16 of 32
Data Sheet
ADP2370/ADP2371
250
200
150
100
50
V
IN
1
2
V
OUT
INDUCTOR CURRENT
–40°C
–5°C
+25°C
+85°C
+125°C
3
0
B
B
W
CH1 5.00V
CH3 500mA Ω
CH2 500mV
M100µs A CH1 2.50V
10.00%
W
3
5
7
9
11
13
15
B
W
INPUT VOLTAGE (V)
T
Figure 57. Startup, VOUT = 1.2 V, 800 mA, VIN = 5 V
Figure 60. PSM to PWM Mode Transition vs. Input Voltage,
Different Temperatures
1200
V
IN
1150
1100
1050
1000
950
1
2
V
OUT
INDUCTOR CURRENT
5.4V
7.2V
12.0V
15.0V
900
3
850
800
B
B
W
CH1 5.00V
CH3 200mA Ω
CH2 2.00mV
M100µs A CH1 2.50V
10.00%
W
–60 –40 –20
0
20
40
60
80
100 120 140
B
W
TEMPERATURE (°C)
T
Figure 61. Overcurrent Limit vs. Temperature, VOUT = 5 V,
Different Input Voltages
Figure 58. Startup, VOUT = 5 V, 10 mA, VIN = 7 V
0.05
V
IN
0.04
0.03
0.02
0.01
0
1
2
V
OUT
3.2V
5.0V
9.0V
15V
INDUCTOR CURRENT
3
B
B
W
CH1 5.00V
CH3 500mA Ω
CH2 2.00mV
M100µs A CH1 2.50V
10.00%
W
0
100
200
300
400
500
600
700
800
B
W
LOAD CURRENT (mA)
T
Figure 59. Startup, VOUT = 5 V, 800 mA, VIN = 7 V
Figure 62. Output Ripple vs. Load Current, VOUT = 1.2 V, Different Input
Voltages, Automatic Mode
Rev. A | Page 17 of 32
ADP2370/ADP2371
Data Sheet
0.025
0.020
0.015
0.010
0.005
0
0.05
0.04
0.03
0.02
0.01
0
3.2V
5.0V
9.0V
15V
4V
5V
9V
15V
0
100
200
300
400
500
600
700
800
0
100
200
300
400
500
600
700
800
LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 63. Output Ripple vs. Load Current, VOUT = 1.8 V, Different Input
Voltages, Automatic Mode
Figure 66. Output Ripple vs. Load Current, VOUT = 3.3 V, Different Input
Voltages, Force PWM Mode
1.0
0.08
3.0V
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
3.5V
4.0V
5.0V
6.0V
7.0V
10.0V
0.06
0.04
4.5V
5.0V
9.0V
15V
0.02
0
–40
–20
0
20
40
60
80
100
120
0
100
200
300
400
500
600
700
800
TEMPERATURE (°C)
LOAD CURRENT (mA)
Figure 64. Output Ripple vs. Load Current, VOUT = 3.3 V, Different Input
Voltages, Automatic Mode
Figure 67. PMOS RDSON vs. Temperature at 400 mA, Different Input Voltages
1.0
0.10
0.08
0.06
3.0V
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
3.5V
4.0V
5.0V
6.0V
7.0V
10.0V
5.8V
6.0V
9.0V
15V
0.04
0.02
0
–40
–20
0
20
40
60
80
100
120
0
100
200
300
400
500
600
700
800
LOAD CURRENT (mA)
TEMPERATURE (°C)
Figure 65. Output Ripple vs. Load Current, VOUT = 5 V, Different Input
Voltages, Automatic Mode
Figure 68. NMOS RDSON vs. Temperature at 400 mA, Different Input Voltages
Rev. A | Page 18 of 32
Data Sheet
ADP2370/ADP2371
1.0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
+125°C
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
+85°C
+25°C
–5°C
+125°C
+85°C
+25°C
–5°C
–40°C
–40°C
3
4
5
6
7
8
9
10
3
4
5
6
7
8
9
10
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Figure 69. PMOS RDSON vs. Input Voltage at 400 mA, Different Temperatures
Figure 70. NMOS RDSON vs. Input Voltage at 400 mA, Different Temperatures
Rev. A | Page 19 of 32
ADP2370/ADP2371
Data Sheet
THEORY OF OPERATION
5V
VIN
REG
1.2V
V
SW
EN_PREC
STANDBY
EN
VIN
1.0V
P_I
LIMIT
1.2A
VIN
VIN
UVLO
2.95V
RDS
RDS
× Kr
ON
ON
I
MIN
N_I
LIMIT
200mA
Kr
–0.5A – (PWM)
0A – (PSM)
VIN
× Kr
SW
ADP2371
ONLY
PWM
PSM
VIN
CONTROL
LOGIC
I
SLOPE
SLOPE COMP
PGND
0.808V
0.8V
H = FPWM
L = PWM/PSM
SYNC
FSEL
OSCILLATOR
DEFAULT = 1.2MHz
VOUT ÷ 2 FREQUENCY
FOLDBACK
H = 1.2MHz
L = 600kHz
FB
150°C
135°C
THSD
I
V
COMP
COMP
0.8V
V
g
M
TOL
PG
0.736V
0.696V
FB
SOFT
START
Figure 71. Functional Block Diagram
The ADP2370/ADP2371 use a high speed, current mode, con-
stant frequency PWM control scheme for excellent stability and
transient response. To ensure the longest battery life in portable
applications, the ADP2370/ADP2371 has a power saving mode.
Under light load conditions, the output capacitor is charged as
needed to maintain regulation; otherwise, the ADP2370/ADP2371
enter sleep mode, a low 14 μA quiescent state. The architecture
ensures smooth transitions from PWM mode to and from PSM,
and maintains high efficiencies at light loads. The following sec-
tions describe the two modes of operation and provide detailed
descriptions of the ADP2370/ADP2371 features.
The ADP2370/ADP2371 use a constant slope compensation
scheme where the inductor scales with the output voltage. The
equation for choosing the inductor for a particular output
voltage is
1.2×VOUT
L =
0.478× fSW
See the Applications Information section for details regarding
choosing an appropriate inductor value.
Cycle to cycle operation of the PWM mode begins with the
falling edge of the internal clock. Note that when using an
external clock, the rising edge synchronizes the regulator and
the falling edge is determined by the internal clock, typically a
25 ns pulse width. The falling edge of the clock starts the cycle
by turning on the high-side switch, which produces a positive
di/dt current in the inductor. The PWM comparator controls
when the high-side switch turns off. The positive input of the
comparator monitors the peak inductor current via the SW node.
PWM OPERATION
The ADP2370/ADP2371 PWM mode is a fixed frequency,
1.2 MHz typical, current mode architecture. Use the SYNC pin
to synchronize the regulator to an external clock frequency or
use the FSEL pin to select an internal clock frequency of
600 kHz or 1.2 MHz.
Rev. A | Page 20 of 32
Data Sheet
ADP2370/ADP2371
The negative side of the comparator input voltage is set by the
voltage control loop minus the slope compensation. When the
high-side switch turns off, the low-side switch turns on for the
remainder of the clock period.
LOAD CURRENT
1
2
V
OUT
While in PWM/PSM mode, the low-side switch turns off when
the inductor current reaches zero, operating in discontinuous
conduction (DCC) mode. If SYNC is tied high to force the device
into PWM only mode, the low-side switch stays on until the
next clock cycle or until the inductor current reaches the
negative current limit.
INDUCTOR CURRENT
3
PSM OPERATION
B
B
W
CH1 200mA Ω
CH3 200mA Ω
CH2 50.0mV
M20.00µs A CH1 156mA
W
W
The ADP2370/ADP2371 smoothly transition to the variable
frequency PSM operation. The ADP2370/ADP2371 select a
minimum current value, IMIN, for the peak current of the inductor
based on the input and output voltages. The design of the IMIN
value is based on the recommended inductor values. Deviating
from the recommended inductor value for a particular output
voltage results in shifting the PSM to PWM threshold and could
result in the device entering DCC mode.
B
T
50.40%
Figure 72. PSM to PWM Transition Waveforms, VOUT = 1.8 V,
10 mA Load to 300 mA Load
LOAD CURRENT
1
2
As long as the required peak inductor current is above IMIN, the
regulator remains in PWM mode. As the load decreases, the
PSM circuitry prevents the peak inductor current from dropping
below the PSM peak current value. This circuitry causes the
regulator to supply more current to the output filter than the
load requires, resulting in the output voltage increasing and the
output of the internal compensation node of the error amplifier,
V
OUT
INDUCTOR CURRENT
3
V
COMP, decreasing.
B
B
W
CH1 200mA Ω
CH2 50.0mV
M20.00µs A CH1 156mA
W
W
B
CH3 200mA Ω
T
50.40%
When the FB pin voltage rises above 1% of the nominal output
voltage and the VCOMP node voltage is below a predetermined
PSM threshold voltage level, the regulator enters sleep mode.
While in sleep mode, the high-side and low-side switches and a
majority of the circuitry are disabled to allow for a low sleep
mode quiescent current as well as high efficiency performance.
Figure 73. PWM to PSM Transition Waveforms, VOUT = 1.8 V,
300 mA Load to 10 mA Load
During sleep mode, the output voltage decreases as the output
capacitor discharges into the load. Fixed frequency operation
starts when the FB voltage reaches the nominal output voltage.
When the load requirement increases past the IMIN peak current
level, the VCOMP node rises and the PWM control loop sets the
duty cycle. While the part is entering and exiting sleep mode,
the PSM voltage ripple is larger than 1% because of the delay in
the comparators.
Figure 72 and Figure 73 illustrate how the output voltage and
inductor current change with loads and transitions in and out of
PSM operation. The output voltage ripple in PSM is ~40 mV p-p,
and the ripple in PWM is <10 mV p-p.
Rev. A | Page 21 of 32
ADP2370/ADP2371
Data Sheet
FEATURES DESCRIPTIONS
PRECISION ENABLE
UNDERVOLTAGE LOCKOUT
The enable circuit of the ADP2370/ADP2371 minimizes the
input current during shutdown and simultaneously provides
an accurate enable threshold. When the enable input voltage
is below 400 mV, the regulators are in shutdown mode and the
supply current is typically 1.2 μA. As the enable input voltage
rises above the standby enable threshold of 1.0 V, the internal
bias currents and voltages are activated, turning on the precision
enable circuitry. This allows the precision enable circuitry to
detect accurately when the EN pin voltage exceeds the precision
enable rising threshold of 1.2 V.
To protect against battery discharge, an undervoltage lockout
(UVLO) circuit is incorporated into the ADP2370/ADP2371.
When the input voltage drops below the UVLO threshold, the
ADP2370/ADP2371 shuts down, and both the power switch
and synchronous rectifier turn off. Once the input voltage rises
above the UVLO threshold, the soft start period is initiated and
the device is enabled.
THERMAL PROTECTION
In the event that the junction temperature on either the ADP2370
or ADP2371 rises above 150°C, the thermal shutdown protec-
tion circuit turns off the regulator. Extreme junction temperature
can be the result of high current operation, poor circuit board
design, and/or high ambient temperature. A 20°C hysteresis is
included in the protection circuit so that when a thermal shut-
down occurs, the device does not return to operation until the
on-chip temperature drops below 130°C. When exiting a
thermal shutdown, soft start is initiated.
FORCED PWM OR PWM/PSM SELECTION
Connecting the SYNC pin to a voltage greater than 1.2 V forces
the device to operate permanently in the PWM mode. This means
that the ADP2370/ADP2371 continue to operate at a fixed fre-
quency even when the output current is less than the PWM/PSM
threshold. In PWM mode, the efficiency is lower compared to the
PSM mode during light loads. The low-side NMOS remains on
when the output current drops to less than zero thereby preventing
the device from entering discontinuous conduction (DCC) mode.
SOFT START
The ADP2370/ADP2371 have an internal soft start function
that ramps the output voltage in a controlled manner upon
startup, thereby limiting the inrush current. This prevents
possible input voltage drops when a battery or a high imped-
ance power source is connected to the input of the converter.
Typical soft start time is 350 μs. The ADP2370/ADP2371 are
also capable of starting up into a precharged output capacitor.
If soft start is invoked when the output capacitor charge is greater
than zero, the device delays the start of switching until the internal
soft start ramp reaches the corresponding FB voltage. This fea-
ture prevents discharging the output capacitor at the beginning
of soft start.
It is possible to switch from FPWM mode to the power-save
mode during operation by pulling the SYNC pin low. The
flexible configuration of the SYNC pin during operation of
the device allows for efficient power management.
Connecting the SYNC pin to a voltage less than 0.4 V allows
the part to operate in either PWM or PSM modes, depending on
the output current. Whenever the average output current goes
below the PWM/PSM threshold, the ADP2370/ADP2371 enter
PSM mode operation. During PSM mode the part operates with
reduced switching frequency and with a minimal quiescent cur-
rent to maintain high efficiency. The low-side NMOS turns off
when the output current reaches zero, causing the part to operate
in DCC mode.
CURRENT LIMIT
The ADP2370/ADP2371 have protection circuitry that limits
the direction and amount of current to 1200 mA that flows
through the power switch and synchronous rectifier, cycle by
cycle. The positive current limit on the power switch limits the
amount of current that can flow from the input to the output.
The negative current limit on the synchronous rectifier prevents
the inductor current from reversing direction and flowing out
of the load.
QUICK OUTPUT DISCHARGE (QOD) FUNCTION
The ADP2371 includes an output discharge resistor that forces the
output voltage to zero when the buck is disabled. This ensures
that the output of the buck is always in a well-defined state, whether
or not it is enabled. The ADP2370 does not include this output
discharge function.
SHORT-CIRCUIT PROTECTION
A negative current limit is provided by the ADP2370/ADP2371
to prevent an excessive reverse inductor current when the switching
section sinks current from the load in forced continuous con-
duction mode. Under negative current-limit conditions, both
the high-side and low-side switches are disabled.
The ADP2370/ADP2371 include frequency foldback to prevent
output current runaway on a hard short. When the voltage at
the feedback pin falls below 0.3 V, indicating the possibility of
a hard short at the output, the switching frequency is reduced
to 1/4 of the internal oscillator frequency. The reduction in the
switching frequency gives more time for the inductor to dis-
charge, preventing a runaway of output current.
Rev. A | Page 22 of 32
Data Sheet
ADP2370/ADP2371
If the device is synchronized to an external clock, the PSM
mode is disabled and the device stays in forced PWM mode.
Connect FSEL to ground when synchronizing to a frequency
range from 400 kHz to 800 kHz, and connect FSEL to the input
voltage when the external frequency is in the range of 800 kHz
to 1600 kHz. FSEL has an internal pull-down resistor and
defaults to the 600 kHz mode when FSEL is unconnected.
100% DUTY CYCLE
The ADP2370/ADP2371 enter and exit 100% duty cycle smoothly.
The control loop seeks the next clock cycle while the high-side
switch is engaged. When this occurs, the clock signal is masked
and the PMOS remains on. When the input voltage increases, the
internal VCOMP node decreases its signal to the control loop; thus,
the device stops skipping clock cycles and exits 100% duty cycle.
INTERNAL 1.2MHZ
1
2
3
4
V
IN
INTERNAL 600kHZ
SYNC
1
2
V
OUT
PWM CLOCK (IF FSEL = 1)
PWM CLOCK (IF FSEL = 0)
INDUCTOR CURRENT
B
3
PWM CLOCK FOLLOWS SYNC UNTIL IT MISSES
4 × 1.2MHZ INTERNAL CLOCK CYCLES
B
CH1 1.00V
CH3 50.0mA Ω
CH2 1.00V
M2.00ms
32.20%
A CH1 4.90V
W
W
B
W
T
Figure 76. Typical SYNC Timing
Figure 74. Transition into and out of Dropout in PSM Mode,
OUT = 5 V, 100 mA Load
V
SW
1
V
IN
V
OUT
V
OUT
2
3
INDUCTOR CURRENT
SYNC
INDUCTOR CURRENT
4
1
3
B
B
CH1 5.00V
CH3 200mA Ω
CH2 100mV
CH4 5.00V
M20.0µs A CH4 2.00V
20.0%
W
W
W
B
B
W
T
B
B
W
CH1 1.00V
CH3 50.0mA Ω
CH2 1.00V
M2.00ms
32.20%
A CH1 4.90V
W
Figure 77. Typical SYNC Transient, 1.2 MHz to 800 kHz to 1.2 MHz
B
W
T
Figure 75. Transition into and out of Dropout in PWM Mode,
OUT = 5 V, 100 mA Load
SW
V
1
SYNCHRONIZING
V
OUT
It is possible to synchronize the ADP2370/ADP2371 to an external
clock within a frequency range from 400 kHz to 1.6 MHz. The
device automatically detects the rising edge of the first clock
and synchronizes to the external clock. When the clock signal
stops, the device automatically switches back to the internal
clock and continues operating.
2
INDUCTOR CURRENT
3
4
SYNC
The switchover is initiated when no rising edge on the SYNC
pin can be detected on the internal clock for a duration of four
clock cycles. Therefore, the maximum delay time can be 6.7 µs if
the internal clock is running at its minimum frequency of 600 kHz.
During this time, there is no clock signal available. The output
stops switching until the ADP2370 circuitry switches to the
internal clock signal.
B
B
W
CH1 5.00V
CH2 50.0mV
CH4 5.00V
M20.0µs A CH4 2.00V
W
B
B
CH3 200mA Ω
W
W
T
20.0%
Figure 78. SYNC Transient 1.2 MHz to 800 kHz
Rev. A | Page 23 of 32
ADP2370/ADP2371
Data Sheet
SW
1
V
OUT
2
INDUCTOR CURRENT
V
OUT
ENABLE
3
4
SYNC
PG
3
2
1
B
B
W
CH1 5.00V
CH3 200mA Ω
CH2 50.0mV
M2.00µs A CH2 –57.0mV
B
B
W
W
CH1 500mV
CH2 1.00V
M40.0µs
10.00%
A CH3 3.40V
W
B
B
CH4 5.00V
B
W
W
CH3 5.00V
W
T
20.0%
T
Figure 79. SYNC Transient 800 kHz to 1.2 MHz
Figure 80. Typical PG Timing at Startup
POWER GOOD
V
OUT
The ADP2370/ADP2371 power-good (PG) output indicates the
state of the monitored output voltage. The PG function is an active
high, open-drain output, requiring an external pull-up resistor that
is typically supplied from the I/O supply rail, as shown in Figure 1.
PG
When the sensed output voltage is below 87% of its nominal value,
the PG pin is held low. When the sensed output voltage rises above
LOAD CURRENT
2
92% of the nominal level, the PG line is pulled high after tRESET
The PG pin remains high when the sensed output voltage is
above 92% of the nominal output voltage level.
.
The typical PG delay when the buck is in PWM mode is 20 μs.
Figure 80 shows the typical PG operation during startup. Figure 81
shows the PG operation when there is a large load transient that
causes the output voltage to fall just below the PG threshold.
3
1
B
B
W
CH1 500mV
CH2 1.00V
M1.00µs A CH3 740mA
10.00%
W
W
B
CH3 500mAΩ
T
Figure 81. Typical PG Timing with 200 mA to 1100 mA Load Transient
When not using the PG function, remove the pull-up resistor
and leave the PG pin either open or shorted to ground.
Rev. A | Page 24 of 32
Data Sheet
ADP2370/ADP2371
APPLICATIONS INFORMATION
ADIsimPower DESIGN TOOL
OUTPUT CAPACITOR
Output capacitance is required to minimize the voltage overshoot,
voltage undershoot, and the ripple voltage present on the output.
Capacitors with low equivalent series resistance (ESR) values
produce the lowest output ripple; therefore, use capacitors such as
the X5R dielectric. Do not use Y5V and Z5U capacitors. Y5V
and Z5U capacitors are unsuitable choices because of their large
capacitance variation over temperature and their dc bias voltage
changes. Because ESR is important, select the capacitor using
the following equation:
ADP2370/ADP2371 are supported by the ADIsimPower™ design
tool set. ADIsimPower is a collection of tools that produce
complete power designs optimized for a specific design goal.
The tools enable the user to generate a full schematic, bill of
materials, and calculate performance in minutes. ADIsimPower
can optimize designs for cost, area, efficiency, and parts count
taking into consideration the operating conditions and limita-
tions of the IC and all real external components. For more
information about, and to obtain ADIsimPower design tools,
visit www.analog.com/ADIsimPower. Users can also request
an unpopulated board through the ADIsimPower tool.
VRIPPLE
ESRCOUT
≤
ΔIL
EXTERNAL COMPONENT SELECTION
where:
ESRCOUT is the ESR of the chosen capacitor.
RIPPLE is the peak-to-peak output voltage ripple.
Table 6 and Table 7 list external component selections for the
ADP2370/ADP2371 application circuit shown in Figure 82. The
selection of components is dependent on the input voltage, output
voltage, and load current requirements. Additionally, trade-offs
among performance parameters, such as efficiency and transient
response, are made by varying the choice of external components.
V
Use the following equations to determine the output
capacitance:
VIN
COUT
≥
(2π × fSW )×2× L ×VRIPPLE
SELECTING THE INDUCTOR
∆IL
The high frequency switching of the ADP2370/ADP2371 allows
for the use of small surface-mount power inductors. The inductor
value affects the transition from PWM to PSM, efficiency, output
ripple, and current-limit values. Use the following equation to cal-
culate the ideal inductance, which is derived from the inductor
current slope compensation, for a given output voltage and
switching frequency:
COUT
≥
8× fSW ×VRIPPLE
Increasing the output capacitor value has no effect on stability
and may reduce output ripple and enhance load transient response.
When choosing the output capacitor value, it is important to
account for the loss of capacitance due to output voltage dc bias.
INPUT CAPACITOR
1.2×VOUT
L =
An input capacitor is required to reduce input voltage ripple, input
ripple current, and source impedance. Place the input capacitor
as close as possible to the VIN pin. A low ESR X7R- or X5R-type
capacitor is highly recommended to minimize the input voltage
ripple. Use the following equation to determine the rms input
current:
0.478× fSW
The ripple current is calculated as follows:
VOUT
VOUT
VIN
∆IL =
× 1−
f
SW ×L
where:
SW is the switching frequency in MHz (1.2 MHz typical).
L is the inductor value in μH.
VOUT (VIN −VOUT
)
ICIN ≥ ILOAD(MAX)
f
VIN
VOUT (VIN −VOUT
)
The dc resistance (DCR) value of the selected inductor affects
efficiency; however, a decrease in this value typically means an
increase in root mean square (rms) losses in the core and skin.
A minimum requirement of the dc current rating of the inductor
is for it to be equal to the maximum load current plus half of
the inductor current ripple, as shown by the following equation:
I rms≥ ILOAD(MAX)
VIN
ADJUSTABLE OUTPUT VOLTAGE PROGRAMMING
The ADP2370/ADP2371 feature an adjustable output voltage range
from 0.8 V to 12 V. The output voltage is set by the ratio of two
external resistors, R2 and R3, as shown in Figure 83. The device
servos the output to maintain the voltage at the FB pin at 0.8 V,
referenced to ground; the current in R2 is then equal to 0.8 V/R3
plus the FB pin bias current. The bias current of the FB pin,
10 nA at 25°C, flows through R2 into the FB pin.
∆IL
IPK = ILOAD(MAX) +(
)
2
The output voltage is calculated using the equation
VOUT = 0.8 V(1 + R2/R3) + (FBI-BIAS)(R2)
Rev. A | Page 25 of 32
ADP2370/ADP2371
Data Sheet
To minimize errors in the output voltage caused by the bias
current of the FB pin, maintain a value of R2 that is less than
250 kΩ. For example, when R2 and R3 each equal 250 kΩ, the
output voltage is 1.6 V. The output voltage error introduced by
the FB pin bias current is 2.5 mV, or 0.156%, assuming a typical
FB pin bias current of 10 nA at 25°C.
frequency. Each time a power device gate is turned on and turned
off, the driver transfers a charge from the input supply to the
gate, and then from the gate to ground.
Estimate switching losses using the following equation:
P
SW = (CGATE_P + CGATE_N) × VIN2 × fSW
where:
Note that in shutdown mode, the output is turned off and the
divider current is zero.
C
C
GATE_P is the gate capacitance of the internal high-side switch.
GATE_N is the gate capacitance of the internal low-side switch.
Select the output inductor and capacitor as described in the
Selecting the Inductor, Output Capacitor, and Input Capacitor
sections, as well as Table 6 for more information.
fSW is the switching frequency.
The typical value for gate capacitances, CGATE_P and CGATE_N
is 150 pF.
,
EFFICIENCY
Transition Losses
Efficiency is defined as the ratio of output power to input power.
The high efficiency of the ADP2370/ADP2371 has two distinct
advantages. First, only a small amount of power is lost in the
dc-to-dc converter package, which in turn, reduces thermal
constraints. Second, high efficiency delivers the maximum
output power for the given input power, thereby extending
battery life in portable applications.
Transition losses occur because the P-channel switch cannot
turn on or turn off instantaneously. In the middle of an SW
node transition, the power switch provides all of the inductor
current. The source-to-drain voltage of the power switch is half
the input voltage, resulting in power loss. Transition losses
increase with both load current and input voltage and occur
twice for each switching cycle.
Power Switch Conduction Losses
Use the following equation to estimate transition losses:
Power switch dc conduction losses are caused by the flow of
output current through the P-channel power switch and the
N-channel synchronous rectifier, which have internal resis-
tances (RDS(ON)) associated with them. The amount of power
loss is approximated by
P
TRAN = VIN/2 × IOUT × (tR + tF) × fSW
where:
tR is the rise time of the SW node.
tF is the fall time of the SW node.
2
The typical value for the rise and fall times, tR and tF, is 2 ns.
PSW _COND = (RDS(ON)_ P ×D + RDS(ON)_ N ×(1− D))×IOUT
RECOMMENDED BUCK EXTERNAL COMPONENTS
where:
The recommended external components for use with the
ADP2370/ADP2371 are listed in Table 6 (inductors) and Table 7
(capacitors).
VOUT
D =
VIN
The internal resistance of the power switches increases with tem-
perature and increases when the input voltage is less than 5.5 V.
V
= 6V
IN
C
IN
10µF
Inductor Losses
POWER GOOD
Inductor conduction losses are caused by the flow of current
through the inductor, which has an internal resistance (DCR)
associated with it. Larger size inductors have smaller DCR,
which can decrease inductor conduction losses. Inductor core
losses relate to the magnetic permeability of the core material.
Because the ADP2370/ADP2371 are high switching frequency
dc-to-dc regulators, shielded ferrite core material is recommended
because of its low core losses and low EMI.
ADP2370/
ADP2371
PGND
VIN
1
2
3
4
8
7
6
5
6.8µH
V
= 3.3V
OUT
SW
PG
FSEL
EN
C
OUT
10µF
ON
OFF
AGND
(EXPOSED PAD)
FB
SYNC
To estimate the total amount of power lost in the inductor, use
the following equation:
PL = DCR × IOUT2 + Core Losses
Figure 82. Typical Application, 1.2 MHz, Fixed Output
Switching Losses
Switching losses are associated with the current drawn by the
driver to turn-on and turn-off the power devices at the switching
Rev. A | Page 26 of 32
Data Sheet
ADP2370/ADP2371
V
= 6V
IN
C
10µF
IN
R1
10kΩ
POWER GOOD
ADP2370/
ADP2371
PGND
VIN
1
2
3
4
8
7
6
5
6.8µH
V
= 1.8V
FSEL
OUT
SW
PG
C
10µF
OUT
ON
EN
OFF
R2
AGND
(EXPOSED PAD)
249kΩ
FB
SYNC
R3
200kΩ
Figure 83. Typical Application, 600 kHz, Adjustable Output
Table 6. Inductors
Output
Frequency Voltage
Ideal Value
(μH)
Standard Value
(μH)
Dimensions
(mm)
ISAT
(A)
DCR
(mΩ)
Vendor Model
Coilcraft XFL4020-222ME
Coilcraft XFL4020-332ME
Coilcraft XFL4020-332ME
Coilcraft XFL4020-472ME
Coilcraft XAL4030-682ME
Coilcraft XAL4030-682ME
Coilcraft XAL4040-103ME
Coilcraft LPS6235-183ML
Coilcraft XFL4020-472ME
Coilcraft XAL4030-682ME
Coilcraft XAL4030-682ME
Coilcraft XAL4040-103ME
Coilcraft XAL4040-103ME
Coilcraft XAL4040-153ME
Coilcraft LPS6235-223ML
Coilcraft LPS6235-333ML
1.2 MHz
1.2 MHz
1.2 MHz
1.2 MHz
1.2 MHz
1.2 MHz
1.2 MHz
1.2 MHz
600 kHz
600 kHz
600 kHz
600 kHz
600 kHz
600 kHz
600 kHz
600 kHz
1.2
1.5
1.8
2.5
3.0
3.3
5
2.5
3.1
3.8
5.2
6.3
6.9
10.5
18.8
5.0
2.2
3.3
3.3
4.7
6.8
6.8
10
4 × 4 × 2
4 × 4 × 2
4 × 4 × 2
4 × 4 × 2
4 × 4 × 3
4 × 4 × 3
4 × 4 × 4
6 × 6 × 3.5
4 × 4 × 2
4 × 4 × 3
4 × 4 × 3
4 × 4 × 4
4 × 4 × 4
4 × 4 × 4
6 × 6 × 3.5
6 × 6 × 3.5
4.1
3.1
3.1
2.0
1.9
1.9
1.5
1.7
2.0
1.9
1.9
1.5
1.5
1.3
1.6
1.3
24
38
38
57
74
74
92
14
57
74
74
92
92
120
145
130
9
18
1.2
1.5
1.8
2.5
3.0
3.3
5
4.7
6.8
6.8
10
10
15
6.3
7.5
10.5
12.6
13.8
20.9
37.7
22
33
9
Table 7. 10 μF Capacitors
Output
Vendor Model
Case Size
Voltage Rating
Location
Input Voltage
<15 V
<12 V
Voltage
Murata GRM32ER7YA106KA12
Murata GRM32DR61E106KA12
Murata GRM31CR61C106KA88
Murata GRM32ER7YA106KA12
Murata GRM32DR61E106KA12
Murata GRM31CR61C106KA88
Murata GRM21BR61C106KE15
1210
1210
1206
1210
1210
1206
0805
35
25
16
35
25
16
16
Input or Output
Input or Output
Input or Output
Input or Output
Input or Output
Input or Output
Output
<8 V
<12 V
<9 V
<7 V
<2.5 V
Rev. A | Page 27 of 32
ADP2370/ADP2371
Data Sheet
Figure 85 depicts the capacitance vs. voltage bias characteristic
of a several 10 µF capacitors in different case sizes and voltage
ratings. The voltage stability of a capacitor is strongly influenced
by the capacitor size and voltage rating. In general, a capacitor in a
larger package or higher voltage rating exhibits better stability.
The temperature variation of the X5R dielectric is about 15%
over the −40°C to +85°C temperature range and is not a
function of package or voltage rating.
CAPACITOR SELECTION
Output Capacitor
The ADP2370/ADP2371 are designed for operation with small,
space-saving ceramic capacitors, but function with most commonly
used capacitors provided that the effective series resistance (ESR)
value is carefully considered. The ESR of the output capacitor
affects stability of the control loop. A minimum output capaci-
tance of 7 µF with an ESR of 10 mΩ or less is recommended to
ensure stability of the ADP2370/ADP2371.
12
11
10µF/25V/1210
10µF/35V/1210
10µF/16V/0805
10µF/16V/1206
Transient response to changes in load current is also affected by
output capacitance. Using a larger value of output capacitance
improves the transient response of the ADP2370/ADP2371 to
large changes in load current. Figure 84 shows the transient
response for an output capacitance value of 10 µF.
10
9
8
7
6
5
4
3
2
1
0
LOAD CURRENT
1
V
OUT
0
5
10
15
20
25
30
35
2
DC BIAS VOLTAGE (V)
Figure 85. Capacitance vs. Voltage Characteristic Different Case Sizes
INDUCTOR CURRENT
Use Equation 1 to determine the worst-case capacitance,
accounting for capacitor variation over temperature,
component tolerance, and voltage.
3
C
EFF = CBIAS × (1 − TEMPCO) × (1 − TOL)
(1)
B
B
W
CH1 500mA Ω
CH2 50.0mV
M20.0µs A CH1 560mA
W
W
B
CH3 500mA Ω
T
10.40%
where:
Figure 84. Output Transient Response, VOUT2 = 1.8 V, COUT = 10 µF,
300 mA to 800 mA, Load Current Rise Time = 200 ns
C
BIAS is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
Input Bypass Capacitor
In this example, the worst-case TEMPCO over −40°C to +85°C
is assumed to be 15% for an X5R dielectric. The tolerance of the
capacitor (TOL) is assumed to be 10%, and CBIAS is 8.53 μF at 12 V
for the 10 μF, 35 V capacitor in a 1210 package (see Figure 85).
Connecting a 10 µF capacitor from VIN to GND reduces the
circuit sensitivity to the PCB layout, especially when long input
traces or high source impedance are encountered. If greater than
10 µF of output capacitance is required, increase the input
capacitor to match it to improve the transient response.
Substituting these values in Equation 1 yields
Input and Output Capacitor Properties
CEFF = 8.53 μF × (1 − 0.15) × (1 − 0.1) = 6.53 μF
Use any good quality ceramic capacitors with the ADP2370/
ADP2371; however they must meet the minimum capacitance
and maximum ESR requirements. Ceramic capacitors are manu-
factured with a variety of dielectrics, each with different behavior
over temperature and applied voltage. Capacitors must have a
dielectric adequate to ensure the minimum capacitance over the
necessary temperature range and dc bias conditions. X5R or X7R
dielectric capacitors with a voltage rating of 6.3 V to 25 V are
recommended for best performance. Y5V and Z5U dielectrics
are not recommended because of their poor temperature and dc
bias characteristics.
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the ADP2370/ADP2371
over temperature and tolerance at the chosen output voltage.
To guarantee the performance of the ADP2370/ADP2371, it is
imperative that the effects of dc bias, temperature, and
tolerances of the capacitors are evaluated for each application.
Rev. A | Page 28 of 32
Data Sheet
ADP2370/ADP2371
THERMAL CONSIDERATIONS
In most applications, the ADP2370/ADP2371 do not dissipate
much heat due to their high efficiency. However, in applications
with high ambient temperature and high supply voltage-to-output
voltage differential, the heat dissipated in the package may be
large enough to cause the junction temperature of the die to
exceed the 125°C maximum.
For a given ambient temperature and total power dissipation,
there exists a minimum copper size requirement for the PCB to
ensure the junction temperature does not rise above 125°C. The
following figures (Figure 86 to Figure 89) show junction
temperature calculations for different ambient temperatures,
total power dissipation, and areas of PCB copper.
145
135
125
115
105
95
If the junction temperature of the ADP2370/ADP2371 exceeds
150°C, the regulator enters thermal shutdown. The regulator
recovers only after the junction temperature has fallen below
130°C, this helps to prevent any permanent damage to the IC.
Thermal analysis for the chosen application is clearly very
important to guarantee reliable operation under all conditions.
The junction temperature of the die is the sum of the ambient
temperature of the environment and the temperature rise of the
package due to the power dissipation, as shown in Equation 2.
85
75
2
65
55
45
35
25
6400mm
2
500mm
100mm
2
To guarantee reliable operation, the junction temperature of the
ADP2370/ADP2371 must not exceed 125°C. To ensure the junc-
tion temperature stays below this maximum value, the user must
be aware of the parameters that contribute to junction temperature
changes. These parameters include ambient temperature, power
dissipation in the power device, and the thermal resistance between
the junction and ambient air (θJA). The θJA number is dependent
on the package assembly compounds that are used and the amount
of PCB copper soldered to the package GND and EPAD. Table 8
shows typical θJA values of the 8-lead, 3 mm × 3 mm LFCSP for
various PCB copper sizes.
T
MAX
J
0
0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50
TOTAL POWER DISSIPATION (W)
Figure 86. Junction Temperature vs. Power Dissipation, TA = 25°C
140
130
120
110
100
Table 8. Typical θJA Values
Copper Size (mm2)
θJA (°C/W)
162.2
124.1
68.7
90
251
2
80
70
60
50
6400mm
2
500mm
100mm
100
500
2
T
MAX
J
1000
6400
56.5
42.4
0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
1 The device is soldered to minimum size pin traces.
TOTAL POWER DISSIPATION (W)
The junction temperature of the ADP2370/ADP2371 is
calculated from the following equation:
Figure 87. Junction Temperature vs. Power Dissipation, TA = 50°C
145
TJ = TA + (PD × θJA)
(2)
(3)
135
125
115
105
95
where:
TA is the ambient temperature.
PD is the total power dissipation in the die, given by
PD = PBUCK = PSW + PTRAN + PSW_COND
where:
P
SW, PTRAN, and PSW_COND are defined in the Efficiency section.
2
6400mm
85
75
65
2
500mm
100mm
2
T
MAX
J
0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
TOTAL POWER DISSIPATION (W)
Figure 88. Junction Temperature vs. Power Dissipation, TA = 65°C
Rev. A | Page 29 of 32
ADP2370/ADP2371
Data Sheet
135
PCB LAYOUT CONSIDERATIONS
Improve heat dissipation from the package by increasing
the amount of copper attached to the pins of the ADP2370/
ADP2371. However, as listed in Table 8, a point of diminishing
returns is eventually reached, beyond which an increase in the
copper size does not yield significant heat dissipation benefits.
125
115
105
95
Poor layout can affect the ADP2370/ADP2371 buck performance
causing electromagnetic interference (EMI), poor electromagnetic
compatibility (EMC) performance, ground bounce, and voltage
losses; thus, regulation and stability can be affected. Implement
a good PCB layout to ensure optimum performance by applying
the following rules:
2
6400mm
2
500mm
100mm
2
T
MAX
J
85
0
0.2
0.4
0.6
0.8
1.0
TOTAL POWER DISSIPATION (W)
•
Place the inductor, input capacitor, and output capacitor
close to the IC using short tracks. These components carry
high switching frequencies and long, large tracks act like
antennas.
Route the output voltage path away from the inductor and
SW node to minimize noise and magnetic interference.
Use a ground plane with several vias connected to the
component-side ground to reduce noise interference on
sensitive circuit nodes.
Figure 89. Junction Temperature vs. Power Dissipation, TA = 85°C
In cases where the board temperature is known, use the thermal
characterization parameter, ΨJB, to estimate the junction temper-
ature rise. Maximum junction temperature (TJ) is calculated
from the board temperature (TB) and power dissipation (PD)
using the formula:
•
•
TJ = TB + (PD × ΨJB)
(5)
The typical ΨJB value for the 8-lead, 3 mm × 3 mm LFCSP is
•
Use of 0402-size or 0603-size capacitors achieves the smallest
possible footprint solution on boards where area is limited.
22.2°C /W.
140
120
100
25°C
50°C
65°C
80
85°C
MAX
60
T
J
40
20
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
TOTAL POWER DISSIPATION (W)
Figure 90. Junction Temperature vs. Power Dissipation,
Different Board Temperatures
Rev. A | Page 30 of 32
Data Sheet
ADP2370/ADP2371
Figure 91. PCB Layout, Top
Figure 92. PCB Layout, Bottom
Rev. A | Page 31 of 32
ADP2370/ADP2371
Data Sheet
PACKAGING AND ORDERING INFORMATION
OUTLINE DIMENSIONS
2.48
2.38
2.23
3.00
BSC SQ
5
8
EXPOSED
PAD
1.74
1.64
1.49
0.50
0.40
0.30
4
1
INDEX
AREA
PIN 1
INDICATOR
(R 0.2)
TOP VIEW
BOTTOM VIEW
0.80 MAX
0.55 NOM
0.80
0.75
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.70
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.30
0.25
0.18
0.20 REF
0.50 BSC
COMPLIANT TO JEDEC STANDARDS MO-229-WEED-4
Figure 93. 8-Lead Lead Frame Chip Scale Package [LFCSP]
(CP-8-5)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Buck Output Voltage (V)
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
8-Lead LFCSP
8-Lead LFCSP
8-Lead LFCSP
8-Lead LFCSP
8-Lead LFCSP
8-Lead LFCSP
8-Lead LFCSP
8-Lead LFCSP
8-Lead LFCSP
8-Lead LFCSP
8-Lead LFCSP
8-Lead LFCSP
REDYKIT
Package Option
Branding
LL4
LL5
LL6
LL7
LL8
LL9
LLB
LGZ
LLJ
ADP2370ACPZ-1.2-R7
ADP2370ACPZ-1.5-R7
ADP2370ACPZ-1.8-R7
ADP2370ACPZ-2.5-R7
ADP2370ACPZ-3.0-R7
ADP2370ACPZ-3.3-R7
ADP2370ACPZ-5.0-R7
ADP2370ACPZ-R7
1.2
1.5
1.8
2.5
3.0
3.3
5.0
CP-8-5
CP-8-5
CP-8-5
CP-8-5
CP-8-5
CP-8-5
CP-8-5
CP-8-5
CP-8-5
CP-8-5
CP-8-5
CP-8-5
Adjustable
1.2 with QOD
1.8 with QOD
3.3 with QOD
Adjustable with QOD
ADP2371ACPZ-1.2-R7
ADP2371ACPZ-1.8-R7
ADP2371ACPZ-3.3-R7
ADP2371ACPZ-R7
LLK
LLL
LLM
ADP2370CPZ-REDYKIT
1 Z = RoHS Compliant Part.
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09531-0-5/12(A)
Rev. A | Page 32 of 32
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