ADN8102ACPZ-R7_技术文档

3.75 Gbps Quad Bidirectional

CX4 Equalizer

ADN8102

FUNCTIONAL BLOCK DIAGRAM

FEATURES

Optimized for dc to 3.75 Gbps data

LOS_B

ADN8102

RECEIVE

EQUALIZATION

TRANSMIT

PRE-EMPHASIS

Programmable input equalization

Up to 22 dB boost at 1.875 GHz

Ix_B[3:0]

LB

PE

EQ

2:1

Ox_B[3:0]

LOS_A

Compensates up to 30 meters of CX4 cable up to 3.75 Gbps

Compensates up to 40 inches of FR4 up to 3.75 Gbps

Programmable output pre-emphasis/de-emphasis

Up to 12 dB boost at 1.875 GHz (3.75 Gbps)

Compensates up to 15 meters of CX4 cable up to 3.75 Gbps

Compensates up to 40 inches of FR4 up to 3.75 Gbps

Flexible 1.8 V to 3.3 V core supply

RECEIVE

EQUALIZATION

TRANSMIT

PRE-EMPHASIS

Ox_A[3:0]

PE

EQ

Ix_A[3:0]

2:1

Per lane P/N pair inversion for routing ease

Low power: 125 mW/channel up to 3.75 Gbps

DC- or ac-coupled differential CML inputs

Programmable CML output levels

EQ_A[1:0]

PE_A[1:0]

EQ_B[1:0]

PE_B[1:0]

ENA

ADDR[1:0]

SCL

SDA

RESET

CONTROL LOGIC

ENB

50 Ω on-chip termination

Loss-of-signal detection

Figure 1.

Temperature range operation: −40°C to +85°C

Supports 8b10b, scrambled, or uncoded NRZ data

I²C control interface

GENERAL DESCRIPTION

The ADN8102 is a quad bidirectional CX4 cable/backplane

equalizer with eight differential PECL-/CML-compatible inputs

with programmable equalization and eight differential CML

outputs with programmable output levels and pre-emphasis or

de-emphasis. The operation of this device is optimized for NRZ

data at rates up to 3.75 Gbps.

64-lead LFSCP (QFN) package

APPLICATIONS

10GBase-CX4

HiGig™

InfiniBand

1×, 2× Fibre Channel

XAUI

Gigabit Ethernet over backplane or cable

CPRI™

50 Ω cables

The receive inputs provide programmable equalization to

compensate for up to 30 meters of CX4 cable (24 AWG) or

40 inches of FR4, and programmable pre-emphasis to compensate

for up to 15 meters of CX4 cable (24 AWG) or 40 inches of FR4

at 3.75 Gbps. Each channel also provides programmable loss-of-

signal detection and loopback capability for system testing and

debugging.

The ADN8102 is controlled through toggle pins, an I²C® control

interface that provides more flexible control, or a combination of

both. Every channel implements an asynchronous path supporting

dc to 3.75 Gbps NRZ data, fully independent of other channels. The

ADN8102 has low latency and very low channel-to-channel skew.

The main application for the ADN8102 is to support switching

in chassis-to-chassis applications over CX4 or InfiniBand® cables.

The ADN8102 is packaged in a 9 mm × 9 mm 64-lead LFCSP

(QFN) package and operates from −40°C to +85°C.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADN8102

TABLE OF CONTENTS

Features .............................................................................................. 1

Lane Inversion ............................................................................ 18

Loopback ..................................................................................... 19

Transmitters ................................................................................ 20

Selective Squelch and Disable................................................... 25

I²C Control Interface...................................................................... 26

Serial Interface General Functionality..................................... 26

I²C Interface Data Transfers—Data Write .............................. 26

I²C Interface Data Transfers—Data Read ............................... 27

PCB Design Guidelines ................................................................. 28

Power Supply Connections and Ground Planes .................... 28

Transmission Lines..................................................................... 28

Soldering Guidelines for Chip Scale Package............................. 28

Register Map ................................................................................... 29

Outline Dimensions....................................................................... 31

Ordering Guide .......................................................................... 31

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Specifications .................................................................. 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 9

Theory of Operation ...................................................................... 16

Introduction ................................................................................ 16

Receivers...................................................................................... 16

Equalization Settings.................................................................. 17

REVISION HISTORY

8/08—Rev. 0 to Rev. A

Changes to Features Section............................................................ 1

Changes to Loss of Signal/Signal Detect Section ....................... 18

Added Recommended LOS Settings Section.............................. 18

Deleted Figure 39; Renumbered Sequentially ............................ 18

Exposed Paddle Notation Added to Outline Dimensions ........ 31

5/08—Revision 0: Initial Version

Rev. A | Page 2 of 32

ADN8102

SPECIFICATIONS

V_CC= 1.8 V, V_EE= 0 V, V_TTI= V_TTO= V_CC, R_L= 50 Ω, differential output swing = 800 mV p-p differential, 3.75 Gbps, PRBS 2⁷− 1,

T_A= 25°C, unless otherwise noted.

Table 1.

Parameter

Conditions

Min

Typ

Max Unit

DYNAMIC PERFORMANCE

Maximum Data Rate/Channel (NRZ)

Deterministic Jitter

3.75

Gbps

ps p-p

ps rms

Data rate < 3.75 Gbps; BER = 1 × 10⁻¹²

V_CC= 1.8 V

33

1.5

Random Jitter

Residual Deterministic Jitter

With Input Equalization

Data rate < 3.25 Gbps; 0 inches to 40 inches FR4

Data rate < 3.25 Gbps; 0 meters to 30 meters CX4

Data rate < 3.75 Gbps; 0 inches to 40 inches FR4

Data rate < 3.75 Gbps; 0 meters to 30 meters CX4

Data rate < 3.25 Gbps; 0 inches to 40 inches FR4

Data rate < 3.25 Gbps; 0 meters to 15 meters CX4

Data rate < 3.75 Gbps; 0 inches to 40 inches FR4

Data rate < 3.75 Gbps; 0 meters to 15 meters CX4

20% to 80%

0.20

0.19

0.24

0.21

0.13

0.37

0.14

0.41

75

UI

ps

ns

ps

With Output Pre-Emphasis

Output Rise/Fall Time

Propagation Delay

Channel-to-Channel Skew

OUTPUT PRE-EMPHASIS

Equalization Method

Maximum Boost

1

50

1-tap programmable pre-emphasis

800 mV p-p output swing

200 mV p-p output swing

Minimum

6

12

2

dB

mA

Pre-Emphasis Tap Range

Maximum

12

INPUT EQUALIZATION

Minimum Boost

Maximum Boost

Number of Equalization Settings

Gain Step Size

EQBY = 1

1.5

22

8

dB

Maximum boost occurs at 1.875 GHz

2.5

dB

INPUT CHARACTERISTICS

Input Voltage Swing

Input Voltage Range

1

Differential, V_ICM= V_CC− 0.6 V

300

45

2000 mV p-p

V p-p

Single-ended absolute voltage level, V_Lminimum

Single-ended absolute voltage level, V_Hmaximum

Single-ended

V_EE+ 0.4

V_CC+ 0.5

50

V p-p

Input Resistance

55

Ω

Input Return Loss

Measured at 2.5 GHz

5

dB

OUTPUT CHARACTERISTICS

Output Voltage Swing

DC, differential, PE = 0, default, V_CC= 1.8 V

DC, differential, PE = 0, default, V_CC= 3.3 V

DC, differential, PE = 0, minimum output level,²V_CC= 1.8 V

DC, differential, PE = 0, minimum output level,²V_CC= 3.3 V

DC, differential, PE = 0, maximum output level,²V_CC= 1.8 V

DC, differential, PE = 0, maximum output level,²V_CC= 3.3 V

635

740

800

100

1300

1800

870

mV p-p

Rev. A | Page 3 of 32

ADN8102

Parameter

Conditions

Min

Typ

Max Unit

Output Voltage Range

Single-ended absolute voltage level, TxHeadroom = 0;

V_Lminimum

V_CC− 1.1

V

Single-ended absolute voltage level, TxHeadroom = 0;

V_Hmaximum

Single-ended absolute voltage level, TxHeadroom = 1;

V_Lminimum

Single-ended absolute voltage level, TxHeadroom = 1;

V_Hmaximum

V

_CC+ 0.6

V

V_CC− 1.2

V_CC+ 0.6

Output Current

Minimum output current per channel

Maximum output current per channel, V_CC= 1.8 V

Single-ended

2

mA

Ω

21

50

5

Output Resistance

Output Return Loss

LOS CHARACTERISTICS

Assert Level

Deassert Level

POWER SUPPLY

Operating Range

V_CC

43

57

Measured at 2.5 GHz

dB

IN_A/IN_B THRESH = 0x0C

IN_A/IN_B HYST = 0x0D

20

225

mV diff

V_EE= 0 V

1.7

3.0

1.8

3.3

3.6

V

DV_CC

V_TTI

V_TTO

V_EE= 0 V, DV_CC≤ (V_CC+ 1.3 V)

(V_EE+ 0.4 V + 0.5 × V_ID) < V_TTI< (V_CC+ 0.5 V)

(V_CC− 1.1 V + 0.5 × V_OD) < V_TTO< (V_CC+ 0.5 V)

V_EE+ 0.4 1.8

V_CC− 1.1 1.8

Supply Current

V_TTO

V_CC

All outputs enabled

63

460

586

69

565

mA

V_EE

LOGIC CHARACTERISTICS

Input High, V_IH

Input Low, V_IL

Output High, V_OH

Output Low, V_OL

THERMAL CHARACTERISTICS

Operating Temperature Range

θ_JA

DV_CC= 3.3 V

2.5

V

1.0

−40

22

+85

°C

°C/W

¹V_ICMis the input common-mode voltage.

²Programmable via I²C.

Rev. A | Page 4 of 32

ADN8102

TIMING SPECIFICATIONS

Table 2. I²C Timing Parameters

Parameter

Min

Max

400

N/A

300

N/A

7

Unit

kHz

μs

ns

μs

ns

pF

Description

f_SCL

0

SCL clock frequency

t_HD:STA

t_SU:STA

t_LOW

t_HIGH

t_HD:DAT

t_SU:DAT

t_R

t_F

t_SU:STO

t_BUF

0.6

1.3

0.6

0

10

1

Hold time for a start condition

Setup time for a repeated start condition

Low period of the SCL clock

High period of the SCL clock

Data hold time

Data setup time

Rise time for both SDA and SCL

Fall time for both SDA and SCL

Setup time for a stop condition

Bus free time between a stop and a start condition

Capacitance for each I/O pin

0.6

1

5

C_IO

SDA

t_SU:DAT

t_R

t_F

t_BUF

t_HD:STA

t_R

t_LOW

t_F

SCL

t_HD:STA

t_SU:STA

t_SU:STO

t_HIGH

t_HD:DAT

S

Sr

P

S

Figure 2. I²C Timing Diagram

Rev. A | Page 5 of 32

ADN8102

ABSOLUTE MAXIMUM RATINGS

Table 3.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress rating

only; functional operation of the device at these or any other

conditions above those indicated in the operational section of

this specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect device reliability.

Parameter

Rating

V_CCto V_EE

3.7 V

V_TTI

V_CC+ 0.6 V

V_TTO

V_CC+ 0.6 V

Internal Power Dissipation

Differential Input Voltage

Logic Input Voltage

Storage Temperature Range

Lead Temperature

4.26 W

2.0 V

V_EE− 0.3 V < V_IN< V_CC+ 0.6 V

−65°C to +125°C

300°C

ESD CAUTION

Rev. A | Page 6 of 32

ADN8102

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

RESET

LOS_A

IN_A0

IP_A0

VCC

IN_A1

IP_A1

VTTI

IN_A2

IP_A2 10

VEE 11

IN_A3 12

IP_A3 13

DVCC 14

EQ_A1 15

EQ_A0 16

1

2

3

4

5

6

7

8

9

48 SCL

47 SDA

46 LOS_B

45 IP_B0

44 IN_B0

43 VCC

42 IP_B1

41 IN_B1

40 VTTI

39 IP_B2

38 IN_B2

37 VEE

36 IP_B3

35 IN_B3

34 EQ_B1

33 EQ_B0

ADN8102

TOP VIEW

(Not to Scale)

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

RESET

LOS_A

IN_A0

IP_A0

VCC

IN_A1

IP_A1

VTTI

IN_A2

IP_A2

VEE

IN_A3

IP_A3

DVCC

EQ_A1

EQ_A0

VEE

Type

Description

1

Control

Digital I/O

I/O

Power

I/O

Power

I/O

Power

I/O

Reset Input, Active Low

2

Port A Loss of Signal Status, Active Low

High Speed Input Complement

High Speed Input

Positive Supply

High Speed Input Complement

High Speed Input

Input Termination Supply

High Speed Input Complement

High Speed Input

Negative Supply

High Speed Input Complement

High Speed Input

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

I/O

Power

Control

Power

Control

I/O

Power

I/O

Power

I/O

Power

Digital Power Supply

Port A Input Equalization MSB

Port A Input Equalization LSB

Negative Supply

Loopback Control

High Speed Output Complement

High Speed Output

Positive Supply

High Speed Output Complement

High Speed Output

Output Termination Supply

High Speed Output Complement

High Speed Output

LB

ON_B0

OP_B0

VCC

ON_B1

OP_B1

VTTO

ON_B2

OP_B2

VEE

Negative Supply

Rev. A | Page 7 of 32

ADN8102

Pin No.

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

EP

Mnemonic

ON_B3

OP_B3

ENB

PE_B1

PE_B0

EQ_B0

EQ_B1

IN_B3

IP_B3

VEE

IN_B2

IP_B2

VTTI

IN_B1

IP_B1

VCC

Type

I/O

Control

I/O

Power

I/O

Power

I/O

Description

High Speed Output Complement

High Speed Output

Port B Enable

Port B Output Pre-Emphasis MSB

Port B Output Pre-Emphasis LSB

Port B Input Equalization LSB

Port B Input Equalization MSB

High Speed Input Complement

High Speed Input

Negative Supply

High Speed Input Complement

High Speed Input

Input Termination Supply

High Speed Input Complement

High Speed Input

Positive Supply

High Speed Input Complement

High Speed Input

Port B Loss of Signal Status, Active Low

I²C Control Interface Data Input/Output

I²C Control Interface Clock Input

I²C Control Interface Address LSB

I²C Control Interface Address MSB

High Speed Output Complement

High Speed Output

Negative Supply

High Speed Output Complement

High Speed Output

Output Termination Supply

High Speed Output Complement

High Speed Output

I/O

Power

I/O

IN_B0

IP_B0

LOS_B

SDA

I/O

Digital I/O

Control

I/O

Power

I/O

Power

I/O

Power

I/O

SCL

ADDR0

ADDR1

ON_A3

OP_A3

VEE

ON_A2

OP_A2

VTTO

ON_A1

OP_A1

VCC

ON_A0

OP_A0

ENA

PE_A0

PE_A1

EPAD

Positive Supply

High Speed Output Complement

High Speed Output

I/O

Control

Power

Port A Enable

Port A Output Pre-Emphasis LSB

Port A Output Pre-Emphasis MSB

EPAD Must Be Connected to VEE

Rev. A | Page 8 of 32

ADN8102

TYPICAL PERFORMANCE CHARACTERISTICS

50Ω CABLES

2

INPUT

OUTPUT

DATA OUT

50Ω

HIGH SPEED

SAMPLING

ADN8102

AC-COUPLED

EVALUATION

BOARD

PATTERN

GENERATOR

TP1

TP2

OSCILLOSCOPE

Figure 4. Standard Test Circuit (No Channel)

50ps/DIV

Figure 5. 3.25 Gbps Input Eye (TP1 from Figure 4)

Figure 7. 3.25 Gbps Output Eye, No Channel (TP2 from Figure 4)

50ps/DIV

Figure 6. 3.75 Gbps Input Eye (TP1 from Figure 4)

Figure 8. 3.75 Gbps Output Eye, No Channel (TP2 from Figure 4)

Rev. A | Page 9 of 32

ADN8102

50Ω CABLES

2

INPUT OUTPUT

PIN PIN

DATA OUT

FR4 TEST BACKPLANE

50Ω

DIFFERENTIAL

STRIPLINE TRACES

8mils WIDE, 8mils SPACE,

8mils DIELECTRIC HEIGHT

ADN8102

AC-COUPLED

EVALUATION

BOARD

PATTERN

GENERATOR

HIGH SPEED

SAMPLING

OSCILLOSCOPE

TP1

TP2

TP3

TRACE LENGTHS = 40''

50ps/DIV

REFERENCE EYE DIAGRAM AT TP1

Figure 9. Input Equalization Test Circuit, FR4

50ps/DIV

Figure 10. 3.25 Gbps Input Eye, 40 Inch FR4 Input Channel (TP2 from Figure 9)

Figure 12. 3.25 Gbps Output Eye, 40 Inch FR4 Input Channel, Best EQ Setting

(TP3 from Figure 9)

50ps/DIV

Figure 11. 3.75 Gbps Input Eye, 40 Inch FR4 Input Channel (TP2 from Figure 9)

Figure 13. 3.75 Gbps Output Eye, 40 Inch FR4 Input Channel, Best EQ Setting

(TP3 from Figure 9)

Rev. A | Page 10 of 32

ADN8102

50Ω CABLES

2

INPUT OUTPUT

PIN PIN

DATA OUT

30m CX4 CABLE

50Ω

ADN8102

AC-COUPLED

EVALUATION

BOARD

PATTERN

GENERATOR

HIGH SPEED

SAMPLING

OSCILLOSCOPE

TP1

TP2

TP3

50ps/DIV

REFERENCE EYE DIAGRAM AT TP1

Figure 14. Input Equalization Test Circuit, CX4

50ps/DIV

Figure 15. 3.25 Gbps Input Eye, 30 Meters CX4 Cable (TP2 from Figure 14)

Figure 17. 3.25 Gbps Output Eye, 30 Meters CX4 Cable, Best EQ Setting

(TP3 from Figure 14)

50ps/DIV

Figure 16. 3.75 Gbps Input Eye, 30 Meters CX4 Cable (TP2 from Figure 14)

Figure 18. 3.75 Gbps Output Eye, 30 Meters CX4 Cable, Best EQ Setting

(TP3 from Figure 14)

Rev. A | Page 11 of 32

ADN8102

50Ω CABLES

2

INPUT OUTPUT

PIN PIN

DATA OUT

FR4 TEST BACKPLANE

50Ω

DIFFERENTIAL

STRIPLINE TRACES

8mils WIDE, 8mils SPACE,

8mils DIELECTRIC HEIGHT

ADN8102

AC-COUPLED

EVALUATION

BOARD

PATTERN

GENERATOR

HIGH SPEED

SAMPLING

TP1

TP2

TP3

OSCILLOSCOPE

TRACE LENGTHS = 40''

50ps/DIV

REFERENCE EYE DIAGRAM AT TP1

Figure 19. Output Pre-Emphasis Test Circuit, FR4

50ps/DIV

Figure 20. 3.25 Gbps Output Eye, 40 Inch FR4 Output Channel,

PE = 0 (TP3 from Figure 19)

Figure 22. 3.25 Gbps Output Eye, 40 Inch FR4 Output Channel,

PE = Best Setting (TP3 from Figure 19)

50ps/DIV

Figure 21. 3.75 Gbps Output Eye, 40 Inch FR4 Output Channel,

PE = 0 (TP3 from Figure 19)

Figure 23. 3.75 Gbps Output Eye, 40 Inch FR4 Output Channel,

PE = Best Setting (TP3 from Figure 19)

Rev. A | Page 12 of 32

ADN8102

50Ω CABLES

2

INPUT OUTPUT

PIN PIN

DATA OUT

15m CX4 CABLE

50Ω

ADN8102

AC-COUPLED

EVALUATION

BOARD

PATTERN

GENERATOR

HIGH SPEED

SAMPLING

OSCILLOSCOPE

TP1

TP2

TP3

50ps/DIV

REFERENCE EYE DIAGRAM AT TP1

Figure 24. Output Pre-Emphasis Test Circuit, CX4

50ps/DIV

Figure 25. 3.25 Gbps Output Eye, 15 Meters CX4 Cable,

PE = 0 (TP3 from Figure 24)

Figure 27. 3.25 Gbps Output Eye, 15 Meters CX4 Cable,

PE = Best Setting (TP3 from Figure 24)

50ps/DIV

Figure 26. 3.75 Gbps Output Eye, 15 Meters CX4 Cable,

PE = 0 (TP3 from Figure 24)

Figure 28. 3.75 Gbps Output Eye, 15 Meters CX4 Cable,

PE = Best Setting (TP3 from Figure 24)

Rev. A | Page 13 of 32

ADN8102

80

100

70

60

50

40

80

60

40

20

V

= 3.3V

CC

30

20

10

V

= 1.8V

CC

0

1.0

20

40

60

2.5

100

1.5

2.0

2.5

3.0

3.5

4.0

DATA RATE (Hz)

INPUT COMMON MODE (V)

Figure 29. Deterministic Jitter vs. Data Rate

Figure 32. Deterministic Jitter vs. Input Common Mode

100

90

80

70

60

50

40

30

20

10

100

80

60

40

20

0

1.0

0.5

1.0

1.5

2.0

1.5

2.0

2.5

(V)

3.0

3.5

4.0

DIFFERENTIAL INPUT SWING (V)

V

CC

Figure 30. Deterministic Jitter vs. Differential Input Swing

Figure 33. Deterministic Jitter vs. Supply Voltage

100

80

60

40

20

80

60

40

20

V

= 1.8V

CC

V

= 3.3V

CC

0

–60

0

1.0

–40

–20

0

20

40

60

80

1.5

2.0

2.5

(V)

3.0

3.5

4.0

TEMPERATURE (°C)

V

TTO

Figure 31. Deterministic Jitter vs. Temperature

Figure 34. Deterministic Jitter vs. Output Termination Voltage

Rev. A | Page 14 of 32

ADN8102

450000

400000

350000

300000

250000

200000

150000

100000

50000

0

100

90

80

70

60

t

/t

F

R

50

–60

–8

–6

–4

–2

0

2

4

6

8

10

–40

–20

0

20

40

60

80

100

JITTER (ps)

TEMPERATURE (°C)

Figure 35. Random Jitter Histogram

Figure 36. Rise Time (t_R)/Fall Time (t_F) vs. Temperature

Rev. A | Page 15 of 32

ADN8102

THEORY OF OPERATION

RECEIVERS

Input Structure and Input Levels

LOS_B

ADN8102

RECEIVE

EQUALIZATION

TRANSMIT

PRE-EMPHASIS

The ADN8102 receiver inputs incorporate 50 Ω termination

resistors, ESD protection, and a multizero transfer function

equalizer that can be optimized for backplane or cable operation.

Each channel also provides a programmable loss-of-signal (LOS)

function that provides an interrupt that can be used to squelch

or disable the associated output when the differential input voltage

falls below the programmed threshold value. Each receive channel

also provides a P/N inversion function that allows the user to

swap the sign of the input signal path to eliminate the need for

board-level crossovers in the receiver channel.

Ix_B[3:0]

LB

PE

EQ

2:1

Ox_B[3:0]

LOS_A

RECEIVE

EQUALIZATION

TRANSMIT

PRE-EMPHASIS

Ox_A[3:0]

PE

Ix_A[3:0]

EQ

2:1

EQ_A[1:0]

PE_A[1:0]

EQ_B[1:0]

PE_B[1:0]

ENA

ADDR[1:0]

SCL

SDA

RESET

CONTROL LOGIC

Table 5 illustrates some, but not all, possible combinations of

input supply voltages.

ENB

Figure 37. Simplified Functional Block Diagram

Table 5. Common Input Voltage Levels

Configuration

INTRODUCTION

V_CC(V)

1.8

3.3

V_TTI(V)

1.6

1.8

3.3

The ADN8102 is a quad bidirectional cable and backplane

equalizer that provides both input equalization and output pre-

emphasis on both the line card and cable sides of the device.

The device supports full loopback and through connectivity

of the two unidirectional half-links, each consisting of four

differential signal pairs.

Low V_TTI, AC-Coupled Input

Single 1.8 V Supply

3.3 V Core

Single 3.3 V Supply

SIMPLIFIED RECEIVER INPUT CIRCUIT

VCC

VTTI

The ADN8102 offers extensively programmable output levels

and pre-emphasis as well as the ability to disable the output

current. The receivers integrate a programmable, multizero

equalizer transfer function that is optimized to compensate

either typical backplane or typical cable losses.

RLN

Q1

RLP

RP

52Ω

RN

52Ω

R1

750Ω

IP

IN

R3

1kΩ

Q2

The I/O on-chip termination resistors are terminated to user-

settable supplies to support dc coupling in a wide range of logic

styles. The ADN8102 supports a wide core supply range; V_CC

can be set from 1.8 V to 3.3 V. These features, together with

programmable output levels, allow for a wide range of dc- and

ac-coupled I/O configurations.

R2

750Ω

I1

VEE

Figure 38. Simplified Input Structure

Rev. A | Page 16 of 32

ADN8102

Setting the LUT SELECT bit = 1 (Bit 1 in the IN_Ax/IN_Bx FR4

control registers) allows the default map selection (CX4 or FR4

optimized) to be overwritten via the LUT FR4/CX4 bit (Bit 0)

in the IN_Ax/IN_Bx FR4 control registers. Setting this bit high

selects the FR4 optimized map, and setting it low selects the CX4

optimized map. These settings are set on a per channel basis

(see Table 7 and Table 17).

EQUALIZATION SETTINGS

The ADN8102 receiver incorporates a multizero transfer function

continuous time equalizer that provides up to 22 dB of high

frequency boost at 1.875 GHz to compensate up to 30 meters

of CX4 cable or 40 inches of FR4 at 3.75 Gbps. The ADN8102

allows joint control of the equalizer transfer function of the

four equalizer channels in a single port through the I²C control

interface. Port A and Port B equalizer transfer functions are

controlled via Register 0x80 and Register 0xA0, respectively.

The equalizer transfer function allows independent control of

the boost in two different frequency ranges for optimal matching

with the loss shape of the user’s channel (for example, skin-effect

loss dominated or dielectric loss dominated). By default, the

equalizer control is simplified to two independent maps of basic

settings that provide nine settings, each optimized for CX4 cable

and FR4 to ease programming for typical channels. The default

state of the part selects the CX4 optimized equalization map for

the IN_A[3:0] channels that interface with the cable and the FR4

optimized equalization map for the IN_B[3:0] channels that

interface with the board. Full control of the equalizer is available via

the I²C control interface by writing register bit MODE[0] = 1 at

Address 0x0F. Table 6 summarizes the high frequency boost for

each of the basic control settings and the typical length of CX4

cable and FR4 trace that each setting compensates. Setting the

EQBY bit of the IN_A/IN_B configuration registers high sets

the equalization to 1.5 dB of boost, which compensates 0 meters

to 2 meters of CX4 or 0 inches to 10 inches of FR4.

The user can also specify the boost in the mid frequency and high

frequency ranges independently. This is done by writing to the

IN_A/IN_B EQ1 control and IN_A/IN_B EQ2 control registers for

the channel of interest. Each of these registers provides 32 settings

of boost, with IN_A/IN_B EQ1 control setting the mid-frequency

boost and IN_A/IN_B EQ2 control setting the high frequency

boost. The IN_A/IN_B EQx control registers are ordered such

that Bit 5 is a sign bit, and midlevel boost is centered on 0x00;

setting Bit 5 low and increasing the LSBs results in decreasing

boost, while setting Bit 5 high and increasing the LSBs results in

increasing boost. The EQ CTL SRC bit (Bit 6) in the IN_A/IN_B

EQ1 Control registers determines whether the equalization

control for the channel of interest is selected from the optimized

map or directly from the IN_A/IN_B EQx control registers (per

port). Setting this bit high selects equalization control directly

from the IN_A/IN_B EQx control registers, and setting it low

selects equalization control from the selected optimized map.

Table 6. Receive Equalizer Boost vs. Setting (CX4 and FR4 Optimized Maps)

IN_Ax/IN_Bx

Cable Optimized

FR4 Optimized

Configuration, EQ[2:0]

0¹

Boost (dB)

Typical CX4 Cable Length (Meters)

Boost (dB)

3.5

Typical FR4 Trace Length (Inches)

10

12

14

17

19

20

21

22

4 to 6

5 to 10

1

8 to 10

3.9

10 to 15

15 to 20

20 to 25

25 to 30

30 to 35

35 to 40

2¹

3

12 to 14

16 to 18

20 to 22

24 to 26

28 to 30

30 to 32

4.25

4.5

4

5¹

4.75

5.0

6

7¹

5.3

5.5

¹These EQ settings are also available via the external device pins, EQ_A[1:0] and EQ_B[1:0].

Table 7. Receive Configuration and Equalization Registers

Name

Address

Bit 7 Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

IN_A/IN_B

0x80, 0xA0

PNSWAP

EQBY

EN

EQ[2]

EQ[1]

EQ[0]

0x30

Configuration

IN_A/IN_B

EQ1 Control

IN_A/IN_B

0x83, 0xA3

0x84, 0xA4

EQ CTL SRC EQ1[5] EQ1[4] EQ1[3] EQ1[2] EQ1[1]

EQ2[5] EQ2[4] EQ2[3] EQ2[2] EQ2[1]

EQ1[0]

EQ2[0]

0x00

EQ2 Control

IN_Ax/IN_Bx

FR4 Control

0x85, 0x8D, 0x95,

0x9D, 0xA5, 0xAD,

0xB5, 0xBD

LUT SELECT LUT FR4/CX4 0x00

Rev. A | Page 17 of 32

ADN8102

Recommended LOS Settings

Loss of Signal/Signal Detect

Recommended settings for LOS are as follows:

An independent signal detect output is provided for all eight

input ports of the device. The signal-detect function measures

the low frequency amplitude of the signal at the receiver input

and compares this measurement with a defined threshold level.

If the measurement indicates that the input signal swing is

smaller than the threshold for 250 μs, the channel indicates a

loss-of-signal event. Assertion and deassertion of the LOS signal

occurs within 100 μs of the event.

•

Set IN_A/IN_B THRESH to 0x0C for an assert voltage of

20 mV differential (40 mV p-p differential).

•

Set IN_A/IN_B HYST to 0x0D for a deassert voltage of

225 mV differential (450 mV p-p differential).

LANE INVERSION

The input P/N inversion is a feature intended to allow the user

to implement the equivalent of a board-level crossover in a much

smaller area and without additional via impedance discontinuities

that degrade the high frequency integrity of the signal path. The

P/N inversion is available on a per port basis and is controlled

through the I²C control interface. The P/N inversion is accom-

plished by writing to the PNSWAP bit (Bit 6) of the IN_A/IN_B

configuration register (see Table 7) with low representing a

noninverting configuration and high representing an inverting

configuration. Note that using this feature to account for signal

inversions downstream of the receiver requires additional attention

when switching connectivity.

The LOS-assert and LOS-deassert levels are set on a per channel

basis through the I²C control interface, by writing to the IN_A/

IN_B LOS threshold and IN_A/IN_B LOS hysteresis registers,

respectively. The recommended settings are IN_A/IN_B THRESH

= 0x0C and IN_A/IN_B HYST = 0x0D. All ports are factory

tested with these settings to ensure that an LOS event is asserted

for single-ended dc input swings less than 20 mV and is deasserted

for single-ended dc input swings greater than 225 mV.

The LOS status for each individual channel can be accessed

through the I²C control interface. The independent channel

LOS status can be read from the IN_A/IN_B LOS status registers

(Address 0x1F and Address 0x3F). The four LSBs of each register

represent the current LOS status of each channel, with high

representing an ongoing LOS event. The four MSBs of each

register represent the historical LOS status of each channel,

with high representing a LOS event at any time on a specific

channel. The MSBs are sticky and remain high once asserted

until cleared by the user by overwriting the bits to 0.

Table 8. LOS Threshold and Hysteresis Control Registers

Name

Address Bit 7 Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

IN_A/IN_B

LOS Threshold

0x81,

0xA1

THRESH[6] THRESH[5] THRESH[4] THRESH[3] THRESH[2] THRESH[1] THRESH[0] 0x04

IN_A/IN_B

0x82,

HYST[6]

HYST[5]

HYST[4]

HYST[3]

HYST[2]

HYST[1]

HYST[0]

0x12

LOS Hysteresis 0xA2

Table 9. LOS Status Registers

Name

Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

IN_A/IN_B

LOS Status

0x1F,

0x3F

STICKY

LOS[3]

STICKY

LOS[2]

STICKY

LOS[1]

STICKY LOS [0]

REAL-TIME

LOS[3]

REAL-TIME

LOS[2]

REAL-TIME

LOS[1]

REAL-TIME

LOS[0]

Rev. A | Page 18 of 32

ADN8102

Bit 1 represents loopback of the Port A inputs to the Port B

LOOPBACK

outputs (cable side loopback). Bit 0 represents loopback of the

Port B inputs to the Port A outputs (board side loopback), with

high representing loopback for both bits. Bit 0 is also controlled

through the LB pin with I²C data overwriting the pin state. Both

input ports can be looped back simultaneously (full loopback)

by writing high to both Bit 0 and Bit 1, but in this case, valid

data is disrupted on each channel. Figure 39 illustrates the three

loopback modes.

The ADN8102 provides loopback on both input ports (Port A:

cable interface input, Port B: line card interface input). The external

loopback toggle pin, LB, controls the loopback of the Port B input

only (board side loopback). When loopback is asserted, valid

data continues to pass through the Port B link, but the Port B

input signals are also shunted to the Port A output to allow testing

and debugging without disrupting valid data. This loopback, as

well as loopback of the Port A input (cable side loopback), can

be programmed through the I²C interface. The loopbacks are

controlled through the I²C interface by writing to Bit 0 and

Bit 1 of the global configuration control register (Register 0x02).

CABLE SIDE LOOPBACK

BOARD SIDE LOOPBACK

FULL LOOPBACK

RECEIVE

EQUALIZATION

TRANSMIT

PRE-EMPHASIS

RECEIVE

EQUALIZATION

TRANSMIT

PRE-EMPHASIS

RECEIVE

EQUALIZATION

TRANSMIT

PRE-EMPHASIS

Ix_B[3:0]

LB

PE

Ox_B[3:0]

LOS_A

Ix_B[3:0]

LB

PE

Ox_B[3:0]

LOS_A

Ix_B[3:0]

LB

PE

Ox_B[3:0]

LOS_A

EQ

TRANSMIT

PRE-EMPHASIS

RECEIVE

EQUALIZATION

TRANSMIT

PRE-EMPHASIS

RECEIVE

EQUALIZATION

TRANSMIT

PRE-EMPHASIS

RECEIVE

EQUALIZATION

Ox_A[3:0]

Ix_A[3:0]

Ox_A[3:0]

Ix_A[3:0]

Ox_A[3:0]

Ix_A[3:0]

PE

EQ

EQ_A[1:0]

PE_A[1:0]

EQ_B[1:0]

PE_B[1:0]

ENA

EQ_A[1:0]

PE_A[1:0]

EQ_B[1:0]

PE_B[1:0]

ENA

EQ_A[1:0]

PE_A[1:0]

EQ_B[1:0]

PE_B[1:0]

ENA

ADDR[1:0]

SCL

SDA

RESET

ADDR[1:0]

SCL

SDA

RESET

ADDR[1:0]

SCL

SDA

RESET

CONTROL LOGIC

ENB

Figure 39. Loopback Modes of Operation

Table 10. Global Configuration Register, Loopback Controls

Name

Address Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

LB[1]

Bit 0

Default

Global Configuration Control

0x02

LB[0]

0x00

Rev. A | Page 19 of 32

ADN8102

The output equalization is optimized for less than 1.75 Gbps

operation but can be optimized for higher speed applications at

up to 3.75 Gbps through the I²C control interface by writing to

the DATA RATE bit (Bit 4) of the OUT_A/OUT_B configuration

registers, with high representing 3.75 Gbps and low representing

1.75 Gbps. The PE CTL SRC bit (Bit 7) in the OUT_A/OUT_B

Output Level Control 1 register determines whether the pre-

emphasis and output current controls for the channel of interest

are selected from the optimized map or directly from the OUT_A/

OUT_B Output Level Control[1:0] registers (per channel). Setting

this bit high selects pre-emphasis control directly from the

OUT_A/OUT_B Output Level Control[1:0] registers, and setting

it low selects pre-emphasis control from the optimized map.

TRANSMITTERS

Output Structure and Output Levels

The ADN8102 transmitter outputs incorporate 50 Ω termina-

tion resistors, ESD protection, and an output current switch. Each

port provides control of both the absolute output level and the

pre-emphasis output level. It should be noted that the choice of

output level affects the output common-mode level. A 600 mV

peak-to-peak differential output level with full pre-emphasis

range requires an output termination voltage of 2.5 V or greater

(V_TTO, V_CC≥ 2.5 V).

Pre-Emphasis

The total output amplitude and pre-emphasis setting space is

reduced to a single map of basic settings that provides seven

settings of output equalization to ease programming for typical

channels. The PE_A/PE_B[1:0] pins provide selections 0, 2, 4,

and 6 of the seven pre-emphasis settings through toggle pin

control, covering the entire range of settings at lower resolution.

The full resolution of seven settings is available through the I²C

interface by writing to Bits[2:0] (PE[2:0] of the OUT_A/OUT_B

configuration registers) with I²C settings overriding the toggle

pin control. Similar to the receiver settings, the ADN8102 allows

joint control of all four channels in a transmit port. Table 11

summarizes the absolute output level, pre-emphasis level, and

high frequency boost for each of the basic control settings and

the typical length of the CX4 cable and FR4 trace that each

setting compensates.

Tx SIMPLIFIED DIAGRAM

VCC

ON-CHIP

ESD

TERMINATION

VTTO

V3

VC

RP

RN

50Ω

V2

VP

OP

ON

V1

VN

Q1

Q2

I

TOT

I

+ I

PE

DC

VEE

Figure 40. Simplified Output Structure

Full control of the transmit output levels is available through the

I²C control interface. This full control is achieved by writing to

the OUT_A/OUT_B Output Level Control[1:0] registers for the

channel of interest. Table 13 shows the supported output level

settings of the OUT_A/OUT_B Output Level Control[1:0]

registers. Register settings not listed in Table 13 are not

supported by the ADN8102.

Table 11. Transmit Pre-Emphasis Boost and Overshoot vs. Setting

PE

0¹

1

Boost (dB) Overshoot DC Swing (mV p-p diff) Typical CX4 Cable Length (Meters) Typical FR4 Trace Length (Inches)

0

0%

800

600

400

0 to 2.5

0 to 5

2

25%

50%

75%

100%

133%

200%

2.5 to 5

0 to 5

2¹

3.5

4.9

6

5 to 7.5

10 to 15

15 to 20

20 to 25

25 to 30

3

7.5 to 10

10 to 12.5

15 to 17.5

20 to 22.5

4¹

5

6¹

7.4

9.5

¹These PE settings are also available via external device pins, PE_A[1:0] and PE_B[1:0].

Table 12. Output Configuration Registers

Name

Address

Bit 7

Bit 6 Bit 5 Bit 4

EN DATA RATE

OUTx_OLEV1[6:0]

OUTx_OLEV0[6:0]

Bit 3 Bit 2 Bit 1 Bit 0 Default

OUT_A/OUT_B Configuration

0xC0, 0xE0

PE[2] PE[1] PE[0] 0x20

OUT_A/OUT_B Output Level Control 1 0xC1, 0xE1 PE CTL SRC

OUT_A/OUT_B Output Level Control 0 0xC2, 0xE2

0x40

Rev. A | Page 20 of 32

ADN8102

Table 13. Output Level Settings

V_OD(mV)

V_DPeak (mV)

PE (dB)

0.00

9.54

13.98

16.90

19.08

20.83

22.28

0.00

6.02

9.54

12.04

13.98

15.56

16.90

0.00

4.44

7.36

9.54

11.29

12.74

13.98

0.00

3.52

6.02

7.96

9.54

10.88

12.04

0.00

2.92

5.11

6.85

8.30

9.54

10.63

0.00

2.50

4.44

6.02

7.36

8.52

9.54

0.00

2.18

3.93

5.38

6.62

7.71

8.67

0.00

1.94

3.52

4.86

6.02

7.04

7.96

I_TOT(mA)

2

6

10

14

18

22

26

4

OUT_A/OUT_B Output Level Control 0 OUT_A/OUT_B Output Level Control 1

50

0x00

0x11

0x22

0x33

0x44

0x55

0x66

0x00

0x11

0x22

0x33

0x44

0x55

0x66

0x00

0x11

0x22

0x33

0x44

0x55

0x66

0x00

0x11

0x22

0x33

0x44

0x55

0x66

0x00

0x11

0x22

0x33

0x44

0x55

0x66

0x00

0x11

0x22

0x33

0x44

0x55

0x66

0x00

0x11

0x22

0x33

0x44

0x55

0x66

0x00

0x11

0x22

0x33

0x44

0x55

0x66

Rev. A | Page 21 of 32

0x81

0x91

0x92

0xA2

0xA3

0xB3

0xB4

0xC4

150

250

350

450

550

650

100

200

300

400

500

600

700

150

250

350

450

550

650

750

200

300

400

500

600

700

800

250

350

450

550

650

750

850

300

400

500

600

700

800

900

350

450

550

650

750

850

950

400

500

600

700

800

900

1000

100

150

200

250

300

350

400

8

12

16

20

24

28

6

10

14

18

22

26

30

8

12

16

20

24

28

32

10

14

18

22

26

30

34

12

16

20

24

28

32

36

14

18

22

26

30

34

38

16

20

24

28

32

36

40

ADN8102

V_OD(mV)

450

500

550

600

650

700

750

800

850

900

V_DPeak (mV)

450

550

650

750

850

950

1050

500

600

700

800

900

1000

1100

550

650

750

850

950

1050

1150

600

700

800

900

1000

1100

1200

650

750

850

PE (dB)

0.00

1.74

3.19

4.44

5.52

6.49

7.36

0.00

1.58

2.92

4.08

5.11

6.02

6.85

0.00

1.45

2.69

3.78

4.75

5.62

6.41

0.00

1.34

2.50

3.52

4.44

5.26

6.02

0.00

1.24

2.33

3.30

4.17

4.96

0.00

1.16

2.18

3.10

3.93

0.00

1.09

2.05

2.92

0.00

1.02

1.94

0.00

0.97

0.00

I_TOT(mA)

18

22

26

30

34

38

42

20

24

28

32

36

40

44

22

26

30

34

38

42

46

24

28

32

36

40

44

48

26

30

34

38

42

46

28

32

36

40

44

30

34

38

42

32

36

40

34

38

36

OUT_A/OUT_B Output Level Control 0 OUT_A/OUT_B Output Level Control 1

0x00

0x11

0x22

0x33

0x44

0x55

0x66

0x00

0x11

0x22

0x33

0x44

0x55

0x66

0x00

0x11

0x22

0x33

0x44

0x55

0x66

0x00

0x11

0x22

0x33

0x44

0x55

0x66

0x01

0x12

0x23

0x34

0x45

0x56

0x02

0x13

0x24

0x35

0x46

0x03

0x14

0x25

0x36

0x04

0x15

0x26

0x05

0x16

0x06

0xC5

0xD5

0xD6

0xE6

950

1050

1150

700

800

900

1000

1100

750

850

950

1050

800

900

1000

850

950

900

Rev. A | Page 22 of 32

ADN8102

High Current Setting and Output Level Shift

VTTO

In low voltage applications, users must pay careful attention to

both the differential and common-mode signal levels (see Figure 41

and Table 14 and Table 15. Failure to understand the implications

of signal level and choice of ac or dc coupling almost certainly leads

to transistor saturation and poor transmitter performance.

ΔV

OCM

V

H

V

OD

V

OCM

TxHeadroom

V

L

The TxHeadroom register (Register 0x23) allows configuration

of the individual transmitters for extra headroom at the output

for high current applications. The bits in this register are active

high (default) and are one per output (see Table 17). Setting a

bit high puts the respective transmitter in a configuration for

extra headroom and setting a bit low does not provide extra

headroom. The TxHeadroom bits should only be set high when

V

p-p = 2 × V

OD

VEE

Figure 41. Simplified Output Voltage Levels Diagram

V_CCexceeds the value listed in Table 14 for a given output swing.

Rev. A | Page 23 of 32

ADN8102

Signal Levels and Common-Mode Shift for DC- and AC-Coupled Outputs

Table 14.

Output Levels and Output Compliance

AC-Coupled Transmitter

V_HV_L

Peak Peak dV_OCMV_H

DC-Coupled Transmitter

V_HV_LMin Max

Peak Peak V_L

TxHeadroom = 0

TxHeadroom = 1

Max

V_CC− V_LMin

V_D

Min

_CC− V_LV_CC

Min

V_L

V_ODI_TOTPeak PE

(mV) (mA) (mV) Boost (dB) (mV) (V) (V) (V)

PE

dV_OCMV_H

V_L

(mV) (V) (V) (V)

V

(V)

V

_CC(V)

V_TTOand V_CC= 3.3 V

200

8

200 1.00 0.00 200

300 1.50 3.52 300

400 2.00 6.02 400

500 2.50 7.96 500

600 3.00 9.54 600

700 3.50 10.88 700

800 4.00 12.04 800

300 1.00 0.00 300

400 1.33 2.50 400

500 1.67 4.44 500

600 2.00 6.02 600

700 2.33 7.36 700

800 2.67 8.52 800

900 3.00 9.54 900

400 1.00 0.00 400

500 1.25 1.94 500

600 1.50 3.52 600

700 1.75 4.86 700

800 2.00 6.02 800

900 2.25 7.04 900

3.2

3

3.2

3

100

3.3 3.1 3.3

3.25 3.05 3.3

3.1

3

2.225 1.1

1.8

1.9

1.8

1.9

1.8

1.9

2

1.2

2

2.2

2

2.2

2

200 12

200 16

200 20

200 24

200 28

200 32

300 12

300 16

300 20

300 24

300 28

300 32

300 36

400 16

400 20

400 24

400 28

400 32

400 36

400 40

600 24

600 28

600 32

600 36

600 40

600 44

600 48

3.1 2.9 3.15 2.85 150

2.8 3.1 2.7 200

2.9 2.7 3.05 2.55 250

2.8 2.6 2.4 300

2.7 2.5 2.95 2.25 350

2.6 2.4 2.9 2.1 400

3.15 2.85 3.15 2.85 150

3.05 2.75 3.1 2.7 200

2.95 2.65 3.05 2.55 250

2.85 2.55 3 2.4 300

2.75 2.45 2.95 2.25 350

2.65 2.35 2.9 2.1 400

2.55 2.25 2.85 1.95 450

3.1 2.7 3.1 2.7 200

2.6 3.05 2.55 250

2.9 2.5 2.4 300

2.8 2.4 2.95 2.25 350

2.7 2.3 2.9 2.1 400

2.6 2.2 2.85 1.95 450

3

3.2

3

3.3

2.9

2.8

2.7

2.6

2.5

3

3.15 2.95 3.3

3.1 2.9 3.3

3.05 2.85 3.3

3

2.8 3.3

3.3

3

3.25 2.95 3.3

3.2 2.9 3.3

3.15 2.85 3.3

3.1 2.8 3.3

3.05 2.75 3.3

2.9

2.8

2.7

2.6

2.5

2.4

2.9

2.8

2.7

2.6

2.5

2.4

2.3

2.7

2.6

2.5

2.4

2.3

2.2

2.1

3

2.7 3.3

3.3 2.9 3.3

3.25 2.85 3.3

3.2 2.8 3.3

3.15 2.75 3.3

3.1 2.7 3.3

3.05 2.65 3.3

3

2

2.2

1000 2.50 7.96 1000 2.5 2.1 2.8

1.8

2.4

500

300

3

2.6 3.3

600 1.00 0.00 600

700 1.17 1.34 700

800 1.33 2.50 800

900 1.50 3.52 900

3

2.4

3

3.3 2.7 3.3

3.25 2.65 3.3

3.2 2.6 3.3

3.15 2.55 3.3

3.1 2.5 3.3

3.05 2.45 3.3

2.1

1.1

2.9 2.3 2.95 2.25 350

2.8 2.2 2.9 2.1 400

2.7 2.1 2.85 1.95 450

2.8 1.8 500

1200 1.83 5.26 1100 2.5 1.9 2.75 1.65 550

2.225 1.1

1000 1.67 4.44 1000 2.6

2

2.1

1.1

1400 2.00 6.02 1200 2.4 1.8 2.7

V_TTOand V_CC= 1.8 V¹

200

1.5

600

3

2.4 3.3

8

200 1.00 0.00 200

300 1.50 3.52 300

400 2.00 6.02 400

500 2.50 7.96 500

600 3.00 9.54 600

300 1.00 0.00 300

400 1.33 2.50 400

500 1.67 4.44 500

600 2.00 6.02 600

700 2.33 7.36 700

400 1.00 0.00 400

500 1.25 1.94 500

600 1.50 3.52 600

700 1.75 4.86 700

800 2.00 6.02 800

600 1.00 0.00 600

1.7 1.5 1.7

1.5

100

1.8 1.6 1.8

1.75 1.55 1.8

1.7 1.5 1.8

1.65 1.45 1.8

1.6 1.4 1.8

1.8 1.5 1.8

1.75 1.45 1.8

1.7 1.4 1.8

1.65 1.35 1.8

1.6 1.3 1.8

1.8 1.4 1.8

1.75 1.35 1.8

1.7 1.3 1.8

1.65 1.25 1.8

1.6 1.2 1.8

1.8 1.2 1.8

1.6

1.5

1.4

1.3

1.2

1.5

1.4

1.3

1.2

1.1

1.4

1.3

1.2

1.1

1

0.725 1.1

1.8

1.9

0.5

NA

200 12

200 16

200 20

200 24

300 12

300 16

300 20

300 24

300 28

400 16

400 20

400 24

400 28

400 32

600 24

1.6 1.4 1.65 1.35 150

1.5 1.3 1.6 1.2 200

1.4 1.2 1.55 1.05 250

1.3 1.1 1.5 0.9 300

1.65 1.35 1.65 1.35 150

1.55 1.25 1.6 1.2 200

1.45 1.15 1.55 1.05 250

1.35 1.05 1.5 0.9 300

1.25 0.95 1.45 0.75 350

1.6 1.2 1.6 1.2 200

1.5 1.1 1.55 1.05 250

1.4 1.5 0.9 300

1.3 0.9 1.45 0.75 350

1

1.2 0.8 1.4

1.5 0.9 1.5

0.6

0.9

400

300

1.2

0.6

1.1

¹TxHeadroom = 1 is not an option at V_TTOand V_CC= 1.8 V.

Rev. A | Page 24 of 32

ADN8102

Table 15. Symbol Definitions for Output Levels vs. Setting

Symbol

Formula

Definition

V_OD

V_ODp-p

dV_{OCM_DC-COUPLED}

dV_{OCM_AC-COUPLED}

I_DC

I_PE

25 Ω × I_DC

Peak differential output voltage

Peak-to-peak differential output voltage

Output common-mode shift

Output current that sets output level

Output current used for PE

25 Ω × I_DC× 2 = 2 × V_OD

25 Ω × I_TOT/2 = V_ODp-p/4 + (I_PE/2 × 25)

50 Ω × I_TOT/2 = V_ODp-p/2 + (I_PE/2 × 50)

V_OD/R_TERM

—

I_TOT

V_H

V_L

I_DC+ I_PE

V_TTO− dV_OCM+ V_OD/2

V_TTO− dV_OCM− V_OD/2

Total transmitter output current

Maximum single-ended output voltage

Minimum single-ended output voltage

SELECTIVE SQUELCH AND DISABLE

Table 16. Squelch Programming

Each transmitter is equipped with output disable and output

squelch controls. Disable is a full power-down state: the trans-

mitter current is reduced to zero and the output pins pull up

to VTTO, but there is a delay of approximately 1 μs associated

with re-enabling the transmitter. The output disable control is

accessed through the EN bit (Bit 5) of the OUT_A/OUT_B

configuration registers through the I²C control interface.

Name

Address

Data

Default

OUT_A/ 0xC3,

SQUELCH[3:0] DISABLE[3:0]

0xFF

OUT_B

Squelch

Control

0xE3

Squelch is not a full power-down state but a state in which only

the output current is reduced to zero and the output pins pull

up to VTTO, and there is a much smaller delay to bring back

the output current. The output squelch and the output disable

control can both be accessed through the OUT_A/OUT_B

squelch control registers, with the top nibble representing the

squelch control for one entire output port and the bottom

nibble representing the output disable for one entire output

port. The ports are disabled or squelched by writing 0s to the

corresponding nibbles. The ports are enabled by writing all 1s,

which is the default setting. For example, to squelch Port A,

Register 0xC3 must be set to 0x0F. The entire nibble must be

written to all 0s for this functionality.

Rev. A | Page 25 of 32

ADN8102

I²C CONTROL INTERFACE

7. Send the data (eight bits) to be written to the register whose

address was set in Step 5. This transfer should be MSB first.

8. Wait for the ADN8102 to acknowledge the request.

9a. Send a stop condition (while holding the SCL line high,

pull the SDA line high) and release control of the bus.

9b. Send a repeated start condition (while holding the SCL line

high, pull the SDA line low) and continue with Step 2 in

this procedure to perform another write.

SERIAL INTERFACE GENERAL FUNCTIONALITY

The ADN8102 register set is controlled through a 2-wire

I²C interface. The ADN8102 acts only as an I²C slave device.

Therefore, the I²C bus in the system needs to include an I²C

master to configure the ADN8102 and other I²C devices that

may be on the bus. Data transfers are controlled using the two

I²C wires: the SCL input clock pin and the SDA bidirectional

data pin.

9c. Send a repeated start condition (while holding the SCL line

high, pull the SDA line low) and continue with Step 2 of

the read procedure (in the I2C Interface Data Transfers—

Data Read section) to perform a read from another address.

9d. Send a repeated start condition (while holding the SCL line

high, pull the SDA line low) and continue with Step 8 of

the read procedure (in the I2C Interface Data Transfers—

Data Read section) to perform a read from the same

address set in Step 5.

The ADN8102 I²C interface can be run in the standard (100 kHz)

and fast (400 kHz) modes. The SDA line only changes value

when the SCL pin is low with two exceptions. To indicate the

beginning or continuation of a transfer, the SDA pin is driven

low while the SCL pin is high, and to indicate the end of a

transfer, the SDA line is driven high while the SCL line is high.

Therefore, it is important to control the SCL clock to toggle

only when the SDA line is stable, unless indicating a start,

repeated start, or stop condition.

Figure 42 shows the ADN8102 write process. The SCL signal is

shown along with a general write operation and a specific example.

In the example, Data 0x92 is written to Address 0x6D of an

ADN8102 part with a part address of 0x4B. The part address is

seven bits wide. The upper five bits of the ADN8102 are internally

set to 10010b. The lower two bits are controlled by the ADDR[1:0]

pins. In this example, the bits controlled by the ADDR[1:0] pins

are set to 11b. In Figure 42, the corresponding step number is

visible in the circle under the waveform. The SCL line is driven by

the I²C master and never by the ADN8102 slave. As for the SDA

line, the data in the shaded polygons is driven by the ADN8102,

whereas the data in the nonshaded polygons is driven by the I²C

master. The end phase case shown is that of Step 9a.

I²C INTERFACE DATA TRANSFERS—DATA WRITE

To write data to the ADN8102 register set, a microcontroller, or

any other I²C master, needs to send the appropriate control signals

to the ADN8102 slave device. The steps that need to be completed

are listed as follows, where the signals are controlled by the I²C

master, unless otherwise specified. A diagram of the procedure

can be seen in Figure 42.

1. Send a start condition (while holding the SCL line high,

pull the SDA line low).

2. Send the ADN8102 part address (seven bits) whose upper

five bits are the static value 10010b and whose lower two

bits are controlled by the ADDR[1:0] input pins. This transfer

should be MSB first.

Note that the SDA line only changes when the SCL line is low,

except for the case of sending a start, stop, or repeated start

condition, Step 1 and Step 9 in this case.

3. Send the write indicator bit (0).

4. Wait for the ADN8102 to acknowledge the request.

5. Send the register address (eight bits) to which data is to be

written. This transfer should be MSB first.

6. Wait for the ADN8102 to acknowledge the request.

SCL

GENERAL CASE

ADDR

[1:0]

START

FIXED PART ADDR

REGISTER ADDR

DATA

STOP

SDA

R/W ACK

ACK

EXAMPLE

SDA

1

2

3

4

5

6

7

8

9a

Figure 42. I²C Write Diagram

Rev. A | Page 26 of 32

ADN8102

I²C INTERFACE DATA TRANSFERS—DATA READ

13a. Send a stop condition (while holding the SCL line high,

pull the SDA line high) and release control of the bus.

13b. Send a repeated start condition (while holding the SCL

line high, pull the SDA line low) and continue with Step 2

of the write procedure (in the I2C Interface Data

To read data from the ADN8102 register set, a microcontroller,

or any other I²C master, needs to send the appropriate control

signals to the ADN8102 slave device. The steps that need to be

completed are listed as follows, where the signals are controlled

by the I²C master, unless otherwise specified. A diagram of the

procedure can be seen in Figure 43.

Transfers—Data Write section) to perform a write.

13c. Send a repeated start condition (while holding the SCL

line high, pull the SDA line low) and continue with Step 2 of

this procedure to perform a read from a another address.

13d. Send a repeated start condition (while holding the SCL

line high, pull the SDA line low) and continue with Step 8 of

this procedure to perform a read from the same address.

1.

Send a start condition (while holding the SCL line high,

pull the SDA line low).

2.

Send the ADN8102 part address (seven bits) whose

upper five bits are the static value 10010b and whose

lower two bits are controlled by the input pins ADDR[1:0].

This transfer should be MSB first.

Figure 43 shows the ADN8102 read process. The SCL signal is

shown along with a general read operation and a specific example.

In the example, Data 0x49 is read from Address 0x6D of an

ADN8102 part with a part address of 0x4B. The part address is

seven bits wide. The upper five bits of the ADN8102 are internally

set to 10010b. The lower two bits are controlled by the ADDR[1:0]

pins. In this example, the bits controlled by the ADDR[1:0] pins

are set to 11b. In Figure 43, the corresponding step number is

visible in the circle under the waveform. The SCL line is driven

by the I²C master and never by the ADN8102 slave. As for the SDA

line, the data in the shaded polygons is driven by the ADN8102,

whereas the data in the nonshaded polygons is driven by the I²C

master. The end phase case shown is that of Step 13a.

3.

4.

5.

Send the write indicator bit (0).

Wait for the ADN8102 to acknowledge the request.

Send the register address (eight bits) from which data is

to be read. This transfer should be MSB first. The register

address is kept in memory in the ADN8102 until the

part is reset or the register address is written over with

the same procedure (Step 1 to Step 6).

6.

7.

Wait for the ADN8102 to acknowledge the request.

Send a repeated start condition (while holding the SCL

line high, pull the SDA line low).

8.

Send the ADN8102 part address (seven bits) whose

upper five bits are the static value 10010b and whose

lower two bits are controlled by the input pins ADDR[1:0].

This transfer should be MSB first.

Note that the SDA line changes only when the SCL line is low,

except for the case of sending a start, stop, or repeated start

condition, as in Step 1, Step 7, and Step 13. In Figure 43, A is the

same as ACK in Figure 42. Equally, Sr represents a repeated

start where the SDA line is brought high before SCL is raised.

SDA is then dropped while SCL is still high.

9.

Send the read indicator bit (1).

10.

11.

Wait for the ADN8102 to acknowledge the request.

The ADN8102 then serially transfers the data (eight bits)

held in the register indicated by the address set in Step 5.

Acknowledge the data.

12.

SCL

GENERAL CASE

R/

W

R/

W

FIXED PART

ADDR

FIXED PART

ADDR

[1:0]

ADDR

[1:0]

START

REGISTER ADDR

DATA

STOP

SDA

A

6

Sr

A

EXAMPLE

SDA

1

2

3

4

5

7

8

9

10

11

12

13a

Figure 43. I²C Read Diagram

Rev. A | Page 27 of 32

ADN8102

PCB DESIGN GUIDELINES

Proper RF PCB design techniques must be used for optimal

performance.

TRANSMISSION LINES

Use of 50 ꢀ transmission lines is required for all high frequency

input and output signals to minimize reflections. It is also necessary

for the high speed pairs of differential input traces to be matched in

length, as well as the high speed pairs of differential output traces,

to avoid skew between the differential traces.

POWER SUPPLY CONNECTIONS AND GROUND

PLANES

Use of one low impedance ground plane is recommended.

The VEE pins should be soldered directly to the ground plane

to reduce series inductance. If the ground plane is an internal

plane and connections to the ground plane are made through

vias, multiple vias can be used in parallel to reduce the series

inductance. The exposed pad should be connected to the VEE

plane using plugged vias so that solder does not leak through

the vias during reflow.

SOLDERING GUIDELINES FOR CHIP SCALE PACKAGE

The lands on the LFCSP are rectangular. The PCB pad for these

should be 0.1 mm longer than the package land length and

0.05 mm wider than the package land width. Center the land on

the pad, which ensures that the solder joint size is maximized.

The bottom of the chip scale package has a central exposed pad.

The pad on the PCB should be at least as large as this exposed pad.

The user must connect the exposed pad to VEE using plugged vias

so that solder does not leak through the vias during reflow. This

ensures a solid connection from the exposed pad to VEE.

Use of a 10 μF electrolytic capacitor between VCC and VEE is

recommended at the location where the 3.3 V supply enters the

printed circuit board (PCB). It is recommended that 0.1 μF and

1 nF ceramic chip capacitors be placed in parallel at each supply

pin for high frequency power supply decoupling. When using

0.1 μF and 1 nF ceramic chip capacitors, they should be placed

between the IC power supply pins (VCC, VTTI, and VTTO)

and VEE, as close as possible to the supply pins.

By using adjacent power supply and GND planes, excellent high

frequency decoupling can be realized by using close spacing

between the planes. This capacitance is given by

C

_PLANE= 0.88ε_r× A/d (pF)

where:

ε_ris the dielectric constant of the PCB material.

A is the area of the overlap of power and GND planes (cm²).

d is the separation between planes (mm).

For FR4, ε_r= 4.4, and 0.25 mm spacing, C ≈ 15 pF/cm².

Rev. A | Page 28 of 32

ADN8102

REGISTER MAP

Table 17. I²C Register Definitions

Name

Address Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

Reset

0x00

RESET

LB[0]

Global

0x02

LB[1]

0x00

Configuration

Control

Mode

0x0F

MODE[1]

TxH_A1

EQ[1]

MODE[0]

TxH_A0

EQ[0]

0x00

0x30

TxHeadroom

0x23

0x80

TxH_B3

TxH_B2

TxH_B1

EQBY

TxH_B0

EN

TxH_A3

TxH_A2

EQ[2]

IN_A

PNSWAP

Configuration

IN_A LOS

Threshold

0x81

0x82

0x1F

0x83

0x84

0x85

0x8D

0x95

0x9D

0xA0

0xA1

0xA2

0x3F

0xA3

0xA4

0xA5

0xAD

0xB5

0xBD

THRESH[6] THRESH[5] THRESH[4] THRESH[3] THRESH[2] THRESH[1] THRESH[0] 0x04

IN_A LOS

Hysteresis

HYST[6]

HYST[5]

HYST[4]

HYST[3]

HYST[2]

HYST[1]

HYST[0]

0x12

IN_A LOS

Status¹

STICKY

LOS[3]

STICKY

LOS[2]

STICKY

LOS[1]

STICKY

LOS[0]

REAL-TIME REAL-TIME REAL-TIME REAL-TIME

LOS[3]

EQ1[3]

LOS[2]

EQ1[2]

LOS[1]

EQ1[1]

LOS[0]

EQ1[0]

IN_A EQ1

Control

EQ CTL

SRC

EQ1[5]

EQ1[4]

0x00

0x30

IN_A EQ2

Control

EQ2[5]

EQ2[4]

EQ2[3]

EQ2[2]

EQ2[1]

EQ2[0]

IN_A0 FR4

Control

LUT

SELECT

LUT

FR4/CX4

IN_A1 FR4

Control

LUT

SELECT

LUT

FR4/CX4

IN_A2 FR4

Control

LUT

SELECT

LUT

FR4/CX4

IN_A3 FR4

Control

LUT

SELECT

LUT

FR4/CX4

IN_B

Configuration

PNSWAP

EQBY

EN

EQ[2]

EQ[1]

EQ[0]

IN_B LOS

Threshold

THRESH[6] THRESH[5] THRESH[4] THRESH[3] THRESH[2] THRESH[1] THRESH[0] 0x04

IN_B LOS

Hysteresis

HYST[6]

HYST[5]

HYST[4]

HYST[3]

HYST[2]

HYST[1]

HYST[0]

0x12

IN_B LOS

Status¹

STICKY

LOS [3]

STICKY

LOS [2]

STICKY

LOS [1]

STICKY

LOS[0]

REAL-TIME REAL-TIME REAL-TIME REAL-TIME

LOS[3]

EQ1[3]

LOS[2]

EQ1[2]

LOS[1]

EQ1[1]

LOS[0]

EQ1[0]

IN_B EQ1

Control

EQ CTL

SRC

EQ1[5]

EQ1[4]

0x00

IN_B EQ2

Control

EQ2[5]

EQ2[4]

EQ2[3]

EQ2[2]

EQ2[1]

EQ2[0]

IN_B3 FR4

Control

LUT

SELECT

LUT

FR4/CX4

IN_B2 FR4

Control

LUT

SELECT

LUT

FR4/CX4

IN_B1 FR4

Control

LUT

SELECT

LUT

FR4/CX4

IN_B0 FR4

Control

LUT

SELECT

FR4/CX4

Rev. A | Page 29 of 32

ADN8102

Name

Address Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

OUT_A

Configuration

0xC0

EN

DATA

RATE

PE[2]

PE[1]

PE[0]

0x20

OUT_A

Output Level

Control 1

0xC1

0xC2

0xC3

PE CTL

SRC

OUTA_OLEV1[6:0]

OUTA_OLEV0[6:0]

0x40

0xFF

OUT_A

Output Level

Control 0

OUT_A

Squelch

Control

SQUELCH[3:0]

EN

DISABLE[3:0]

PE[1]

OUT_B

Configuration

0xE0

0xE1

DATA

RATE

PE[2]

PE[0]

0x20

0x40

OUT_B

Output Level

Control 1

PE CTL

SRC

OUTB_OLEV1[6:0]

OUTB_OLEV0[6:0]

OUT_B

Output Level

Control 0

0xE2

0xE3

0x40

0xFF

OUT_B

Squelch

Control

SQUELCH[3:0]

DISABLE[3:0]

¹Read-only register.

Rev. A | Page 30 of 32

ADN8102

OUTLINE DIMENSIONS

0.30

0.25

0.18

9.00

BSC SQ

0.60 MAX

PIN 1

INDICATOR

64

49

48

1

PIN 1

INDICATOR

*

6.15

6.00 SQ

5.85

8.75

BSC SQ

TOP

VIEW

EXPOSED PAD

(BOTTOM VIEW)

0.50

0.40

0.30

33

32

16

17

7.50

REF

0.80 MAX

0.65 TYP

12° MAX

1.00

0.85

0.80

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

SEATING

PLANE

0.50 BSC

SECTION OF THIS DATA SHEET.

0.20 REF

*

COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4

EXCEPT FOR EXPOSED PAD DIMENSION

Figure 44. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

9 mm × 9 mm Body, Very Thin Quad

(CP-64-2)

Dimensions shown in millimeters

ORDERING GUIDE

Model

ADN8102ACPZ¹

ADN8102ACPZ-R7¹

ADN8102-EVALZ¹

Temperature Range

Package Description

Package Option

CP-64-2

−40°C to +85°C

64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

Evaluation Board

¹Z = RoHS Compliant Part.

Rev. A | Page 31 of 32

ADN8102

NOTES

Purchase of licensed I²C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I²C Patent

Rights to use these components in an I²C system, provided that the system conforms to the I²C Standard Specification as defined by Philips.

registered trademarks are the property of their respective owners.

D07060-0-8/08(A)

Rev. A | Page 32 of 32


型号：	ADN8102ACPZ-R7
厂家：	ADI
描述：	3.75 Gbps Quad Bidirectional CX4 Equalizer 3.75 Gbps的双向四CX4均衡器
文件：	总32页 (文件大小：1705K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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