ADM812 [ADI]

Microprocessors Supervisory Circuit in 4-Lead SOT-143; 微处理器监控电路采用4引脚SOT -143


型号：	ADM812
厂家：	ADI
描述：	Microprocessors Supervisory Circuit in 4-Lead SOT-143 微处理器监控电路采用4引脚SOT -143 微处理器监控
文件：	总6页 (文件大小：87K)
中文：	中文翻译
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Microprocessors

Supervisory Circuit in 4-Lead SOT-143

ADM811/ADM812

FEATURES

FUNCTIONAL BLOCK DIAGRAM

Superior Upgrade for MAX811/MAX812

Specified Over Temperature

Low Power Consumption (5 ␮A Typ)

ADM811/ADM812

Precision Voltage Monitor: +3 V, +3.3 V, +5 V Options

Reset Assertion Down to 1 V V_CC

140 ms Min Power-On Reset

RESET

GENERATOR

RESET/RESET

REF

Logic Low RESET Output (ADM811)

Logic High RESET Output (ADM812)

Built-In Manual Reset

DEBOUNCE

GND

APPLICATIONS

Microprocessor Systems

Controllers

Intelligent Instruments

Automotive Systems

Safety Systems

Portable Instruments

GENERAL DESCRIPTION

The ADM811/ADM812 are reliable voltage monitoring devices

suitable for use in most voltage monitoring applications.

␮P

SYSTEM

The ADM811/ADM812 are designed to monitor five different

voltages, each allowing for a 5% or 10% degradation of standard

PSU voltages before a reset occurs. These voltages have been

selected for the effective monitoring of +3 V, +3.3 V and +5 V

supply voltage levels.

ADM811

RESET

100k⍀

GND

Included in this circuit is a debounced Manual Reset input.

Reset can be activated using an electrical switch (or an input

from another digital device) or by a degradation of the supply

voltage. The Manual Reset function is very useful especially if

the circuit in which the ADM811/ADM812 is operating enters

into a state that can only be detected by the user. Allowing the

user to manually reset a system can reduce the damage or dan-

ger that could be otherwise caused by an out-of-control or

locked up system.

Figure 1. Typical Operating Circuit

REV. 0

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

(V_CC= Full Operating Range, T_A= T_MINto T_MAX, V_CCtyp = +5 V

for L/M, +3.3 V for T/S, +3 V for R Models unless otherwise noted)

ADM811/ADM812–SPECIFICATIONS

arameter

Min

Typ

Max

Units

Test Conditions/Comments

SUPPLY

Voltage

1.0

1.2

5.5

µA

_A= 0°C to +70°C

T_A= –40°C to +85°C

_CC< +5.5 V, ADM81_L/M, I_OUT= 0 A

Current

V_CC< +3.6 V, ADM81_R/S/T, I_OUT= 0 A

RESET VOLTAGE THRESHOLD

ADM81_L

ADM81_M

ADM81_T

ADM81_S

4.54

4.50

4.30

4.25

3.03

3.00

2.88

2.85

2.58

2.55

4.63

4.38

3.08

2.93

2.63

4.72

4.75

4.46

4.50

3.14

3.15

2.98

3.00

2.68

2.70

T_A= +25°C

_A= –40°C to +85°C

T_A= +25°C

_A= –40°C to +85°C

T_A= +25°C

_A= –40°C to +85°C

T_A= +25°C

_A= –40°C to +85°C

ADM81_R

T_A= +25°C

T_A= –40°C to +85°C

RESET THRESHOLD

TEMPERATURE COEFFICIENT

ppm/°C

_CCTO RESET/RESET DELAY

µs

V_OD= 125 mV, ADM81_L/M

V_OD= 125 mV, ADM81_R/S/T

RESET ACTIVE TIMEOUT PERIOD

140

300

560

700

V_CC= V_TH(MAX)

(ADM811-3T Only)

MANUAL RESET

Minimum Pulsewidth

µs

Glitch Immunity

RESET/RESET Propagation Delay

Pull-Up Resistance

100

0.5

µs

kΩ

The Manual Reset Circuit Will Act On

An Input Rising Above

An Input Falling Below

An Input Rising Above

An Input Falling Below

2.3

_CC> V_TH(MAX),ADM81_L/M

0.8

0.7 × V_CC

V_CC> V_TH(MAX),ADM81_R/S/T

0.25 × V_CC

RESET Output Voltage

Low (ADM812R/S/T)

Low (ADM812L/M)

High (ADM812R/S/T/L/M)

Low (ADM811R/S/T)

Low (ADM811L/M)

Low (ADM811R/S/T/L/M)

High (ADM811R/S/T)

High (ADM811L/M)

0.3

0.4

V_CC= V_TH(MAX), I_SINK= 1.2 mA

V_CC= V_TH(MAX), I_SINK= 3.2 mA

1.8 V < V_CC< V_TH(MIN), I_SOURCE= 150 µA

V_CC= V_TH(MIN), I_SINK= 1.2 mA

0.8 V_CC

0.3

0.4

0.3

_CC= V_TH(MIN), I_SINK= 3.2 mA

V_CC> 1.0 V, I_SINK= 50 µA

V_CC> V_TH(MAX), I_SOURCE= 500 µA

V_CC> V_TH(MAX), I_SOURCE= 800 µA

0.8 V_CC

V_CC– 1.5

Specifications subject to change without notice.

Operating Temperature Range . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +160°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . .+300°C

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . .+215°C

Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C

ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 kV

ABSOLUTE MAXIMUM RATINGS*

(Typical values are at T_A= +25°C unless otherwise noted)

Terminal Voltage (With Respect to Ground)

V_CC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V

All Other Inputs . . . . . . . . . . . . . . . . .–0.3 V to V_CC+ 0.3 V

Input Current

V_CC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

MR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Output Current

RESET, RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Power Dissipation (T_A= +70°C)

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those listed in the operational

sections of this specification is not implied. Exposure to absolute maximum ratings

for extended periods of time may affect device reliability.

RT-4, SOT-143 . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mW

Derate by 4 mW/°C above +70°C

θ_JAThermal Impedance . . . . . . . . . . . . . . . . . . . . 330°C/W

–2–

REV. 0

ADM811/ADM812

PIN CONFIGURATION

PIN FUNCTION DESCRIPTIONS

Pin Mnemonic

Function

GND

0 V. Ground reference for all signals.

ADM811/

ADM812

TOP VIEW

RESET (ADM811) Active Low Logic Output. RESET

remains low while V_CCis below the

reset threshold or when MR is low,

RESET then remains low for at least

140 ms (at least 300 ms for the

(Not to Scale)

RESET/RESET

ADM811-3T) after V_CCrises above

the reset threshold.

RESET (ADM812) Active High Logic Output. RESET

remains high while V_CCis below the

reset threshold or when MR is low,

RESET then remains high for 240 ms

(typical) after V_CCrises above the

reset threshold.

Manual Reset. This active low

debounced input will ignore input

pulses of 100 ns or less (typical) and

is guaranteed to accept input pulses

of greater than 10 µs. Leave floating

when not used.

V_CC

+3 V, +3.3 V or +5 V monitored

supply voltage.

ORDERING GUIDE

Reset

Threshold

Temperature

Range

Brand

Information

Model*

Quantity

ADM811LART-REEL

ADM811LART-REEL-7

ADM811MART-REEL

ADM811MART-REEL-7

ADM811TART-REEL

ADM811TART-REEL-7

ADM811-3TART-REEL

ADM811-3TART-RL7

ADM811SART-REEL

ADM811SART-REEL-7

ADM811RART-REEL

ADM811RART-REEL-7

4.63 V

4.38 V

3.08 V

2.93 V

2.63 V

–40

C to +85

°C

MBV

MBT

MBG

MB3

MBE

MBB

10K

°C

ADM812LART-REEL

ADM812LART-REEL-7

ADM812MART-REEL

ADM812MART-REEL-7

ADM812TART-REEL

ADM812TART-REEL-7

ADM812SART-REEL

ADM812SART-REEL-7

ADM812RART-REEL

ADM812RART-REEL-7

4.63 V

4.38 V

3.08 V

2.93 V

2.63 V

–40°C to +85°C

MCV

MCT

MCG

MCE

MCB

10K

*Only available in reels.

Parts in bold are ex-stock, please contact factory for availability.

REV. 0

–3–

–Typical Performance Characteristics

ADM811/ADM812

@ V = 5.5V

@ V = 3V

@ V = 1V

DD CC

TEMPERATURE – ؇C

Figure 5. Supply Current vs. Temperature (ADM81_L/M)

Figure 2. Supply Current vs. Temperature (ADM81_R/S/T)

1000

900

800

700

600

500

400

900

800

700

600

500

= 20mV

400

300

200

100

= 20mV

300

200

= 125mV

100

= 200mV

TEMPERATURE – ؇C

Figure 3. Power-Down RESET Delay vs. Temperature

(ADM81__R/S/T)

Figure 6. Power-Down RESET Delay vs. Temperature

(ADM81_L/M)

289

1.007

1.006

1.005

1.004

1.003

1.002

1.001

1.000

0.999

0.998

0.997

0.996

0.995

284

ADM81_L/M

279

274

269

264

259

254

ADM81_R/S/T

249

244

TEMPERATURE – ؇C

Figure 7. Reset Threshold Deviation vs. Temperature

Figure 4. Power-Up Reset Timeout vs. Temperature

–4–

REV. 0

ADM811/ADM812

CIRCUIT INFORMATION

GLITCH IMMUNITY

RESET THRESHOLDS

The ADM811/ADM812 contain internal filtering circuitry

providing glitch immunity from fast transient glitches on the

power supply line.

The reset output provides a RESET (for the ADM811) or a

RESET (for the ADM812) output to the microprocessor when-

ever the V_CCinput is below the reset threshold. The actual reset

threshold is dependant on whether a L, M, T, S or R suffix is

used. Please refer to Table I.

REF

RESET

t₁

Table I. Reset Threshold Options

RESET

t₁= RESET TIME = 240ms TYPICAL

= RESET VOLTAGE THRESHOLD

REF

Model

Threshold

Figure 8. Power Fail RESET Timing

ADM811LART

ADM811MART

ADM811TART

ADM811-3TART

ADM811SART

ADM811RART

4.63 V

4.38 V

3.08 V

2.93 V

2.63 V

INTERFACING TO OTHER DEVICES

Output

The ADM811/ADM812 series is designed to integrate with

as many devices as possible. One feature of the ADM811/

ADM812 is the reset output, which is directly proportional to

V_CC(this is guaranteed only while V_CCis greater than 1 V). This

enables the part to be used in both 3 V and 5 V or any nominal

ADM812LART

ADM812MART

ADM812TART

ADM812SART

ADM812RART

4.63 V

4.38 V

3.08 V

2.93 V

2.63 V

voltage within the minimum and maximum specifications for V_CC

THE BENEFITS OF A VERY ACCURATE RESET

THRESHOLD

Parts in bold type are ex-stock, please contact factory for availability.

Because the ADM811/ADM812 series can operate effectively

even when there are large degradations of the supply voltages,

RESET OUTPUT

the possibility of a malfunction during a power failure is greatly

reduced. Another advantage of the ADM811/ADM812 series is

its very accurate internal voltage reference circuit. Combined,

these benefits produce an exceptionally reliable Microprocessor

Supervisory Circuit.

On power-up and after V_CCrises above the reset threshold, an

internal timer holds the reset output active for 240 ms (typical).

This is intended as a power-on reset signal for the processor. It

allows time for both the power supply and the microprocessor

to stabilize after power-up. If a power supply brownout or inter-

ruption occurs, the reset output is similarly activated and re-

mains active for 240 ms (typical) after the supply recovers. This

allows time for the power supply and microprocessor to stabilize.

The ADM811 provides an active low reset output (RESET)

while the ADM812 provides an active high output (RESET).

ADM811

RESET

During power-down of the ADM811, the RESET output re-

mains valid (low) with V_CCas low as 1 V. This ensures that the

microprocessor is held in a stable shutdown condition as the

supply falls and also ensures that no spurious activity can occur

via the µP as it powers up.

GND

Figure 9. Ensuring a Valid RESET Output Down to

V_CC= 0 V

MANUAL RESET

ENSURING A VALID RESET OUTPUT DOWN TO

_CC= 0 V

The ADM811/ADM812 is equipped with a manual reset input.

This input is designed to operate in a noisy environment where

unwanted glitches could be induced. These glitches could be

produced by the bouncing action of a switch contact or where a

Manual Reset switch may be located some distance away from

the circuit (the cabling of which may pickup noise).

When V_CCfalls below 0.8 V, ADM811s RESET no longer sinks

current. Therefore, a high impedance CMOS logic input con-

nected to RESET may drift to undetermined logic levels. To

eliminate this problem a 100 kΩ resistor should be connected

from RESET to ground.

The Manual Reset input is guaranteed to ignore logically valid

inputs which are faster than 100 ns and accept inputs longer in

duration than 10 µs.

REV. 0

–5–

ADM811/ADM812

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

4-Lead Plastic Surface Mount Package

(SOT-143)

0.079 (2.00)

0.071 (1.80)

0.055 (1.40)

0.047 (1.20)

0.098 (2.50)

0.083 (2.10)

PIN 1

0.080 (2.03)

0.070 (1.78)

0.120 (3.05)

0.105 (2.67)

7؇

0.004 (0.10)

0.001 (0.03)

0.040 (1.02)

0.031 (0.79)

8؇

0؇

0.0059 (0.089)

0.0035 (0.15)

0.037 (0.94)

0.030 (0.77)

0.021 (0.54)

0.015 (0.38)

0.010 (0.25)

0.005 (0.13)

SEATING

PLANE

–6–

REV. 0

ADM812 [ADI]

相关型号：

ADM812LART

ADM812LART-REEL

ADM812LART-REEL-7

ADM812LART-REEL7

ADM812LARTZ-REEL

ADM812LARTZ-REEL7

ADM812MART

ADM812MART-REEL

ADM812MART-REEL-7

ADM812MART-REEL7

ADM812MARTZ-REEL

ADM812MARTZ-REEL7