ADG729 [ADI]
CMOS, Low-Voltage, 2-Wire Serially-Controlled, Matrix Switches; CMOS ，低电压， 2线串行控制，矩阵开关
| 型号： | ADG729 |
| 厂家： | 
ADI |
| 描述： | CMOS, Low-Voltage, 2-Wire Serially-Controlled, Matrix Switches |
| 文件： | 总12页 (文件大小：151K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS, Low-Voltage, 2-Wire
Serially-Controlled, Matrix Switches
a
ADG728/ADG729
FEATURES
2-Wire Serial Interface
FUNCTIONAL BLOCK DIAGRAMS
2.7 V to 5.5 V Single Supply
2.5 ⍀ On Resistance
ADG728
ADG729
0.75 ⍀ On-Resistance Flatness
100 pA Leakage Currents
Single 8-to-1 Matrix Switch ADG728
Dual 4-to-1 Matrix Switch ADG729
Power-On Reset
S1
S1A
S4A
DA
DB
D
Small 16-Lead TSSOP Package
S1B
S4B
APPLICATIONS
S8
Data Acquisition Systems
Communication Systems
Relay Replacement
Audio and Video Switching
Automatic Test Equipment
INPUT SHIFT
REGISTER
INPUT SHIFT
REGISTER
RESET
SDA SCL A0 A1
SDA SCL A0 A1
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG728 and ADG729 are CMOS analog matrix switches
with a serially controlled 2-wire interface. The ADG728 is an
8-channel matrix switch, while the ADG729 is a dual 4-channel
matrix switch. On resistance is closely matched between switches
and very flat over the full signal range. These parts can operate
equally well as either multiplexers, demultiplexers or switch
arrays and the input signal range extends to the supplies.
1. 2-Wire Serial Interface.
2. Single Supply Operation. The ADG728 and ADG729 are
fully specified and guaranteed with 3 V and 5 V supply rails.
3. Low On Resistance 2.5 Ω typical.
4. Any configuration of switches may be on at any one time.
5. Guaranteed Break-Before-Make Switching Action.
6. Small 16-Lead TSSOP Package.
The ADG728 and ADG729 utilize a 2-wire serial interface that
is compatible with the I2C™ interface standard. Both have two
external address pins (A0 and A1). This allows the 2 LSBs of
the 7-bit slave address to be set by the user. Four of each of the
devices can be connected to the one bus. The ADG728 also has
a RESET pin that should be tied high if not in use.
Each channel is controlled by one bit of an 8-bit word. This
means that these devices may be used in a number of different
configurations; all, any, or none of the channels may be on at
any one time.
On power-up of the device, all switches will be in the OFF con-
dition and the internal shift register will contain all zeros.
All channels exhibit break-before-make switching action pre-
venting momentary shorting when switching channels.
The ADG728 and ADG729 are available in 16-lead TSSOP
packages.
I2C is a trademark of Philips Corporation.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
ADG728/ADG729–SPECIFICATIONS1
(VDD = 5 V ؎ 10%, GND = 0 V, unless otherwise noted.)
B Version
–40؇C
Parameter
25؇C
to +85؇C
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
0 V to VDD
V
On Resistance (RON
)
2.5
4.5
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
VS = 0 V to VDD, IS = 10 mA;
Test Circuit 1
5
0.4
0.8
On-Resistance Match Between
VS = 0 V to VDD, IS = 10 mA
Channels (∆RON
)
On-Resistance Flatness (RFLAT(ON)
)
0.75
VS = 0 V to VDD, IS = 10 mA
1.2
LEAKAGE CURRENTS
VDD = 5.5 V
Source OFF Leakage IS (OFF)
0.01
0.1
0.01
0.1
0.01
0.1
nA typ
nA max
nA typ
nA max
nA typ
nA max
VD = 4.5 V/1 V, VS = 1 V/4.5 V, Test Circuit 2
VD = 4.5 V/1 V, VD = 1 V/4.5 V, Test Circuit 3
VD = VS = 4.5 V/1 V, Test Circuit 4
0.3
1
Drain OFF Leakage ID (OFF)
Channel ON Leakage ID, IS (ON)
1
LOGIC INPUTS (A0, A1)2
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.4
0.8
V min
V max
IINL or IINH
0.005
6
µA typ
µA max
pF typ
0.1
CIN, Input Capacitance
LOGIC INPUTS (SCL, SDA)2
Input High Voltage, VINH
0.7 VDD
V min
V max
V min
V max
µA typ
µA max
V min
pF typ
V
DD + 0.3
Input Low Voltage, VINL
–0.3
0.3 VDD
I
IN, Input Leakage Current
0.005
VIN = 0 V to VDD
1.0
VHYST, Input Hysteresis
CIN, Input Capacitance
0.05 VDD
6
LOGIC OUTPUT (SDA)2
VOL, Output Low Voltage
0.4
0.6
V max
V max
ISINK = 3 mA
ISINK = 6 mA
DYNAMIC CHARACTERISTICS2
tON
95
85
8
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
RL = 300 Ω, CL = 35 pF, Test Circuit 5;
140
130
1
VS1 = 3 V
tOFF
VS1 = 3 V, RL = 300 Ω, CL = 35 pF;
Test Circuit 5
Break-Before-Make Time Delay, tD
Charge Injection
RL = 300 Ω, CL = 35 pF;
VS1 = VS2 = 3 V, Test Circuit 5
VS = 2.5 V, RS = 0 Ω, CL = 1 nF;
Test Circuit 6
RL = 50 Ω, CL = 5 pF, f = 10 MHz;
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 8
RL = 50 Ω, CL = 5 pF, f = 10 MHz;
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 7
3
Off Isolation
–55
–75
dB typ
dB typ
Channel-to-Channel Crosstalk
–55
–75
dB typ
dB typ
–3 dB Bandwidth
ADG728
65
100
13
MHz typ
MHz typ
pF typ
RL = 50 Ω, CL = 5 pF, Test Circuit 8
ADG729
CS (OFF)
CD (OFF)
ADG728
85
42
pF typ
pF typ
ADG729
CD, CS (ON)
ADG728
96
48
pF typ
pF typ
ADG729
POWER REQUIREMENTS
IDD
V
DD = 5.5 V
10
µA typ
µA max
Digital Inputs = 0 V or 5.5 V
20
N
OTES
1Temperature range is as follows: B Version: –40°C to +85°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–2–
REV. 0
ADG728/ADG729
SPECIFICATIONS1
(VDD = 3 V ؎ 10%, GND = 0 V, unless otherwise noted.)
B Version
–40؇C
to +85؇C
Parameter
25؇C
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
0 V to VDD
V
On Resistance (RON
)
6
11
Ω typ
Ω max
Ω typ
Ω max
Ω typ
VS = 0 V to VDD, IS = 10 mA;
Test Circuit 1
12
On-Resistance Match Between
0.4
1.2
3.5
VS = 0 V to VDD, IS = 10 mA
Channels (∆RON
)
On-Resistance Flatness (RFLAT(ON)
)
VS = 0 V to VDD, IS = 10 mA
LEAKAGE CURRENTS
VDD = 3.3 V
Source OFF Leakage IS (OFF)
0.01
0.1
0.01
0.1
0.01
0.1
nA typ
nA max
nA typ
nA max
nA typ
nA max
VS = 3 V/1 V, VD = 1 V/3 V, Test Circuit 2
VD = 3 V/1 V, VD = 1 V/3 V, Test Circuit 3
VD = VS = 3 V/1 V, Test Circuit 4
0.3
1
Drain OFF Leakage ID (OFF)
Channel ON Leakage ID, IS (ON)
1
LOGIC INPUTS (A0, A1)2
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.0
0.4
V min
V max
I
INL or IINH
0.005
3
µA typ
µA max
pF typ
0.1
CIN, Input Capacitance
LOGIC INPUTS (SCL, SDA)2
Input High Voltage, VINH
0.7 VDD
V min
V max
V min
V max
µA typ
µA max
V min
pF typ
V
DD + 0.3
Input Low Voltage, VINL
–0.3
0.3 VDD
I
IN, Input Leakage Current
0.005
VIN = 0 V to VDD
1.0
V
HYST, Input Hysteresis
0.05 VDD
3
CIN, Input Capacitance
LOGIC OUTPUT (SDA)2
VOL, Output Low Voltage
0.4
0.6
V max
V max
ISINK = 3 mA
ISINK = 6 mA
DYNAMIC CHARACTERISTICS2
tON
130
115
8
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
RL = 300 Ω, CL = 35 pF, Test Circuit 5;
200
180
1
VS1 = 2 V
tOFF
RL = 300 Ω, CL = 35 pF;
VS = 2 V, Test Circuit 5
RL = 300 Ω, CL = 35 pF;
Break-Before-Make Time Delay, tD
Charge Injection
V
S1 = VS8 = 2 V, Test Circuit 5
3
VS = 1.5 V, RS = 0 Ω, CL = 1 nF;
Test Circuit 6
Off Isolation
–55
–75
dB typ
dB typ
R
R
L = 50 Ω, CL = 5 pF, f = 10 MHz;
L = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 8
Crosstalk
–55
–75
dB typ
dB typ
R
R
L = 50 Ω, CL = 5 pF, f = 10 MHz;
L = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 7
–3 dB Bandwidth
ADG728
65
100
13
MHz typ
MHz typ
pF typ
RL = 50 Ω, CL = 5 pF, Test Circuit 8
ADG729
CS (OFF)
C
D (OFF)
ADG728
ADG729
85
42
pF typ
pF typ
CD, CS (ON)
ADG728
ADG729
96
48
pF typ
pF typ
POWER REQUIREMENTS
IDD
VDD = 3.3 V
Digital Inputs = 0 V or 3.3 V
10
µA typ
µA max
20
NOTES
1Temperature ranges are as follows: B Versions: –40°C to +85°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
REV. 0
–3–
ADG728/ADG729
TIMING CHARACTERISTICS1
(VDD = 2.7 V to 5.5 V. All specifications –40؇C to +85؇C, unless otherwise noted.)
Parameter
Limit at TMIN, TMAX
Unit
Conditions/Comments
fSCL
t1
400
2.5
0.6
1.3
0.6
100
kHz max
ms min
ms min
ms min
ms min
ns min
SCL Clock Frequency
SCL Cycle Time
t2
tHIGH, SCL High Time
t3
tLOW, SCL Low Time
t4
tHD, STA, Start/Repeated Start Condition Hold Time
tSU, DAT, Data Setup Time
tHD, DAT, Data Hold Time
t5
2
t6
0.9
0
ms max
ms min
t7
t8
t9
0.6
0.6
1.3
ms min
ms min
ms min
tSU, STA, Setup Time for Repeated Start
tSU, STO, Stop Condition Setup Time
tBUF, Bus Free Time Between a STOP Condition and
a Start Condition
t10
t11
300
20 + 0.1Cb
ns max
ns min
tR, Rise Time of Both SCL and SDA when Receiving
3
250
300
20 + 0.1Cb
ns max
ns max
ns min
tF, Fall Time of SDA when Receiving
tF, Fall Time of SDA when Transmitting
3
Cb
400
50
pF max
ns max
Capacitive Load for Each Bus Line
Pulsewidth of Spike Suppressed
4
tSP
NOTES
1See Figure 1.
2A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) in order to bridge the undefined region of
the falling edge of SCL.
3Cb is the total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD
4Input filtering on both the SCL and SDA inputs suppress noise spikes which are less than 50 ns.
.
Specifications subject to change without notice.
SDA
t3
t4
t9
t11
t10
SCL
t2
t6
t8
t4
t5
t7
t1
START
CONDITION
START
CONDITION
REPEATED
START
CONDITION
STOP
CONDITION
Figure 1. 2-Wire Serial Interface Timing Diagram
–4–
REV. 0
ADG728/ADG729
PIN FUNCTION DESCRIPTIONS
Function
ADG728
ADG729
Mnemonic
1
1
SCL
Serial Clock Line. This is used in conjunction with the SDA line to clock data into
the 8-bit input shift register. Clock rates of up to 400 kbit/s can be accommodated
with this 2-wire serial interface.
2
3
RESET
Active low control input that clears the input register and turns all switches to the
OFF condition.
Serial Data Line. This is used in conjunction with the SCL line to clock data into
the 8-bit input shift register during the write cycle and used to read back 1 byte of
data during the read cycle. It is a bidirectional open-drain data line which should be
pulled to the supply with an external pull-up resistor.
3
SDA
4, 5, 6, 7
8
4, 5, 6, 7
8, 9
Sxx
Dx
Source. May be an input or output.
Drain. May be an input or output.
9, 10, 11, 12
10, 11, 12, 13 Sxx
Source. May be an input or output.
13
14
15
16
14
15
2
VDD
GND
A1
Power Supply Input. These parts can be operated from a supply of 2.7 V to 5.5 V.
Ground Reference.
Address Input. Sets the second least significant bit of the 7-bit slave address.
Address Input. Sets the least significant bit of the 7-bit slave address.
16
A0
PIN CONFIGURATIONS
ADG729
ADG728
SCL
A1
A0
16
1
2
3
4
5
6
7
8
SCL
A0
16
1
2
3
4
5
6
7
8
15 GND
RESET
15 A1
14
13
12
11
10
9
V
DD
SDA
S1A
S2A
S3A
S4A
DA
14
13
12
11
10
9
SDA
S1
S2
S3
S4
D
GND
ADG729
ADG728
S1B
S2B
S3B
S4B
DB
V
DD
TOP VIEW
(Not to Scale)
TOP VIEW
(Not to Scale)
S5
S6
S7
S8
ORDERING GUIDE
Package Description
Model
Temperature Range
Package Option
ADG728BRU
ADG729BRU
–40°C to +85°C
–40°C to +85°C
Thin Shrink Small Outline Package (TSSOP)
Thin Shrink Small Outline Package (TSSOP)
RU-16
RU-16
REV. 0
–5–
ADG728/ADG729
ABSOLUTE MAXIMUM RATINGS1
TSSOP Package
(TA = 25°C unless otherwise noted.)
θ
JA Thermal Impedance . . . . . . . . . . . . . . . . . . . 150.4°C/W
θ
JC Thermal Impedance . . . . . . . . . . . . . . . . . . . . 27.6°C/W
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Analog, Digital Inputs2 . . . . . . . . . . –0.3 V to VDD + 0.3 V or
30 mA, Whichever Occurs First
Lead Temperature, Soldering (10 seconds) . . . . . . . . . . 300°C
IR Reflow, Peak Temperature . . . . . . . . . . . . . . . . . . . . 220°C
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
(Pulsed at 1 ms, 10% Duty Cycle max)
Continuous Current, Each S . . . . . . . . . . . . . . . . . . . . . 30 mA
Continuous Current D, ADG729 . . . . . . . . . . . . . . . . . 80 mA
Continuous Current D, ADG728 . . . . . . . . . . . . . . . . 120 mA
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
2Overvoltages at IN, S or D will be clamped by internal diodes. Current should be
limited to the maximum ratings given.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG728/ADG729 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
TERMINOLOGY
VDD
IDD
GND
S
Most Positive Power Supply Potential.
Positive Supply Current.
CD, CS (ON) “ON” Switch Capacitance. Measured with refer-
ence to ground.
CIN
tON
Digital Input Capacitance.
Ground (0 V) Reference.
Delay time between the 50% and 90% points
of the STOP condition and the switch “ON”
condition.
Source Terminal. May be an input or output.
Drain Terminal. May be an input or output.
Analog Voltage on Terminals D, S.
Ohmic Resistance between D and S.
D
V
D (VS)
tOFF
Delay time between the 50% and 90% points
of the STOP condition and the switch “OFF”
condition.
RON
∆RON
On Resistance Match Between any Two Chan-
nels, i.e., RONmax – RONmin.
tD
“OFF” time measured between the 80% points of
both switches when switching from one switch to
another.
RFLAT(ON)
Flatness is defined as the difference between the
maximum and minimum value of on resistance
as measured over the specified analog signal range.
Charge
Injection
A measure of the glitch impulse transferred from
the digital input to the analog output during
switching.
IS (OFF)
Source Leakage Current with the Switch “OFF.”
Drain Leakage Current with the Switch “OFF.”
Channel Leakage Current with the Switch “ON.”
Maximum Input Voltage for Logic “0.”
Minimum Input Voltage for Logic “1.”
Input Current of the Digital Input.
I
D (OFF)
Off Isolation A measure of unwanted signal coupling through
an “OFF” switch.
ID, IS (ON)
VINL
Crosstalk
A measure of unwanted signal which is coupled
through from one channel to another as a result
of parasitic capacitance.
VINH
I
INL (IINH
)
Bandwidth
The frequency at which the output is attenuated
by 3 dBs.
CS (OFF)
“OFF” Switch Source Capacitance. Measured
with reference to ground.
On Response The frequency response of the “ON” switch.
C
D (OFF)
“OFF” Switch Drain Capacitance. Measured
with reference to ground.
Insertion
Loss
The loss due to the ON resistance of the switch.
–6–
REV. 0
Typical Performance Characteristics–ADG728/ADG729
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
0
V
V
= 3V
= 0V
V
V
= 5V
= 0V
T
V
= 25؇C
DD
SS
DD
SS
A
= 0V
SS
V
= 2.7V
DD
+85
؇C
V
= 3.3V
DD
V
= 4.5V
DD
+25؇C
–40؇C
V
= 5.5V
DD
+85؇C
+25
؇
C
–40؇C
0
0
1
2
3
4
5
0
D
1
2
3
4
5
0
0.5
1.0
1.5
2.0
2.5
3.0
V
OR V – DRAIN OR SOURCE VOLTAGE – V
V
OR V – DRAIN OR SOURCE VOLTAGE – V
V
OR V – DRAIN OR SOURCE VOLTAGE – V
D
S
S
D
S
Figure 2. On Resistance as a Function
of VD (VS) for Single Supply
Figure 3. On Resistance as a Function
of VD (VS) for Different Temperatures,
Single Supply
Figure 4. On Resistance as a Function
of VD (VS) for Different Temperatures,
Single Supply
0.12
0.12
0.35
V
V
= 5V
= 0V
DD
SS
V
V
T
= 5V
= 0V
V
V
= 3V
= 0V
DD
SS
A
DD
0.30
0.25
0.20
0.15
0.08
0.04
0.08
0.04
SS
= 25
؇
C
T = 25؇C
A
I
(ON)
I
(ON)
D
D
0.00
0.00
I
(OFF)
0.10
0.05
D
I
(OFF)
I
(OFF)
I
(OFF)
–0.04
–0.08
–0.12
–0.04
–0.08
–0.12
S
S
D
I
(ON)
75
D
I
(OFF)
4
D
0.00
I
(OFF)
S
–0.05
0
1
0
0.5
1.0
V
1.5
2.0
2.5
3.0
15
25
35
45
55
65
85
2
3
5
V
(V ) – Volts
(V ) – Volts
TEMPERATURE – ؇C
D
D
S
S
Figure 5. Leakage Currents as a Func-
tion of VD (VS)
Figure 6. Leakage Currents as a Func-
tion of VD (VS)
Figure 7. Leakage Currents as a
Function of Temperature
0.35
1m
20
T
= 25؇C
V
V
= 3V
= 0V
T
= 25؇C
A
DD
SS
A
0.30
0.25
0.20
0.15
10
V
V
= 5V
= 0V
DD
SS
100
10
1
0
–10
–20
–30
–40
V
V
= 3V
= 0V
DD
V
= 5V
DD
SS
0.10
0.05
I
(OFF)
D
V
= 3V
DD
0.00
I
(ON)
I
(OFF)
55
D
S
–0.05
15
25
35
45
65
75
85
10k
100k
FREQUENCY – Hz
1M
0
1
2
3
4
5
VOLTAGE – Volts
TEMPERATURE – ؇C
Figure 8. Leakage Currents as a Func-
tion of Temperature
Figure 9. Input Current vs. Switch-
ing Frequency
Figure 10. Charge Injection vs. Source
Voltage
REV. 0
–7–
ADG728/ADG729
0
–20
–40
0
–20
–40
160
V
T
= 5V
= 25؇C
V
T
= 5V
DD
DD
= 25
T
, V = 3V
ON DD
؇
C
A
140
120
100
80
A
T
, V = 3V
OFF DD
–60
–80
–60
–80
T
, V = 5V
OFF DD
T
, V = 5V
ON DD
60
40
–100
–120
–100
–120
20
0
30k 100k
1M
10M
100M
30k 100k
1M
10M
100M
–40
–20
0
20
40
60
80
FREQUENCY – Hz
FREQUENCY – Hz
TEMPERATURE – ؇C
Figure 11. TON /TOFF Times vs.
Temperature
Figure 12. Off Isolation vs. Frequency
Figure 13. Crosstalk vs. Frequency
0
V
T
= 5V
DD
= 25
؇
C
ADG728
ADG729
A
–5
–10
–15
–20
30k 100k
1M
10M
100M
FREQUENCY – Hz
Figure 14. On Response vs.
Frequency
–8–
REV. 0
ADG728/ADG729
GENERAL DESCRIPTION
The slave whose address corresponds to the transmitted
address responds by pulling the SDA line low during the
ninth clock pulse (this is termed the Acknowledge bit). At
this stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from its
serial register. If the R/W bit is high, the master will read
from the slave device. However, if the R/W bit is low, the
master will write to the slave device.
The ADG728 and ADG729 are serially controlled, 8-channel
and dual 4-channel matrix switches respectively. While provid-
ing the normal multiplexing and demultiplexing functions, these
devices also provide the user with more flexibility as to where
their signal may be routed. Each bit of the serial word corre-
sponds to one switch of the device. A Logic 1 in the particular
bit position turns on the switch, while a Logic 0 turns the switch
off. Because each switch is independently controlled by an indi-
vidual bit, this provides the option of having any, all, or none of
the switches ON. This feature may be particularly useful in the
demultiplexing application where the user may wish to direct
one signal from the drain to a number of outputs (sources). Care
must be taken, however, in the multiplexing situation where a
number of inputs may be shorted together (separated only by
the small on resistance of the switch).
2. Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge bit).
The transitions on the SDA line must occur during the low
period of SCL and remain stable during the high period of
SCL.
3. When all data bits have been read or written, a STOP condition
is established by the master. A STOP condition is defined as
a low-to-high transition on the SDA line while SCL is high.
In Write mode, the master will pull the SDA line high during
the 10th clock pulse to establish a STOP condition. In Read
mode, the master will issue a No Acknowledge for the ninth
clock pulse (i.e., the SDA line remains high). The master will
then bring the SDA line low before the tenth clock pulse and
then high during the tenth clock pulse to establish a STOP
condition.
When changing the switch conditions, a new 8-bit word is writ-
ten to the input shift register. Some of the bits may be the same
as the previous write cycle, as the user may not wish to change
the state of some switches. In order to minimize glitches on the
output of these switches, the part cleverly compares the state of
switches from the previous write cycle. If the switch is already
in the ON condition, and is required to stay ON, there will be
minimal glitches on the output of the switch.
See Figures 18 to 21 below for a graphical explanation of the
serial interface.
POWER-ON RESET
On power-up of the device, all switches will be in the OFF con-
dition and the internal shift register is filled with zeros and will
remain so until a valid write takes place.
A repeated write function gives the user flexibility to update the
matrix switch a number of times after addressing the part only
once. During the write cycle, each data byte will update the con-
figuration of the switches. For example, after the matrix switch
has acknowledged its address byte, and receives one data byte,
the switches will update after the data byte, if another data byte
is written to the matrix switch while it is still the addressed slave
device, this data byte will also cause an switch configuration
update. Repeat read of the matrix switch is also allowed.
SERIAL INTERFACE
2-Wire Serial Bus
The ADG728/ADG729 are controlled via an I2C compatible
serial bus. These parts are connected to this bus as a slave device
(no clock is generated by the multiplexer).
The ADG728/ADG729 have different 7-bit slave addresses.
The five MSBs of the ADG728 are 10011, while the MSBs of
the ADG729 are 10001 and the two LSBs are determined by
the state of the A0 and A1 pins.
INPUT SHIFT REGISTER
The input shift register is eight bits wide. Figure 15 illustrates
the contents of the input shift register. Data is loaded into the
device as an 8-bit word under the control of a serial clock input,
SCL. The timing diagram for this operation is shown in Figure 1.
The 8-bit word consists of eight data bits each controlling one
switch. MSB (Bit 7) is loaded first.
The 2-wire serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a START
condition which is when a high-to-low transition on the SDA
line occurs while SCL is high. The following byte is the
address byte, which consists of the 7-bit slave address fol-
lowed by a R/W bit (this bit determines whether data will be
read from or written to the slave device).
DB0 (LSB)
DB7 (MSB)
S8
S7
S6
S5
S4
S3
S2
S1
DATA BITS
Figure 15. ADG728/ADG729 Input Shift Register Contents
REV. 0
–9–
ADG728/ADG729
WRITE OPERATION
When writing to the ADG728/ADG729, the user must begin
with an address byte and R/W bit, after which the switch will
acknowledge that it is prepared to receive data by pulling SDA
low. This address byte is followed by the 8-bit word. The write
operations for each matrix switch are shown in the figures below.
SCL
A1
SDA
1
0
0
1
1
A0
R/W
S8
S7
S6
S5
S4
S3
S2
S1
STOP
COND
BY
ACK
BY
ADG728
START
COND
BY
ACK
BY
ADG728
ADDRESS BYTE
DATA BYTE
MASTER
MASTER
Figure 16. ADG728 Write Sequence
SCL
SDA
A1
1
0
0
0
1
A0
R/W
S8
S7
S6
S5
S4
S3
S2
S1
STOP
COND
BY
ACK
BY
ADG729
START
COND
BY
ACK
BY
ADG729
ADDRESS BYTE
DATA BYTE
MASTER
MASTER
Figure 17. ADG729 Write Sequence
READ OPERATION
When reading data back from the ADG728/ADG729, the user
must begin with an address byte and R/W bit, after which the
matrix switch will acknowledge that it is prepared to transmit data
by pulling SDA low. The readback operation is a single byte
that consists of the eight data bits in the input register. The read
operations for each part are shown in Figures 18 and 19.
SCL
A1
SDA
1
0
0
1
1
A0
R/W
S8
S7
S6
S5
S4
S3
S2
S1
STOP
COND
BY
NO ACK
BY
MASTER
START
COND
BY
ACK
BY
ADG728
ADDRESS BYTE
DATA BYTE
MASTER
MASTER
Figure 18. ADG728 Readback Sequence
SCL
SDA
A1
1
0
0
0
1
A0
R/W
S8
S7
S6
S5
S4
S3
S2
S1
STOP
COND
BY
NO ACK
BY
MASTER
START
COND
BY
ACK
BY
ADG729
ADDRESS BYTE
DATA BYTE
MASTER
MASTER
Figure 19. ADG729 Readback Sequence
–10–
REV. 0
ADG728/ADG729
MULTIPLE DEVICES ON ONE BUS
Figure 20 shows four ADG728s devices on the same serial bus.
Each has a different slave address since the state of their A0 and
A1 pins is different. This allows each Matrix Switch to be writ-
ten to or read from independently. Because the ADG729 has a
different address to the ADG728, it would be possible for four
of each of these devices to be connected to the same bus.
+5V
R
R
P
P
SDA
SCL
MASTER
V
V
V
DD
DD
DD
SDA
A1
SCL
SDA
A1
SCL
SDA
A1
SCL
SDA
A1
SCL
A0
A0
A0
A0
ADG728
ADG728
ADG728
ADG728
Figure 20. Multiple ADG728s on the Same Bus
TEST CIRCUITS
I
V
V
DS
DD
DD
V
1
S1
S2
I
(OFF)
A
D
D
S
D
S8
V
D
GND
V
S
V
S
R
= V /I
DS
1
ON
Test Circuit 1. On Resistance
Test Circuit 3. IS (OFF)
V
DD
V
DD
V
DD
V
I
(ON)
DD
D
I
(OFF)
A
S
S1
S8
D
S1
S2
S8
A
V
D
V
S
D
GND
V
V
S
GND
D
Test Circuit 2. ID (OFF)
Test Circuit 4. ID (ON)
V
V
DD
DD
SCL
50%
50%
ADG728*
V
S1
S1
S2 THRU S7
S8
V
V
R
S1
S8
V
= V
S8
S1
90%
V
D
80%
OUT
80%
V
V
OUT
OUT
C
GND
L
L
35pF
300⍀
90%
tOPEN
* SIMILAR CONNECTION FOR ADG729
tOFF
tON
Test Circuit 5. Switching Times and Break-Before-Make Times
REV. 0
–11–
ADG728/ADG729
V
V
DD
DD
ADG728*
SWITCH ON
R
S
D
SWITCH OFF
⌬V
S
OUT
V
OUT
Q
= C x ⌬V
C
1nF
OUT
INJ
L
L
V
S
INPUT LOGIC
GND
SDA SCL
* SIMILAR CONNECTION FOR ADG729
Test Circuit 6. Charge Injection
V
V
V
V
DD
DD
DD
DD
S1
S8
ADG728*
V
S
50⍀
S1
D
V
ADG728*
OUT
R
L
S2
S8
50⍀
D
V
OUT
R
L
V
S
GND
50⍀
GND
*SIMILAR CONNECTION FOR ADG729
* SIMILAR CONNECTION FOR ADG729
CHANNEL-TO-CHANNEL CROSSTALK = 20LOG (V
S1 IS SWITCHED OFF FOR OFF ISOLATION MEASURE-
MENTS AND ON FOR BANDWIDTH MEASUREMENTS
/V )
10 OUT
S
OFF ISOLATION = 20LOG (V
/V )
S
10
OUT
Test Circuit 7. Channel-to-Channel Crosstalk
V
WITH SWITCH
OUT
INSERTION LOSS = 20LOG
10
V
WITHOUT SWITCH
OUT
Test Circuit 8. Off Isolation and Bandwidth
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead TSSOP
(RU-16)
0.201 (5.10)
0.193 (4.90)
16
9
0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
0.246 (6.25)
8
1
PIN 1
0.006 (0.15)
0.002 (0.05)
0.0433 (1.10)
MAX
8؇
0؇
0.0118 (0.30)
0.0075 (0.19)
0.0256 (0.65)
0.028 (0.70)
0.020 (0.50)
0.0079 (0.20)
0.0035 (0.090)
SEATING
PLANE
BSC
REV. 0
–12–
相关型号：
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