ADG5436FBRUZ-RL7 [ADI]
Fault Protection and Detection, 10 ohm RON, Dual SPDT Switch;
| 型号： | ADG5436FBRUZ-RL7 |
| 厂家： | 
ADI |
| 描述： | Fault Protection and Detection, 10 ohm RON, Dual SPDT Switch 输入元件 光电二极管 输出元件 |
| 文件： | 总30页 (文件大小：1421K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Fault Protection and Detection,
10 Ω RON, Dual SPDT Switch
ADG5436F
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Overvoltage protection up to −55 V and +55 V
Power-off protection up to −55 V and +55 V
Overvoltage detection on source pins
Interrupt flags indicate fault status
ADG5436F
S1A
D1
S2A
D2
S1B
S2B
Low on resistance: 10 Ω (typical)
On-resistance flatness of 0.5 Ω (maximum)
6 kV human body model (HBM) ESD rating
Latch-up immune under any circumstance
Known state without digital inputs present
FAULT
DETECTION
+
SF
FF
SWITCH DRIVER
V
SS to VDD analog signal range
IN1
IN2 EN
DR
5 V to 22 V dual supply operation
8 V to 44 V single-supply operation
Fully specified at 15 V, 20 V, +12 V, and +36 V
NOTES
1. SWITCHES SHOWN FOR A LOGIC 1 INPUT.
Figure 1.
APPLICATIONS
Analog input/output modules
Process control/distributed control systems
Data acquisition
Instrumentation
Avionics
Automatic test equipment
Communication systems
Relay replacement
GENERAL DESCRIPTION
The ADG5436F is an analog multiplexer, containing two
independently selectable single-pole, double-throw (SPDT)
switches. An EN input is used to disable all the switches. For use
in multiplexer applications, both switches exhibit break-before-
make switching action.
resistance of the ADG5436F, combined with the on-resistance
flatness over a significant portion of the signal range, makes it
an ideal solution for data acquisition and gain switching
applications where excellent linearity and low distortion are
critical.
Each channel conducts equally well in both directions when on,
and each switch has an input signal range that extends to the
supplies. The digital inputs are compatible with 3 V logic inputs
over the full operating supply range.
Note that, throughout this data sheet, the dual function pin names
are referenced only by the relevant function where applicable. See
the Pin Configurations and Function Descriptions section for
full pin names and function descriptions.
When no power supplies are present, the switch remains in the off
condition, and the channel inputs are high impedance. Under
normal operating conditions, if the analog input signal level on
any Sxx pin exceeds VDD or VSS by a threshold voltage, VT, the
channel turns off and that Sxx pin becomes high impedance. If
the channel is on, the drain pin reacts according to the drain
response (DR) input pin. If the DR pin is left floating or pulled
high, the drain remains high impedance and floats. If the DR pin
is pulled low, the drain pulls to the exceeded rail. Input signal
levels of up to +55 V or −55 V relative to ground are blocked, in
both the powered and unpowered conditions. The low on
PRODUCT HIGHLIGHTS
1. Source pins are protected against voltages greater than the
supply rails, up to −55 V and +55 V.
2. Source pins are protected against voltages between −55 V
and +55 V in an unpowered state.
3. Overvoltage detection with digital output indicates the
operating state of the switches.
4. Trench isolation guards against latch-up.
5. Optimized for low on resistance and on-resistance flatness.
6. The ADG5436F operates from a dual supply of 5 V up to
22 V, or a single power supply of 8 V up to 44 V.
Rev. B
Document Feedback
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Technical Support
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ADG5436F
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Test Circuits..................................................................................... 20
Terminology.................................................................................... 24
Theory of Operation ...................................................................... 26
Switch Architecture.................................................................... 26
Fault Protection .......................................................................... 27
Applications Information .............................................................. 28
Power Supply Rails ..................................................................... 28
Power Supply Sequencing Protection...................................... 28
Signal Range................................................................................ 28
Low Impedance Channel Protection....................................... 28
Power Supply Recommendations............................................. 28
High Voltage Surge Suppression .............................................. 28
Intelligent Fault Detection ........................................................ 29
Large Voltage, High Frequency Signals................................... 29
Outline Dimensions....................................................................... 30
Ordering Guide .......................................................................... 30
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
15 V Dual Supply ....................................................................... 3
20 V Dual Supply ....................................................................... 5
12 V Single Supply........................................................................ 7
36 V Single Supply........................................................................ 9
Continuous Current per Channel, Sxx or Dx......................... 11
Absolute Maximum Ratings.......................................................... 12
ESD Caution................................................................................ 12
Pin Configurations and Function Descriptions ......................... 13
Truth Tables for Switches .......................................................... 14
Typical Performance Characteristics ........................................... 15
REVISION HISTORY
1/16—Rev. A to Rev. B
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 5
Changes to Table 3............................................................................ 7
Changes to Table 4............................................................................ 9
Changes to ESD Performance Section......................................... 26
5/15—Rev. 0 to Rev. A
Added 16-Lead LFCSP Package........................................Universal
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 5
Changes to Table 3............................................................................ 7
Changes to Table 4............................................................................ 9
Changes to Table 5.......................................................................... 11
Changes to Table 6.......................................................................... 12
Added Figure 3; Renumbered Sequentially ................................ 13
Changes to Table 7.......................................................................... 13
Added Figure 53.............................................................................. 30
Updated Outline Dimensions....................................................... 30
Changes to Ordering Guide .......................................................... 30
1/15—Revision 0: Initial Version
Rev. B | Page 2 of 30
Data Sheet
ADG5436F
SPECIFICATIONS
15 V DUAL SUPPLY
VDD = 15 V 10%, VSS = −15 V 10%, GND = 0 V, CDECOUPLING = 0.1 µF, unless otherwise noted.
Table 1.
−40°C to
+25°C +85°C
−40°C to
+125°C
Parameter
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
VDD = 13.5 V, VSS = −13.5 V, see Figure 30
VDD to VSS
16.5
V
10
11.2
9.5
10.7
0.15
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Voltage on the Sxx pins (VS) = 10 V, IS = −10 mA
VS = 9 V, IS = −10 mA
14
13.5
16
On-Resistance Match
VS = 10 V, IS = −10 mA
Between Channels, ∆RON
0.65
0.15
0.6
0.8
0.7
0.95
0.8
Ω max
Ω typ
Ω max
Ω typ
VS = 9 V, IS = −10 mA
VS = 10 V, IS = −10 mA
On-Resistance Flatness,
RFLAT(ON)
0.6
0.9
0.1
0.4
0.7
1.1
0.5
1.1
0.5
Ω max
Ω typ
Ω max
V typ
VS = 9 V, IS = −10 mA
Threshold Voltage, VT
LEAKAGE CURRENTS
See Figure 26
VDD = 16.5 V, VSS = −16.5 V
Source Off Leakage, IS (Off)
0.1
1.5
0.1
1.5
0.5
nA typ
nA max
nA typ
nA max
nA typ
VS = 10 V, voltage on the Dx pin (VD) = ∓10 V, see Figure 31
5.0
7.0
21
25
Drain Off Leakage, ID (Off)
VS = 10 V, VD = ∓10 V, see Figure 31
Channel On Leakage, ID (On),
IS (On)
VS = VD = 10 V, see Figure 32
1.5
5.0
21
nA max
FAULT
Source Leakage Current, IS
With Overvoltage
72
49
µA typ
µA typ
VDD = 16.5 V, VSS = −16.5 V, GND = 0 V, VS = 55 V,
see Figure 35
VDD = 0 V or floating, VSS = 0 V or floating, GND = 0 V, EN = 0 V
or floating, INx = 0 V or floating, VS = 55 V, see Figure 36
Power Supplies
Grounded or Floating
Drain Leakage Current, ID
With Overvoltage
DR = floating or >2 V
VDD = 16.5 V, VSS = −16.5 V, GND = 0 V, VS = 55 V, see
Figure 35
2.0
nA typ
8.0
10
15
49
nA max
nA typ
Power Supplies
Grounded
VDD = 0 V, VSS = 0 V, GND = 0 V, INx = 0 V or floating,
VS = 55 V, EN = 0 V, see Figure 36
30
10
50
10
100
10
nA max
µA typ
Power Supplies Floating
VDD = floating, VSS = floating, GND = 0 V, VS = 55 V,
EN = 0 V, see Figure 36
DIGITAL INPUTS/OUTPUTS
Input Voltage High, VINH
Input Voltage Low, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
µA typ
µA max
pF typ
V min
0.7
VIN = VGND or VDD
1.2
Digital Input Capacitance, CIN
Output Voltage High, VOH
Output Voltage Low, VOL
6.0
2.0
0.8
V max
Rev. B | Page 3 of 30
ADG5436F
Data Sheet
−40°C to
+25°C +85°C
−40°C to
+125°C
Parameter
DYNAMIC CHARACTERISTICS1
Unit
Test Conditions/Comments
Transition Time, tTRANSITION
400
540
435
515
165
210
320
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
RL = 300 Ω, CL = 35 pF
VS = 10 V, see Figure 46
RL = 300 Ω, CL = 35 pF
VS = 10 V, see Figure 45
RL = 300 Ω, CL = 35 pF
VS = 10 V, see Figure 45
RL = 300 Ω, CL = 35 pF
555
530
215
570
550
220
tON (EN)
tOFF (EN)
Break-Before-Make Time
Delay, tD
190
750
ns min
ns typ
VS = 10 V, see Figure 44
RL = 1 kΩ, CL = 2 pF, see Figure 39
Overvoltage Response
Time, tRESPONSE
510
680
725
ns max
ns typ
Overvoltage Recovery Time, 820
tRECOVERY
RL = 1 kΩ, CL = 2 pF, see Figure 40
1100
85
1150
1200
115
ns max
ns typ
Interrupt Flag Response
Time, tDIGRESP
Interrupt Flag Recovery
Time, tDIGREC
CL = 12 pF, see Figure 41
CL = 12 pF, see Figure 42
60
85
µs typ
600
−724
−71
ns typ
pC typ
dB typ
dB typ
% typ
CL = 12 pF, RPULLUP = 1 kΩ, see Figure 43
VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 47
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 33
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 34
RL = 10 kΩ, VS = 15 V p-p, f = 20 Hz to 20 kHz, see Figure 38
Charge Injection, QINJ
Off Isolation
Channel-to-Channel Crosstalk −73
Total Harmonic Distortion
Plus Noise, THD + N
0.001
−3 dB Bandwidth
Insertion Loss
Source Capacitance (CS), Off 12
Drain Capacitance (CD), Off
CD (On), CS (On)
169
−0.8
MHz typ RL = 50 Ω, CL = 5 pF, see Figure 37
dB typ
pF typ
pF typ
pF typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 37
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
24
37
VS = 0 V, f = 1 MHz
POWER REQUIREMENTS
VDD = 16.5 V, VSS = −16.5 V, GND = 0 V, digital inputs = 0 V,
5 V, or VDD
Normal Mode
IDD
0.9
1.2
0.4
0.55
0.5
mA typ
mA max
mA typ
mA max
mA typ
mA max
1.3
0.6
0.7
IGND
ISS
0.65
Fault Mode
IDD
VS = 55 V
1.2
1.6
0.8
1.0
0.5
1.0
mA typ
mA max
mA typ
mA max
mA typ
1.8
1.1
IGND
ISS
Digital inputs = 5 V
mA max VS = 55 V, VD = 0 V
1.8
5
22
VDD/VSS
V min
V max
GND = 0 V
GND = 0 V
1 Guaranteed by design. Not subject to production test.
Rev. B | Page 4 of 30
Data Sheet
ADG5436F
20 V DUAL SUPPLY
VDD = 20 V 10%, VSS = −20 V 10%, GND = 0 V, CDECOUPLING = 0.1 µF, unless otherwise noted.
Table 2.
−40°C to
+85°C
−40°C to
+125°C
Parameter
+25°C
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
VDD = 18 V, VSS = −18 V, see Figure 30
VDD to VSS
16.5
16.5
0.95
0.8
V
10
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
V typ
VS = 15 V, IS = −10 mA
11.5
9.5
11
14.5
14
VS = 13.5 V, IS = −10 mA
VS = 15 V, IS = −10 mA
On-Resistance Match Between Channels, ∆RON
On-Resistance Flatness, RFLAT(ON)
0.15
0.65
0.15
0.6
1.0
1.4
0.1
0.4
0.7
0.8
0.7
1.5
0.5
VS = 13.5 V, IS = −10 mA
VS = 15 V, IS = −10 mA
1.5
VS = 13.5 V, IS = −10 mA
0.5
Threshold Voltage, VT
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
See Figure 26
VDD = 22 V, VSS = −22 V
VS = 15 V, VD = 15 V, see Figure 31
0.1
1.5
0.1
1.5
0.5
1.5
nA typ
nA max
nA typ
nA max
nA typ
nA max
5.0
7.0
5.0
21
25
21
Drain Off Leakage, ID (Off)
VS = 15 V, VD = 15 V, see Figure 31
VS = VD = 15 V, see Figure 32
Channel On Leakage, ID (On), IS (On)
FAULT
Source Leakage Current, IS
With Overvoltage
84
49
µA typ
µA typ
VDD = +22 V, VSS = −22 V, GND = 0 V,
VS = 55 V, see Figure 35
VDD = 0 V or floating, VSS = 0 V or floating,
GND = 0 V, EN = 0 V or floating, INx = 0 V
or floating, VS = 55 V, see Figure 36
Power Supplies Grounded or Floating
Drain Leakage Current, ID
With Overvoltage
DR = floating or >2 V
5.0
nA typ
VDD = +22 V, VSS = −22 V, GND = 0 V,
INx = 0 V or floating, VS = 55 V, see
Figure 35
1.0
10
1.0
1.0
µA max
nA typ
Power Supplies Grounded
Power Supplies Floating
VDD = 0 V, VSS = 0 V, GND = 0 V, VS =
55 V, EN = 0 V, see Figure 36
30
10
50
10
100
10
nA max
µA typ
VDD = floating, VSS = floating, GND =
0 V, VS = 55 V, EN = 0 V, see Figure 36
DIGITAL INPUTS
Input Voltage High, VINH
Input Voltage Low, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
µA typ
µA max
pF typ
V min
0.7
VIN = VGND or VDD
1.2
Digital Input Capacitance, CIN
Output Voltage High, VOH
Output Voltage Low, VOL
6.0
2.0
0.8
V max
Rev. B | Page 5 of 30
ADG5436F
Data Sheet
−40°C to
+85°C
−40°C to
+125°C
Parameter
DYNAMIC CHARACTERISTICS1
+25°C
Unit
Test Conditions/Comments
Transition Time, tTRANSITION
405
540
430
535
170
205
330
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
ns typ
µs typ
ns typ
pC typ
RL = 300 Ω, CL = 35 pF
VS = 10 V, see Figure 46
RL = 300 Ω, CL = 35 pF
VS = 10 V, see Figure 45
RL = 300 Ω, CL = 35 pF
VS = 10 V, see Figure 45
RL = 300 Ω, CL = 35 pF
VS = 10 V, see Figure 44
RL = 1 kΩ, CL = 2 pF, see Figure 39
555
560
210
570
585
215
205
630
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD
Overvoltage Response Time, tRESPONSE
Overvoltage Recovery Time, tRECOVERY
430
560
930
1300
85
60
600
−737
605
RL = 1 kΩ, CL = 2 pF, see Figure 40
1500
1700
115
85
Interrupt Flag Response Time, tDIGRESP
Interrupt Flag Recovery Time, tDIGREC
CL = 12 pF, see Figure 41
CL = 12 pF, see Figure 42
CL = 12 pF, RPULLUP = 1 kΩ, see Figure 43
VS = 0 V, RS = 0 Ω, CL = 1 nF, see
Figure 47
Charge Injection, QINJ
Off Isolation
−72
dB typ
dB typ
% typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see
Figure 33
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see
Figure 34
RL = 10 kΩ, VS = 20 V p-p, f = 20 Hz to
20 kHz, see Figure 38
Channel-to-Channel Crosstalk
Total Harmonic Distortion Plus Noise, THD + N
−73
0.001
−3 dB Bandwidth
Insertion Loss
171
−0.8
MHz typ RL = 50 Ω, CL = 5 pF, see Figure 37
dB typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see
Figure 37
CS (Off)
CD (Off)
CD (On), CS (On)
POWER REQUIREMENTS
11
23
36
pF typ
pF typ
pF typ
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VDD = 22 V, VSS = −22 V, digital inputs =
0 V, 5 V, or VDD
Normal Mode
IDD
0.9
1.2
0.4
0.55
0.5
mA typ
mA max
mA typ
mA max
mA typ
mA max
1.3
0.6
0.7
IGND
ISS
0.65
Fault Mode
IDD
VS = 55 V
1.2
1.6
0.8
1.0
0.5
1.0
mA typ
mA max
mA typ
mA max
mA typ
mA max
V min
1.8
1.1
IGND
ISS
Digital inputs = 5 V
VS = 55 V, VD = 0 V
GND = 0 V
1.8
5
VDD/VSS
22
V max
GND = 0 V
1 Guaranteed by design. Not subject to production test.
Rev. B | Page 6 of 30
Data Sheet
ADG5436F
12 V SINGLE SUPPLY
VDD = 12 V 10%, VSS = 0 V, GND = 0 V, CDECOUPLING = 0.1 µF, unless otherwise noted.
Table 3.
−40°C to
+25°C +85°C
−40°C to
+125°C
Parameter
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
VDD = 10.8 V, VSS = 0 V, see Figure 30
VS = 0 V to 10 V, IS = −10 mA
VS = 3.5 V to 8.5 V, IS = −10 mA
VS = 0 V to 10 V, IS = −10 mA
VS = 3.5 V to 8.5 V, IS = −10 mA
VS = 0 V to 10 V, IS = −10 mA
VS = 3.5 V to 8.5 V, IS = −10 mA
0 V to VDD
37
V
22
24.5
10
11.2
0.2
0.65
0.2
0.65
12.5
14.5
0.6
0.9
0.7
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
V typ
31
14
16.5
0.95
0.95
23
On-Resistance Match Between Channels, ∆RON
On-Resistance Flatness, RFLAT(ON)
0.8
0.8
19
1.1
1.3
Threshold Voltage, VT
LEAKAGE CURRENTS
See Figure 26
VDD = 13.2 V, VSS = 0 V
Source Off Leakage, IS (Off)
0.1
1.5
0.1
1.5
0.5
1.5
nA typ
nA max
nA typ
nA max
nA typ
nA max
VS = 1 V/10 V, VD = 10 V/1 V, see Figure 31
5.0
21
25
21
Drain Off Leakage, ID (Off)
VS = 1 V/10 V, VD = 10 V/1 V, see Figure 31
VS = VD = 1 V/10 V, see Figure 32
7.0
5.0
Channel On Leakage, ID (On), IS (On)
FAULT
Source Leakage Current, IS
With Overvoltage
65
49
µA typ
µA typ
VDD = 13.2 V, VSS = 0 V, GND = 0 V,
VS = 55 V, see Figure 35
VDD = 0 V or floating, VSS = 0 V or floating,
GND = 0 V, EN = 0 V or floating, VS =
55 V, see Figure 36
Power Supplies Grounded or Floating
Drain Leakage Current, ID
With Overvoltage
DR = floating or >2 V
2.0
nA typ
VDD = 13.2 V, VSS = 0 V, GND = 0 V,
INx = 0 V or floating, VS = 55 V,
see Figure 35
8.0
10
15
49
nA max
nA typ
Power Supplies Grounded
Power Supplies Floating
VDD = 0 V, VSS = 0 V, GND = 0 V, VS = 55 V,
EN = 0 V, see Figure 36
30
10
50
10
100
10
nA max
µA typ
VDD = floating, VSS = floating, GND = 0 V,
VS = 55 V, EN = 0 V, see Figure 36
DIGITAL INPUTS
Input Voltage High, VINH
Input Voltage Low, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
µA typ
µA max
pF typ
V min
0.7
VIN = VGND or VDD
1.2
Digital Input Capacitance, CIN
Output Voltage High, VOH
Output Voltage Low, VOL
6.0
2.0
0.8
V max
Rev. B | Page 7 of 30
ADG5436F
Data Sheet
−40°C to
+25°C +85°C
−40°C to
+125°C
Parameter
DYNAMIC CHARACTERISTICS1
Unit
Test Conditions/Comments
Transition Time, tTRANSITION
400
545
435
515
185
230
300
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
ns typ
µs typ
ns typ
pC typ
dB typ
dB typ
% typ
RL = 300 Ω, CL = 35 pF
VS = 10 V, see Figure 46
RL = 300 Ω, CL = 35 pF
VS = 8 V, see Figure 45
RL = 300 Ω, CL = 35 pF
VS = 8 V, see Figure 45
RL = 300 Ω, CL = 35 pF
VS = 8 V, see Figure 44
RL = 1 kΩ, CL = 2 pF, see Figure 39
560
530
240
570
550
250
180
870
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD
Overvoltage Response Time, tRESPONSE
Overvoltage Recovery Time, tRECOVERY
590
770
680
850
85
830
910
RL = 1 kΩ, CL = 2 pF, see Figure 40
1000
115
85
Interrupt Flag Response Time, tDIGRESP
Interrupt Flag Recovery Time, tDIGREC
CL = 12 pF, see Figure 41
CL = 12 pF, see Figure 42
60
600
−341
−68
−70
0.007
CL = 12 pF, RPULLUP = 1 kΩ, see Figure 43
VS = 6 V, RS = 0 Ω, CL = 1 nF, see Figure 47
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 33
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 34
RL = 10 kΩ, VS = 6 V p-p, f = 20 Hz to
20 kHz, see Figure 38
Charge Injection, QINJ
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion Plus Noise, THD + N
−3 dB Bandwidth
Insertion Loss
CS (Off)
CD (Off)
CD (On), CS (On)
POWER REQUIREMENTS
152
−0.8
14
30
41
MHz typ RL = 50 Ω, CL = 5 pF, see Figure 37
dB typ
pF typ
pF typ
pF typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 37
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VDD = 13.2 V, VSS = 0 V, digital inputs = 0 V,
5 V, or VDD
Normal Mode
IDD
0.9
1.2
0.4
0.55
0.5
mA typ
mA max
mA typ
mA max
mA typ
mA max
1.3
0.6
0.7
IGND
ISS
0.65
Fault Mode
IDD
VS = 55 V
1.2
1.6
0.8
1.0
0.5
1.0
mA typ
mA max
mA typ
mA max
mA typ
1.8
1.1
IGND
ISS
Digital inputs = 5 V
mA max VS = 55 V, VD = 0 V
1.8
8
44
VDD
V min
V max
GND = 0 V
GND = 0 V
1 Guaranteed by design. Not subject to production test.
Rev. B | Page 8 of 30
Data Sheet
ADG5436F
36 V SINGLE SUPPLY
VDD = 36 V 10%, VSS = 0 V, GND = 0 V, CDECOUPLING = 0.1 µF, unless otherwise noted.
Table 4.
−40°C to
+25°C +85°C
−40°C to
+125°C
Parameter
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
VDD = 32.4 V, VSS = 0 V, see Figure 30
VS = 0 V to 30 V, IS = −10 mA
VS = 4.5 V to 28 V, IS = −10 mA
VS = 0 V to 30 V, IS = −10 mA
VS = 4.5 V to 28 V, IS = −10 mA
VS = 0 V to 30 V, IS = −10 mA
VS = 4.5 V to 28 V, IS = −10 mA
0 V to VDD
37
V
22
24.5
10
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
V typ
31
11
14
16.5
0.95
0.8
On-Resistance Match Between Channels, ∆RON 0.15
0.65
0.15
0.6
12.5
14.5
0.1
0.8
0.7
19
On-Resistance Flatness, RFLAT(ON)
23
0.4
0.7
0.5
0.5
Threshold Voltage, VT
LEAKAGE CURRENTS
See Figure 26
VDD =39.6 V, VSS = 0 V
Source Off Leakage, IS (Off)
0.1
1.5
0.1
1.5
0.5
1.5
nA typ
nA max
nA typ
nA max
nA typ
nA max
VS = 1 V/30 V, VD = 30 V/1 V, see Figure 31
5.0
21
25
21
Drain Off Leakage, ID (Off)
VS = 1 V/30 V, VD = 30 V/1 V, see Figure 31
VS = VD = 1 V/30 V, see Figure 32
7.0
5.0
Channel On Leakage, ID (On), IS (On)
FAULT
Source Leakage Current, IS
With Overvoltage
60
49
µA typ
µA typ
VDD = 39.6 V, VSS = 0 V, GND = 0 V,
INx = 0 V or floating, VS = +55 V, −40 V,
see Figure 35
VDD = 0 V or floating, VSS = 0 V or
floating, GND = 0 V, INx = 0 V or
floating, VS = +55 V, −40 V, see Figure 36
Power Supplies Grounded or Floating
Drain Leakage Current, ID
With Overvoltage
DR = floating or >2 V
VDD = 39.6 V, VSS = 0 V, GND = 0 V,
VS = +55 V, −40 V, see Figure 35
2.0
nA typ
8.0
10
15
49
nA max
nA typ
Power Supplies Grounded
Power Supplies Floating
VDD = 0 V, VSS = 0 V, GND = 0 V, VS =
+55 V, −40 V, EN = 0 V, see Figure 36
30
10
50
10
100
10
nA max
µA typ
VDD = floating, VSS = floating, GND = 0 V,
VS = +55 V, −40 V, EN = 0 V, see Figure 36
DIGITAL INPUTS
Input Voltage High, VINH
Input Voltage Low, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
µA typ
µA max
pF typ
V min
0.7
VIN = VGND or VDD
1.2
Digital Input Capacitance, CIN
Output Voltage High, VOH
Output Voltage Low, VOL
6.0
2.0
0.8
V max
Rev. B | Page 9 of 30
ADG5436F
Data Sheet
−40°C to
+25°C +85°C
−40°C to
+125°C
Parameter
DYNAMIC CHARACTERISTICS1
Unit
Test Conditions/Comments
Transition Time, tTRANSITION
400
540
440
520
160
190
330
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
ns typ
µs typ
ns typ
pC typ
RL = 300 Ω, CL = 35 pF
VS = 10 V, see Figure 46
RL = 300 Ω, CL = 35 pF
VS = 18 V, see Figure 45
RL = 300 Ω, CL = 35 pF
VS = 18 V, see Figure 45
RL = 300 Ω, CL = 35 pF
VS = 18 V, see Figure 44
RL = 1 kΩ, CL = 2 pF, see Figure 39
555
540
195
570
560
200
210
385
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD
Overvoltage Response Time, tRESPONSE
Overvoltage Recovery Time, tRECOVERY
260
340
1500
2100
85
60
600
−627
360
RL = 1 kΩ, CL = 2 pF, see Figure 40
2400
2700
115
85
Interrupt Flag Response Time, tDIGRESP
Interrupt Flag Recovery Time, tDIGREC
CL = 12 pF, see Figure 41
CL = 12 pF, see Figure 42
CL = 12 pF, RPULLUP = 1 kΩ, see Figure 43
VS = 18 V, RS = 0 Ω, CL = 1 nF, see
Figure 47
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see
Figure 33
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see
Figure 34
RL = 10 kΩ, VS = 18 V p-p, f = 20 Hz to
20 kHz, see Figure 38
Charge Injection, QINJ
Off Isolation
−71
−73
dB typ
dB typ
% typ
Channel-to-Channel Crosstalk
Total Harmonic Distortion Plus Noise, THD + N 0.001
−3 dB Bandwidth
Insertion Loss
173
−0.8
MHz typ
dB typ
RL = 50 Ω, CL = 5 pF, see Figure 37
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see
Figure 37
CS (Off)
CD (Off)
CD (On), CS (On)
POWER REQUIREMENTS
11
23
36
pF typ
pF typ
pF typ
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
VDD = 39.6 V, VSS = 0 V, digital inputs =
0 V, 5 V, or VDD
Normal Mode
IDD
0.9
1.2
0.4
0.55
0.5
mA typ
mA max
mA typ
mA max
mA typ
mA max
1.3
0.6
0.7
IGND
ISS
0.65
Fault Mode
IDD
VS = +55 V, −40 V
1.2
1.6
0.8
1.0
0.5
1.0
mA typ
mA max
mA typ
mA max
mA typ
mA max
V min
1.8
1.1
IGND
ISS
Digital inputs = 5 V
VS = 55 V, VD = 0 V
GND = 0 V
1.8
8
VDD
44
V max
GND = 0 V
1 Guaranteed by design. Not subject to production test.
Rev. B | Page 10 of 30
Data Sheet
ADG5436F
CONTINUOUS CURRENT PER CHANNEL, Sxx OR Dx
Table 5.
Parameter
25°C
85°C
125°C
Unit
Test Conditions/Comments
16-Lead TSSOP
θJA = 112.6°C/W
113
88
77
61
50
42
mA max
mA max
VS = VSS + 4.5 V to VDD − 4.5 V
VS = VSS to VDD
16-Lead LFCSP
θJA = 30.4°C/W
207
161
125
103
68
61
mA max
mA max
VS = VSS + 4.5 V to VDD − 4.5 V
VS = VSS to VDD
Rev. B | Page 11 of 30
ADG5436F
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 6.
Parameter
Rating
VDD to VSS
48 V
VDD to GND
VSS to GND
Sxx to GND
Sxx to VDD or VSS
VS to VD
−0.3 V to +48 V
−48 V to +0.3 V
−55 V to +55 V
80 V
Only one absolute maximum rating can be applied at any
one time.
80 V
Dx Pin1 to GND
VSS − 0.7 V to VDD + 0.7 V or
30 mA, whichever occurs first
ESD CAUTION
Digital Inputs to GND
GND − 0.7 V to 48 V or
30 mA, whichever occurs first
Peak Current, Sxx or Dx Pins
288 mA (pulsed at 1 ms,
10% duty cycle maximum)
Continuous Current, Sxx or Dx
Digital Output
Data2 + 15%
GND − 0.7 V to 6 V or 30 mA,
whichever occurs first
Dx Pin, Overvoltage State,
DR = GND, Load Current
1 mA
Operating Temperature Range
Storage Temperature Range
Junction Temperature
−40°C to +125°C
−65°C to +150°C
150°C
Thermal Impedance, θJA
16-Lead TSSOP (4-Layer Board)
16-Lead LFCSP (4-Layer Board)
112.6°C/W
30.4°C/W
Reflow Soldering Peak
Temperature, Pb-Free
As per JEDEC J-STD-020
ESD Rating, HBM: ESDA/JEDEC
JS-001-2011
Input/Output (I/O) Port to
Supplies
6 kV
I/O Port to I/O Port
All Other Pins
6 kV
6 kV
1 Overvoltages at the Dx pin are clamped by internal diodes. Limit current to
the maximum ratings given.
2 See Table 5.
Rev. B | Page 12 of 30
Data Sheet
ADG5436F
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
D1
1
2
3
4
12 EN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IN1/F1
S1A
D1
SF
FF
EN
S1B
11
10
9
V
DD
ADG5436F
TOP VIEW
(Not to Scale)
V
S2B
D2
SS
ADG5436F
TOP VIEW
(Not to Scale)
GND
S1B
V
DD
V
S2B
D2
SS
GND
NIC
DR
S2A
IN2/F2
NOTES
1. NIC = NO INTERNAL CONNECTION.
2. THE EXPOSED PAD IS INTERNALLY CONNECTED. FOR
INCREASED RELIABILITY OF THE SOLDER JOINTS AND
MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED
THAT THE PAD BE CONNECTED TO THE LOWEST
NOTES
1. NIC = NO INTERNAL CONNECTION.
SUPPLY VOLTAGE, V
.
SS
Figure 2. TSSOP Pin Configuration
Figure 3. LFCSP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
TSSOP LFCSP
Mnemonic
Description
1
15
IN1/F1
Logic Control Input 1 (IN1). See Table 8.
Decoder Pin (F1). This pin is used together with the specific fault pin (SF) to indicate which input is in
a fault condition. See Table 9.
2
3
4
5
6
7
8
16
1
2
3
4
S1A
D1
S1B
VSS
GND
NIC
DR
Overvoltage Protected Source Terminal 1A. This pin can be an input or output.
Drain Terminal 1. This pin can be an input or output.
Overvoltage Protected Source Terminal 1B. This pin can be an input or output.
Most Negative Power Supply Potential.
Ground (0 V) Reference.
No Internal Connection.
Drain Response Digital Input. Tying this pin to GND enables the drain to pull to VDD or VSS during an
overvoltage fault condition. The default condition of the drain is open-circuit when the pin is left
floating or if it is tied to VDD.
7
5
9
6
IN2/F2
Logic Control Input 2 (IN2). See Table 8.
Decoder Pin (F2). This pin is used together with the specific fault pin (SF) to indicate which input is in
a fault condition. See Table 9.
10
11
12
13
14
8
9
10
11
12
S2A
D2
S2B
VDD
EN
Overvoltage Protected Source Terminal 2A. This pin can be an input or output.
Drain Terminal 2. This pin can be an input or output.
Overvoltage Protected Source Terminal 2B. This pin can be an input or output.
Most Positive Power Supply Potential.
Active High Digital Input. When this pin is low, the device is disabled and all switches are off. When
this pin is high, the INx logic inputs determine the on switches.
15
13
FF
Fault Flag Digital Output. This pin has a high output when the device is in normal operation or a low
output when a fault condition occurs on any of the Sxx inputs. The FF pin has a weak internal pull-up
that allows the signals to be combined into a single interrupt for larger modules that contain
multiple devices.
16
14
EP
SF
Specific Fault Digital Output. This pin has a high output when the device is in normal operation, or a
low output when a fault condition is detected on a specific pin, depending on the state of F1 and F2
per Table 9.
The exposed pad is connected internally. For increased reliability of the solder joints and maximum
thermal capability, it is recommended that the pad be soldered to the lowest supply voltage, VSS.
Exposed Pad
Rev. B | Page 13 of 30
ADG5436F
Data Sheet
TRUTH TABLES FOR SWITCHES
Table 8. Truth Table
INx
SxA
Off
SxB
On
0
1
On
Off
Table 9. Fault Diagnostic Output Truth Table
State of Specific Fault Pin (SF) with Decoder Pins (F2, F1)
Switch in Fault1
F2 = 0, F1 = 0
F2 = 0, F1 = 1
F2 = 1, F1 = 0
F2 = 1, F1 = 1
State of Fault Flag (FF)
None
S1A
S1B
S2A
1
0
1
1
1
0
0
0
1
1
1
0
0
0
1
0
1
1
0
1
1
0
1
1
0
0
1
0
0
1
0
0
1
1
1
1
0
1
1
0
1
0
0
1
0
0
0
0
1
1
1
0
1
1
0
1
0
1
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
S2B
S1A, S1B
S1A, S2A
S1A, S2B
S1B, S2A
S1B, S2B
S2A, S2B
S1A, S1B, S2A
S1A, S1B, S2B
S1A, S2A, S2B
S1B, S2A, S2B
S1A, S1B, S2A, S2B
1 Note that more than one pin can be in fault at any one time. See the Applications Information section for more details.
Rev. B | Page 14 of 30
Data Sheet
ADG5436F
TYPICAL PERFORMANCE CHARACTERISTICS
25
40
35
30
25
20
15
10
5
V
V
= +22V
= –22V
V
V
= +15V
= –15V
DD
SS
T
= 25°C
DD
A
SS
V
V
= +20V
= –20V
DD
SS
20
15
10
5
V
V
= +16.5V
= –16.5V
DD
SS
V
V
= +18V
= –18V
DD
SS
V
V
= +13.5V
= –13.5V
DD
SS
+125°C
+85°C
V
V
= +15V
= –15V
DD
+25°C
–40°C
SS
0
–25 –20 –15 –10
–5
0
5
10
15
20
25
0
–15 –12
–9
–6
–3
0
3
6
9
12
15
V , V (V)
S
D
V , V (V)
S
D
Figure 4. RON as a Function of VS and VD, Various Dual Supplies
Figure 7. RON as a Function of VS and VD for Different Temperatures,
15 V Dual Supply
25
40
T
= 25°C
V
V
= +20V
= –20V
A
DD
SS
35
30
25
20
15
10
5
20
15
10
5
V
V
= 12V
= 0V
DD
SS
V
V
= 10.8V
= 0V
DD
SS
+125°C
+85°C
V
V
= 13.2V
= 0V
DD
SS
+25°C
–40°C
0
0
2
4
6
8
10
12
14
0
–20
–15
–10
–5
0
5
10
15
20
V
, V (V)
D
S
V , V (V)
S
D
Figure 5. RON as a Function of VS and VD, 12 V Single Supply
Figure 8. RON as a Function of VS and VD for Different Temperatures,
20 V Dual Supply
25
20
15
10
5
40
V
V
= 12V
DD
T
= 25°C
A
= 0V
SS
35
30
25
20
15
10
5
V
V
= 36V
= 0V
DD
SS
V
V
= 32.4V
= 0V
DD
SS
+125°C
+85°C
V
V
= 39.6V
= 0V
DD
SS
+25°C
–40°C
0
0
5
10
15
20
V , V (V)
25
30
35
40
0
0
2
4
6
8
10
12
S
D
V , V (V)
S
D
Figure 6. RON as a Function of VS and VD, 36 V Single Supply
Figure 9. RON as a Function of VS and VD for Different Temperatures,
12 V Single Supply
Rev. B | Page 15 of 30
ADG5436F
Data Sheet
2
0
40
35
30
25
20
15
10
5
V
V
= 36V
DD
= 0V
SS
V
V
V
= +12V
= 0V
DD
SS
= V = +1V, –10V
S
D
–2
–4
–6
I
I
(OFF) +-
(OFF) –+
I
I
(OFF) +–
(OFF) –+
S
S
D
D
+125°C
+85°C
I , I (ON)++
I , I (ON) ––
S D
S
D
+25°C
–40°C
0
0
20
40
60
80
100
120
0
4
8
12
16
20
24
28
32
36
TEMPERATURE (°C)
V , V (V)
S
D
Figure 13. Leakage Current vs. Temperature, 12 V Single Supply
Figure 10. RON as a Function of VS and VD for Different Temperatures,
36 V Single Supply
1
0
5
V
V
= +15V
= –15V
DD
SS
0
–5
–1
V
V
V
= +15V
= –15V
DD
SS
–2
–3
–4
–5
–6
–7
–8
= V = +10V, –10V
S
D
I
I
(OFF) +-
(OFF) –+
I
I
(OFF) +–
(OFF) –+
–10
–15
–20
S
S
D
D
I , I (ON)++
I , I (ON) ––
S D
S
D
V
V
V
V
= –30V
= –55V
= +30V
= +55V
S
S
S
S
0
20
40
60
80
100
120
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 14. Overvoltage Leakage Current vs. Temperature, 15 V Dual Supply
Figure 11. Leakage Current vs. Temperature, 15 V Dual Supply
5
2
0
V
V
= +20V
= –20V
DD
SS
0
–5
V
V
V
= +20V
= –20V
DD
SS
–2
–4
= V = +15V, –15V
S
D
–10
–15
–20
–25
I
I
(OFF) +-
(OFF) –+
I
I
(OFF) +–
(OFF) –+
S
S
D
D
–6
I , I (ON)++
I , I (ON) ––
S D
S
D
V
V
V
V
= –30V
= –55V
= +30V
= +55V
S
S
S
S
–8
–10
0
20
40
60
80
100
120
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 12. Leakage Current vs. Temperature, 20 V Dual Supply
Figure 15. Overvoltage Leakage Current vs. Temperature, 20 V Dual Supply
Rev. B | Page 16 of 30
Data Sheet
ADG5436F
0
–20
2
V
V
= 12V
= 0V
DD
SS
T
V
V
= 25°C
A
0
= +15V
= –15V
DD
SS
–2
–40
–4
–6
–60
–8
–80
–10
–12
V
V
V
V
= –30V
= –55V
= +30V
= +55V
S
S
S
S
–100
–14
–16
–120
0
20
40
60
80
100
120
10k
100k
1M
10M
100M
1G
10G
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 16. Overvoltage Leakage Current vs. Temperature, 12 V Single Supply
Figure 19. Channel-to-Channel Crosstalk vs. Frequency
800
2
V
V
= 36V
= 0V
T
= 25°C
DD
SS
A
700
600
500
400
300
200
100
0
0
–2
–4
–6
–8
–10
–12
–14
V
V
= 12V,
= 36V,
V
V
= 0V
= 0V
DD
DD
SS
SS
V
V
V
V
= –38V
= –40V
= +38V
= +55V
S
S
S
S
–100
–200
0
20
40
60
80
100
120
0
5
10
15
20
(V)
25
30
35
40
TEMPERATURE (°C)
V
S
Figure 17. Overvoltage Leakage Current vs. Temperature, 36 V Single Supply
Figure 20. Charge Injection vs. Source Pin Voltage (VS), Single Supply
0
900
T
V
= 25°C
= 15V
A
T
= 25°C
A
800
700
600
500
400
300
200
100
0
DD
–20
–40
–60
–80
V
V
= +15V,
= +20V,
V
V
= –15V
= –20V
DD
DD
SS
SS
–100
–120
–100
10k
100k
1M
10M
100M
1G
10G
–200
–20
–15
–10
–5
0
5
10
15
20
FREQUENCY (Hz)
V
(V)
S
Figure 18. Off Isolation vs. Frequency
Figure 21. Charge Injection vs. Source Pin Voltage (VS), Dual Supply
Rev. B | Page 17 of 30
ADG5436F
Data Sheet
0
490
480
470
460
450
440
430
420
T
V
V
= 25°C
A
V
V
V
V
= +12V,
= +36V,
= +15V,
= +20V,
V
V
V
V
= 0V
= 0V
= –15V
= –20V
DD
DD
DD
DD
SS
SS
SS
SS
–100
–200
–300
–400
–500
–600
–700
–800
–900
–100
= +15V
= –15V
DD
SS
WITH DECOUPLING CAPACITORS
10k
100k
1M
10M
100M
1G
–40
–20
0
20
40
60
80
100
120
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 22. ACPSRR vs. Frequency
Figure 25. tTRANSITION vs. Temperature
0.020
0.9
0.8
0.7
0.6
0.5
V
V
V
V
= +12V,
= +36V,
= +15V,
= +20V,
V
V
V
V
= 0V,
= 0V,
= –15V,
V
V
= 6V p-p
= 18V p-p
DD
DD
DD
DD
SS
SS
SS
SS
S
S
LOAD = 10kΩ
= 25°C
T
A
V
V
= 15V p-p
= 20V p-p
S
S
= –20V,
0.015
0.010
0.005
0
0
5
10
15
20
–40
–20
0
20
40
60
80
100
120
FREQUENCY (kHz)
TEMPERATURE (°C)
Figure 23. THD + N vs. Frequency
Figure 26. Threshold Voltage (VT) vs. Temperature
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
T
T
V
V
= 25°C
= +15V
A
SOURCE
DD
= –15V
SS
V
DD
2
DRAIN
10k
100k
1M
10M
100M
CH1 5.00V CH2 5.00V
CH3 5.00V
M400ns
–10.00ns
A
CH2
10.1V
T
FREQUENCY (Hz)
Figure 27. Drain Output Response to Positive Overvoltage
(DR Pin = Floating or High)
Figure 24. Bandwidth vs. Frequency
Rev. B | Page 18 of 30
Data Sheet
ADG5436F
24
20
16
12
8
T
V
V
= 25°C
A
= +10V
= –10V
DD
SS
DRAIN
1
DISTORTIONLESS
OPERATING
REGION
V
SS
4
SOURCE
0
1
10
FREQUENCY (MHz)
100
CH1 5.00V CH2 5.00V
CH3 5.00V
M400ns
–10.00ns
A
CH2
–14.7V
T
Figure 28. Drain Output Response to Negative Overvoltage
(DR Pin = Floating or High)
Figure 29. Large Signal Voltage Tracking vs. Frequency
Rev. B | Page 19 of 30
ADG5436F
Data Sheet
TEST CIRCUITS
V
V
DD
SS
0.1µF
0.1µF
NETWORK
ANALYZER
V
V
DD
SS
V
OUT
SxA
R
L
50Ω
Dx
R
L
50Ω
SxB
V
V
S
GND
Sxx
Dx
V
I
OUT
DS
V
S
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
V
R
= V/I
DS
S
ON
Figure 30. On Resistance
Figure 34. Channel-to-Channel Crosstalk
I
(OFF)
S
SxA
SxB
I
(OFF)
A
D
A
Dx
I
I
D
S
A
Sxx
Dx
A
A
R
10kΩ
L
V
V
D
S
|V | > |V | OR |V
DD
|
SS
S
Figure 35. Switch Overvoltage Leakage
Figure 31. Off Leakage
SxA
I
(ON)
A
D
NC
V
= V = GND = 0V
SS
DD
Dx
I
I
D
S
SxB
A
Sxx
Dx
A
A
I
(OFF)
S
R
10kΩ
V
D
L
V
S
V
S
Figure 32. Channel On Leakage
Figure 36. Switch Unpowered Leakage
V
V
DD
SS
V
V
SS
DD
0.1µF
0.1µF
0.1µF
0.1µF
NETWORK
ANALYZER
NETWORK
ANALYZER
V
V
DD
SS
V
V
DD
SS
Sxx
50Ω
Sxx
INx
IN
50Ω
V
S
INx
IN
V
S
Dx
V
Dx
OUT
V
R
V
OUT
L
50Ω
V
R
L
50Ω
GND
GND
V
OUT
V
WITH SWITCH
OFF ISOLATION = 20 log
OUT
V
S
INSERTION LOSS = 20 log
V
WITHOUT SWITCH
OUT
Figure 37. Bandwidth
Figure 33. Off Isolation
Rev. B | Page 20 of 30
Data Sheet
ADG5436F
V
V
SS
DD
0.1µF
0.1µF
AUDIO
PRECISION
V
V
DD
SS
R
S
Sxx
V
INx
S
V p-p
Dx
V
OUT
V
IN
R
L
10kΩ
GND
Figure 38. THD + N
V
V
V
V
DD
SS
0.1µF
0.1µF
V
+ 0.5V
DD
DD
SS
SOURCE
SxA
SxB
VOLTAGE
Dx
(V )
S
V
D
V
S
R
C *
L
0V
L
1kΩ
2pF
tRESPONSE
INx
2.4V
V
× 0.9V
DD
OUTPUT
GND
(V
)
D
0V
*INCLUDES TRACK CAPACITANCE
Figure 39. Overvoltage Response Time, tRESPONSE
V
V
V
DD
SS
SS
0.1µF
0.1µF
V
+ 0.5V
DD
SOURCE
V
DD
VOLTAGE
(V
)
S
SxA
SxB
0V
Dx
V
D
V
S
R
1kΩ
C *
L
2pF
L
tRECOVERY
INx
2.4V
OUTPUT
(V
)
D
V
× 1
0V
DD
GND
*INCLUDES TRACK CAPACITANCE
Figure 40. Overvoltage Recovery Time, tRECOVERY
Rev. B | Page 21 of 30
ADG5436F
Data Sheet
V
V
V
V
DD
SS
0.1µF
0.1µF
V
+ 0.5V
DD
DD
SS
SOURCE
S1A
VOLTAGE
(V
)
S
V
S
0V
ADG5436F
tDIGRESP
S1B
FF
C *
L
12pF
D1
OUTPUT
(V
)
GND
FF
0.1V
OUT
0V
*INCLUDES TRACK CAPACITANCE
Figure 41. Interrupt Flag Response Time, tDIGRESP
V
V
DD
SS
SS
0.1µF
0.1µF
V
+ 0.5V
V
V
DD
DD
S1A
SOURCE
VOLTAGE
V
S
(V )
S
ADG5436F
0V
S1B
FF
tDIGREC
C *
L
12pF
D1
0.9V
OUT
OUTPUT
GND
(V
)
FF
0V
*INCLUDES TRACK CAPACITANCE
Figure 42. Interrupt Flag Recovery Time, tDIGREC
V
V
V
V
DD
DD
SS
SS
0.1µF
0.1µF
V
+ 0.5V
DD
SOURCE
S1A
VOLTAGE
(V )
S
V
S
5V
0V
ADG5436F
R
PULLUP
1kΩ
tDIGREC
S1B
OUTPUT
FF
5V
C *
L
12pF
D1
3V
OUTPUT
GND
(V
)
FF
0V
*INCLUDES TRACK CAPACITANCE
Figure 43. Interrupt Flag Recovery Time, tDIGREC, with a 1 kΩ Pull-Up Resistor
Rev. B | Page 22 of 30
Data Sheet
ADG5436F
V
V
V
DD
SS
0.1µF
0.1µF
V
IN
V
DD
SS
SxB
SxA
V
S
Dx
V
OUT
80%
V
R
C
OUT
L
L
35pF
300Ω
INx
tD
tD
GND
V
IN
Figure 44. Break-Before-Make Time Delay, tD
V
V
V
V
DD
SS
0.1µF
0.1µF
3V
DD
SS
V
IN
50%
50%
INx
SxB
V
S
SxA
0V
tON (EN)
tOFF (EN)
0.9V
Dx
V
EN
OUT
OUT
V
V
OUT
35pF
IN
50Ω
300Ω
GND
0.1V
OUT
Figure 45. Enable Delay, tON (EN), tOFF (EN)
V
V
V
DD
SS
0.1µF
0.1µF
V
DD
SS
SxB
SxA
V
V
Dx
IN
S
50%
50%
V
OUT
R
300Ω
C
35pF
L
L
90%
INx
V
OUT
10%
GND
V
IN
tON
tOFF
Figure 46. Address to Output Switching Times, tTRANSITION
V
V
DD
SS
0.1µF
0.1µF
V
V
SS
DD
SxB
NC
V
Dx
V
S
V
V
IN
OUT
SxA
C
1nF
INx
L
ΔV
OUT
OUT
V
IN
GND
Q
= C × ΔV
L
OUT
INJ
Figure 47. Charge Injection, QINJ
Rev. B | Page 23 of 30
ADG5436F
Data Sheet
TERMINOLOGY
IDD
tOFF
OFF represents the delay between applying the digital control
I
DD represents the positive supply current.
t
input and the output switching off (see Figure 45).
ISS
I
SS represents the negative supply current.
tD
tD represents the off time measured between the 90% point of
both switches when switching from one address state to
another.
VD, VS
VD and VS represent the analog voltage on the Dx pins and the
Sxx pins, respectively.
tDIGRESP
RON
tDIGRESP is the time required for the FF pin to go low (0.3 V),
measured with respect to the voltage on the source pin
exceeding the supply voltage by 0.5 V.
R
ON represents the ohmic resistance between the Dx pins and
the Sxx pins.
∆RON
tDIGREC
∆RON represents the difference between the RON of any two
channels.
tDIGREC is the time required for the FF pin to return high,
measured with respect to the voltage on the Sxx pin falling
below the supply voltage plus 0.5 V.
RFLAT(ON)
RFLAT(ON) is the flatness defined as the difference between the
maximum and minimum value of on resistance measured over
the specified analog signal range.
tRESPONSE
tRESPONSE represents the delay between the source voltage
exceeding the supply voltage by 0.5 V and the drain voltage
falling to 90% of the supply voltage.
IS (Off)
IS (Off) is the source leakage current with the switch off.
tRECOVERY
ID (Off)
tRECOVERY represents the delay between an overvoltage on the
ID (Off) is the drain leakage current with the switch off.
Sxx pin falling below the supply voltage plus 0.5 V and the drain
voltage rising from 0 V to 10% of the supply voltage.
ID (On), IS (On)
ID (On) and IS (On) represent the channel leakage currents with
the switch on.
Off Isolation
Off isolation is a measure of unwanted signal coupling through
an off switch.
VINL
V
INL is the maximum input voltage for Logic 0.
VINH
INH is the minimum input voltage for Logic 1.
INL, IINH
INL and IINH represent the low and high input currents of the
Charge Injection
Charge injection is a measure of the glitch impulse transferred
from the digital input to the analog output during switching.
V
I
I
Channel-to-Channel Crosstalk
Channel-to-channel crosstalk is a measure of unwanted signal
that is coupled through from one channel to another as a result
of parasitic capacitance.
digital inputs.
CD (Off)
CD (Off) represents the off switch drain capacitance, which is
measured with reference to ground.
−3 dB Bandwidth
−3 dB bandwidth is the frequency at which the output is
attenuated by 3 dB.
CS (Off)
CS (Off) represents the off switch source capacitance, which is
measured with reference to ground.
On Response
On response is the frequency response of the on switch.
CD (On), CS (On)
Insertion Loss
CD (On) and CS (On) represent on switch capacitances, which
are measured with reference to ground.
Insertion loss is the loss due to the on resistance of the switch.
Total Harmonic Distortion Plus Noise (THD + N)
THD + N is the ratio of the harmonic amplitude plus noise of
the signal to the fundamental.
CIN
C
IN is the digital input capacitance.
tON
tON represents the delay between applying the digital control
input and the output switching on (see Figure 45).
Rev. B | Page 24 of 30
Data Sheet
ADG5436F
AC Power Supply Rejection Ratio (ACPSRR)
VT
ACPSRR is the ratio of the amplitude of the signal on the output
to the amplitude of the modulation. ACPSRR is a measure of
the ability of the device to avoid coupling noise and spurious
signals that appear on the supply voltage pin to the output of the
switch. The dc voltage on the device is modulated by a sine wave
of 0.62 V p-p.
VT is the voltage threshold at which the overvoltage protection
circuitry engages (see Figure 26).
Rev. B | Page 25 of 30
ADG5436F
Data Sheet
THEORY OF OPERATION
During overvoltage conditions, the leakage current into and out
of the source pins (Sxx) is limited to tens of microamperes. If the
DR pin is allowed to float or is driven high, only nanoamperes of
leakage are seen on the drain pin (Dx). If the DR pin is driven
low, the drain pin (Dx) is pulled to the rail. The device that pulls
the drain pin to the rail has an impedance of approximately 40 kΩ;
therefore, the Dx pin current is limited to about 1 mA during a
shorted load condition. This internal impedance also determines
the minimum external load resistance required to ensure that the
drain pin is pulled to the desired voltage level during a fault.
SWITCH ARCHITECTURE
Each channel of the ADG5436F consists of a parallel pair of
NDMOS and PDMOS transistors. This construction provides
excellent performance across the signal range. The ADG5436F
channels operate as standard switches when input signals with a
voltage between VSS and VDD are applied. For example, the on
resistance is 10 Ω typically and the appropriate control pin, INx,
controls the opening or closing of the switch.
Additional internal circuitry enables the switch to detect
overvoltage inputs by comparing the voltage on the source pin
with VDD and VSS. A signal is considered overvoltage if it
exceeds the supply voltages by the voltage threshold, VT. The
threshold voltage is typically 0.7 V, but can range from 0.8 V at
−40°C down to 0.6 V at +125°C. See Figure 26 to see the change
in VT with operating temperature.
When an overvoltage event occurs, the channels undisturbed by
the overvoltage input continue to operate normally without
additional crosstalk.
ESD Performance
The ADG5436F has an ESD (HBM) rating of 6 kV.
The drain pins (Dx) have ESD protection diodes to the supply
rails, and the voltage at these pins must not exceed the supply
voltage.
The maximum voltage that can be applied to any source input is
−55 V or +55 V. When the device is powered using a single
supply of greater than 25 V, the maximum undervoltage signal
level reduces down from −55 V. For example, the undervoltage
signal reduces to −40 V at VDD = 40 V to remain within the 80 V
maximum rating. The construction of the process allows the
channel to withstand 80 V across the switch when it is opened.
These overvoltage limits apply whether the power supplies are
present or not.
The source pins (Sxx) have specialized ESD protection that allows
the signal voltage to reach 55 V with a 22 V dual supply, and
from −40 V to +55 V with a +40 V single supply. See Figure 48
for the switch channel overview. Exceeding 55 V on any source
input may damage the ESD protection circuitry on the device.
Trench Isolation
V
DD
ESD
PROTECTION
In the ADG5436F, an insulating oxide layer (trench) is placed
between the NDMOS and the PDMOS transistors of each switch.
Parasitic junctions, which occur between the transistors in
junction isolated switches, are eliminated, and the result is a
switch that is latch-up immune under all circumstances. This
device passes a JESD78D latch-up test of 500 mA for 1 sec, the
strictest test in the specification.
ESD
DIODE
Sxx
Dx
ESD
DIODE
FAULT
DETECTOR
SWITCH
DRIVER
V
SS
LOGIC
BLOCK
DR
Figure 48. Switch Channel and Control Function
NDMOS
PDMOS
When an overvoltage condition is detected on a source pin
(Sxx), the switch automatically opens and the source pin (Sxx)
becomes high impedance and ensures that no current flows
through the switch. If the DR pin is driven low, the drain pin,
Dx, is pulled to the supply that was exceeded. For example, if
the source voltage exceeds VDD, the drain output pulls to VDD
.
The same is true for VSS. If the DR pin is allowed to float or is
driven high, the Dx pin also becomes open circuit. The voltage
on the Dx pin follows the voltage on the source pin, Sxx, until the
switch turns off completely and the drain voltage discharges
through the load. The maximum voltage on the drain is limited
by the internal ESD diodes and the rate at which the output
voltage discharges is dependent on the load at the pin.
P-WELL
N-WELL
TRENCH
BURIED OXIDE LAYER
HANDLE WAFER
Figure 49. Trench Isolation
Rev. B | Page 26 of 30
Data Sheet
ADG5436F
+22V
V
0V
–22V
FAULT PROTECTION
When the voltages at the source inputs exceed VDD or VSS by VT,
the switch turns off, or, if the device is unpowered, the switch
remains off. The switch input remains high impedance regardless
of the digital input state or the load resistance, and the output
acts as a virtual open circuit. Signal levels up to +55 V and −55 V
are blocked in both the powered and unpowered conditions as long
as the 80 V limitation between the source and supply pins is met.
GND
V
SS
DD
ADG5436F
+22V S1A
D1
S2A +22V
D2
–55V S1B
S2B +55V
Power-On Protection
FAULT
DETECTION
+
SF
3V
The following three conditions must be satisfied for the switch
to be in the on condition:
FF
0V
SWITCH DRIVER
•
•
•
VDD to VSS ≥ 8 V.
The input signal is between VSS − VT and VDD + VT.
The digital logic control input, INx, is turned on.
F1
F2
EN DR
5V
Figure 50. ADG5436F Under Example Overvoltage Conditions
Power-Off Protection
When the switch is turned on, the signal levels up to the supply
rails are passed.
When no power supplies are present, the switch remains in the off
condition, and the switch inputs are high impedance. This state
ensures that no current flows and prevents damage to the switch or
downstream circuitry. The switch output is a virtual open circuit.
The switch responds to an analog input that exceeds VDD or VSS by a
threshold voltage, VT, by turning off. The absolute input voltage
limits are −55 V and +55 V, while maintaining an 80 V limit
between the source pin and the supply rails. The switch remains off
until the voltage at the source pin returns to between VDD and VSS.
The switch remains off regardless of whether the VDD and VSS
supplies are 0 V or floating. A GND reference must always be
present to ensure proper operation. Signal levels of up to 55 V
are blocked in the unpowered condition.
The fault response time (tRESPONSE) when powered by a 15 V
dual supply is typically 510 ns, and the fault recovery time
(tRECOVERY) is 820 ns. These vary with supply voltages and output
load conditions.
Digital Input Protection
The ADG5436F can tolerate unpowered digital input signals
present on the device. When the device is unpowered, the switch
is guaranteed to be in the off state, regardless of the state of the
digital logic signals.
Exceeding 55 V on any source input may damage the ESD
protection circuitry on the device.
The maximum stress across the switch channel is 80 V.
Therefore, the user must pay close attention to this limit when
using the device with a 40 V single supply. In this case, the
maximum undervoltage condition is −40 V to maintain the
80 V across the switch channel.
The digital inputs are protected against positive faults up to
44 V. The digital inputs do not offer protection against negative
overvoltages. ESD protection diodes connected to GND are
present on the digital inputs.
Overvoltage Interrupt Flag
For undervoltage and overvoltage conditions, consider the case
where the device is set up as shown in Figure 50.
The voltages on the source inputs of the ADG5436F are
continuously monitored, and the state of the switches is
indicated by an active low digital output pin, FF.
•
•
V
DD/VSS = 22 V.
S1A and S2A = 22 V, and are both on. Therefore, D1 and
D2 = 22 V.
The voltage on the FF pin indicates if any of the source input
pins are experiencing a fault condition. The output of the FF pin
is a nominal 3 V when all source pins are within normal
operating range. If any source pin voltage exceeds the supply
voltage by VT, the FF output reduces to below 0.8 V.
•
•
•
S1B has a −55 V fault and S2B has a +55 V fault.
The voltage between S1B and D1 = 22 V − (−55 V) = +77 V.
The voltage between S2B and D2= 22 V− 55 V = -33 V.
These calculations are all within device specifications: a 55 V
maximum fault on source inputs and a maximum of 80 V
across the off switch channel.
Use the specific fault digital output pin, SF, to decode which
inputs are experiencing a fault condition. The SF pin reduces to
below 0.8 V when a fault condition is detected on a specific pin,
depending on the state of F1 and F2 (see Table 9). The specific
fault feature also works with the switches disabled (EN pin low),
which allows the user to cycle through and check the fault
conditions without connecting the fault to the drain output.
FF is low due to the fault conditions. The specific switches in
fault can be deduced by cycling through F2 and F1 and noting
the state of SF. In this example, SF is low (asserted) when F2 = 0
and F1 = 1; it is also low when F2 = 1 and F1 = 0. This signifies
a fault on S1B and S2B. See Table 9 for details on how to decode
SF by F2 and F1.
Rev. B | Page 27 of 30
ADG5436F
Data Sheet
APPLICATIONS INFORMATION
The overvoltage protected family of switches and multiplexers
provide a robust solution for instrumentation, industrial,
aerospace, and other harsh environments where overvoltage
signals can be present and the system must remain operational
both during and after the overvoltage has occurred.
LOW IMPEDANCE CHANNEL PROTECTION
The ADG5436F can be used as a protective element in signal
chains that are sensitive to both channel impedance and
overvoltage signals. Traditionally, series resistors limit the
current during an overvoltage condition to protect susceptible
components.
POWER SUPPLY RAILS
To guarantee correct operation of the device, 0.1 µF decoupling
capacitors are required.
These series resistors affect the performance of the signal chain
and reduce the signal chain precision. A compromise must be
reached on the value of the series resistance that is high enough
to sufficiently protect sensitive components, but low enough
that the precision performance of the signal chain is not
sacrificed.
The ADG5436F can operate with bipolar supplies between 5 V
and 22 V. The supplies on VDD and VSS do not need to be
symmetrical, but the VDD to VSS range must not exceed 44 V.
The ADG5436F can also operate with single supplies between
8 V and 44 V, with VSS connected to GND.
The ADG5436F enables the designer to remove these resistors
and retain precision performance without compromising the
protection of the circuit.
The ADG5436F is fully specified at the 15 V, 20 V, 12 V, and
+36 V supply ranges.
POWER SUPPLY RECOMMENDATIONS
POWER SUPPLY SEQUENCING PROTECTION
Analog Devices, Inc., has a wide range of power management
products to meet the requirements of most high performance
signal chains.
The switch channel remains open when the device is
unpowered and signals from −55 V to +55 V can be applied
without damaging the device. The switch channel closes only
when the supplies are connected, a suitable digital control signal
is placed on the INx pins, and the signal is within the normal
operating range. Placing the ADG5436F between external
connectors and sensitive components offers protection in systems
where a signal is presented to the source pins before the supply
voltages are available.
An example of a bipolar power solution is shown in Figure 51.
The ADP7118 and ADP7182 can be used to generate clean positive
and negative rails from the dual switching regulator output. These
rails can be used to power the ADG5436F, amplifier, and/or
precision converter in a typical signal chain.
+16V
ADP7118
LDO
+15V
DUAL
SWITCHING
REGULATOR
SIGNAL RANGE
12V
INPUT
–16
V
The ADG5436F has overvoltage detection circuitry on the
inputs that compares the voltage levels at the source terminals
with VDD and VSS. To protect downstream circuitry from
overvoltage conditions, supply the ADG5436F with voltages
that match the intended signal range. The low on-resistance
switch allows signals to the supply rails to be passed with very
little distortion. A signal that exceeds the supply rail by the
threshold voltage is then blocked. This signal block offers
protection to both the device and any downstream circuitry.
ADP7182
LDO
–15V
Figure 51. Bipolar Power Solution
Table 10. Recommended Power Management Devices
Product Description
ADP7118 20 V, 200 mA, low noise, CMOS LDO
ADP7142 40 V, 200 mA, low noise, CMOS LDO
ADP7182 −28 V, −200 mA, low noise, linear regulator
HIGH VOLTAGE SURGE SUPPRESSION
The ADG5436F is not intended for use in very high voltage
applications. The maximum operating voltage of the transistor
is 80 V. In applications where the inputs are likely to be subject
to overvoltage conditions exceeding the breakdown voltage, use
transient voltage suppressors (TVSs) or similar devices.
Rev. B | Page 28 of 30
Data Sheet
ADG5436F
The recovery time, tDIGREC, can be decreased from a typical 60 µs
to 600 ns by using a 1 kΩ pull-up resistor.
INTELLIGENT FAULT DETECTION
The ADG5436F digital output pin, FF, can interface with a
microprocessor or control system and can be used as an
interrupt flag. This feature provides real-time diagnostic
information on the state of the device and the system to
which it connects.
The specific fault digital output, SF decodes which inputs are
experiencing a fault condition. The SF pin reduces to below
0.8 V when a fault condition is detected on a specific pin,
depending on the state of F1 and F2 (see Table 9). The specific
fault feature also works with the switches disabled (EN pin low),
which allows the user to cycle through and check the fault
conditions without connecting the fault to the drain output.
The control system can use the digital interrupt, FF, to start a
variety of actions, as follows:
•
•
•
Initiating an investigation into the source of an overvoltage
fault.
Shutting down critical systems in response to the overvoltage
condition.
Using data recorders to mark data during these events as
unreliable or out of specification.
LARGE VOLTAGE, HIGH FREQUENCY SIGNALS
Figure 29 shows the voltage range and frequencies that the
ADG5436F can reliably convey. For signals extending across the
full signal range from VSS to VDD, keep the frequency below 3 MHz.
If the required frequency is greater than 3 MHz, decrease the signal
range appropriately to ensure signal integrity.
For systems sensitive during a start-up sequence, the active low
operation of the flag allows the system to ensure that the
ADG5436F is powered on and that all input voltages are within
the normal operating range before initiating operation.
The FF pin is a weak pull-up, which allows the signals to
combine into a single interrupt for larger modules that contain
multiple devices.
Rev. B | Page 29 of 30
ADG5436F
Data Sheet
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 52. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
4.10
4.00 SQ
3.90
0.35
0.30
0.25
PIN 1
INDICATOR
PIN 1
INDICATOR
13
16
0.65
BSC
12
1
EXPOSED
PAD
2.70
2.60 SQ
2.50
4
9
8
5
0.45
0.40
0.35
0.20 MIN
TOP VIEW
BOTTOM VIEW
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGC.
Figure 53. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-16-17)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
Package Option
RU-16
RU-16
ADG5436FBRUZ
ADG5436FBRUZ-RL7
ADG5436FBCPZ-RL7
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
CP-16-17
1 Z = RoHS Compliant Part.
©2015–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12882-0-1/16(B)
Rev. B | Page 30 of 30
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