ADG3241BKSZ [ADI]
3241 SERIES, 1-BIT DRIVER, TRUE OUTPUT, PDSO6;
| 型号： | ADG3241BKSZ |
| 厂家： | 
ADI |
| 描述： | 3241 SERIES, 1-BIT DRIVER, TRUE OUTPUT, PDSO6 驱动 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总16页 (文件大小：306K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2.5 V/3.3 V, 1-Bit, 2-Port
Level Translator Bus Switch in SOT-66
ADG3241
FUNCTIONAL BLOCK DIAGRAM
FEATURES
225 ps propagation delay through the switch
4.5 Ω switch connection between ports
Data rate 1.5 Gbps
A
B
2.5 V/3.3 V supply operation
Selectable level shifting/translation
Level translation
BE
Figure 1.
3.3 V to 2.5 V
3.3 V to 1.8 V
2.5 V to 1.8 V
Small signal bandwidth 770 MHz
Tiny 6-lead SC70 package and 6-lead SOT-66 package
APPLICATIONS
3.3 V to 1.8 V voltage translation
3.3 V to 2.5 V voltage translation
2.5 V to 1.8 V voltage translation
Bus switching
Bus isolation
Hot swap
Hot plug
Analog switch applications
GENERAL DESCRIPTION
SEL
SEL
is low, VCC is
translating select pin (
) is included. When
The ADG3241 is a 2.5 V or 3.3 V single digital switch. It is
designed on a low voltage CMOS process that provides low
power dissipation yet gives high switching speed and very low
on resistance. This allows the input to be connected to the
output without additional propagation delay or generating
additional ground bounce noise.
reduced internally, allowing for level translation between 3.3 V
inputs and 1.8 V outputs. This makes the device suited to
applications requiring level translation between different
supplies, such as converter to DSP/microcontroller interfacing.
PRODUCT HIGHLIGHTS
BE
The switch is enabled by means of the bus enable ( ) input
1. 3.3 V or 2.5 V supply operation.
signal. This digital switch allows a bidirectional signal to be
switched when on. In the off condition, signal levels up to the
supplies are blocked.
2. Extremely low propagation delay through switch.
3. 4.5 Ω switches connect inputs to outputs.
4. Level and voltage translation.
This device is ideal for applications requiring level translation.
When operated from a 3.3 V supply, level translation from 3.3 V
inputs to 2.5 V outputs is allowed. Similarly, if the device is
operated from a 2.5 V supply and 2.5 V inputs are applied, the
device translates the outputs to 1.8 V. In addition to this, a level
5. Tiny, SC70 package and SOT-66 package.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
ADG3241
TABLE OF CONTENTS
Features .............................................................................................. 1
Timing Measurement Information.............................................. 11
Bus Switch Applications ................................................................ 12
Mixed Voltage Operation, Level Translation.......................... 12
3.3 V to 2.5 V Translation ......................................................... 12
2.5 V to 1.8 V Translation ......................................................... 12
3.3 V to 1.8 V Translation ......................................................... 12
Bus Isolation................................................................................ 13
Hot Plug and Hot Swap Isolation............................................. 13
Analog Switching ....................................................................... 13
High Impedance During Power-Up/Power-Down................ 13
Outline Dimensions....................................................................... 14
Ordering Guide .......................................................................... 14
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Typical Performance Characteristics ............................................. 6
Terminology .................................................................................... 10
REVISION HISTORY
Changes to Absolute Maximum Ratings........................................3
Changes to Pin Configurations .......................................................4
Changes to Ordering Guide.............................................................4
Updated Outline Dimensions....................................................... 11
5/06 — Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to Table 4............................................................................ 5
Changes to Ordering Guide ......................................................... 14
7/03—Revision 0: Initial Version
10/04 — Rev. 0 to Rev. A.
Changes to Features.......................................................................... 1
Changes to Specifications................................................................ 2
Rev. B | Page 2 of 16
ADG3241
SPECIFICATIONS
VCC = 2.3 V to 3.6 V, GND = 0 V, all specifications TMIN to TMAX, unless otherwise noted.1
Table 1.
B Version
Typ2
Parameter
Symbol
Conditions
Min
Max
Unit
DC ELECTRICAL CHARACTERISTICS
Input High Voltage
VINH
VINH
VINL
VINL
II
VCC = 2.7 V to 3.6 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 2.3 V to 2.7 V
2.0
1.7
V
V
V
V
μA
μA
μA
V
Input Low Voltage
0.8
0.7
1
1
1
2.7
2.1
2.1
Input Leakage Current
Off State Leakage Current
On State Leakage Current
Maximum Pass Voltage
0.01
0.01
0.01
2.5
IOZ
0 ≤ A, B ≤ VCC
0 ≤ A, B ≤ VCC
VA/VB = VCC = SEL = 3.3 V, IO = −5 μA
VA/VB = VCC = SEL = 2.5 V, IO = −5 μA
VA/VB = VCC = 3.3 V, SEL = 0 V, IO = −5 μA
VP
2.2
1.5
1.5
1.8
V
1.8
V
CAPACITANCE3
A Port Off Capacitance
B Port Off Capacitance
CA OFF
CB OFF
CA, CB ON
CIN
f = 1 MHz
f = 1 MHz
f = 1 MHz
f = 1 MHz
3.5
3.5
7
pF
pF
pF
pF
A, B Port On Capacitance
Control Input Capacitance
SWITCHING CHARACTERISTICS3
Propagation Delay A to B or B to A, tPD
Bus Enable Time BE to A or B5
Bus Disable Time BE to A or B5
Bus Enable Time BE to A or B5
Bus Disable Time BE to A or B5
Bus Enable Time BE to A or B5
Bus Disable Time BE to A or B5
Maximum Data Rate
4
4
tPHL, tPLH
tPZH, tPZL
tPHZ, tPLZ
tPZH, tPZL
tPHZ, tPLZ
tPZH, tPZL
tPHZ, tPLZ
CL = 50 pF, VCC = SEL = 3 V
VCC = 3.0 V to 3.6 V; SEL = VCC
VCC = 3.0 V to 3.6 V; SEL = VCC
VCC = 3.0 V to 3.6 V; SEL = 0 V
VCC = 3.0 V to 3.6 V; SEL = 0 V
VCC = 2.3 V to 2.7 V; SEL = VCC
VCC = 2.3 V to 2.7 V; SEL = VCC
VCC = SEL = 3.3 V; VA/VB = 2 V
VCC = SEL = 3.3 V; VA/VB = 2 V
0.225 ns
1
1
1
1
1
1
3.2
3
4.6
4
ns
ns
3
4
ns
2.5
3
3.8
4
ns
ns
2.5
1.5
45
3.4
ns
Gbps
ps p-p
Channel Jitter
DIGITAL SWITCH
On Resistance
RON
VCC = 3 V, SEL = VCC, VA = 0 V, IBA = 8 mA
VCC = 3 V, SEL = VCC, VA = 1.7 V, IBA = 8 mA
VCC = 2.3 V, SEL = VCC, VA = 0 V, IBA = 8 mA
VCC = 2.3 V, SEL = VCC, VA = 1 V, IBA = 8 mA
VCC = 3 V, SEL = 0 V, VA = 0 V, IBA = 8 mA
VCC = 3 V, SEL = 0 V, VA = 1 V, IBA = 8 mA
4.5
12
5
8
Ω
Ω
Ω
Ω
Ω
Ω
28
9
9
18
8
5
12
POWER REQUIREMENTS
VCC
Quiescent Power Supply Current
2.3
3.6
1
V
ICC
Digital Inputs = 0 V or VCC; SEL = VCC
Digital Inputs = 0 V or VCC; SEL = 0 V
VCC = 3.6 V, BE = 3.0 V; SEL = VCC
0.01
0.1
μA
mA
μA
0.2
8
Increase in ICC per Input6
∆ICC
0.15
1 Temperature range is as follows: B Version: −40°C to +85°C.
2 Typical values are at 25°C, unless otherwise stated.
3 Guaranteed by design, not subject to production test.
4 The digital switch contributes no propagation delay other than the RC delay of the typical RON of the switch and the load capacitance when driven by an ideal voltage
source. Since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay
of the digital switch, when used in a system, is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side.
5 See Timing Measurement Information section.
6
BE
This current applies to the Control Pin only. The A and B ports contribute no significant ac or dc currents as they transition.
Rev. B | Page 3 of 16
ADG3241
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 2.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
VCC to GND
Digital Inputs to GND
DC Input Voltage
DC Output Current
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Junction Temperature
SC70 Package
−0.5 V to +4.6 V
−0.5 V to +4.6 V
−0.5 V to +4.6 V
25 mA per channel
Only one absolute maximum rating can be applied at any one
time.
−40°C to +85°C
−65°C to +150°C
150°C
θJA Thermal Impedance
SOT-66 Package
332°C/W
θJA Thermal Impedance
191°C/W (4-layer board)
Lead Temperature, Soldering (10 sec) 300°C
IR Reflow, Peak Temperature
(<20 sec)
235°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. B | Page 4 of 16
ADG3241
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
BE
GND
A
1
2
3
6
5
4
SEL
V
1
2
3
6
5
4
CC
BE
B
ADG3241
V
ADG3241
TOP VIEW
(Not to Scale)
TOP VIEW
CC
SEL
A
(Not to Scale)
GND
B
Figure 3. 6-Lead SOT-66
Figure 2. 6-Lead SC70
Table 3. Pin Function Descriptions
Pin No.
SC70
SOT-66
Mnemonic
Description
BE
1
2
3
4
5
6
6
4
3
5
1
2
Bus Enable (Active Low)
Ground Reference
Port A, Input or Output
Port B, Input or Output
Positive Power Supply Voltage
Level Translation Select
GND
A
B
VCC
SEL
Table 4. Truth Table
BE
SEL1
Function
L
L
H
L
H
X
A = B, 3.3 V to 1.8 V level shifting
A = B, 3.3 V to 2.5 V/2.5 V to 1.8 V level shifting
Disconnect
1 SEL
= 0 V only when VDD = 3.3 V 10ꢀ.
Rev. B | Page 5 of 16
ADG3241
TYPICAL PERFORMANCE CHARACTERISTICS
40
20
15
10
V
= 3.3V
CC
T
= 25°C
A
35
30
25
20
SEL = V
CC
SEL = V
CC
V
= 3V
CC
V
= 3.3V
CC
V
= 3.6V
+85°C
CC
15
10
5
+25°C
5
0
–40°C
0
1.0
/V (V)
2.0
0
0.5
1.0
1.5
V
2.0
/V (V)
2.5
3.0
3.5
0
0.5
1.5
V
A
B
A
B
Figure 4. On Resistance vs. Input Voltage
Figure 7. On Resistance vs. Input Voltage for Different Temperatures
40
35
30
25
20
15
15
T
= 25°C
A
V
= 2.5V
CC
SEL = V
CC
SEL = V
CC
10
+85°C
V
= 2.3V
= 2.5V
CC
–40°C
5
V
CC
10
+25°C
V
= 2.7V
CC
5
0
0
1.0
0
0.5
1.0
1.5
/V (V)
2.0
2.5
3.0
0
0.5
1.2
V
V
/V (V)
B
A
B
A
Figure 5. On Resistance vs. Input Voltage
Figure 8. On Resistance vs. Input Voltage for Different Temperatures
40
35
30
25
20
15
10
5
3.0
V
= 3.6V
CC
T
= 25°C
T = 25°C
A
A
SEL = 0V
SEL = V
CC
2.5
2.0
1.5
I
= –5µA
O
V
= 3V
CC
V
= 3.3V
CC
V
= 3V
V
= 3.3V
CC
CC
V
= 3.6V
CC
1.0
0.5
0
0
0
0.5
1.0
1.5
V
2.0
2.5
3.0
3.5
0
0.5
1.0
1.5
V
2.0
/V (V)
2.5
3.0
3.5
/V (V)
A
B
A
B
Figure 6. On Resistance vs. Input Voltage
Figure 9. Pass Voltage vs. VCC
Rev. B | Page 6 of 16
ADG3241
3.0
2.5
2.0
1.5
2.5
2.0
1.5
T
= 25°C
T
= 25°C
V = 0V
A
A
A
V
= 2.7V
SEL = V
CC
CC
I
= –5µA
BE = 0
O
V
= 3.3V; SEL = 0V
CC
V
= 2.5V
CC
V
= 2.3V
CC
V
= SEL = 3.3V
CC
1.0
0.5
0
1.0
0.5
0
V
= SEL = 2.5V
0.08 0.10
CC
0
0.02
0.04
I
0.06
0
0.5
1.0
1.5
/V (V)
2.0
2.5
3.0
(A)
V
O
A
B
Figure 10. Pass Voltage vs. VCC
Figure 13. Output Low Characteristic
2.5
2.0
1.5
1.0
3.0
2.5
T
= 25°C
A
T
V
= 25°C
= V
CC
A
V
= 3.6V
SEL = 0V
= –5µA
CC
A
I
O
BE = 0
2.0
1.5
V
= SEL = 3.3V
CC
V
= 3.3V
CC
V
= 3V
CC
1.0
0.5
0
V
= SEL = 2.5V
CC
0.5
0
V
= 3.3V; SEL = 0V
–0.08
CC
–0.10
–0.06
–0.04
–0.02
0
0
0.5
1.0
1.5
2.0
/V (V)
2.5
3.0
3.5
I
(A)
O
V
A
B
Figure 14. Output High Characteristic
Figure 11. Pass Voltage vs. VCC
0
500
450
400
350
300
250
T
= 25°C
T = 25°C
A
A
SEL = V
CC
V
= 2.5V
CC
–0.2
ON→OFF
= 1nF
C
L
–0.4
–0.6
–0.8
V
= SEL = 3.3V
CC
V
= 3.3V; SEL = 0V
V
= 3.3V
CC
CC
200
150
100
50
–1.0
–1.2
V
= SEL = 2.5V
CC
0
0
0.5
1.0
1.5
2.0
2.5
3.0
0
5
10
15
20
25
30
35
40
45
50
V
/V (V)
B
A
ENABLE FREQUENCY (MHz)
Figure 15. Charge Injection vs. Source Voltage
Figure 12. ICC vs. Enable Frequency
Rev. B | Page 7 of 16
ADG3241
4.0
3.5
2
1
0
–1
–2
–3
ENABLE
DISABLE
3.0
2.5
V
= SEL = 2.5V
CC
2.0
1.5
1.0
0.5
0
T
V
= 25°C
A
–4
= 3.3V/2.5V
CC
–5
–6
SEL = V
V
CC
= 0dBm
IN
N/W ANALYZER:
= R = 50Ω
R
L
S
–7
–8
–40
–20
0
20
40
60
80
0.03
0.1
1
10
100
1000
1000
80
TEMPERATURE (°C)
FREQUENCY (MHz)
Figure 19. Enable/Disable Time vs. Temperature
Figure 16. Bandwidth vs. Frequency
100
90
80
70
60
50
40
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
T
V
= 25°C
A
V
V
= SEL = 3.3V
= 1.5V p-p
CC
= 3.3V/2.5V
CC
IN
SEL = V
V
20dB ATTENUATION
CC
= 0dBm
IN
N/W ANALYZER:
= R = 50Ω
R
L
S
30
20
10
0
0.1
1
10
100
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
FREQUENCY (MHz)
DATA RATE (Gbps)
Figure 17. Off Isolation vs. Frequency
Figure 20. Jitter vs. Data Rate; PRBS 31
100
95
4.0
ENABLE
V
= SEL = 3.3V
CC
DISABLE
3.5
3.0
2.5
V
V
= SEL = 3.3V
= 1.5V p-p
CC
90
IN
20dB ATTENUATION
85
80
ENABLE
DISABLE
75
70
65
2.0
1.5
V
= 3.3V, SEL = 0V
CC
1.0
0.5
0
60
55
50
% EYE WIDTH = ((CLOCK PERIOD –
JITTER p-p)/CLOCK PERIOD) × 100%
–40
–20
0
20
40
60
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
TEMPERATURE (°C)
DATA RATE (Gbps)
Figure 18. Enable/Disable Time vs. Temperature
Figure 21. Eye Width vs. Data Rate; PRBS 31
Rev. B | Page 8 of 16
ADG3241
V
= 3.3V
20dB
ATTENUATION
V
= 2.5V
20dB
ATTENUATION
= 25°C
CC
SEL = 3.3V
= 1.5V p-p
CC
SEL = 2.5V
= 1.5V p-p
50mV/DIV
200ps/DIV
20mV/DIV
200ps/DIV
T
= 25°C
T
V
A
V
A
IN
IN
Figure 22. Eye Pattern; 1.5 Gbps, VCC = 3.3 V, PRBS 31
Figure 23. Eye Pattern; 1.244 Gbps, VCC = 2.5 V, PRBS 31
Rev. B | Page 9 of 16
ADG3241
TERMINOLOGY
VCC
CIN
Positive power supply voltage.
BE
SEL
and .
Control input capacitance. This consists of
GND
ICC
Ground (0 V) reference.
Quiescent power supply current. This current represents the
leakage current between the VCC and ground pins. It is
measured when all control inputs are at a logic high or low level
and the switches are off.
VINH
Minimum input voltage for Logic 1.
VINL
ΔICC
Maximum input voltage for Logic 0.
BE
Extra power supply current component for the
when the input is not driven at the supplies.
control input
II
Input leakage current at the control inputs.
tPLH, tPHL
Data propagation delay through the switch in the on state.
Propagation delay is related to the RC time constant RON × CL,
where CL is the load capacitance.
IOZ
Off state leakage current. It is the maximum leakage current at
the switch pin in the off state.
tPZH, tPZL
IOL
Bus enable times. These are the times taken to cross the VT
voltage at the switch output when the switch turns on in
On state leakage current. It is the maximum leakage current at
the switch pin in the on state.
BE
response to the control signal,
.
VP
tPHZ, tPLZ
Maximum pass voltage. The maximum pass voltage relates to
the clamped output voltage of an NMOS device when the
switch input voltage is equal to the supply voltage.
Bus disable times. These are the times taken to place the switch
in the high impedance off state in response to the control signal.
It is measured as the time taken for the output voltage to change
by VΔ from the original quiescent level, with reference to the
logic level transition at the control input. Refer to Figure 26 for
enable and disable times.
RON
Ohmic resistance offered by a switch in the on state. It is
measured at a given voltage by forcing a specified amount of
current through the switch.
Max Data Rate
CX OFF
Off switch capacitance.
Maximum rate at which data can be passed through the switch.
Channel Jitter
CX ON
On switch capacitance.
Peak-to-peak value of the sum of the deterministic and random
jitter of the switch channel.
Rev. B | Page 10 of 16
ADG3241
TIMING MEASUREMENT INFORMATION
DISABLE
ENABLE
For the following load circuit and waveforms, the notation that
is used is VIN and VOUT where
V
V
INH
T
CONTROL INPUT BE
0V
V
IN = VA and VOUT = VB or VIN = VB and VOUT = VA
tPZL
tPLZ
V
CC
V
V
2 × V
CC
CC
V
V
V
CC
SW1
V
OUT
SW1 @ 2V
V
= 0V
IN
T
+ V
L
L
Δ
CC
GND
tPHZ
R
R
L
L
tPZH
V
V
IN
OUT
C
V
V
PULSE
H
H
DUT
V
OUT
SW1 @ GND
GENERATOR
V
= V
CC
V
– V
IN
T
Δ
0V
0V
R
T
L
Figure 26. Enable and Disable Times
NOTES
1. PULSE GENERATOR FOR ALL PULSES: tR
FREQUENCY 10MHz.
2. C INCLUDES BOARD, STRAY, AND LOAD CAPACITANCES.
≤ 2.5ns, tF ≤ 2.5ns,
Table 5. Switch Position
Test
≤
L
S1
3. R ISTHETERMINATION RESISTOR, SHOULD BE EQUALTO Z
T
OUT
OFTHE PULSE GENERATOR.
tPLZ, tPZL
tPHZ, tPZH
2 × VCC
GND
Figure 24. Load Circuit
V
V
IH
T
CONTROL
INPUT BE
0V
tPLH
tPLH
V
V
V
H
T
L
V
OUT
Figure 25. Propagation Delay
Table 6. Test Conditions
Symbol
VCC = 3.3 V 0.3 V (SEL = VCC
)
VCC = 2.5 V 0.2 V (SEL = VCC
)
VCC = 3.3 V 0.3 V (SEL = 0 V)
Unit
RL
VΔ
CL
VT
500
300
50
500
150
30
500
150
30
Ω
mV
pF
V
1.5
0.9
0.9
Rev. B | Page 11 of 16
ADG3241
BUS SWITCH APPLICATIONS
MIXED VOLTAGE OPERATION, LEVEL
TRANSLATION
2.5 V TO 1.8 V TRANSLATION
When VCC is 2.5 V (
= 2.5 V) and the input signal range is
SEL
Bus switches can provide an ideal solution for interfacing
between mixed voltage systems. The ADG3241 is suitable for
applications where voltage translation from 3.3 V technology to
a lower voltage technology is needed. This device can translate
from 3.3 V to 1.8 V, from 2.5 V to 1.8 V, or bidirectionally from
3.3 V directly to 2.5 V.
0 V to VCC, the maximum output signal is, as before, clamped to
within a voltage threshold below the VCC supply. In this case, the
output is limited to approximately 1.8 V, as shown in Figure 31.
2.5V
Figure 27 shows a block diagram of a typical application in
which a user needs to interface between a 3.3 V ADC and a
2.5 V microprocessor. The microprocessor may not have 3.3 V
tolerant inputs, therefore placing the ADG3241 between the
two devices allows the devices to communicate easily. The bus
switch directly connects the two blocks, thus introducing
minimal propagation delay, timing skew, or noise.
ADG3241
2.5V
1.8V
SEL
Figure 30. 2.5 V to 1.8 V Voltage Translation,
= 2.5 VCC
V
OUT
2.5V SUPPLY
SEL = 2.5V
3.3V
3.3V
2.5V
1.8V
2.5V
3.3V ADC
MICROPROCESSOR
V
IN
SWITCH
INPUT
Figure 27. Level Translation Between a 3.3 V ADC and a 2.5 V Microprocessor
0V
2.5V
SEL
Figure 31. 2.5 V to 1.8 V Voltage Translation,
= VCC
3.3 V TO 2.5 V TRANSLATION
SEL
When VCC is 3.3 V (
= 3.3 V) and the input signal range is
3.3 V TO 1.8 V TRANSLATION
0 V to VCC, the maximum output signal will be clamped to
within a voltage threshold below the VCC supply.
The ADG3241 offers the option of interfacing between a 3.3 V
device and a 1.8 V device. This is possible through the use of
3.3V
SEL
SEL
SEL
the
pin. The
pin is an active low control pin.
activates internal circuitry in the ADG3241 that allows voltage
translation between 3.3 V devices and 1.8 V devices.
3.3V
2.5V
2.5V
2.5V
3.3V
ADG3241
SEL
Figure 28. 3.3 V to 2.5 V Voltage Translation,
= VCC
3.3V
ADG3241
1.8V
In this case, the output is limited to 2.5 V, as shown in Figure 29.
This device can be used for translation from 2.5 V to 3.3 V
devices and also between two 3.3 V devices.
SEL
Figure 32. 3.3 V to 1.8 V Voltage Translation,
= 0 V
V
OUT
When VCC is 3.3 V and the input signal range is 0 V to VCC,
the maximum output signal is clamped to 1.8 V, as shown in
3.3V SUPPLY
SEL = 3.3V
2.5V
SEL
Figure 32. To do this, the
pin must be tied to Logic 0. If
SEL
is unused, it should be tied directly to VCC.
V
IN
SWITCH
INPUT
0V
3.3V
SEL
Figure 29. 3.3 V to 2.5 V Voltage Translation,
= VCC
Rev. B | Page 12 of 16
ADG3241
V
OUT
3.3V SUPPLY
SEL = 0V
PLUG-IN
CARD (1)
CARD I/O
1.8V
CPU
RAM
PLUG-IN
CARD (2)
CARD I/O
V
IN
SWITCH
INPUT
0V
3.3V
SEL
Figure 33. 3.3 V to 1.8 V Voltage Translation,
= 0 V
BUS
Figure 35. ADG3241 in a Hot Plug Application
BUS ISOLATION
A common requirement of bus architectures is low capacitance
loading of the bus. Such systems require bus bridge devices that
extend the number of loads on the bus without exceeding the
specifications. Because the ADG3241 is designed specifically for
applications that do not need drive yet require simple logic
functions, it solves this requirement. The device isolates access
to the bus, thus minimizing capacitance loading.
There are many systems, such as docking stations, PCI boards
for servers, and line cards for telecommunications switches, that
require the ability to handle hot swapping. If the bus can be
isolated prior to insertion or removal, there is more control over
the hot swap event. This isolation can be achieved using bus
switches. The bus switches are positioned on the hot swap card
between the connector and the devices. During hot swap, the
ground pin of the hot swap card must connect to the ground
pin of the backplane before any other signal or power pins.
LOAD A
LOAD C
BUS/
BACKPLANE
ANALOG SWITCHING
Bus switches can be used in many analog switching
applications, such as video graphics. Bus switches can have
lower on resistance, smaller on and off channel capacitance, and
thus improved frequency performance over their analog
counterparts.
LOAD B
LOAD D
BUS SWITCH
LOCATION
Figure 34. Location of Bus Switched in a Bus Isolation Application
HOT PLUG AND HOT SWAP ISOLATION
The ADG3241 is suitable for hot swap and hot plug
applications. The output signal of the ADG3241 is limited to a
voltage that is below the VCC supply, as shown in Figure 29,
Figure 31, and Figure 33. Therefore the switch acts like a buffer
to take the impact from hot insertion, protecting vital and
expensive chipsets from damage.
The bus switch channel itself, consisting solely of an NMOS
switch, limits the operating voltage (see Figure 4 for a typical
plot), but in many cases this does not present an issue.
HIGH IMPEDANCE DURING POWER-UP/POWER-
DOWN
To ensure the high impedance state during power-up or power-
In hot plug applications, the system cannot be shut down when
new hardware is being added. To overcome this, a bus switch
can be positioned on the backplane between the bus devices
and the hot plug connectors. The bus switch is turned off
during hot plug. Figure 35 shows a typical example of this type
of application.
BE
down,
should be tied to VCC through a pull-up resistor; the
minimum value of the resistor is determined by the current-
sinking capability of the driver.
Rev. B | Page 13 of 16
ADG3241
OUTLINE DIMENSIONS
2.20
2.00
1.80
2.40
2.10
1.80
6
1
5
2
4
3
1.35
1.25
1.15
PIN 1
1.30 BSC
0.65 BSC
1.00
0.90
0.70
0.40
0.10
1.10
0.80
0.46
0.36
0.26
0.30
0.15
0.22
0.08
0.10 MAX
SEATING
PLANE
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-203-AB
Figure 36. 6-Lead Thin Shrink Small Outline Transistor Package [SC70]
(KS-6)
Dimensions shown in millimeters
1.70
1.66
1.50
0.20 MIN
0.26
0.19
0.11
6
1
4
3
5
1.70
1.65
1.50
1.30
1.20
1.10
BOTTOM
VIEW
TOP VIEW
2
0.10 NOM
0.05 MIN
0.30
0.23
0.10
PIN 1
12° MAX
0.50
BSC
0.60
0.57
0.53
0.25 MAX
0.17 MIN
0.18
0.17
0.13
SEATING
PLANE
0.34 MAX
0.27 NOM
Figure 37. 6-Lead Small Outline Transistor Package [SOT-66]
(RY-6-1)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature
Range
Package
Option
Model
Package Description
Branding
SKA
SKA
S19
S19
ADG3241BKS-REEL7
ADG3241BKS-500RL7
−40°C to +85°C
−40°C to +85°C
6-Lead Thin Shrink Small Outline Transistor Package (SC70)
6-Lead Thin Shrink Small Outline Transistor Package (SC70)
6-Lead Thin Shrink Small Outline Transistor Package (SC70)
6-Lead Thin Shrink Small Outline Transistor Package (SC70)
6-Lead Thin Shrink Small Outline Transistor Package (SC70)
6-Lead Small Outline Transistor Package (SOT-66)
KS-6
KS-6
KS-6
KS-6
KS-6
RY-6-1
ADG3241BKSZ-500RL71 −40°C to +85°C
ADG3241BKSZ-REEL71
ADG3241BKSZ-REEL1
ADG3241BRYZ-REEL71
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
S19
00
1 Z = Pb-free part.
Rev. B | Page 14 of 16
ADG3241
NOTES
Rev. B | Page 15 of 16
ADG3241
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C04221-0-4/06(B)
Rev. B | Page 16 of 16
相关型号：
ADG3241BKSZ-500RL7
3241 SERIES, 1-BIT DRIVER, TRUE OUTPUT, PDSO6, LEAD FREE, MO-203AB, SC-70, TSSOP-6
ROCHESTER
ADG3241BKSZ-REEL
3241 SERIES, 1-BIT DRIVER, TRUE OUTPUT, PDSO6, LEAD FREE, MO-203AB, SC-70, TSSOP-6
ADI
ADG3241BKSZ-REEL7
3241 SERIES, 1-BIT DRIVER, TRUE OUTPUT, PDSO6, LEAD FREE, MO-203AB, SC-70, TSSOP-6
ROCHESTER
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