ADG1219 [ADI]
Low Capacitance, Low Charge Injection, 【15 V/12 V iCMOS⑩ SPDT in SOT-23; 低电容，低电荷注入， 【 15 V / 12 V iCMOS⑩ SPDT采用SOT -23
| 型号： | ADG1219 |
| 厂家： | 
ADI |
| 描述： | Low Capacitance, Low Charge Injection, 【15 V/12 V iCMOS⑩ SPDT in SOT-23 |
| 文件： | 总17页 (文件大小：306K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Capacitance, Low Charge Injection,
± ±1 ꢀV±ꢁ ꢀ iCMOS™ SPDT in SOT-ꢁ3
Preliminary Technical Data
ADG±ꢁ±9
FEATURES
FUNCTIONAL BLOCK DIAGRAM
<0.5 pC charge injection over full signal range
2.5 pF off capacitance
ADG1219
SA
D
Low leakage; 0.6 nA maximum @ 85°C
120 Ω on resistance
SB
DECODER
Fully specified at +12 V, 15 V
No VL supply required
3 V logic-compatible inputs
Rail-to-rail operation
IN
EN
SWITCHES SHOWN FOR A LOGIC “0” INPUT
8-lead SOT-23 package
Figure 1.
APPLICATIONS
Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Audio/video signal routing
Communication systems
GENERAL DESCRIPTION
minimum charge injection over the entire signal range of the
device. iCMOS construction also ensures ultralow power
dissipation, making the parts ideally suited for portable and
battery-powered instruments.
The ADG1219 is a monolithic iCMOS device containing an
SPDT switch. An EN input is used to enable or disable the
device. When disabled, all channels are switched off. When on,
each channel conducts equally well in both directions and has
an input signal range that extends to the supplies. Each switch
exhibits break-before-make switching action.
0.5
T
= 25ºC
A
0.4
0.3
V
V
= +15V
= –15V
DD
SS
The iCMOS (industrial CMOS) modular manufacturing
process combines high voltage CMOS (complementary metal-
oxide semiconductor) and bipolar technologies. It enables the
development of a wide range of high performance analog ICs
capable of 33 V operation in a footprint that no other generation
of high voltage parts has been able to achieve. Unlike analog ICs
using conventional CMOS processes, iCMOS components can
tolerate high supply voltages while providing increased perfor-
mance, dramatically lower power consumption, and reduced
package size.
0.2
0.1
0
V
V
= 12V
= 0V
DD
SS
–0.1
–0.2
–0.3
–0.4
–0.5
V
V
= +5V
= –5V
DD
SS
–15
–10
–5
0
5
10
15
The ultralow capacitance and exceptionally low charge injection
of these multiplexers make them ideal solutions for data
acquisition and sample-and-hold applications, where low glitch
and fast settling are required. Figure 2 shows that there is
INPUT VOLTAGE (V)
Figure 2. Charge Injection vs. Input Voltage
Rev. PrB
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2008 Analog Devices, Inc. All rights reserved.
ADG±ꢁ±9
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ............................................................6
ESD Caution...................................................................................6
Pin Configuration and Function Descriptions..............................7
Terminology.................................................................................... 14
Typical Performance Characteristics ..............................................8
Test Circuits..................................................................................... 12
Outline Dimensions....................................................................... 14
Ordering Guide .......................................................................... 15
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Dual Supply................................................................................... 3
Single Supply................................................................................. 4
REVISION HISTORY
7/07—Revision 0: Initial Version
Rev. PrB | Page 2 of 17
Preliminary Technical Data
ADG±ꢁ±9
SPECIFICATIONS
DUAL SUPPLY
VDD = 15 V 10%, VSS = −15 V 10%, GND = 0 V, unless otherwise noted.
Table 1.
B Version1
Parameters
25°C
−40°C to +85°C
−40°C to +125°C
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
VDD to VSS
V
120
190
3.5
Ω typ
Ω max
Ω typ
VS = 10 V, IS = −1 mA; see Figure 23
VDD = +13.5 V, VSS = −13.5 V
VS = 10 V, IS = −1 mA
230
260
On Resistance Match Between
Channels (∆RON)
6
20
60
10
72
12
79
Ω max
Ω typ
Ω max
On Resistance Flatness (RFLAT(ON)
)
VS = −5 V, 0 V, +5 V; IS = −1 mA
LEAKAGE CURRENTS
VDD = +16.5 V, VSS = −16.5 V
Source Off Leakage, IS (Off)
0.01
nA typ
VS = 10 V, VS = ±10 V; see Figure 24
0.1
0.01
0.6
1
nA max
nA typ
Drain Off Leakage, ID (Off)
VS = 10 V, VS = ±10 V; see Figure 24
0.1
0.02
0.2
0.6
0.6
1
1
nA max
nA typ
nA max
Channel On Leakage, ID, IS (On)
VS = VD = 10 V; see Figure 25
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
μA typ
μA max
pF typ
0.005
2
VIN = VINL or VINH
0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS2
Transition Time, tTRANSITION
140
170
85
105
105
125
40
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 26
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 26
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 26
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 10 V; Figure 27
VS = 0 V, RS = 0 Ω, CL = 1 nF;
see Figure 28
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 29
200
130
150
230
140
170
10
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tBBM
Charge Injection
0.1
77
80
Off Isolation
dB typ
dB typ
Channel-to-Channel Crosstalk
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 30
Total Harmonic Distortion + Noise
−3 dB Bandwidth
CS (Off)
0.15
520
2.5
3.3
4.3
5.1
7.5
10
% typ
RL = 10 kΩ, 5 V rms, f = 20 Hz to 20 kHz
RL = 50 Ω, CL = 5 pF; see Figure 31
f = 1 MHz; VS = 0 V
f = 1 MHz; VS = 0 V
f = 1 MHz; VS = 0 V
f = 1 MHz; VS = 0 V
f = 1 MHz; VS = 0 V
f = 1 MHz; VS = 0 V
MHz typ
pF typ
pF max
pF typ
pF max
pF typ
pF max
CD (Off)
CD, CS (On)
Rev. PrB | Page 3 of 17
ADG±ꢁ±9
Preliminary Technical Data
B Version1
−40°C to +85°C −40°C to +125°C
Parameters
25°C
0.001
140
Unit
Test Conditions/Comments
POWER REQUIREMENTS
IDD
VDD = +16.5 V, VSS = −16.5 V
Digital inputs = 0 V or VDD
μA typ
μA max
μA typ
μA max
μA typ
μA max
1.0
170
1.0
IDD
Digital inputs = 5 V
ISS
0.001
Digital inputs = 0 V, 5 V or VDD
VDD/VSS
5/ 16.5
V min/max |VDD | = |VSS|
1 Temperature range for B version is −40°C to +125°C.
2 Guaranteed by design; not subject to production test.
SINGLE SUPPLY
VDD = 12 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 2.
B Version1
Parameters
25°C
−40°C to +85°C −40°C to +125°C
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
0 V to VDD
V
300
475
4.5
Ω typ
Ω max
Ω typ
VS = 0 V to 10 V, IS = −1 mA; see Figure 23
VDD = 10.8 V, VSS = 0 V
VS = 0 V to 10 V, IS = −1 mA
567
26
625
27
On Resistance Match Between
Channels (∆RON)
16
60
Ω max
Ω typ
On Resistance Flatness (RFLAT(ON)
LEAKAGE CURRENTS
)
VS = 3 V, 6 V, 9 V, IS = −1 mA
VDD = 13.2 V
Source Off Leakage, IS (Off)
0.01
0.1
0.01
0.1
0.02
0.2
nA typ
nA max
nA typ
nA max
nA typ
nA max
VS = 1 V/10 V, VD = 10 V/1 V; see Figure 24
0.6
0.6
0.6
1
1
1
Drain Off Leakage, ID (Off)
VS = 1 V/10 V, VD = 10 V/1 V; see Figure 24
VS = VD = 1 V or 10 V, see Figure 25
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
μA typ
μA max
pF typ
0.001
3
VIN = VINL or VINH
0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS2
Transition Time, tTRANSITION
195
250
120
150
145
185
70
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 26
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 26
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 26
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 8 V; see Figure 27
VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 28
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 29;
300
190
220
340
210
235
10
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tBBM
Charge Injection
Off Isolation
−0.8
80
Channel-to-Channel Crosstalk
−3 dB Bandwidth
80
dB typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 30
RL = 50 Ω, CL = 5 pF; see Figure 31
400
MHz typ
Rev. PrB | Page 4 of 17
Preliminary Technical Data
ADG±ꢁ±9
B Version1
Parameters
25°C
2.9
3.7
5
5.8
8.5
11
−40°C to +85°C −40°C to +125°C
Unit
Test Conditions/Comments
CS (Off)
pF typ
pF max
pF typ
pF max
pF typ
pF max
f = 1 MHz; VS = 6 V
f = 1 MHz; VS = 6 V
f = 1 MHz; VS = 6 V
f = 1 MHz; VS = 6 V
f = 1 MHz; VS = 6 V
f = 1 MHz; VS = 6 V
VDD = 13.2 V
CD (Off)
CD, CS (On)
POWER REQUIREMENTS
IDD
0.001
140
μA typ
μA max
μA typ
μA max
V min/max
Digital inputs = 0 V or VDD
1.0
IDD
Digital inputs = 5 V
VSS = 0 V, GND = 0 V
170
VDD
5/16.5
1 Temperature range for B version is −40°C to +125°C.
2 Guaranteed by design; not subject to production test.
Rev. PrB | Page 5 of 17
ADG±ꢁ±9
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 3.
Parameter
Rating
VDD to VSS
35 V
VDD to GND
VSS to GND
Analog Inputs1
−0.3 V to +25 V
+0.3 V to −25 V
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
GND − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
Digital Inputs1
ESD CAUTION
Peak Current, S or D
100 mA (pulsed at 1 ms,
10% duty cycle maximum)
Continuous Current per
Channel, S or D
30 mA
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Junction Temperature
−40°C to +125°C
−65°C to +150°C
150°C
8-Lead SOT-23, θJA Thermal
Impedance
211.5°C/W
Reflow Soldering Peak
Temperature, Pb Free
260°C
1 Overvoltages at IN, S, or D are clamped by internal diodes. Current should be
limited to the maximum ratings given.
Rev. PrB | Page 6 of 17
Preliminary Technical Data
ADG±ꢁ±9
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
EN
1
2
3
4
8
7
6
5
IN
ADG1219
V
SA
D
DD
TOP VIEW
GND
(Not to Scale)
V
SB
SS
NC = NO CONNECT
Figure 3. SOT-23 Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
EN
Active High Digital Input. When this pin is low, the device is disabled and all switches are turned off.
When this pin is high, the IN logic input determines which switch is turned on.
1
2
3
4
5
6
7
8
VDD
GND
VSS
SB
D
SA
IN
Most Positive Power Supply Potential.
Ground (0 V) Reference.
Most Negative Power Supply Potential.
Source Terminal. Can be an input or output.
Drain Terminal. Can be an input or output.
Source Terminal. Can be an input or output.
Logic Control Input.
Table 5. Truth Table
EN
IN
X
Switch A
Off
Switch B
Off
0
1
0
On
Off
1
1
Off
On
Rev. PrB | Page 7 of 17
ADG±ꢁ±9
Preliminary Technical Data
TYPICAL PERFORMANCE CHARACTERISTICS
200
250
V
V
= 15V
= –15V
DD
SS
T
= 25°C
A
V
V
= 15V
DD
SS
180
160
140
120
100
80
= –15V
V
V
= 13.5V
= –13.5V
DD
SS
200
150
T
T
= +125°C
= +85°C
A
A
T
= +25°C
= –40°C
A
A
V
V
= 16.5V
= –16.5V
DD
SS
100
T
60
40
50
0
20
0
–18 –15 –12 –9 –6 –3
0
3
6
9
12 15 18
–15
–10
–5
0
5
10
15
SOURCE OR DRAIN VOLTAGE (V)
TEMPERATURE (°C)
Figure 4. On Resistance as a Function of VD (VS) for Dual Supply
Figure 7. On Resistance as a Function of VD (VS) for Different Temperatures,
Dual Supply
600
600
V
V
= 12V
= 0V
DD
SS
T
= 25°C
V
V
= 4.5V
= –4.5V
A
DD
SS
T
= +125°C
A
500
500
400
300
200
V
V
= 5V
= –5V
DD
SS
T
= +85°C
A
400
300
T
= +25°C
A
V
V
= 5.5V
= –5.5V
DD
SS
T
= –40°C
A
200
100
0
100
0
–6
–4
–2
0
2
4
6
0
2
4
6
8
10
12
SOURCE OR DRAIN VOLTAGE (V)
TEMPERATURE (°C)
Figure 5. On Resistance as a Function of VD (VS) for Dual Supply
Figure 8. On Resistance as a Function of VD (VS) for Different Temperatures,
Single Supply
200
450
V
V
V
= +15V
= –15V
T
= 25°C
V
V
= 10.8V
= 0V
DD
SS
A
DD
SS
400
350
300
250
200
150
100
100
0
= +10V/–10V
BIAS
V
V
= 12V
= 0V
DD
SS
–100
–200
–300
–400
–500
V
V
= 13.2V
= 0V
DD
SS
I (OFF)+–
S
I
(OFF)+–
D
I (OFF)–+
S
I
I
I
(OFF)–+
D
(ON)++
(ON)––
D,S
D,S
50
0
0
2
4
6
8
10
12
14
0
20
40
60
80
100
120
SOURCE OR DRAIN VOLTAGE (V)
TEMPERATURE (°C)
Figure 6. On Resistance as a Function of VD (VS) for Single Supply
Figure 9. Leakage Currents as a Function of Temperature, 15 V Dual Supply
Rev. PrB | Page 8 of 17
Preliminary Technical Data
ADG±ꢁ±9
350
0.5
0.4
I
I
I
I
I
I
(OFF)+–
T
= 25ºC
S
A
300
250
200
150
100
50
(OFF)+–
(OFF)–+
D
V
V
= +15V
= –15V
DD
SS
S
0.3
(OFF)–+
D
0.2
(ON)++
(ON)––
D,S
D,S
0.1
V
V
V
= 12V
= 0V
DD
SS
0
= 1V/10V
BIAS
V
V
= 12V
= 0V
DD
SS
–0.1
–0.2
–0.3
–0.4
–0.5
0
V
V
= +5V
= –5V
DD
SS
–50
–100
0
20
40
60
80
100
120
–15
–10
–5
0
5
10
15
TEMPERATURE (°C)
INPUT VOLTAGE (V)
Figure 10.Leakage Currents as a Function of Temperature, 12 V Single Supply
Figure 13. Charge Injection vs. Input Voltage
100
300
250
200
150
100
50
V
V
V
= 5V
= –5V
DD
SS
12V SS
50
0
= +4.5V/–4.5V
BIAS
–50
15V DS
I
I
I
I
I
I
(OFF)+–
S
–100
–150
–200
(OFF)+–
(OFF)–+
D
S
(OFF)–+
D
(ON)++
(ON)––
D,S
D,S
0
–40
0
20
40
60
80
100
120
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (ºC)
Figure 11. Leakage Currents as a Function of Temperature, 5 V Dual Supply
Figure 14. tTRANSITION Time vs. Temperature
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
200
V
V
= 15V
= –15V
= 25ºC
DD
SS
I
T
PER CHANNEL
= 25°C
DD
180
160
140
120
100
80
A
T
A
V
V
= +15V
= –15V
DD
SS
60
40
V
= +12V
= 0V
DD
20
0
V
SS
10k
100k
1M
10M
100M
1G
0
2
4
6
8
10
12
14
16
LOGIC, IN (V)
FREQUENCY (Hz)
X
Figure 15. Off Isolation vs. Frequency
Figure 12. IDD vs. Logic Level
Rev. PrB | Page 9 of 17
ADG±ꢁ±9
Preliminary Technical Data
0
8
7
6
5
4
3
2
1
0
V
V
T
= 15V
= –15V
= 25ºC
DD
SS
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
A
SOURCE/DRAIN ON
DRAIN OFF
SOURCE OFF
V
V
= 15V
= –15V
DD
SS
T
= 25ºC
A
10k
100k
1M
10M
100M
1G
–15
–10
–5
0
5
10
15
12
5
FREQUENCY (Hz)
SOURCE VOLTAGE (V)
Figure 16. Crosstalk vs. Frequency
Figure 19. Capacitance vs. Source Voltage for Dual Supply
0
–2
9
8
V
V
= 15V
= –15V
= 25ºC
DD
SS
T
A
SOURCE/DRAIN ON
7
–4
6
–6
DRAIN OFF
5
4
–8
SOURCE OFF
3
2
1
0
–10
–12
–14
V
V
= 12V
= 0V
= 25ºC
DD
SS
T
A
10k
100k
1M
10M
100M
1G
0
2
4
6
8
10
FREQUENCY (Hz)
SOURCE VOLTAGE (V)
Figure 17. On Response vs. Frequency
Figure 20. Capacitance vs. Source Voltage for Single Supply
10
9
10.00
1.00
LOAD = 10kΩ
= 25°C
T
A
8
SOURCE/DRAIN ON
7
6
V
= 5V, V = –5V, V = 3.5Vrms
SS
DD
S
DRAIN OFF
5
V
= 15V, V = –15V, V = 5Vrms
SS
DD
S
4
SOURCE OFF
0.10
0.01
3
2
V
V
= 5V
= –5V
= 25ºC
DD
SS
1
0
T
A
10
100
1k
FREQUENCY (Hz)
10k
100k
–5
–3
–1
1
3
SOURCE VOLTAGE (V)
Figure 18. THD + N vs. Frequency
Figure 21. Capacitance vs. Source Voltage for Dual Supply
Rev. PrB | Page 10 of 17
Preliminary Technical Data
ADG±ꢁ±9
0
V
V
= +15V
= –15V
DD
SS
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
NO DECOUPLING CAPS ON
Vp-p = 0.63V
= 25ºC
T
A
DECOUPLING CAPS ON
100k
1M
10M
FREQUENCY (Hz)
100M
Figure 22. ACPSRR vs Frequency
Rev. PrB | Page 11 of 17
ADG±ꢁ±9
Preliminary Technical Data
TEST CIRCUITS
V
S
D
I
DS
V
S
Figure 23. On Resistance
I
(OFF)
A
I (OFF)
D
S
S
D
A
V
V
S
D
Figure 24. Off Leakage
I
(ON)
D
S
D
NC
A
V
D
NC = NO CONNECT
Figure 25. On Leakage
V
V
DD
SS
0.1µF
0.1µF
V
V
IN
50%
50%
50%
V
V
SS
DD
SB
V
IN
S
50%
90%
D
V
OUT
SA
R
300Ω
C
35pF
L
L
90%
IN
V
OUT
V
IN
GND
tON
tOFF
Figure 26. Switching Times
V
V
DD
DD
SS
0.1µF
0.1µF
V
IN
V
V
SS
SB
V
S
D
V
OUT
SA
80%
V
R
C
OUT
L
L
35pF
300Ω
IN
tBBM
tBBM
V
IN
GND
Figure 27. Break-Before-Make Time Delay
V
V
V
SS
DD
0.1µF
0.1µF
V
(NORMALLY
IN
CLOSED SWITCH)
V
DD
SS
SB
ON
OFF
NC
V
D
V
S
V
(NORMALLY
IN
OPEN SWITCH)
OUT
SA
C
1nF
L
IN
V
ΔV
OUT
OUT
V
IN
Q
= C × ΔV
L
OUT
GND
INJ
Figure 28. Charge Injection
Rev. PrB | Page 12 of 17
Preliminary Technical Data
ADG±ꢁ±9
V
V
DD
SS
0.1µF
0.1µF
V
V
DD
SS
0.1µF
0.1µF
NETWORK
ANALYZER
V
V
DD
SS
NETWORK
ANALYZER
V
V
SA
DD
SS
V
OUT
NC
R
L
50Ω
50Ω
SA
SB
50Ω
SB
D
R
50Ω
IN
V
S
D
IN
V
V
OUT
S
V
IN
R
L
GND
V
50Ω
GND
V
OUT
OUT
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
OFF ISOLATION = 20 log
V
S
V
S
Figure 29. Off Isolation
Figure 31. Bandwidth
V
V
DD
SS
0.1µF
0.1µF
V
V
DD
SS
NETWORK
ANALYZER
0.1µF
0.1µF
V
V
DD
SS
NC
50Ω
AUDIO PRECISION
V
V
DD
SS
SA
SB
50Ω
R
S
IN
V
S
S
D
IN
V
V
S
V p-p
OUT
V
IN
R
L
50Ω
D
GND
V
OUT
V
IN
R
L
10kΩ
GND
V
WITH SWITCH
OUT
INSERTION LOSS = 20 log
V
WITHOUT SWITCH
OUT
Figure 32. THD + Noise
Figure 30. Channel-to-Channel Crosstalk
Rev. PrB | Page 13 of 17
ADG±ꢁ±9
Preliminary Technical Data
TERMINOLOGY
IDD
t
ON (EN)
The positive supply current.
Delay time between the 50% and 90% points of the digital input
and switch on condition.
ISS
The negative supply current.
tOFF (EN)
Delay time between the 50% and 90% points of the digital input
and switch off condition.
VD (VS)
The analog voltage on Terminal D and Terminal S.
tTRANSITION
RON
Delay time between the 50% and 90% points of the digital
inputs and the switch on condition when switching from one
address state to another.
The ohmic resistance between D and S.
RFLAT(ON)
Flatness is defined as the difference between the maximum and
minimum value of on resistance as measured over the specified
analog signal range.
TBBM
Off time measured between the 80% point of both switches
when switching from one address state to another.
IS (Off)
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
The source leakage current with the switch off.
ID (Off)
The drain leakage current with the switch off.
Off Isolation
ID, IS (On)
A measure of unwanted signal coupling through an off switch.
The channel leakage current with the switch on.
Crosstalk
VINL
A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance.
The maximum input voltage for Logic 0.
VINH
Bandwidth
The minimum input voltage for Logic 1.
The frequency at which the output is attenuated by 3 dB.
I
INL (IINH)
On Response
The frequency response of the on switch.
The input current of the digital input.
CS (Off)
Insertion Loss
The loss due to the on resistance of the switch.
The off switch source capacitance, measured with reference to
ground.
THD + N
CD (Off)
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental.
The off switch drain capacitance, measured with reference to
ground.
ACPSRR (AC Power Supply Rejection Ratio)
CD, CS (On)
Measures the ability of a part to avoid coupling noise and
spurious signals that appear on the supply voltage pin to the
output of the switch. The dc voltage on the device is modulated
by a sine wave of 0.62 V p-p. The ratio of the amplitude of signal on
the output to the amplitude of the modulation is the ACPSRR.
The on switch capacitance, measured with reference to ground.
CIN
The digital input capacitance.
Rev. PrB | Page 14 of 17
Preliminary Technical Data
OUTLINE DIMENSIONS
ADG±ꢁ±9
2.90 BSC
8
1
7
2
6
3
5
4
1.60 BSC
2.80 BSC
PIN 1
INDICATOR
0.65 BSC
1.95
BSC
1.30
1.15
0.90
1.45 MAX
0.22
0.08
0.60
0.45
0.30
8°
4°
0°
0.38
0.22
0.15 MAX
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-178-BA
Figure 33. 8-Lead Lead Small Outline Transistor Package [SOT-23]
(RJ-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option Branding
ADG1219BRJZ-R21
ADG1219BRJZ-REEL71
−40°C to +125°C
−40°C to +125°C
8-Lead Lead Small Outline Transistor Package [SOT-23]
8-Lead Lead Small Outline Transistor Package [SOT-23]
RJ-8
RJ-8
S24
S24
1 Z = RoHS Compliant Part.
Rev. PrB | Page 15 of 17
ADG±ꢁ±9
NOTES
Preliminary Technical Data
Rev. PrB | Page 16 of 17
Preliminary Technical Data
NOTES
ADG±ꢁ±9
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR06575-0-3/08(PrB)
Rev. PrB | Page 17 of 17
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