ADG1213YRUZ [ADI]
Low Capacitance, Low Charge Injection, ±15 V/12 V iCMOS Quad SPST Switches; 低电容，低电荷注入，A ±15 V / 12 V的iCMOS四通道SPST开关
| 型号： | ADG1213YRUZ |
| 厂家： | 
ADI |
| 描述： | Low Capacitance, Low Charge Injection, ±15 V/12 V iCMOS Quad SPST Switches |
| 文件： | 总16页 (文件大小：330K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Capacitance, Low Charge Injection,
15 V/+12 V CMOS Quad SPST Switches
i
Data Sheet
ADG1211/ADG1212/ADG1213
FUNCTIONAL BLOCK DIAGRAM
FEATURES
1 pF off capacitance
S1
S1
S1
IN1
IN2
IN3
IN4
IN1
IN2
IN3
IN4
IN1
IN2
IN3
IN4
2.6 pF on capacitance
<1 pC charge injection
33 V supply range
D1
S2
D1
S2
D1
S2
120 Ω on resistance
D2
S3
D2
S3
D2
S3
ADG1211
ADG1212
ADG1213
Fully specified at 15 V, +12 V
No VL supply required
3 V logic-compatible inputs
Rail-to-rail operation
16-lead TSSOP and 16-lead LFCSP
Typical power consumption: <0.03 µW
D3
S4
D3
S4
D3
S4
D4
D4
D4
SWITCHES SHOWN FOR A LOGIC 1 INPUT
Figure 1.
APPLICATIONS
Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Audio signal routing
iCMOS construction ensures ultralow power dissipation,
making the parts ideally suited for portable and battery-
powered instruments.
Video signal routing
Communication systems
The ADG1211/ADG1212/ADG1213 contain four independent
single-pole/single-throw (SPST) switches. The ADG1211 and
ADG1212 differ only in that the digital control logic is inverted.
The ADG1211 switches are turned on with Logic 0 on the
appropriate control input, while Logic 1 is required for the
ADG1212. The ADG1213 has two switches with digital control
logic similar to that of the ADG1211; the logic is inverted on
the other two switches. The ADG1213 exhibits break-before-
make switching action for use in multiplexer applications.
GENERAL DESCRIPTION
The ADG1211/ADG1212/ADG1213 are monolithic complemen-
tary metal-oxide semiconductor (CMOS) devices containing
four independently selectable switches designed on an iCMOS®
(industrial CMOS) process. iCMOS is a modular manufacturing
process combining high voltage CMOS and bipolar technologies.
It enables the development of a wide range of high performance
analog ICs capable of 33 V operation in a footprint that no
previous generation of high voltage parts has been able to achieve.
Unlike analog ICs using conventional CMOS processes, iCMOS
components can tolerate high supply voltages while providing
increased performance, dramatically lower power consumption,
and reduced package size.
Each switch conducts equally well in both directions when on
and has an input signal range that extends to the supplies. In the
off condition, signal levels up to the supplies are blocked.
PRODUCT HIGHLIGHTS
1. Ultralow capacitance.
The ultralow capacitance and charge injection of these switches
make them ideal solutions for data acquisition and sample-and-
hold applications, where low glitch and fast settling are required.
Fast switching speed coupled with high signal bandwidth make
the parts suitable for video signal switching.
2. <1 pC charge injection.
3. 3 V logic-compatible digital inputs: VIH = 2.0 V, V IL = 0.8 V.
4. No VL logic power supply required.
5. Ultralow power dissipation: <0.03 µW.
6. 16-lead TSSOP and 3 mm × 3 mm LFCSP packages.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted byimplication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2005–2012 Analog Devices, Inc. All rights reserved.
ADG1211/ADG1212/ADG1213
Data Sheet
TABLE OF CONTENTS
Specifications..................................................................................... 3
Terminology.......................................................................................8
Typical Performance Characteristics ..............................................9
Test Circuits..................................................................................... 12
Outline Dimensions....................................................................... 14
Ordering Guide .......................................................................... 15
Dual Supply ................................................................................... 3
Single Supply ................................................................................. 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
REVISION HISTORY
8/12—Rev. A to Rev. B
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 5
Change to Table 6 ............................................................................. 7
Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 15
2/09—Rev. 0 to Rev. A
Changes to Power Requirements, IDD, Digital Inputs = 5 V
Parameter, Table 1............................................................................. 4
Changes to Power Requirements, IDD, Digital Inputs = 5 V
Parameter, Table 2............................................................................. 5
7/05—Revision 0: Initial Version
Rev. B | Page 2 of 16
Data Sheet
ADG1211/ADG1212/ADG1213
SPECIFICATIONS
DUAL SUPPLY
VDD = 15 V 10%, VSS = −15 V 10%, GND = 0 V, unless otherwise noted.
Table 1.
Y Version1
−40°C to
+85°C
−40°C to
+125°C
Parameter
25°C
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
VDD to VSS
260
V
On Resistance (RON
)
120
190
2.5
Ω typ
Ω max
Ω typ
VS = 10 V, IS = −1 mA; see Figure 20
VDD = +13.5 V, VSS = −13.5 V
VS = 10 V, IS = −1 mA
230
On Resistance Match Between
Channels (∆RON
)
6
20
57
10
72
11
79
Ω max
Ω typ
Ω max
On Resistance Flatness (RFLAT(ON)
)
VS = −5 V/0 V/+5 V; IS = −1 mA
LEAKAGE CURRENTS
VDD = +16.5 V, VSS = −16.5 V
Source Off Leakage, IS (Off)
0.02
nA typ
VS = 10 V, VD = ∓10 V; see Figure 21
0.1
0.02
0.6
1
nA max
nA typ
Drain Off Leakage, ID (Off)
VS = 10 V, VD = ∓10 V; see Figure 21
0.1
0.02
0.1
0.6
0.6
1
1
nA max
nA typ
nA max
Channel On Leakage, ID, IS (On)
VS = VD = 10 V; see Figure 22
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
µA typ
µA max
pF typ
0.005
2.5
VIN = VINL or VINH
0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS2
tON
110
130
85
115
25
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
% typ
MHz typ
pF typ
pF max
pF typ
pF max
pF typ
pF max
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 23
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 23
160
130
195
150
10
tOFF
Break-Before-Make Time Delay, tD
(ADG1213 Only)
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion + Noise 0.15
−3 dB Bandwidth
CS (Off)
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 10 V; see Figure 24
VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 25
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 26
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 27
RL = 10 kΩ, 5 V rms, f = 20 Hz to 20 kHz
RL = 50 Ω, CL = 5 pF; see Figure 28
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
−0.3
80
90
1000
0.9
1.1
1
1.2
2.6
3
CD (Off)
CD, CS (On)
VS = 0 V, f = 1 MHz
Rev. B | Page 3 of 16
ADG1211/ADG1212/ADG1213
Data Sheet
Y Version1
−40°C to
+85°C
−40°C to
+125°C
Parameter
25°C
0.001
220
Unit
Test Conditions/Comments
POWER REQUIREMENTS
IDD
VDD = +16.5 V, VSS = −16.5 V
Digital inputs = 0 V or VDD
µA typ
µA max
µA typ
µA max
µA typ
µA max
µA typ
1.0
380
1.0
IDD
Digital inputs = 5 V
ISS
0.001
0.001
Digital inputs = 0 V or VDD
Digital inputs = 5 V
ISS
1.0
4.5/ 16.5
µA max
V min/max
VDD/VSS
1 Temperature range for Y version is −40°C to +125°C.
2 Guaranteed by design, not subject to production test.
Rev. B | Page 4 of 16
Data Sheet
ADG1211/ADG1212/ADG1213
SINGLE SUPPLY
VDD = 12 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 2.
Y Version1
−40°C to
−40°C to
+125°C
Parameter
25°C
+85°C
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
0 V to VDD
625
V
On Resistance (RON
)
300
475
4.5
Ω typ
Ω max
Ω typ
VS = 0 V to 10 V, IS = −1 mA; see Figure 20
VDD = 10.8 V, VSS = 0 V
VS = 0 V to 10 V, IS = −1 mA
567
26
On Resistance Match Between
Channels (∆RON
)
12
60
27
Ω max
Ω typ
On Resistance Flatness (RFLAT(ON)
)
VS = 3 V/6 V/9 V, IS = −1 mA
LEAKAGE CURRENTS
VDD = 13.2 V, VSS = 0 V
Source Off Leakage, IS (Off)
0.02
0.1
0.02
0.1
0.02
0.1
nA typ
nA max
nA typ
nA max
nA typ
nA max
VS = 1 V/10 V, VD = 10 V/1 V; see Figure 21
0.6
0.6
0.6
1
1
1
Drain Off Leakage, ID (Off)
VS = 1 V/10 V, VD = 10 V/1 V; see Figure 21
VS = VD = 1 V or 10 V; see Figure 22
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
µA typ
µA max
pF typ
0.001
3
VIN = VINL or VINH
0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS2
tON
130
170
95
120
50
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
MHz typ
pF typ
pF max
pF typ
pF max
pF typ
pF max
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 23
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 23
210
145
240
180
10
tOFF
Break-Before-Make Time Delay, tD
(ADG1213 Only)
Charge Injection
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 8 V; see Figure 24
VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 25
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 26
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 27
RL = 50 Ω, CL = 5 pF; see Figure 28
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
0
80
90
900
1.2
1.4
1.3
1.5
3.2
3.9
Off Isolation
Channel-to-Channel Crosstalk
−3 dB Bandwidth
CS (Off)
CD (Off)
CD, CS (On)
VS = 6 V, f = 1 MHz
POWER REQUIREMENTS
IDD
VDD = 13.2 V
Digital inputs = 0 V or VDD
0.001
220
µA typ
µA max
µA typ
µA max
1.0
IDD
Digital inputs = 5 V
1.0
VDD
5/165
V min/max VSS = 0 V, GND = 0 V
1 Temperature range for Y version is −40°C to +125°C.
2 Guaranteed by design, not subject to production test.
Rev. B | Page 5 of 16
ADG1211/ADG1212/ADG1213
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
VDD to VSS
35 V
VDD to GND
VSS to GND
Analog Inputs1
−0.3 V to +25 V
+0.3 V to −25 V
VSS – 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
GND – 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
Digital Inputs1
Only one absolute maximum rating may be applied at any one
time.
Peak Current, S or D
100 mA (pulsed at 1 ms,
10% duty cycle max)
Continuous Current per
Channel, S or D
25 mA
Table 4. ADG1211/ADG1212 Truth Table
Operating Temperature Range
Automotive (Y Version)
Storage Temperature Range
Junction Temperature
ADG1211 INx
ADG1212 INx
Switch Condition
−40°C to +125°C
−65°C to +150°C
150°C
0
1
1
0
On
Off
16-Lead TSSOP, θJA Thermal
Impedance (4-Layer Board)
112°C/W
Table 5. ADG1213 Truth Table
16-Lead LFCSP, θJA Thermal
Impedance
Reflow Soldering Peak
Temperature, Pb free
72.7°C/W
260°C
ADG1213 INx
Switch 1, 4
Switch 2, 3
0
1
Off
On
On
Off
1 Overvoltages at IN, S, or D are clamped by internal diodes. Current should be
limited to the maximum ratings given.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. B | Page 6 of 16
Data Sheet
ADG1211/ADG1212/ADG1213
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
ADG1211/ADG1212/ADG1213
PIN 1
INDICATOR
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IN1
D1
S1
IN2
D2
S2
V
12 S2
11 V
S1
1
2
3
4
V
DD
SS
GND
10 NC
9 S3
TOP VIEW
(Not to Scale)
ADG1211/
ADG1212/
ADG1213
TOP VIEW
S4
V
SS
DD
GND
NC
S3
S4
D4
D3
IN3
NC = NO CONNECT
IN4
NOTES
1. EXPOSED PAD TIED TO SUBSTRATE, V
.
NC = NO CONNECT
SS
Figure 3. LFCSP Pin Configuration
Figure 2. TSSOP Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
LFCSP
TSSOP
Mnemonic
IN1
D1
Description
1
2
3
15
16
1
Logic Control Input.
Drain Terminal. Can be an input or output.
Source Terminal. Can be an input or output.
Most Negative Power Supply Potential.
Ground (0 V) Reference.
Source Terminal. Can be an input or output.
Drain Terminal. Can be an input or output.
Logic Control Input.
S1
4
2
VSS
5
6
3
4
GND
S4
7
5
D4
8
9
6
7
8
9
10
11
12
13
14
IN4
IN3
D3
S3
NC
VDD
S2
D2
Logic Control Input.
10
11
12
13
14
15
16
Drain Terminal. Can be an input or output.
Source Terminal. Can be an input or output.
No Internal Connection.
Most Positive Power Supply Potential.
Source Terminal. Can be an input or output.
Drain Terminal. Can be an input or output.
Logic Control Input.
IN2
Rev. B | Page 7 of 16
ADG1211/ADG1212/ADG1213
TERMINOLOGY
Data Sheet
IDD
CD, CS (On)
The positive supply current.
The on switch capacitance, measured with reference to ground.
ISS
CIN
The negative supply current.
The digital input capacitance.
VD (VS)
tON
The analog voltage on Terminals D and S.
The delay between applying the digital control input and the
output switching on. See Figure 23.
RON
The ohmic resistance between D and S.
tOFF
The delay between applying the digital control input and the
output switching off. See Figure 23.
RFLAT(ON)
Flatness is defined as the difference between the maximum and
minimum value of on resistance, as measured over the specified
analog signal range.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
IS (Off)
The source leakage current with the switch off.
Off Isolation
A measure of unwanted signal coupling through an off switch.
ID (Off)
The drain leakage current with the switch off.
Crosstalk
A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance.
ID, IS (On)
The channel leakage current with the switch on.
Bandwidth
VINL
The frequency at which the output is attenuated by 3 dB.
The maximum input voltage for Logic 0.
On Response
The frequency response of the on switch.
VINH
The minimum input voltage for Logic 1.
Insertion Loss
The loss due to the on resistance of the switch.
IINL (IINH
)
The input current of the digital input.
THD + N
CS (Off)
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental.
The off switch source capacitance, measured with reference
to ground.
CD (Off)
The off switch drain capacitance, measured with reference
to ground.
Rev. B | Page 8 of 16
Data Sheet
ADG1211/ADG1212/ADG1213
TYPICAL PERFORMANCE CHARACTERISTICS
200
250
200
150
100
V
V
= +15V
= –15V
T
= +25°C
DD
SS
A
180
160
140
120
100
80
V
V
= +13.5V
= –13.5V
DD
SS
T
= +125°C
A
T
= +85°C
A
V
V
= +15V
= –15V
V
V
= +16.5V
= –16.5V
DD
SS
DD
SS
T
= +25°C
A
T
= –40°C
A
60
40
50
0
20
0
–18 –15 –12 –9 –6
–3
0
3
6
9
12 15 18
–15
–10
–5
0
5
10
15
SOURCE OR DRAIN VOLTAGE (V)
SOURCE OR DRAIN VOLTAGE (V)
Figure 4. On Resistance as a Function of VD (VS) for Dual Supply
Figure 7. On Resistance as a Function of VD (VS) for Different Temperatures,
Dual Supply
450
600
T
= +25°C
V
V
= +12V
= 0V
A
DD
SS
400
350
300
250
200
T
= +125°C
500
400
300
200
A
T
= +85°C
A
V
V
= +5.5V
= –5.5V
DD
SS
150
100
T
= –40°C
A
T
= +25°C
A
100
0
50
0
–5
–4
–3
–2
–1
0
1
2
3
4
5
0
2
4
6
8
10
12
SOURCE OR DRAIN VOLTAGE (V)
SOURCE OR DRAIN VOLTAGE (V)
Figure 5. On Resistance as a Function of VD (VS) for Dual Supply
Figure 8. On Resistance as a Function of VD (VS) for Different Temperatures,
Single Supply
450
0.20
T
= 25°C
V
V
V
= +15V
= –15V
A
DD
SS
400
350
300
250
200
150
0.15
0.10
0.05
V
V
= 12V
= 0V
= +10V/–10V
DD
SS
BIAS
V
V
= 10.8V
DD
I
, I (ON)
S
D
= 0V
SS
I
(OFF)
D
V
V
= 13.2V
= 0V
0
–0.05
–0.10
DD
SS
I
(OFF)
S
100
–0.15
–0.20
50
0
0
2
4
6
8
10
12
0
20
40
60
80
100
120
SOURCE OR DRAIN VOLTAGE (V)
TEMPERATURE (°C)
Figure 6. On Resistance as a Function of VD (VS) for Single Supply
Figure 9. Leakage Currents as a Function of Temperature, Dual Supply
Rev. B | Page 9 of 16
ADG1211/ADG1212/ADG1213
Data Sheet
0.30
200
180
V
V
V
= 12V
= 0V
DD
SS
0.25
0.20
0.15
= 1V/10V
BIAS
12V SS T
ON
160
140
I
, I (ON)
S
D
120
100
15V DS T
ON
0.10
0.05
I
(OFF)
S
80
60
40
12V SS T
OFF
0
–0.05
–0.10
15V DS T
OFF
I
(OFF)
D
20
0
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 13. TON/TOFF Times vs. Temperature
Figure 10. Leakage Currents as a Function of Temperature, Single Supply
0
60
I
T
PER CHANNEL
= +25°C
V
V
T
= +15V
DD
DD
–10
–20
–30
–40
–50
–60
–70
–80
–90
= –15V
A
SS
= +25°C
50
40
30
20
A
V
= +15V, V = –15V
SS
DD
V
= +12V, V = 0V
DD SS
10
0
–100
–110
10k
100k
1M
10M
100M
1G
0
2
4
6
8
10
12
14
FREQUENCY (Hz)
LOGIC, IN (V)
X
Figure 11. IDD vs. Logic Level
Figure 14. Off Isolation vs. Frequency
6
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
SOURCE TO DRAIN
DRAIN TO SOURCE
V
V
T
= +15V
= –15V
= +25°C
DD
SS
T
= +25°C
A
4
2
A
0
V
= +5V, V = –5V
SS
DD
V
= +12V, V = 0V
SS
DD
–2
–4
–6
V
= +15V, V = –15V
SS
DD
–110
–120
–15
–10
–5
0
5
10
15
10k
100k
1M
10M
100M
V
(V)
FREQUENCY (Hz)
S
Figure 12. Charge Injection vs. Source Voltage
Figure 15. Crosstalk vs. Frequency
Rev. B | Page 10 of 16
Data Sheet
ADG1211/ADG1212/ADG1213
0
3.0
V
V
= +15V
= –15V
DD
SS
SOURCE/DRAIN ON
T
= +25°C
A
–5
V
V
= +15V
= –15V
= +25°C
DD
SS
2.5
2.0
1.5
T
A
–10
–15
–20
–25
–30
DRAIN OFF
1.0
0.5
SOURCE OFF
10k
100k
1M
10M
100M
1G
10G
–10
–8
–6
–4
–2
0
2
4
6
8
10
FREQUENCY (Hz)
V
(V)
BIAS
Figure 16. On Response vs. Frequency
Figure 18. Capacitance vs. Source Voltage, Dual Supply
10.00
1.00
4.0
3.5
3.0
2.5
2.0
1.5
1.0
V
V
= 12V
= 0V
= 25°C
LOAD = +10kΩ
= +25°C
DD
SS
T
A
T
A
SOURCE/DRAIN ON
V
= +5V, V = –5V, V = +3.5Vrms
SS
DD
S
V
= +15V, V = –15V, V = +5Vrms
SS
DD
S
DRAIN OFF
0.10
0.01
SOURCE OFF
0.5
0
10
100
1k
FREQUENCY (Hz)
10k
100k
0
2
4
6
8
10
12
V
(V)
BIAS
Figure 17. THD + N vs. Frequency
Figure 19. Capacitance vs. Source Voltage, Single Supply
Rev. B | Page 11 of 16
ADG1211/ADG1212/ADG1213
TEST CIRCUITS
Data Sheet
I
DS
V1
I
D
(ON)
A
I
(OFF)
A
I
(OFF)
A
S
D
S
D
S
D
S
D
NC
V
R
= V1/I
DS
V
D
V
V
D
S
ON
S
NC = NO CONNECT
Figure 20. On Resistance
Figure 21. Off Leakage
Figure 22. On Leakage
V
V
DD
SS
0.1µF
0.1µF
ADG1212
V
V
50%
50%
50%
IN
V
V
SS
DD
V
L
OUT
S
D
50%
90%
IN
ADG1211
R
300Ω
C
L
V
S
35pF
IN
90%
V
OUT
GND
tOFF
tON
Figure 23. Switching Times
V
V
DD
SS
V
0.1µF
0.1µF
IN
50%
50%
0V
0V
V
V
SS
DD
90%
90%
V
V
S1
D1
OUT1
OUT2
V
V
V
S1
OUT1
C
35pF
R
300Ω
L
L
S2
D2
V
S2
OUT2
C
35pF
R
300Ω
L
L
90%
90%
IN1,
IN2
0V
ADG1213
GND
tD
tD
Figure 24. Break-Before-Make Time Delay
V
V
V
DD
SS
V
DD
SS
V
ADG1212
IN
ON
OFF
V
R
S
OUT
S
D
C
1nF
L
V
V
S
IN
ADG1211
IN
V
OUT
DV
OUT
GND
Q
= C × DV
L
OUT
INJ
Figure 25. Charge Injection
Rev. B | Page 12 of 16
Data Sheet
ADG1211/ADG1212/ADG1213
V
V
V
DD
V
DD
SS
SS
0.1µF
0.1µF
0.1µF
0.1µF
NETWORK
ANALYZER
NETWORK
ANALYZER
V
V
V
DD
V
DD
SS
SS
S
S
50Ω
50Ω
50Ω
IN
IN
V
S
V
S
D
D
V
V
OUT
OUT
V
V
IN
R
50Ω
IN
R
50Ω
L
L
GND
GND
V
V
WITH SWITCH
OUT
OUT
OFF ISOLATION = 20 LOG
INSERTION LOSS = 20 LOG
V
S
V
WITHOUT SWITCH
OUT
Figure 26. Off Isolation
Figure 28. Bandwidth
V
V
DD
SS
V
V
DD
SS
0.1µF
0.1µF
0.1µF
0.1µF
NETWORK
ANALYZER
AUDIO PRECISION
V
V
DD
SS
V
V
DD
SS
V
OUT
R
S
S1
R
L
50Ω
S
D
IN
R
50Ω
V
V p-p
S
S2
D
V
OUT
V
V
IN
S
R
L
10kΩ
GND
GND
V
OUT
CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG
V
S
Figure 27. Channel-to-Channel Crosstalk
Figure 29. THD + Noise
Rev. B | Page 13 of 16
ADG1211/ADG1212/ADG1213
OUTLINE DIMENSIONS
Data Sheet
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 30. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
0.50
0.40
0.60 MAX
0.30
3.00
BSC SQ
PIN 1
INDICATOR
BOTTOM VIEW
*
1.65
1.50 SQ
1.35
13
12
16
1
0.45
PIN 1
INDICATOR
2.75
BSC SQ
TOP
VIEW
EXPOSED
PAD
4
9
8
0.50
BSC
5
0.25 MIN
1.50 REF
0.80 MAX
12° MAX
0.65 TYP
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.90
0.85
0.80
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
*
COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2
EXCEPT FOR EXPOSED PAD DIMENSION.
Figure 31. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
3 mm × 3 mm Body, Very Thin Quad
(CP-16-3)
Dimensions shown in millimeters
Rev. B | Page 14 of 16
Data Sheet
ADG1211/ADG1212/ADG1213
ORDERING GUIDE
Model1
ADG1211YRUZ
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
Package Option Branding
Thin Shrink Small Outline Package (TSSOP)
Thin Shrink Small Outline Package (TSSOP)
Thin Shrink Small Outline Package (TSSOP)
Lead Frame Chip Scale Package (LFCSP_VQ)
Lead Frame Chip Scale Package (LFCSP_VQ)
Thin Shrink Small Outline Package (TSSOP)
Thin Shrink Small Outline Package (TSSOP)
Thin Shrink Small Outline Package (TSSOP)
Lead Frame Chip Scale Package (LFCSP_VQ)
Lead Frame Chip Scale Package (LFCSP_VQ)
Thin Shrink Small Outline Package (TSSOP)
Thin Shrink Small Outline Package (TSSOP)
Thin Shrink Small Outline Package (TSSOP)
Lead Frame Chip Scale Package (LFCSP_VQ)
Lead Frame Chip Scale Package (LFCSP_VQ)
RU-16
RU-16
RU-16
ADG1211YRUZ-REEL
ADG1211YRUZ-REEL7
ADG1211YCPZ-500RL7
ADG1211YCPZ-REEL7
ADG1212YRUZ
ADG1212YRUZ-REEL
ADG1212YRUZ-REEL7
ADG1212YCPZ-500RL7
ADG1212YCPZ-REEL7
ADG1213YRUZ
CP-16-3
CP-16-3
RU-16
S07
S07
RU-16
RU-16
CP-16-3
CP-16-3
RU-16
S08
S08
ADG1213YRUZ-REEL
ADG1213YRUZ-REEL7
ADG1213YCPZ-500RL7
ADG1213YCPZ-REEL7
RU-16
RU-16
CP-16-3
CP-16-3
S09
S09
1 Z = RoHS Compliant Part.
Rev. B | Page 15 of 16
ADG1211/ADG1212/ADG1213
NOTES
Data Sheet
©2005–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04778-0-8/12(B)
Rev. B | Page 16 of 16
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