ADE7757 [ADI]
Energy Metering IC with Integrated Oscillator; 电能计量IC，具有集成振荡器
| 型号： | ADE7757 |
| 厂家： | 
ADI |
| 描述： | Energy Metering IC with Integrated Oscillator |
| 文件： | 总14页 (文件大小：532K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY TECHNICAL DATA
Energy Metering IC
a
Preliminary Technical Data
with Integrated Oscillator
ADE7757*
The ADE7757 specifications surpass the accuracy require-
ments as quoted in the IEC1036 standard. Due to the
similarity between the ADE7757 and AD7755, the Appli-
cation Note AN-559 can be used as a basis for a descrip-
tion of an IEC1036 low cost watt-hour meter reference
design.
FEATURES
On Chip Oscillator as clock source
High Accuracy, Supports 50 Hz/60 Hz IEC 521/1036
Less than 0.1% Error Over a Dynamic Range of
500 to 1
The ADE7757 Supplies Average Real Power on the
Frequency Outputs F1 and F2
The only analog circuitry used in the ADE7757 is in the
sigma-delta ADCs and reference circuit. All other signal
processing (e.g., multiplication and filtering) is carried
out in the digital domain. This approach provides superior
stability and accuracy over time and extreme environmen-
tal conditions.
The High Frequency Output CF Is Intended for
Calibration and Supplies Instantaneous Real Power
Direct Drive for Electromechanical Counters and
Two Phase Stepper Motors (F1 and F2)
Proprietary ADCs and DSP Provide High Accuracy over
Large Variations in Environmental Conditions and
Time
On-Chip Power Supply Monitoring
On-Chip Creep Protection (No Load Threshold)
On-Chip Reference 2.5 V ؎ 8% (30 ppm/؇C Typical)
with External Overdrive Capability
Single 5 V Supply, Low Power (15 mW Typical)
Low Cost CMOS Process
The ADE7757 supplies average real power information on
the low frequency outputs F1 and F2. These outputs may
be used to directly drive an electromechanical counter or
interface with an MCU. The high frequency CF logic
output, ideal for calibration purposes, provides instanta-
neous real power information.
The ADE7757 includes a power supply monitoring circuit
on the VDD supply pin. The ADE7757 will remain in reset
mode until the supply voltage on VDD reaches approxi-
mately 4 V. If the supply falls below 4 V, the ADE7757
will also reset and the F1, F2 and CF outputs will be in
their non-active modes.
AC Input only
GENERAL DESCRIPTION
The ADE7757 is a high accuracy electrical energy mea-
surement IC. It is a pin reduction version of AD7755
with an enhancement of a precise oscillator circuit that
serves as a clock source to the chip. The ADE7757
eliminates the cost of an external crystal or resonator,
thus reducing the overall cost of a meter built with this
IC. The chip directly interfaces with shunt resistor and
only operates with AC input.
Internal phase matching circuitry ensures that the voltage
and current channels are phase matched while the HPF in
the current channel eliminates dc offsets. An internal no-
load threshold ensures that the ADE7757 does not exhibit
creep when no load is present.
The ADE7757 is available in 16-lead SOIC narrow-body
package.
FUNCTIONAL BLOCK DIAGRAM
V
AGND
DGND
DD
ADE7757
POWER
SUPPLY MONITOR
SIGNAL
PROCESSING
BLOCK
V2P
V2N
...110101...
∑ ∆
ADC
MULTIPLIER
PHASE
LPF
CORRECTION
HPF
...11011001...
V1N
V1P
∑ ∆
Φ
ADC
DIGITAL-TO-FREQUENCY
CONVERTER
4kV
2.5V
REFERENCE
INTERNAL
OSCILLATOR
RCLKIN
F1
REF
IN/OUT
RESERVED
CF
SCF S0 S1
F2
*U.S. Patents 5,745,323, 5,760,617, 5,862,069, 5,872,469; other pending.
REV. PrC.
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, USA.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., February 2002
PRELIMINARY TECHNICAL DATA
(VDD = 5 V ؎ 5%, AGND = DGND = 0 V, On-Chip Reference, rCKLIN = 5 kΩ 0.1% 5ppm/°C,
TMIN to TMAX = –40؇C to +85؇C)
ADE7757–SPECIFICATIONS
Parameter
Value
Units
Test Conditions/Comments
ACCURACY1,2
Measurement Error1 on Channel V1
Channel V2 with Full-Scale Signal ( 165 mV),+25°C
TBD
% Reading typ Over a Dynamic Range 500 to 1
Phase Error1 Between Channels
V1 Phase Lead 37°
Line Frequency = 45 Hz to 65 Hz
(PF = 0.8 Capacitive)
V1 Phase Lag 60°
0.1
0.1
Degrees(°) max
(PF = 0.5 Inductive)
Degrees(°) max
AC Power Supply Rejection1
Output Frequency Variation (CF)
S0 = S1 = 1,
TBD
% Reading typ V1 = V2 = 100 mV rms, @50 Hz
Ripple on VDD of 200 mV rms @ 100 Hz
S0 = S1 = 1,
DC Power Supply Rejection1
Output Frequency Variation (CF)
TBD
% Reading typ V1 = 100 mV rms, V2 = 100 mV rms,
V
DD = 5 V 250 mV
ANALOGINPUTS
SeeAnalogInputsSection
ChannelV1MaximumSignalLevel
ChannelV2MaximumSignalLevel
InputImpedance(DC)
30
165
TBD
7
25
TBD
mVmax
mV max
kΩ min
kHz typ
mVmax
% Ideal typ
V1P and V1N to AGND
V2N and V2P to AGND
rCKLIN = 5 kΩ 0.1% 5ppm/°C
rCKLIN = 5 kΩ 0.1% 5ppm/°C
SeeTerminologyandPerformanceGraphs
External 2.5 V Reference,
Bandwidth(–3dB)
ADC Offset Error1,2
FrequencyOutputError1
V1 = 30 mV DC, V2 = 165 mV dc
External 2.5 V Reference, Gain = 1
V1 = 30 mV dc, V2 = 165 mV dc
GainError1
7
% Ideal typ
REFERENCEINPUT
REFIN/OUT Input Voltage Range
2.7
2.3
TBD
10
Vmax
V min
kΩ min
pFmax
2.5 V + 8%
2.5 V – 8%
InputImpedance
InputCapacitance
ON-CHIPREFERENCE
ReferenceError
TemperatureCoefficient
Nominal 2.5 V
200
30
mV max
ppm/°Ctyp
ppm/°Cmax
LOGICINPUTS3
SCF,S0,S1,
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
2.4
0.8
3
V min
VDD = 5 V 5%
VDD = 5 V 5%
Typically 10 nA, VIN = 0 V to VDD
Vmax
µAmax
pFmax
InputCapacitance,CIN
10
LOGICOUTPUTS3
F1 and F2
Output High Voltage, VOH
ISOURCE = 10 mA
VDD = 5 V
ISINK = 10 mA
4.5
0.5
V min
Vmax
Output Low Voltage, VOL
V
DD = 5 V
CF
Output High Voltage, VOH
ISOURCE = 5 mA
VDD = 5 V
ISINK = 5 mA
VDD = 5 V
4
V min
Vmax
Output Low Voltage, VOL
0.5
POWER SUPPLY
VDD
For Specified Performance
4.75
5.25
TBD
V min
V max
TBD
5 V – 5%
5 V + 5%
TBD
IDD
NOTES
1 SeeTerminologySectionforexplanationofspecifications.
2 See Plots in Typical Performance Graphs.
3Sample tested during initial release and after any redesign or process change that may affect this parameter.
Specifications subject to change without notice.
REV. PrC.
–2–
PRELIMINARY TECHNICAL DATA
ADE7757
(VDD = 5 V ؎ 5%, AGND = DGND = 0 V, On-Chip Reference, rCKLIN = 5 kΩ 0.1% 5ppm/°C,
TIMING CHARACTERISTICS1, 2
TMIN to TMAX = –40؇C to +85؇C)
Parameter
A, B Versions
Units
TestConditions/Comments
t13
t2
550
See Table II
1/2 t2
180
See Table III
TBD
ms
sec
sec
ms
sec
sec
F1 and F2 Pulsewidth (Logic Low)
Output Pulse Period. See Transfer Function Section
Time Between F1 Falling Edge and F2 Falling Edge
CF Pulsewidth (Logic High)
CF Pulse Period. See Transfer Function Section
Minimum Time Between F1 and F2 Pulse
t33,4
t4
t5
t6
NOTES
1Sample tested during initial release and after any redesign or process change that may affect this parameter.
2See Figure 1.
3The pulsewidths of F1, F2 and CF are not fixed for higher output frequencies. See Frequency Outputs Section.
4The CF pulse is always 18 µs in the high frequency mode. See Frequency Outputs section and Table III.
Specifications subject to change without notice.
t1
F1
.t6
.t2
F2
.t3
.t5
t4
CF
Figure 1. Timing Diagram for Frequency Outputs
ORDERING GUIDE
Model
Package Description
SOIC narrow-body
Evaluation Board
Package Options
ADE7757ARN
EVAL-ADE7757EB
RN-16
Evaluation Board
REV. PrC.
–3–
PRELIMINARY TECHNICAL DATA
ADE7757
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
16-Lead Plastic SOIC, Power Dissipation . . . . . . . . . 350mW
JA Thermal Impedance** . . . . . . . . . . . . . . . . . 124.9°C/W
Lead Temperature, Soldering
θ
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Analog Input Voltage to AGND
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . +220°C
V1P, V1N, V2P and V2N . . . . . . . . . . . . . . . –6 V to +6 V
Reference Input Voltage to AGND . . . –0.3 V to VDD + 0.3 V
Digital Input Voltage to DGND . . . . . –0.3 V to VDD + 0.3 V
Digital Output Voltage to DGND . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (A, B Versions) . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C
*Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
**JEDEC 1S Standard (2 layer) Board Data
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADE7757 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
TERMINOLOGY
ADC OFFSET ERROR
This refers to the small dc signal (offset) associated with the
analog inputs to the ADCs. However, the HPF in Channel V1
eliminates the offset in the circuitry. Therefore, the power cal-
culation is not affected by this offset.
MEASUREMENT ERROR
The error associated with the energy measurement made by the
ADE7757 is defined by the following formula:
Energyregisteredby ADE7757−TrueEnergy
FREQUENCY OUTPUT ERROR
%Error =
×100%
TrueEnergy
The frequency output error of the ADE7757 is defined as
the difference between the measured output frequency (mi-
nus the offset) and the ideal output frequency. The differ-
ence is expressed as a percentage of the ideal frequency.
The ideal frequency is obtained from the ADE7757 trans-
fer function—see Transfer Function section.
PHASE ERROR BETWEEN CHANNELS
The HPF (High Pass Filter) in the current channel (Channel
V1) has a phase lead response. To offset this phase response
and equalize the phase response between channels, a phase
correction network is also placed in Channel V1. The phase
correction network matches the phase to within ±±.1° over a
range of 45 Hz to 65 Hz and ±±.ꢀ° over a range 4± Hz to 1
kHz. See Figures 19 and ꢀ±.
GAIN ERROR
The gain error of the ADE7757 is defined as the differ-
ence between the measured output frequency (minus the
offset) and the ideal output frequency. It is measured with
a gain of 1 in channel V1. The difference is expressed as a
percentage of the ideal frequency. The ideal frequency is
obtained from the ADE7757 transfer function—see Trans-
fer Function section.
POWER SUPPLY REJECTION
This quantifies the ADE7757 measurement error as a percent-
age of reading when the power supplies are varied.
For the ac PSR measurement a reading at nominal supplies
(5 V) is taken. A ꢀ±± mV rms/1±± Hz signal is then introduced
onto the supplies and a second reading obtained under the
same input signal levels. Any error introduced is expressed as a
percentage of reading—see Measurement Error definition.
For the dc PSR measurement a reading at nominal supplies
(5 V) is taken. The supplies are then varied ±5% and a second
reading is obtained with the same input signal levels. Any error
introduced is again expressed as a percentage of reading.
REV. PrC.
–4–
PRELIMINARY TECHNICAL DATA
ADE7757
PIN FUNCTION DESCRIPTIONS
Description
Pin No.
Mnemonic
1
VDD
Power Supply. This pin provides the supply voltage for the circuitry in the ADE7757. The
supply voltage should be maintained at 5 V ± 5% for specified operation. This pin should be
decoupled with a 1± µF capacitor in parallel with a ceramic 1±± nF capacitor.
ꢀ,3
4, 5
6
VꢀP, VꢀN
V1N, V1P
AGND
Analog Inputs for Channel Vꢀ (voltage channel). These inputs provide a fully differential
input pair. The maximum differential input voltage is ±165 mV for specified operation. The
maximum signal level at these pins is ±165 mV with respect to AGND. Both inputs have
internal ESD protection circuitry and an overvoltage of ±6 V can also be sustained on these
inputs without risk of permanent damage.
Analog Inputs for Channel V1 (current channel). These inputs are fully differential voltage
inputs with a maximum signal level of ±3± mV with respect to pin V1N for specified opera-
tion. The maximum signal level at this pin is ±165 mV with respect to AGND. Both inputs
have internal ESD protection circuitry and in addition an overvoltage of ±6 V can be sus-
tained on these inputs without risk of permanent damage.
This provides the ground reference for the analog circuitry in the ADE7757, i.e., ADCs and
reference. This pin should be tied to the analog ground plane of the PCB. The analog ground
plane is the ground reference for all analog circuitry, e.g., antialiasing filters, current and
voltage sensors, etc. For accurate noise suppression, the analog ground plane should only be
connected to the digital ground plane at one point. A star ground configuration will help to
keep noisy digital currents away from the analog circuits.
7
REFIN/OUT
This pin provides access to the on-chip voltage reference. The on-chip reference has a nomi-
nal value of ꢀ.5 V ± ꢁ% and a typical temperature coefficient of 3± ppm/°C. An external
reference source may also be connected at this pin. In either case this pin should be
decoupled to AGND with a 1 µF tantalum capacitor and 1±± nF ceramic capacitor.
ꢁ
SCF
Select Calibration Frequency. This logic input is used to select the frequency on the calibra-
tion output CF. Table III shows calibration frequencies selection.
9,1±
S1, S±
These logic inputs are used to select one of four possible frequencies for the digital-to-fre-
quency conversion. With this logic input, designers have greater flexibility when designing an
energy meter. See Selecting a Frequency for an Energy Meter Application.
11
RCLKIN
To enable the internal oscillator as a clock source to the chip, a precise 5 kΩ resistor must be
connected from this pin to DGND.
1ꢀ
13
RESERVED
DGND
Reserved pin. No load should be connected to this pin.
This provides the ground reference for the digital circuitry in the ADE7757, i.e., multiplier,
filters and digital-to-frequency converter. This pin should be tied to the digital ground plane
of the PCB. The digital ground plane is the ground reference for all digital circuitry, e.g.,
counters (mechanical and digital), MCUs and indicator LEDs. For accurate noise suppres-
sion the analog ground plane should only be connected to the digital ground plane at one
point only, e.g., a star ground.
14
C F
Calibration Frequency Logic Output. The CF logic output provides instantaneous real power
information. This output is intended for calibration purposes. Also see SCF pin description.
15,16
Fꢀ,F1
Low Frequency Logic Outputs. F1 and Fꢀ supply average real power information. The logic
outputs can be used to directly drive electromechanical counters and two phase stepper mo-
tors. See Transfer Function.
1
2
3
4
5
6
7
8
V
16
15
14
13
12
F1
DD
V2P
V2N
F2
PINCONFIGURATION
SOIC-16nb Package
CF
V1N
ADE7757
TOP VIEW
(Not to Scale)
DGND
RESERVED
V1P
AGND
11 RCLKIN
REF
10
S0
IN/OUT
SCF
9
S1
REV. PrC.
–5–
PRELIMINARY TECHNICAL DATA
–Typical Performance Characteristics
ADE7757
TBD
TBD
Figure 5. Error as a % of Reading over Temperature with
External Reference (PF=0.5)
Figure 2. Error as a % Reading over Temperature on-chip
reference (PF=1)
TBD
TBD
Figure 3. Error as a % of Reading over Temperature with
on-chip reference (PF=0.5)
Figure 6. Error as a %of Reading over Input Frequency
V
DD
100nF
10µF
K7
K8
VDD
U3
Ω
Ω
602k
F1
V2P
V2N
150nF
220V
200
F2
U1
ADE7757
CF
200Ω
PS2501-1
150nF
40A TO
40mA
RESERVED
RCLKIN
Ω
200
TBD
5 kΩ
V1P
V1N
150nF
V
DD
500µΩ
Ω
200
10kΩ
150nF
S0
S1
REF
IN/OUT
SCF
AGND DGND
100nF
1µF
10nF
10nF
10nF
Figure 4. Error as a % of Reading over Temperature with
External Reference (PF=1)
Figure 7. Test Circuit for Performance Curves
–6–
REV. PrC.
PRELIMINARY TECHNICAL DATA
ADE7757
TBD
TBD
Figure 10. PSR with External Reference
Figure 8. Channel V1 Offset Distribution
TBD
Figure 9. PSR with Internal Reference
–7–
REV. PrC.
PRELIMINARY TECHNICAL DATA
ADE7757
THEORY OF OPERATION
phase. Figure 1ꢀ displays the unity power factor condition
and a DPF (Displacement Power Factor) = ±.5, i.e., cur-
rent signal lagging the voltage by 6±°. If we assume the
voltage and current waveforms are sinusoidal, the real
power component of the instantaneous power signal (i.e.,
the dc term) is given by:
The two ADCs digitize the voltage signals from the cur-
rent and voltage sensors. These ADCs are 16-bit sigma-
delta with an oversampling rate of 45± kHz. This analog
input structure greatly simplifies sensor interfacing by
providing a wide dynamic range for direct connection to
the sensor and also simplifies the antialiasing filter design.
A high pass filter in the current channel removes any dc
component from the current signal. This eliminates any
inaccuracies in the real power calculation due to offsets in
the voltage or current signals. Because the HPF is always
enabled, the IC will only operate with AC Input—see HPF
and Offset Effects.
V × I
2
× cos(60°)
This is the correct real power calculation.
INSTANTANEOUS
POWER SIGNAL
INSTANTANEOUS REAL
POWER SIGNAL
POWER
The real power calculation is derived from the instanta-
neous power signal. The instantaneous power signal is
generated by a direct multiplication of the current and
voltage signals. In order to extract the real power compo-
nent (i.e., the dc component), the instantaneous power
signal is low-pass filtered. Figure 11 illustrates the instan-
taneous real power signal and shows how the real power
information can be extracted by low-pass filtering the in-
stantaneous power signal. This scheme correctly calculates
real power for sinusoidal current and voltage waveforms at
all power factors. All signal processing is carried out in the
digital domain for superior stability over temperature and
time.
×
2
V
I
TIME
0V
CURRENT
VOLTAGE
POWER
INSTANTANEOUS
POWER SIGNAL
INSTANTANEOUS REAL
POWER SIGNAL
×
2
V
I
°
cos(60 )
TIME
0V
DIGITAL-TO-
FREQUENCY
HPF
F1
F2
⌺
PGA
CH1
CH2
ADC
MULTIPLIER
VOLTAGE
CURRENT
LPF
°
60
DIGITAL-TO-
FREQUENCY
ADC
⌺
CF
Figure 12. DC Component of Instantaneous Power Signal
Conveys Real Power Information PF < 1
INSTANTANEOUS
POWER SIGNAL- p (t)
INSTANTANEOUS REAL
POWER SIGNAL
Nonsinusoidal Voltage and Current
The real power calculation method also holds true for
nonsinusoidal current and voltage waveforms. All voltage and
current waveforms in practical applications will have some
harmonic content. Using the Fourier Transform, instantaneous
voltage and current waveforms can be expressed in terms of
their harmonic content.
V
؋
I p(t) = i(t)
؋
v(t) WHERE:
V
؋
I 2
v(t) = V
؋
cos(t) i(t) = I
؋
cos(t) V
؋
I {1+cos(2t)}
V
؋
I 2
p(t) =
2
TIME
∞
Figure 11. Signal Processing Block Diagram
v(t) = V0 + 2 × Vh × sin (hωt + αh)
∑
(1)
The low frequency outputs (F1, Fꢀ) of the ADE7757 is
generated by accumulating this real power information.
This low frequency inherently means a long accumulation
time between output pulses. Consequently, the resulting
output frequency is proportional to the average real power.
This average real power information is then accumulated
(e.g., by a counter) to generate real energy information.
Conversely, due to its high output frequency and hence
shorter integration time, the CF output frequency is pro-
portional to the instantaneous real power. This is useful
for system calibration, which can be done faster under
steady load conditions.
h≠0
where:
v(t) is the instantaneous voltage
VO is the average value
Vh
and
is the rms value of voltage harmonic h
␣h is the phase angle of the voltage harmonic.
∞
i(t) = I0 + 2 × Ih × sin (hωt +βh)
∑
(ꢀ)
h≠0
where:
i(t) is the instantaneous current
IO is the dc component
Power Factor Considerations
The method used to extract the real power information from
the instantaneous power signal (i.e., by low-pass filtering) is still
valid even when the voltage and current signals are not in
Ih
is the rms value of current harmonic h
and
h is the phase angle of the current harmonic.
–8–
REV. PrC.
PRELIMINARY TECHNICAL DATA
ADE7757
Using Equations 1 and ꢀ, the real power P can be ex-
pressed in terms of its fundamental real power (P1) and
harmonic real power (PH).
Channel V2 (Voltage Channel)
The output of the line voltage sensor is connected to the
ADE7757 at this analog input. Channel Vꢀ is a fully differen-
tial voltage input with maximum peak differential signal
of ±165 mV. Figure 14 illustrates the maximum signal
levels that can be connected to the ADE7757 Channel Vꢀ.
P = P + PH
1
where:
V2
+165mV
P = V × I1 cosφ1
φ1 = α1 −β1
1
1
V2P
V2N
(3)
DIFFERENTIAL INPUT
V2
165mV MAX PEAK
V
CM
COMMON-MODE
25mV MAX
V
CM
and
AGND
-165mV
∞
Figure 14. Maximum Signal Levels, Channel V2
PH =
Vh × Ih cosφh
∑
h≠1
Channel Vꢀ is usually driven from a common-mode volt-
age, i.e., the differential voltage signal on the input is
referenced to a common mode (usually AGND). The
analog inputs of the ADE7757 can be driven with com-
mon-mode voltages of up to ꢀ5 mV with respect to
AGND. However best results are achieved using a com-
mon mode equal to AGND.
(4)
φh = αh −βh
As can be seen from Equation 4 above, a harmonic real
power component is generated for every harmonic, pro-
vided that harmonic is present in both the voltage and
current waveforms. The power factor calculation has pre-
viously been shown to be accurate in the case of a pure
sinusoid, therefore the harmonic real power must also
correctly account for power factor since it is made up of a
series of pure sinusoids.
Typical Connection Diagrams
Figure 15 shows a typical connection diagram for Channel V1.
A shunt is the current sensor selected for this example because of
its low cost compared to other current sensors such as the CT
(current transformer). This IC is ideal for low current
meters.
Note that the input bandwidth of the analog inputs is
14 kHz with.
Rf
V1P
V1N
ANALOG INPUTS
Cf
Cf
30mV
Channel V1 (Current Channel )
SHUNT
The voltage output from the current sensor is connected to the
ADE7757 here. Channel V1 is a fully differential voltage input.
V1P is the positive input with respect to V1N.
Rf
AGND
NEUTRAL
PHASE
The maximum peak differential signal on Channel V1 should
be less than ±3± mV (ꢀ1 mV rms for a pure sinusoidal signal)
for specified operation.
Figure 15. Typical Connection for Channel V1
Figure 16 shows a typical connection for Channel Vꢀ.
Typically, ADE7757 is biased around the neutral wire,
and a resistor divider is used to provide a voltage signal
that is proportional to the line voltage. Adjusting the ratio
of Ra, Rb and VR is also a convenient way of carrying out
a gain calibration on a meter.
V1
+30mV
V1P
DIFFERENTIAL INPUT
V1
30mV MAX PEAK
V1N
V
CM
Cf
COMMON-MODE
6.25mV MAX
*
Ra
V
CM
*
Rb
AGND
V2P
V2N
165mV
-30mV
*
VR
Rf
Cf
Figure 13. Maximum Signal Levels, Channel V1
*
*
Ra>> Rf + VR
Rb+ VR = Rf
PHASE NEUTRAL
The diagram in Figure 13 illustrates the maximum signal
levels on V1P and V1N. The maximum differential voltage
is ±3± mV. The differential voltage signal on the inputs
must be referenced to a common mode, e.g. AGND. The
maximum common mode signal is ±6.ꢀ5 mV as shown in
Figure 13.
Figure 16. Typical Connections for Channel V2
–9–
REV. PrC.
PRELIMINARY TECHNICAL DATA
ADE7757
POWER SUPPLY MONITOR
The ADE7757 contains an on-chip power supply monitor.
The power supply (VDD) is continuously monitored by the
ADE7757. If the supply is less than 4 V, the ADE7757
will reset. This is useful to ensure proper device operation
at power-up and power-down. The power supply monitor
has built in hysteresis and filtering that provide a high
degree of immunity to false triggering from noisy sup-
plies.
DC COMPONENT (INCLUDING ERROR TERM) IS
EXTRACTED BY THE LPF FOR REAL POWER CALCULATION
×
V
I
os
os
×
V
I
2
×
I
V
I
os
×
V
os
As can be seen from Figure 17, the trigger level is nomi-
nally set at 4 V. The tolerance on this trigger level is
within ±5%. The power supply and decoupling for the
part should be such that the ripple at VDD does not exceed
5 V ± 5% as specified for normal operation.
0
FREQUENCY - Rad/s
Figure 18. Effect of Channel Offset on the Real Power
Calculation
The HPF in Channel V1 has an associated phase response
that is compensated for on-chip. Figures 19 and ꢀ± show
the phase error between channels with the compensation
network activated. The ADE7757 is phase compensated up
to 1 kHz as shown. This will ensure correct active har-
monic power calculation even at low power factors.
V
DD
5V
4V
0V
0.30
0.25
0.20
0.15
TIME
INTERNAL
ACTIVATION
INACTIVE
ACTIVE
INACTIVE
0.10
0.05
0
Figure 17. On-Chip Power Supply Monitor
HPF and Offset Effects
Figure 1ꢁ illustrates the effect of offsets on the real power cal-
culation. As can be seen, offsets on Channel V1 and Channel
Vꢀ will contribute a dc component after multiplication. Since
this dc component is extracted by the LPF and used to gener-
ate the real power information, the offsets will contribute a
constant error to the real power calculation. This problem is
easily avoided by the built-in HPF in Channel V1. By removing
the offsets from at least one channel, no error component can
be generated at dc by the multiplication. Error terms at the line
frequency (ω) are removed by the LPF and the digital-to-
frequency conversion—see Digital-to-Frequency Conver-
sion.
-0.05
-0.10
0
400
FREQUENCY - Hz
700
1000
900
100
200
300
500
600
800
Figure 19. Phase Error Between Channels (0 Hz to 1 kHz)
0.30
0.25
0.20
0.15
0.10
0.05
0
The equation below shows how power calculation is affected by
the dc offsets in the current and voltage channels:
{
Vcos(ωt) + Vos
V × I
}
× Icos(ωt) + Ios
{
=
}
+ Vos × Ios + Vos × Icos(ωt) + Ios × Vcos(ωt)
2
-0.05
-0.10
V × I
2
+
× cos(2ωt)
40
45
50
55
60
65
70
FREQUENCY - Hz
Figure 20. Phase Error Between Channels (40 Hz to 70 Hz)
–10–
REV. PrC.
PRELIMINARY TECHNICAL DATA
ADE7757
DIGITAL-TO-FREQUENCY CONVERSION
As previously described, the digital output of the low-pass filter
after multiplication contains the real power information. How-
ever, since this LPF is not an ideal “brick wall” filter imple-
mentation, the output signal also contains attenuated
components at the line frequency and its harmonics, i.e.,
cos(hωt) where h = 1, ꢀ, 3, . . . etc.
ing it to a frequency. This shorter accumulation period
means less averaging of the cos (ꢀωt) component. Conse-
quently, some of this instantaneous power signal passes
through the digital-to-frequency conversion. This will not
be a problem in the application. Where CF is used for
calibration purposes, the frequency should be averaged by
the frequency counter which will remove any ripple. If CF
is being used to measure energy; for example, in a micro-
processor-based application, the CF output should also be
averaged to calculate power.
The magnitude response of the filter is given by:
1
H( f ) =
2
Because the outputs F1 and Fꢀ operate at a much lower
frequency, a lot more averaging of the instantaneous real
power signal is carried out. The result is a greatly attenu-
ated sinusoidal content and a virtually ripple-free fre-
quency output.
f
(5)
1+
8.92
For a line frequency of 5± Hz this would give an attenua-
tion of the ꢀω (1±± Hz) component of approximately –
ꢀꢀ dB. The dominating harmonic will be at twice the line
frequency (ꢀω) due to the instantaneous power calculation.
Interfacing the ADE7757 to a Microcontroller for Energy
Measurement
Figure ꢀ1 shows the instantaneous real power signal at the
output of the LPF which still contains a significant amount
of instantaneous power information, i.e., cos (ꢀωt). This
signal is then passed to the digital-to-frequency converter
where it is integrated (accumulated) over time in order to
produce an output frequency. The accumulation of the
signal will suppress or average out any non-dc components
in the instantaneous real power signal. The average value
of a sinusoidal signal is zero. Hence the frequency gener-
ated by the ADE7757 is proportional to the average real
power. Figure ꢀ1 shows the digital-to-frequency conver-
sion for steady load conditions, i.e., constant voltage and
current.
The easiest way to interface the ADE7757 to a
microcontroller is to use the CF high frequency output
with the output frequency scaling set to ꢀ±4ꢁ x F1, Fꢀ.
This is done by setting SCF = ± and S± = S1 = 1, see
Table III. With full-scale ac signals on the analog inputs,
the output frequency on CF will be approximately
ꢀ.ꢁ67 kHz. Figure ꢀꢀ illustrates one scheme which could
be used to digitize the output frequency and carry out the
necessary averaging mentioned in the previous section.
CF
FREQUENCY
RIPPLE
AVERAGE
FREQUENCY
10%
F1
DIGITAL-TO-
FREQUENCY
F1
∑
TIME
V
MULTIPLIER
I
F2
LPF
TIME
MCU
DIGITAL-TO-
FREQUENCY
ADE7757
COUNTER
CF
∑
CF
CF
LPF TO EXTRACT
REAL POWER
(DC TERM)
TIME
TIMER
×
V
I
2
ω
cos(2 t)
ATTENUATED BY LPF
Figure 22. Interfacing the ADE7757 to an MCU
ω
ω
2
0
FREQUENCY (RAD/S)
As shown, the frequency output CF is connected to an
MCU counter or port. This will count the number of
pulses in a given integration time which is determined by
an MCU internal timer. The average power is propor-
tional to the average frequency is given by:
INSTANTANEOUS REAL POWER SIGNAL
(FREQUENCY DOMAIN)
Figure 21. Real Power-to-Frequency Conversion
As can be seen in the diagram, the frequency output CF is
seen to vary over time, even under steady load conditions.
This frequency variation is primarily due to the cos (ꢀωt)
component in the instantaneous real power signal. The
output frequency on CF can be up to ꢀ±4ꢁ times higher
than the frequency on F1 and Fꢀ. This higher output fre-
quency is generated by accumulating the instantaneous
real power signal over a much shorter time while convert-
Counter
Average Frequency= AveragePower =
Time
The energy consumed during an integration period is
given by:
Counter
Energy = AveragePower ×Time =
×Time = Counter
Time
–11–
REV. PrC.
PRELIMINARY TECHNICAL DATA
ADE7757
For the purpose of calibration, this integration time could
be 1± to ꢀ± seconds in order to accumulate enough pulses
to ensure correct averaging of the frequency. In normal
operation the integration time could be reduced to one or
two seconds depending, for example, on the required up-
date rate of a display. With shorter integration times on
the MCU the amount of energy in each update may still
have some small amount of ripple, even under steady load
conditions. However, over a minute or more the measured
energy will have no ripple.
Table I. F1–4 Frequency Selection
S1
S0
F1–4 (Hz)
±
±
1
1
±
1
±
1
±.ꢁ5
1.7
3.4
6.ꢁ
NOTE
*F1–4 is a binary fraction of the internal oscillator frequency
Example
Power Measurement Considerations
In this example, with ac voltages of ±3± mV peak applied
to V1 and ±165 mV peak applied to Vꢀ, the expected
output frequency is calculated as follows:
Calculating and displaying power information will always
have some associated ripple that will depend on the inte-
gration period used in the MCU to determine average
power and also the load. For example, at light loads the
output frequency may be 1± Hz. With an integration pe-
riod of two seconds, only about ꢀ± pulses will be counted.
The possibility of missing one pulse always exists as the
ADE7757 output frequency is running asynchronously to
the MCU timer. This would result in a one-in-twenty or
5% error in the power measurement.
F
= ±.ꢁ5 Hz, S± = S1 = ±
1−4
V1rms = ±.±3/ volts
2
V 2rms
= ±.165/
volts
2
Vref
= ꢀ.5 V (nominal reference value).
TRANSFER FUNCTION
Frequency Outputs F1 and F2
NOTE: If the on-chip reference is used, actual
output frequencies may vary from device to device
due to reference tolerance of ±ꢁ%.
The ADE7757 calculates the product of two voltage signals (on
Channel V1 and Channel Vꢀ) and then low-pass filters this
product to extract real power information. This real power
information is then converted to a frequency. The frequency
information is output on F1 and Fꢀ in the form of active low
pulses. The pulse rate at these outputs is relatively low,
e.g., ±.175 Hz maximum for ac signals with S± = S1 =
±—see Table II. This means that the frequency at these
outputs is generated from real power information accumu-
lated over a relatively long period of time. The result is an
output frequency that is proportional to the average real
power. The averaging of the real power signal is implicit
to the digital-to-frequency conversion. The output fre-
quency or pulse rate is related to the input voltage signals
by the following equation:
515 .85 × 0.03 × 0.165 × 0.85
Freq =
= 0.175
2 × 2 × 2.52
Table II. Maximum Output Frequency on F1 and F2
Max Frequency
S1
S0
for AC Inputs (Hz)
±
±
1
1
±
1
±
1
±.175
±.35
±.7
1.4
Frequency Output CF
515.84×V1rms ×V 2rms × F
The pulse output CF (Calibration Frequency) is intended for
calibration purposes. The output pulse rate on CF can be up to
ꢀ±4ꢁ times the pulse rate on F1 and Fꢀ. The lower the F1–4
frequency selected, the higher the CF scaling (except for the
high frequency mode SCF = ±, S1 = S± = 1). Table III shows
how the two frequencies are related, depending on the states of
the logic inputs S±, S1 and SCF. Due to its relatively high
pulse rate, the frequency at CF logic output is proportional to
the instantaneous real power. As with F1 and Fꢀ, CF is derived
from the output of the low-pass filter after multiplication. How-
ever, because the output frequency is high, this real power
information is accumulated over a much shorter time. Hence
less averaging is carried out in the digital-to-frequency con-
version. With much less averaging of the real power signal, the
CF output is much more responsive to power fluctua-
tions—see Signal Processing Block in Figure 11.
1−4
Freq=
2
Vref
where:
Freq
= Output frequency on F1 and Fꢀ (Hz)
V1rms = Differential rms voltage signal on Channel V1
(volts)
V 2rms
= Differential rms voltage signal on Channel Vꢀ
(volts)
Vref
= The reference voltage (ꢀ.5 V ± ꢁ%) (volts)
F
= One of four possible frequencies selected by us-
1−4
ing the logic inputs S± and S1—see Table I.
–12–
REV. PrC.
PRELIMINARY TECHNICAL DATA
ADE7757
Table III. Maximum Output Frequency on CF
SCF S1 S0 CF Max for AC Signals (Hz)
Column 4 of Table V. The closest frequency in Table V
will determine the best choice of frequency (F1–4). For
example, if a meter with a maximum current of ꢀ5 A is
being designed, the output frequency on F1 and Fꢀ with
a meter constant of 1±± imp/kWhr is ±.153 Hz at ꢀ5 A and
ꢀꢀ± V (from Table IV). Looking at Table V, the closest
frequency to ±.153 Hz in column four is ±.175 Hz. There-
fore F3 (3.4 Hz—see Table I) is selected for this design.
1
±
1
±
1
±
1
±
±
±
±
±
1
1
1
1
±
±
1
1
±
±
1
1
1ꢀꢁ x F1, Fꢀ = ꢀꢀ.4
64 x F1, Fꢀ = 11.ꢀ
64 x F1, Fꢀ = ꢀꢀ.4
3ꢀ x F1, Fꢀ = 11.ꢀ
3ꢀ x F1, Fꢀ = ꢀꢀ.4
16 x F1, Fꢀ = 11.ꢀ
16 x F1, Fꢀ = ꢀꢀ.4
ꢀ±4ꢁ x F1, Fꢀ = ꢀ.ꢁ67 kHz
Frequency Outputs
Figure 1 shows a timing diagram for the various frequency
outputs. The outputs F1 and Fꢀ are the low frequency outputs
that can be used to directly drive a stepper motor or elec-
tromechanical impulse counter. The F1 and Fꢀ outputs
provide two alternating low frequency pulses. The
pulsewidth (t1) is set such that if F1 and Fꢀ falls below
11±± ms (±.9±9 Hz) the pulsewidth of F1 and Fꢀ is set to
half of their period. The maximum output frequencies for
F1 and Fꢀ are shown in Table II.
SELECTING A FREQUENCY FOR AN ENERGY
METER APPLICATION
As shown in Table I, the user can select one of four fre-
quencies. This frequency selection determines the maxi-
mum frequency on F1 and Fꢀ. These outputs are intended
for driving an energy register (electromechanical or oth-
ers). Since only four different output frequencies can be
selected, the available frequency selection has been opti-
mized for a meter constant of 1±± imp/kWhr with a maxi-
mum current of between 1± A and 1ꢀ± A. Table IV shows
The high frequency CF output is intended to be used for
communications and calibration purposes. CF produces a
1ꢁ± ms-wide active high pulse (t4) at a frequency propor-
tional to active power. The CF output frequencies are
given in Table III. As in the case of F1 and Fꢀ, if the
period of CF (t5) falls below 36± ms, the CF pulsewidth is
set to half the period. For example, if the CF frequency is
ꢀ± Hz, the CF pulsewidth is ꢀ5 ms.
the output frequency for several maximum currents (IMAX
with a line voltage of ꢀꢀ± V. In all cases the meter con-
stant is 1±± imp/kWhr.
)
Table IV. F1 and F2 Frequency at 100 imp/kWhr
NOTE: When the high frequency mode is selected, (i.e.,
SCF = ±, S1 = S± = 1) the CF pulsewidth is fixed at
36 µs. Therefore t4 will always be 36 µs, regardless of
output frequency on CF.
IMAX
F1 and F2 (Hz)
1ꢀ.5 A
ꢀ5.± A
4±.± A
6±.± A
ꢁ±.± A
1ꢀ±.± A
±.±76
±.153
±.ꢀ44
±.367
±.4ꢁ9
±.733
NO LOAD THRESHOLD
The ADE7757 also includes a “no load threshold” and “start-
up current” feature that will eliminate any creep effects in
the meter. The ADE7757 is designed to issue a minimum
output frequency. Any load generating a frequency lower than
this minimum frequency will not cause a pulse to be issued on
F1, Fꢀ or CF. The minimum output frequency is given as
±.±±14% of the full-scale output frequency for each of the F1–4
frequency selections—see Table I. For example, an energy
meter with a meter constant of 1±± imp/kWhr on F1, Fꢀ
using F3 (3.4 Hz), the minimum output frequency at F1
or Fꢀ would be ±.±±14% of 3.4 Hz or 4.76 x 1±–5 Hz.
This would be 3.±5 x 1±–3 Hz at CF (64 x F1 Hz) when
SCF = S± = 1, S1 = ±. In this example the no load
threshold would be equivalent to 1.7 W of load or a start-
up current of ꢁ mA at ꢀꢀ± V. Comparing this value to
the IEC1±36 specification which states that the meter
must start up with a load equal to or less than ±.4% Ib.
For a 5A (Ib) meter ±.4% of Ib is equivalent to ꢀ± mA.
The F1–4 frequencies allow complete coverage of this range of
output frequencies (F1, Fꢀ). When designing an energy meter
the nominal design voltage on Channel Vꢀ (voltage) should be
set to half-scale to allow for calibration of the meter constant.
The current channel should also be no more than half-scale
when the meter sees maximum load. This will allow over cur-
rent signals and signals with high crest factors to be accommo-
dated. Table V shows the output frequency on F1 and Fꢀ when
both analog inputs are half-scale. The frequencies listed in
Table V align very well with those listed in Table IV for maxi-
mum load.
Table V. F1 and F2 Frequency with Half-Scale AC Inputs
Frequency on F1 and F2–
S1
S0
F1–4
CH1 and CH2 Half-Scale AC Inputs
±
±
1
1
±
1
±
1
±.ꢁ5
1.7
3.4
6.ꢁ
±.±43ꢁ Hz
±.±ꢁ75 Hz
±.175 Hz
±.35 Hz
When selecting a suitable F1–4 frequency for a meter de-
sign, the frequency output at IMAX (maximum load) with a
meter constant of 1±± imp/kWhr should be compared with
–13–
REV. PrC.
PRELIMINARY TECHNICAL DATA
ADE7757
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead SOIC narrow-body
0.3937 (10.00)
0.3859 (9.80)
16
9
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
1
8
PIN 1
0.0688 (1.75)
0.050 (1.27)
BSC
0.0196 (0.50)
0.0099 (0.25)
×
°
45
0.0532 (1.35)
°
°
8
0.0098 (0.25)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
SEATING
PLANE
0
0.0500 (1.27)
0.0160 (0.41)
0.0099 (0.25)
0.0075 (0.19)
–14–
REV. PrC.
相关型号：
ADE7757AARZ-RL
IC SPECIALTY ANALOG CIRCUIT, PDSO16, LEAD FREE, MS-012AC, SOIC-16, Analog IC:Other
ADI
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