ADAU1590ACPZ-RL7 [ADI]
Class-D Audio Power Amplifier; D类音频功率放大器
| 型号： | ADAU1590ACPZ-RL7 |
| 厂家： | 
ADI |
| 描述： | Class-D Audio Power Amplifier |
| 文件： | 总24页 (文件大小：588K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Class-D Audio Power Amplifier
ADAU1590
FEATURES
GENERAL DESCRIPTION
Integrated stereo modulator and power stage
0.005% THD + N
101 dB dynamic range
PSRR >55 dB
The ADAU1590 is a 2-channel, bridge-tied load (BTL)
switching audio power amplifier with an integrated Σ-Δ
modulator.
The modulator accepts an analog input signal and generates
a switching output to drive speakers directly. A digital,
microcontroller-compatible interface provides control of reset,
mute and PGA gain as well as output signals for thermal and
overcurrent error conditions. The output stage can operate
from supply voltages ranging from 9 V to 15 V. The analog
modulator and digital logic operate from a 3.3 V supply.
R
DS-ON < 0.3 Ω (per transistor)
Efficiency > 90% (8 Ω)
EMI-optimized modulator
On/off-mute pop-noise suppression
Short-circuit protection
Overtemperature protection
APPLICATIONS
Flat panel televisions
PC audio systems
Mini-components
FUNCTIONAL BLOCK DIAGRAM
PGA0
PGA1
PVDD
PGA
AINL
A1
A2
OUTL+
PGND
PVDD
B1
B2
OUTL–
SLC_TH
SLICER
PGND
PVDD
LEVEL SHIFT
AND DEAD
TIME CONTROL
Σ-Δ
MODULATOR
C1
C2
OUTR+
PGND
PVDD
AINR
PGA
D1
D2
PGA0
PGA1
OUTR–
PGND
AVDD
fCLK/2
VREF
VOLTAGE
REFERENCE
TEMPERATURE
OVERCURRENT
PROTECTION
AGND
CLOCK
OSCILLATOR
MODE CONTROL
LOGIC
DVDD
DGND
ADAU1590
XTI XTO MO/ST STDN MUTE ERR OTW
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2007 Analog Devices, Inc. All rights reserved.
ADAU1590
TABLE OF CONTENTS
Features .............................................................................................. 1
Slicer............................................................................................. 15
Power Stage ................................................................................. 16
Gain.............................................................................................. 16
Protection Circuits ..................................................................... 16
Thermal Protection.................................................................... 16
Overcurrent Protection ............................................................. 16
Undervoltage Protection ........................................................... 17
Clock Loss Detection................................................................. 17
Automatic Recovery from Protections.................................... 17
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Audio Performance ...................................................................... 3
DC Specifications ......................................................................... 4
Power Supplies .............................................................................. 4
Digital I/O ..................................................................................... 4
Digital Timing............................................................................... 5
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 15
Overview...................................................................................... 15
Modulator.................................................................................... 15
MUTE
STDN
...................................................................... 17
and
Power-Up/Power-Down Sequence .......................................... 18
DC Offset and Pop Noise.......................................................... 19
Selecting Value for CREF and CIN ............................................... 19
Mono Mode................................................................................. 19
Power Supply Bypassing............................................................ 19
Clock ............................................................................................ 20
Applications Information.............................................................. 21
Outline Dimensions....................................................................... 23
Ordering Guide........................................................................... 23
REVISION HISTORY
5/07—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
ADAU1590
SPECIFICATIONS
AVDD = DVDD = 3.3 V, PVDD = 12 V, ambient temperature = 25°C, load impedance = 6 Ω, clock frequency = 24.576 MHz,
measurement bandwidth = 20 Hz to 20 kHz, unless otherwise noted.
AUDIO PERFORMANCE
Table 1.
Parameter
OUTPUT POWER1
Min
Typ
Max
Unit
Test Conditions/Comments
1 kHz
7
9
9
11.5
12.5
15.5
87
W
W
W
W
W
W
%
1% THD + N, 8 Ω
10% THD + N , 8 Ω
1% THD + N, 6 Ω
10% THD + N, 6 Ω
1% THD + N , 4 Ω
10% THD + N , 4 Ω
@ 12 W, 6 Ω
EFFICIENCY
RDS-ON
@ TCASE = 25°C
Per High-Side Transistor
Per Low-Side Transistor
THERMAL CHARACTERISTICS
Thermal Warning Active2
Thermal Shutdown Active
OVERCURRENT SHUTDOWN ACTIVE
PVDD UNDERVOLTAGE SHUTDOWN
INPUT LEVEL FOR FULL-SCALE OUTPUT
0.28
0.25
Ω
Ω
@ 100 mA
@ 100 mA
135
150
6
°C
°C
A
Die temperature
Die temperature
Peak current
5
5.1
V
Full-scale output @ 1% THD + N
PGA gain = 0 dB
PGA gain = 6 dB
PGA gain = 12 dB
PGA gain = 18 dB
1.0
0.5
VRMS
VRMS
VRMS
VRMS
%
0.25
0.125
0.005
101
101
−90
TOTAL HARMONIC DISTORTION + NOISE (THD+N)
SIGNAL-TO-NOISE RATIO (SNR)
DYNAMIC RANGE (DNR)
CROSSTALK (LEFT TO RIGHT OR RIGHT TO LEFT)
AMPLIFIER GAIN
1 kHz, POUT = 1 W, PGA gain = 0 dB
A-weighted, referred to 1% THD + N output
A-weighted, measured with −60 dBFS input
@ full-scale output voltage, 1%THD + N, 1 kHz
PVDD = 12 V, 6 Ω
99
99
dB
dB
dB
PGA = 0 dB
PGA = 6 dB
PGA = 12 dB
PGA = 18 dB
17
23
29
35
dB
dB
dB
dB
OUTPUT NOISE VOLTAGE
PGA = 0 dB
PGA = 6 dB
PGA = 12 dB
PGA = 18 dB
PVDD = 12 V, 6 Ω
65
83
130
230
57
μV
μV
μV
μV
dB
POWER SUPPLY REJECTION RATIO (PSRR)
20 Hz to 20 kHz, 1.2 V p-p ripple, inputs ac-
coupled to AGND
1 Output powers above 12 W at 4 Ω and above 18 W at 6 Ω are not continuous and are thermally limited by the package dissipation.
2 Thermal warning flag is for indication of device TJ reaching close to shutdown temperature.
Rev. 0 | Page 3 of 24
ADAU1590
DC SPECIFICATIONS
Table 2.
Parameter
Min
Typ
20
3
Max
Unit
kΩ
Test Conditions/Comments
INPUT IMPEDANCE
OUTPUT DC OFFSET VOLTAGE
AINL/AINR
mV
POWER SUPPLIES
Table 3.
Parameter
Min
3.0
3.0
9
Typ
3.3
3.3
12
Max
3.6
3.6
15
Unit
Test Conditions/Comments
STDN held low
ANALOG SUPPLY VOLTAGE (AVDD)
V
V
V
DIGITAL SUPPLY VOLTAGE (DVDD)
POWER TRANSISTOR SUPPLY VOLTAGE (PVDD)
POWER-DOWN CURRENT
AVDD
DVDD
PVDD
6
0.14
0.06
60
0.24
0.25
μA
mA
mA
MUTE CURRENT
AVDD
DVDD
MUTE held low
13
1.8
4.5
20
3.2
8
mA
mA
mA
PVDD
OPERATING CURRENT
AVDD
DVDD
STDN and MUTE held high, no input
13
2.7
34
30
4
65
mA
mA
mA
PVDD
DIGITAL I/O
Table 4.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
INPUT VOLTAGE
Input Voltage High
Input Voltage Low
OUTPUT VOLTAGE
Output Voltage High
Output Voltage Low
LEAKAGE CURRENT ON DIGITAL INPUTS
2
2
V
V
0.8
V
V
@ 2 mA
@ 2 mA
0.4
10
μA
Rev. 0 | Page 4 of 24
ADAU1590
DIGITAL TIMING
Table 5.
Parameter
tWAIT
tINT
tHOLD
Min
Typ
10002
650
Unit
ms
ms
μs
Test Conditions/Comments
Wait time for unmute
Internal mute time
0.011
101
2503
Wait time for shutdown
tOUTx+/OUTx− SW
tOUTx+/OUTx− MUTE
200
μs
Time delay after MUTE held high until output starts switching
Time delay after MUTE held low until output stops switching
200
μs
1 tWAIT MIN and tHOLD MIN are the minimum times for fast turn-on and do not guarantee pop-and-click suppression.
2 tWAIT TYP is the recommended value for minimum pop and click during the unmute of the amplifier. The recommended value is 1 sec. It is calculated using the input
coupling capacitor value and the input resistance of the device. See the Power-Up/Power-Down Sequence section.
3 tHOLD TYP is the recommended value for minimum pop and click during the mute of the amplifier.
tHOLD MIN
STDN
tINT
INTERNAL MUTE
tWAIT MIN
MUTE
OUTx+/OUTx–
NOTES
1. INTERNAL MUTE IS INTERNAL TO CHIP.
Figure 2.Timing Diagram (Minimum)
tHOLD TYP
STDN
tINT
INTERNAL MUTE
tWAIT TYP
MUTE
OUTx+/OUTx–
NOTES
tOUTx+/OUTx– SW
tOUTx+/OUTx– MUTE
1. INTERNAL MUTE IS INTERNAL TO CHIP.
Figure 3. Timing Diagram (Typical)
Rev. 0 | Page 5 of 24
ADAU1590
ABSOLUTE MAXIMUM RATINGS
Table 6.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Parameter
Rating
DVDD to DGND
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−0.3 V to +20.0 V
DGND − 0.3 V to DVDD + 0.3 V
−40°C to +85°C
−65°C to +150°C
150°C
AVDD to AGND
PVDD to PGND1
Table 7. Thermal Resistance
1
1, 2
Package Type
θJA
θJC
ΨJB
8.05
11
ΨJT
Unit
°C/W
°C/W
MUTE/STDN Inputs
Operating Temperature Range
Storage Temperature Range
LFCSP-48
TQFP-48
24.6
24.7
2.0
1.63
0.18
0.8
1 With exposed pad (ePAD) soldered to 4-layer JEDEC standard PCB.
2 Through the bottom (ePAD) surface.
Maximum Junction
Temperature
Lead Temperature
Soldering (10 sec)
Vapor Phase (60 sec)
Infrared (15 sec)
260°C
215°C
220°C
ESD CAUTION
1 Includes any induced voltage due to inductive load.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 6 of 24
ADAU1590
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
OUTL–
OUTL–
OUTL–
OUTL+
OUTL+
OUTL+
TEST1
TEST0
ERR
1
2
3
4
5
6
7
8
9
36 OUTR–
35 OUTR–
34 OUTR–
33 OUTR+
32 OUTR+
31 OUTR+
30 TEST13
29 TEST12
28 AINR
PIN 1
INDICATOR
ADAU1590
TOP VIEW
(Not to Scale)
27 AINL
OTW 10
MO/ST 11
TEST3 12
26 TEST9
25 TEST8
NOTES
1. EPAD NOT SHOWN AND INTERNALLY CONNECTED TO
PGND, DGND, AND AGND FOR TQFP-48.
2. EPAD NOT SHOWN AND INTERNALLY CONNECTED TO
PGND AND DGND FOR LFCSP-48.
Figure 4. Pin Configuration
Table 8. Pin Function Descriptions
Pin. Number
Mnemonic
OUTL−
OUTL+
TEST1
TEST0
ERR
Type1
Description
1, 2, 3
4, 5, 6
7
8
9
O
O
I
Output of High Power Transistors, Left Channel Negative Polarity.
Output of High Power Transistors, Left Channel Positive Polarity.
Reserved for Internal Use. Connect to DGND.
Reserved for Internal Use. Connect to DGND.
Error Indicator (Active Low, Open-Drain Output).
I
O
O
I
10
OTW
Overtemperature Warning Indicator (Active Low Open-Drain Output).
11
MO/ST
TEST3
PGA1
PGA0
MUTE
STDN
XTI
Mono/Stereo Mode Setting Pin for Stereo. Connect to DGND (for mono mode, connect to DVDD).
Reserved for Internal Use. Connect to DVDD.
Programmable Gain Amplifier Select, MSB.
Programmable Gain Amplifier Select, LSB.
Mute (Active Low Input).
12
13
14
15
I
I
I
I
16
I
Shutdown/Reset Input (Active Low Input).
17
18
19
20
21
22
23
24
I
Quartz Crystal Connection/External Clock Input.
Quartz Crystal Connection/Clock Output.
Digital Ground for Digital Circuitry. Internally connected to exposed pad (ePAD).
Positive Supply for Digital Circuitry.
Positive Supply for Analog Circuitry. (Can be tied to DVDD.)
Analog Ground for Analog Circuitry. (See the notes in Figure 4 for connection to ePAD.)
AVDD/2 Voltage Reference Connection for External Filter.
Slicer Threshold Adjust. (Connect to AGND via a resistor for slicer operation.)
Reserved for Internal Use. Connect to DGND.
XTO
O
P
P
P
P
I
I
I
I
I
DGND
DVDD
AVDD
AGND
VREF
SLC_TH
TEST8
TEST9
AINL
25
26
27
Reserved for Internal Use. Connect to DGND.
Analog Input Left Channel.
28
AINR
I
Analog Input Right Channel.
29
30
31, 32, 33
TEST12
TEST13
OUTR+
I
I
O
Reserved for Internal Use. Connect to DGND.
Reserved for Internal Use. Connect to DGND.
Output of High Power Transistors, Right Channel Positive Polarity.
Rev. 0 | Page 7 of 24
ADAU1590
Pin. Number
34, 35, 36
37, 38, 47, 48
39, 40, 41, 42,
43, 44, 45, 46
Mnemonic
OUTR−
PGND
Type1
Description
O
P
P
Output of High Power Transistors, Right Channel Negative Polarity.
Power Ground for High Power Transistors. Internally connected to EPAD.
Positive Power Supply for High Power Transistors.
PVDD
1 I = input, O = output, P = power.
Rev. 0 | Page 8 of 24
ADAU1590
TYPICAL PERFORMANCE CHARACTERISTICS
–20
–20
–30
–30
–40
–50
–60
–40
–50
–60
THD + N
THD
–70
–80
–70
THD + N
THD
–80
–90
–90
–100
–110
–120
–100
–110
–120
10m
100m
1
10
10m
100m
1
10
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 5. THD or THD + N vs. Output Power, 4 Ω, PVDD = 9 V
Figure 8. THD or THD + N vs. Output Power, 4 Ω, PVDD = 12 V
–20
–20
–30
–40
–50
–60
–30
–40
–50
–60
THD + N
THD
–70
–70
–80
THD + N
THD
–80
–90
–90
–100
–110
–120
–100
–110
–120
10m
100m
1
10
10m
100m
1
10
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 6. THD or THD + N vs. Output Power, 6 Ω, PVDD = 9 V
Figure 9. THD or THD + N vs. Output Power, 6 Ω, PVDD = 12 V
–20
–20
–30
–40
–50
–60
–30
–40
–50
–60
THD + N
THD
–70
–70
–80
THD + N
THD
–80
–90
–90
–100
–110
–120
–100
–110
–120
10m
100m
1
10
10m
100m
1
10
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 7. THD or THD + N vs. Output Power, 8 Ω, PVDD = 9 V
Figure 10. THD or THD + N vs. Output Power, 8 Ω, PVDD = 12 V
Rev. 0 | Page 9 of 24
ADAU1590
25
0
–10
0dBr = 9.5W
POWER LIMITED DUE TO PACKAGE DISSIPATION
–20
–30
20
15
10
5
–40
4Ω
–50
–60
–70
6Ω
8Ω
–80
–90
–100
–110
–120
–130
–140
–150
–160
0
9
10
11
12
13
14
15
0
2
4
6
8
10
12
14
16
18
20
PVDD (V)
FREQUENCY (kHz)
Figure 11. Output Power vs. PVDD @ 0.1% THD + N
Figure 14. FFT @ 1W, 6 Ω, PVDD = 12 V, PGA = 0 dB, 1 kHz Sine
25
20
15
10
5
0
0dBr = 9.5W
POWER LIMITED DUE TO PACKAGE DISSIPATION
–10
–20
–30
–40
–50
–60
–70
–80
–90
4Ω
6Ω
8Ω
–100
–110
–120
–130
–140
–150
–160
0
9
10
11
12
13
14
15
0
2
4
6
8
10
12
14
16
18
20
PVDD (V)
FREQUENCY (kHz)
Figure 15. FFT @ −60 dBFS, 6 Ω, PVDD = 12 V, PGA = 0 dB, 1 kHz Sine
Figure 12. Output Power vs. PVDD @ 1% THD + N
0
–10
30
25
20
15
10
5
–20
4Ω
–30
–40
–50
6Ω
8Ω
–60
–70
–80
–90
–100
–110
–120
–130
–140
POWER LIMITED DUE TO PACKAGE DISSIPATION
0
0
2
4
6
8
10
12
14
16
18
20
9
10
11
12
13
14
15
FREQUENCY (kHz)
PVDD (V)
Figure 16. FFT No Input, 6 Ω, PVDD = 12 V, PGA = 0 dB
Figure 13. Output Power vs. PVDD @ 10% THD + N
Rev. 0 | Page 10 of 24
ADAU1590
0
–10
0
–10
0dBr = 9.5W
–20
–20
–30
–40
–30
–50
–40
–60
–50
–70
–80
–60
–90
–70
–100
–110
–120
–130
–140
–150
–160
–80
THD + N
THD
–90
–100
–110
–120
20
100
1k
FREQUENCY (Hz)
10k
0
2
4
6
8
10
12
14
16
18
20
22
FREQUENCY (kHz)
Figure 17. FFT @ 1 W, 6 Ω, PVDD = 12 V, PGA = 0 dB, 19 kHz and 20 kHz Sine
Figure 20. THD or THD + N vs. Frequency @ 1 W, 4 Ω, PVDD = 12 V, PGA = 0 dB
0
–10
–20
–30
–40
–50
–60
0
–10
–20
–30
–40
–50
–60
–70
RIGHT TO LEFT
–70
–80
–90
–80
THD + N
–90
–100
–100
LEFT TO RIGHT
THD
–110
–110
–120
–120
20
100
1k
10k
20
100
1k
10k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 18. Crosstalk @ 1 W, 6 Ω, PVDD = 12 V, PGA = 0 dB
Figure 21. THD or THD + N vs. Frequency @ 1 W, 6 Ω, PVDD = 12 V, PGA = 0 dB
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–10
–20
–30
–40
–50
–60
RIGHT TO LEFT
–70
–80
THD + N
–90
–90
–100
–100
–110
–120
THD
LEFT TO RIGHT
10k
–110
–120
20
100
1k
10k
20
100
1k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 22. THD or THD + N vs. Frequency @ 1 W, 8 Ω, PVDD = 12 V, PGA = 0 dB
Figure 19. Crosstalk @ Full Scale, 6 Ω, PVDD = 12 V, PGA = 0 dB
Rev. 0 | Page 11 of 24
ADAU1590
90
80
70
60
50
40
30
20
10
0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
–1.6
–1.8
POWER LIMITED DUE TO PACKAGE DISSIPATION
–2.0
0
2
4
6
8
10
12
14
16
18
20
100
1k
10k
OUTPUT POWER (W)
FREQUENCY (Hz)
Figure 23. Frequency Response @ 1 W, 6 Ω, PVDD = 12 V, PGA = 0 dB
Figure 26. Efficiency vs. Output Power, 12 V, 4 Ω
37
100
90
80
70
60
50
40
30
20
10
0
PGA 18dB
35
33
31
PGA 12dB
29
27
25
PGA 6dB
23
21
19
PGA 0dB
17
15
20
100
1k
10k
0
2
4
6
8
10
12
14
FREQUENCY (Hz)
OUTPUT POWER (W)
Figure 24. Gain vs. Frequency @ 1 W, 6 Ω, PVDD = 12 V, 6 Ω
Figure 27. Efficiency vs. Output Power,12 V, 6 Ω
0
100
90
80
70
60
50
40
30
20
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
20
100
1k
10k
0
2
4
6
8
10
12
FREQUENCY (Hz)
OUTPUT POWER (W)
Figure 25. PSRR vs. Frequency, No Input Signal
Ripple = 1.2 V p-p, PVDD = 12 V, 6 Ω
Figure 28. Efficiency vs. Output Power, 12 V, 8 Ω
Rev. 0 | Page 12 of 24
ADAU1590
10
9
8
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
POWER LIMITED DUE TO PACKAGE DISSIPATION
0
5
10
15
20
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160
(°C)
P
PER CHANNEL STEREO MODE
OUT
T
AMBIENT
Figure 29. Power Dissipation vs. Output Power, 12 V, 4 Ω, Stereo Mode,
Both Channels Driven
Figure 32. Power Dissipation Derating vs. Ambient Temperature
4
3
2
1
0
40
35
3Ω
30
4Ω
25
20
6Ω
15
10
5
8Ω
0
0
5
10
15
9
10
11
12
13
14
15
P
PER CHANNEL STEREO MODE
PVDD (V)
OUT
Figure 30. Power Dissipation vs. Output Power, 12 V, 6 Ω, Stereo Mode,
Both Channels Driven
Figure 33. Output Power vs. PVDD, Mono Mode, THD + N, 20 dB
3
2
1
0
30
3Ω
25
4Ω
20
6Ω
15
8Ω
10
5
0
9
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
10 11 12
P
PER CHANNEL STEREO MODE
PVDD (V)
OUT
Figure 34. Output Power vs. PVDD, Mono Mode, THD + N, 40 dB
Figure 31. Power Dissipation vs. Output Power, 12 V, 8 Ω, Stereo Mode,
Both Channels Driven
Rev. 0 | Page 13 of 24
ADAU1590
25
20
15
10
5
100
90
80
70
60
50
40
30
20
10
0
3Ω
4Ω
6Ω
8Ω
0
9
10
11
12
13
14
15
0
2
4
6
8
10
12
14
16
18
20
PVDD (V)
OUTPUT POWER (W)
Figure 35. Output Power vs. PVDD, Mono Mode, THD + N, 60 dB
Figure 37. Efficiency vs. Output Power, Mono Mode, 12 V, 4 Ω
90
80
70
60
50
40
30
20
10
0
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28
OUTPUT POWER (W)
Figure 36. Efficiency vs. Output Power, Mono Mode, 12 V, 3 Ω
Rev. 0 | Page 14 of 24
ADAU1590
THEORY OF OPERATION
feature allows the user to adjust the slicer to the desired value
and to limit the output power. For input signals higher than the
set threshold, the slicer clips the input signal to the modulator.
This adds distortion due to clipping of the signal input to the
modulator. This is especially helpful in applications where the
output power available needs to be reduced instead of reducing
the supply voltage.
OVERVIEW
The ADAU1590 is a 2-channel high performance switching
audio power amplifier. Each of the two Σ-Δ modulators converts
a single-ended analog input into a 2-level PDM output. This
PDM pulse stream is output from the internal full differential
power stage. The ADAU1590 has built-in circuits to suppress the
turn-on and turn off pop and click. The ADAU1590 also offers
extensive thermal and overcurrent protection circuits.
Figure 38 is a plot showing THD + N vs. the input level at
0 dB PGA, 12 V, and 6 Ω, and demonstrates the difference
between a device with and without the slicer.
0
MODULATOR
The modulator is a 5th-order Σ-Δ with feedback from the power
stage connected internally. This helps reduce the external
connections. The 5th-order modulator switches to a lower order
near full-scale inputs. The modulator gain is optimized at 19 dB
for 15 V operation. The Σ-Δ modulator outputs a pulse density
modulation (PDM) 1-bit stream, which does not produce
distinct sharp peaks and harmonics in the AM band like
conventional fixed-frequency PWM.
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
SLICER 1.1V
SLICER 1.17V
SLICER 1.24V
SLICER 1.32V
SLICER DISABLED
The Σ-Δ modulators require feedback to generate PDM stream
with respect to the input. The feedback for the modulators
comes from the power stage. This helps reduce the nonlinearity
in the power stages and achieve excellent THD + N perform-
ance. The feedback also helps in achieving good PSRR. In the
ADAU1590, the feedback from the power stage is internally
connected. This helps reduce the external connections for ease
in PCB layout.
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
INPUT (V rms)
Figure 38. THD + N vs. Input Level @ PGA = 0 dB, 12 V
Figure 39 depicts the typical output power vs. input at different
The Σ-Δ modulators operate in a discrete time domain and
Nyquist frequency limit, which is half the sampling frequency.
The modulator uses the master clock of 12.288 MHz. This is
generated by dividing the external clock input by 2. This sets
the fS/2 around 6.144 MHz. This is sufficient for the audio
bandwidth of 22 kHz. The modulator shapes the quantization
noise and transfers it outside the audio band. The noise floor
rises sharply above 20 kHz. This ensures very good signal-to-
noise ratio (SNR) in the audio band of 20 kHz. The 6.144 MHz
bandwidth allows the modulator order to be set around the 5th
order. The modulator uses proprietary dynamic hysteresis to
reduce the switching rate or frequency to around 700 kHz.
This reduces the switching losses and achieves good efficiency.
The dynamic hysteresis helps the modulator to continuously
track the change in PVDD and the input level to keep the
modulator stable.
slicer settings.
12.0
11.5
SLICER DISABLED
11.0
SLICER 1.32V
10.5
SLICER 1.24V
10.0
SLICER 1.17V
9.5
SLICER 1.10V
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
INPUT (V rms)
Figure 39. Typical Output Power vs. Input, at Different Slicer Settings
SLICER
From Figure 39, it can be seen that the slicer effectively reduces
the output power depending on its setting.
The ADAU1590 has a built-in slicer block following the PGA
and before the modulator. The slicer block is essentially a hard
limiter included for limiting the input signal to the modulator.
This, in turn, limits the output power at a given supply voltage.
The slicer in the ADAU1590 is normally inactive at lower input
levels but is activated as soon as the peak input voltage exceeds
the set threshold. The threshold can be set externally by
Internally, the slicer block receives the input from the PGA.
Figure 40 shows the block for slicer threshold adjust, SLC_TH
(Pin 24).
connecting a resistor from SLC_TH (Pin 24) to ground. This
Rev. 0 | Page 15 of 24
ADAU1590
GAIN
V
CM
The gain of the amplifier is set internally using feedback resis-
tors optimized for 12 V nominal operation. The typical gain
values are tabulated in Table 1. The typical gain is 17 dB with
PGA set to 0 dB. PGA0 (Pin 14) and PGA1 (Pin 13) are used
for setting the desired gain.
50kΩ
SLICER_LEVEL
V
TH
PIN 24 (SLC_TH)
The gain can be set according to Table 10. Note that the ampli-
fier full-scale input level changes as per the PGA gain setting.
R
EXTERNAL
Table 10. Gain Settings
Full-Scale
Input Level
PGA1 PGA0
(Pin 13) (Pin14)
PGA Amplifier
Gain (dB) Gain (dB)
(VRMS
)
Figure 40. Block for Slicer Threshold Adjust, SLC_TH
0
0
1
1
0
1
0
1
0
6
12
18
17
23
29
35
1
0.5
0.25
0.125
The slicer threshold can be set externally using a resistor as
follows:
V
TH = (AVDD/2) × (50 kΩ/50 kΩ + REXTERNAL)
where:
AVDD = 3.3 V typical.
PROTECTION CIRCUITS
The ADAU1590 includes comprehensive protection circuits. It
includes thermal warning, thermal overheat, and overcurrent or
short-circuit protection on the outputs. The
outputs are open drain and require external pull-up resistors.
The outputs are capable of sinking 10 mA. The open-drain
outputs are useful in multichannel applications where more
than one ADAU1590 is used. The error outputs of multiple
ADAU1590s can be OR’ed to simplify the system design.
The logic outputs of the error flags ease the system design of
using a microcontroller.
V
TH is the voltage threshold at which the slicer is activated.
The following equation can be used to calculate the input signal
at which the slicer becomes active:
ERR
OTW
and
VTH
VIN RMS
=
1.414 ×0.9
Therefore, for AVDD = 3.3 V typical and VTH = 1.1 V,
EXTERNAL = 24.9 kΩ
IN RMS = 0.864 V
Thus, the slicer is activated at and above 0.864 VIN RMS
R
V
.
THERMAL PROTECTION
This feature allows the user to set the slicer and, in turn, reduces
the output power at a given supply voltage.To disable the slicer,
SLC_TH should be connected to AGND. Table 9 shows the
Thermal protection in the ADAU1590 is categorized into two
error flags: one as thermal warning and the other as thermal
shutdown. When the device junction temperature reaches near
135°C ( 5°C), the ADAU1590 outputs a thermal warning error
typical values for REXTERNAL
.
OTW
flag by pulling
(Pin 10) low. This flag can be used by the
Table 9. Typical REXTERNAL Values
microcontroller in the system for indication to the user or can
be used to lower the input level to the amplifier to prevent
thermal shutdown. The device continues operation until
shutdown temperature is reached.
VTH (V)
1.1
REXTERNAL (kΩ)
24.9
VIN RMS (V)
0.864
0.919
0.974
1.037
1.17
1.24
1.32
20.5
16.5
12.4
When the device junction temperature exceeds 150°C, the
ERR
device outputs an error flag by pulling
(Pin 9) low. This
(Pin 15)
POWER STAGE
error flag is latched. To restore the operation,
MUTE
The ADAU1590 power stage comprises a high-side PMOS and
a low-side NMOS. The typical RDS-ON is ~300 mΩ. The PMOS-
NMOS stage does not need an external bootstrap capacitor and
simplifies the high-side driver design. The power stage also has
comprehensive protection circuits to detect the faults in typical
applications. See the Protection Circuits section for further details.
needs to be toggled to low and then to high again.
OVERCURRENT PROTECTION
The overcurrent protection in the ADAU1590 is set internally at
a 5 A peak output current. The device protects the output
ERR
devices against excessive output current by pulling
low. This error flag is latched. To restore the normal operation,
(Pin 15) needs to be toggled to low and then to high
(Pin 9)
MUTE
again. The error flag is useful for the microcontroller in the
system to indicate abnormal operation and to initiate the audio
sequence. The device senses the short-circuit condition
MUTE
Rev. 0 | Page 16 of 24
ADAU1590
on the outputs after the LC filter. Typical short-circuit condi-
tions include shorting of the output load, and shorting to either
PVDD or PGND.
device operation that is safely below the shutdown temperature
of 150°C and allows the amplifier to recover itself without the
need for microcontroller intervention.
ERR
Option 2: Using
UNDERVOLTAGE PROTECTION
The ADAU1590 is also comprised of an undervoltage protec-
tion circuit, which senses the undervoltage on PVDD. When
the PVDD supply goes below the operating threshold, the
output FETs are turned to a high-Z condition. In addition, the
ERR
pin is tied to
OTW
. See the circuit in Figure 42.
Option 2 is similar to Option 1 except the
MUTE
instead of
DVDD
ADAU1590
R1
100kΩ
D1
ERR
device issues an error flag by pulling
low. This condition
1N4148
9
is latched. To restore the operation,
(Pin 15) needs to
MUTE
TO MUTE
LOGIC INPUT
ERR
C1
47µF
be toggled to low and then to high again.
15
CLOCK LOSS DETECTION
MUTE
The ADAU1590 includes a clock loss detection circuit. In case
Figure 42. Option 2 Schematic for Autorecovery
ERR
the master clock to the part is lost, the
condition is latched. To restore operation,
toggled low and high again.
flag is set. This
MUTE
In this case, the part goes into shutdown mode due to any of the
error generating events like output overcurrent, overtempera-
ture, missing PVDD or DVDD, or clock loss. The part recovers
itself based on the same circuit operation in Figure 41.
needs to be
AUTOMATIC RECOVERY FROM PROTECTIONS
In certain applications, it is desired for the amplifier to recover
itself from thermal protection without the need for system
microcontroller intervention.
However, if the part goes into error mode due to overtempera-
ture, then the device would have reached its maximum limit of
150°C (15°C to 20°C higher than Option 1). If it goes into error
mode due to an overcurrent from a short circuit on the speaker
outputs, then the part keeps itself recycling on and off until the
short circuit is removed.
The ADAU1590 thermal protection circuit issues two error
OTW
signals for this purpose: one a thermal warning (
ERR
) and the
other a thermal shutdown (
).
It is possible that, with this operation, the part is subjected to a
much higher temperature and current stress continuously. This,
in turn, reduces the part’s reliability in the long term. Therefore,
using Option 1 for autorecovery from thermal protection and
using the system microcontroller to indicate to the user of an
error condition is recommended.
With the two error signals, there are two options available for
using the protections:
OTW
ERR
•
•
Option 1: Using
Option 2: Using
The following sections provide further details of these two options.
MUTE AND STDN
OTW
Option 1: Using
MUTE
STDN
pins are 3.3 V logic-compatible inputs
The
used to control the turn-on/turn-off for ADAU1590.
STDN STDN
pin is pulled low
and
OTW
The
pin is pulled low when the die temperature reaches
MUTE
130°C to 135°C. This pin can be wired to
Figure 41, using an RC circuit.
as shown in
The
input is active low when the
and the device is in its energy saving mode. The modulator is
inactive and the power stage is in high-Z state. The high logic
level input on the
modulator is running internally but the power stage is still in
high-Z state.
DVDD
ADAU1590
R1
100kΩ
D1
1N4148
STDN
pin wakes up the device. The
10
TO MUTE
LOGIC INPUT
OTW
C1
47µF
15
MUTE
MUTE
When the
active with a soft turn-on to avoid the pop and clicks. The low
MUTE
pin is pulled high, the power stage becomes
Figure 41. Option 1 Schematic for Autorecovery
level on the
pin disables the power stage and is
OTW
MUTE
pin.
The low logic level on
The bridge is shut down and starts cooling or the die temperature
OTW
also pulls down the
recommended to be used to mute the audio output. See the
Power-Up/Power-Down Sequence section for more details.
starts reducing. When it reaches around 120°C, the
signal
starts going high. While this pin is tied to a capacitor with a
resistor pulled to DVDD, the voltage on this pin starts rising
slowly towards DVDD. When it reaches the CMOS threshold,
MUTE
is deasserted and the amplifier starts functioning again.
This cycle repeats itself depending on the input signal
conditions and the temperature of the die. This option allows
Rev. 0 | Page 17 of 24
ADAU1590
AVDD/DVDD
PVDD
POWER-UP/POWER-DOWN SEQUENCE
Figure 43 shows the recommended power-up sequence for the
ADAU1590.
AVDD/DVDD
STDN
tINT
PVDD
INTERNAL MUTE
tWAIT
MUTE
STDN
tINT
PVDD/2
INTERNAL MUTE
OUTx+/OUTx–
AINx
tPDL-H
AVDD/2
tWAIT
MUTE
PVDD/2
tINT = 650ms @ 24.576MHz CLOCK
tWAIT < T
INT
OUTx+/OUTx–
NOTES
AVDD/2
1. INTERNAL MUTE IS INTERNAL TO CHIP.
AINx
Figure 44. Power-Up Sequence, tWAIT < tINT
tINT = 650ms @ 24.576MHz CLOCK
tPDL-H = 200µs
The ADAU1590 uses three separate supplies: AVDD (3.3 V
analog for PGA and modulator), DVDD (3.3 V digital for
control logic and clock oscillator), and PVDD (9 V to 18 V
power stage and level shifter). Separate pins are provided for
the AVDD, DVDD, and PVDD supply connections, as well as
AGND, DGND, and PGND.
tWAIT = 10 × R × C
IN
IN
NOTES
1. INTERNAL MUTE IS INTERNAL TO CHIP.
Figure 43. Recommended Power-Up Sequence
The ADAU1590 has a special turn-on sequence that consists of
a fixed internal mute time during which the power stage does
not start switching. This internal mute time depends on the
master clock frequency and is 650 ms for a 24.576 MHz clock.
In addition, the ADAU1590 incorporates a built-in undervolt-
age lockout logic on DVDD as well as PVDD. This helps detect
undervoltage operation and eliminates the need to have an external
mechanism to sense the supplies.
MUTE
Also, the internal mute overrides the external
ensures that the power stage does not switch on immediately
MUTE
and
even if the external
signal is pulled high in less than
. The power stage starts switching only
after 650 ms plus a small propagation delay of 200 μs has
MUTE
The ADAU1590 monitors the DVDD and PVDD supply voltages
and prevents the power stage from turning on if either of the
supplies are not present or are below the operating threshold.
Therefore, if DVDD is missing or below the operating thresh-
old, for example, the power stage does not turn on, even if
PVDD is present, or vice versa.
STDN
650 ms after
elapsed and after
is deasserted. Therefore, it is recom-
mended to ensure that tWAIT > tINT to prevent the pop and click
during power-on.
MUTE
Ensure that the
signal is delayed by at least tWAIT seconds
Because this protection is only present on DVDD and PVDD
and not on AVDD, shorting both AVDD and DVDD externally
or generating AVDD and DVDD from one power source is
recommended. This ensures that both AVDD and DVDD
supplies are tracking each other and avoids the need to monitor
the sequence with respect to PVDD. This also ensures minimal
pop and click during power-up.
STDN
after
. This time is approximately 10 times the charging
time constant of the input coupling capacitor.
For example, if the input coupling capacitor is 4.7 μF, the time
constant is
T = R × C = 20 kꢀ × 4.7 μF = 94 ms
Therefore, tWAIT = 10 × T = 940 ms ~ 1 sec.
When using separate AVDD and DVDD supplies, ensure that
both supplies are stable before unmuting or turning on the
power stage.
t
WAIT is needed to ensure that the input capacitors are charged to
AVDD/2 before turning on the power stage.
MUTE
Similarly, during shutdown, pulling
to logic low before
When tWAIT < tINT, the power stage does not start switching until
STDN
STDN
650 ms has elapsed after
that this method does not ensure pop-and-click suppression
because of less than recommended or insufficient tWAIT
(see Figure 44). However, note
pulling
down is recommended. However, where a fault
event occurs, the power stage shuts down to protect the part. In
this case, depending on the signal level, there is some pop at the
speaker.
.
Rev. 0 | Page 18 of 24
ADAU1590
To shut down the power supplies, it is highly recommended to
mute the amplifier before shutting down any of the supplies.
The amount of pop at the turn-on depends on tWAIT, which in
turn depends on the values of CREF and CIN. The following
section describes how to select the value for the CREF and CIN.
MUTE
After
is shut down, shut down the supplies in the follow-
ing order: PVDD, DVDD, then AVDD. Where AVDD and
DVDD are generated from a single source, turn PVDD off
SELECTING VALUE FOR CREF AND CIN
The CREF is the capacitor used for filtering the noise from
AVDD on VREF. VREF is used for the biasing of the internal
analog amplifier as well as the modulator. Therefore, care must
be taken to ensure that the recommended minimum value is
used. The minimum recommended value for CREF is 4.7 μF.
MUTE
before DVDD and AVDD, and after issuing
.
DC OFFSET AND POP NOISE
This section describes the cause of dc offset and pop noise
during turn-on/turn-off. The turn-on/turn-off pop in
amplifiers depend mainly on the dc offset, therefore, care must
be taken to reduce the dc offset at the output.
CIN is the input coupling capacitor and is used to decouple the
inputs from the external dc. The CIN value determines the low
corner frequency of the amplifier. It can be determined from
the following equation:
The first stage of ADAU1590 has an inverting PGA amplifier, as
shown in Figure 45.
CHANGES WITH PGA SETTING
1
R
FB
fLOW
=
2× π× RIN ×CIN
C
IN
AINx
V
R
IN
where:
LOW is the low corner frequency (−3 dB).
IN is the input resistance (20 kΩ).
IN is the input coupling capacitor.
R
SOURCE
TO NEXT STAGE
f
R
C
V
REF
MIS
C
REF
Note that RIN = 20 kΩ, provided that RSOURCE is <1 kΩ. If RSOURCE
is sizable with respect to RIN, it also must be taken into account
in calculation.
Figure 45. Input Equivalent Circuit
where:
R
R
IN = 20 kΩ, fixed internally.
FB is the gain feedback resistor (value depends on the PGA
From the preceding equation, fLOW can be found for the desired
frequency response.
setting).
SOURCE is the source resistance.
IN is the input coupling capacitor (2.2 μF typical).
REF is the filter capacitor for VREF
The recommended value for CIN is 2.2 μF, giving fLOW = 3.6 Hz,
and should keep 20 Hz roll-off within −0.5 dB.
R
C
C
.
However, if a higher than recommended CIN value is used for
better low frequency response, care must be taken to ensure
that appropriate tWAIT is used. See the Power-Up/Power-Down
Sequence section for more details.
VREF is the analog reference voltage (AVDD/2 typical).
MIS is the dc offset due to mismatch in the op amp.
V
As shown in Figure 45, the dc offset at the output can be due to
VMIS (the dc offset from mismatch in the op amp) and due to
leakage current of the CIN capacitor.
MONO MODE
ST
The ADAU1590 mono mode can be enabled by pulling MO/
Normally, the offset due to leakage current in the CIN is less and
can be ignored compared to VMIS. The VMIS is mainly responsi-
ble for the dc offset at the output. The ADAU1590 uses special
self-calibration or a dc offset trim circuit, which controls the dc
offset (due to VMIS) to within 3 mV. The VMIS can vary for each
part as well as for voltage and temperature. The trim circuit
ensures that the offset is limited within specified limits and
provides virtually pop-free operation every time the part is
turned on. However, care must be taken while unmuting or
during the power-up sequence.
(Pin 11) to logic high. In this mode, the left channel input and
modulator is active and feeds PWM data to both the left and
right power stages. However, the respective power FETs need to
be connected externally for higher current capability. That is,
connect OUTL+ with OUTR+ and OUTL− with OUTR−. The
mono mode gives the capability to drive lower impedance loads
without invoking current limit. However, the output power is
limited by PVDD and temperature limits. See the typical applica-
tion schematic in Figure 47 for details.
POWER SUPPLY BYPASSING
During the initial power-up, CIN and CREF are charging to
AVDD/2 and, during this time, there can be dc offset at the
output (see Figure 45). This depends on the PGA gain setting.
The dc offset is multiplied by the PGA gain setting. If the
amplifier is kept in mute during this charging and self-trimming
event for the recommended tWAIT time, the dc offset at the
output remains within 3 mV. For more details on tWAIT, refer
to the Power-Up/Power-Down Sequence section.
Because Class-D amplifiers utilize high frequency switching,
care must be taken to bypassing the power supply.
For reliable operation, using 100 nF ceramic surface-mount
capacitors for the PVDD and PGND pins is recommended. The
minimum of two capacitors are needed: one between Pin 45/Pin 46
(PVDD) and Pin 47/Pin 48 (PGND), the other between Pin 39/
Pin 40 (PVDD) and Pin 37/Pin 38 (PGND). In addition, these
Rev. 0 | Page 19 of 24
ADAU1590
must be placed very close to the respective pins with direct
connection. This is important for reliable and safe operation
of the device. One additional 1 μF capacitor in parallel to the
100 nF capacitor is also recommended. A bulk bypass capacitor
of 470 μF is also recommended to remove the low frequency
ripple due to load current.
Option 3: Using an External Clock
The ADAU1590 can be provided with an external clock of
24.576 MHz at the XTI pin. The logic level for the clock input
should be in the range of 3.3 V and 50% typical duty cycle.
For systems using multiple ADAU1590s, it is recommended to
use only one clock source if the ADAU1590s share the same
power supply to prevent the beat frequencies of asynchronous
clocks from appearing in the audio band.
Similarly, one 100 nF capacitor is recommended between each
DVDD/DGND and AVDD/AGND. These capacitors also must
be placed close to their respective pins with direct connection.
Multiple ADAU1590s can be connected in a daisy chain by
providing or generating a master clock from one ADAU1590
and subsequently connecting its XTO output to the XTI input
of the next ADAU1590, and so on. However, using a simple
logic buffer between the XTO pin of one ADA1590 to the XTI
pin of the next ADAU1590 is recommended. Because the clock
output is now buffered, it can be connected to the XTI inputs of
the remaining ADAU1590s, depending on the fanout capability
of the logic buffer used.
CLOCK
The ADAU1590 uses 24.576 MHz for the master clock, which is
512 × fS (fS = 48 kHz). There are several options for providing
the clock.
Option 1: Using a Quartz Crystal
A quartz crystal of 24.576 MHz frequency can be connected
between the XTI and XTO pins using two load capacitors
suitable for the crystal oscillation mode.
Option 2: Using a Ceramic Resonator
The ADAU1590 can also be used with ceramic resonators
similar to crystal by using the XTI and XTO pins.
Rev. 0 | Page 20 of 24
ADAU1590
APPLICATIONS INFORMATION
3.3V
PVDD
100nF
100nF
1µF
100nF
470µF
100nF
2.2µF
ANALOG
INPUT LEFT
AINL
L1
L2
100kΩ
OUTL+
OUTL–
C1
C2
SLC_TH
R3
VREF
AINR
L3
L4
OUTR+
OUTR–
4.7µF
100nF
C3
C4
ADAU1590
2.2µF
ANALOG
INPUT RIGHT
100kΩ
STDN
MUTE
ERR
SYSTEM LOGIC
MICROCONTROLLER
OTW
24.576MHz
CRYSTAL OR
RESONATOR
Figure 46. Typical Stereo Application Circuit
Table 12. Output Filter Component Values
Table 11. R3—Slicer Threshold Resistor
Inductance
Load Impedance (Ω) L1 to L4 (μH)
Capacitance
C1 to C4 (ꢀF)
VTH (V)
R3 (kΩ)
1.1
24.9
4
6
8
10
15
22
1.5
1
0.68
1.17
1.24
1.32
20.5
16.5
12.4
Rev. 0 | Page 21 of 24
ADAU1590
3.3V
PVDD
100nF
100nF
1µF
100nF
100nF
470µF
2.2µF
ANALOG
INPUT LEFT
AINL
L1
L2
100kΩ
OUTL+
OUTL–
C1
C2
SLC_TH
VREF
AINR
R3
OUTR+
OUTR–
4.7µF
100nF
ADAU1590
2.2µF
ANALOG
INPUT RIGHT
100kΩ
STDN
MUTE
ERR
SYSTEM LOGIC
MICROCONTROLLER
OTW
24.576MHz
CRYSTAL OR
RESONATOR
Figure 47. Typical Mono Application Circuit
For component values, refer to the stereo application circuit in Figure 46.
Rev. 0 | Page 22 of 24
ADAU1590
OUTLINE DIMENSIONS
0.30
0.23
0.18
7.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
37
36
48
1
PIN 1
INDICATOR
EXPOSED
5.25
5.10 SQ
4.95
TOP
VIEW
6.75
BSC SQ
PAD
(BOTTOM VIEW)
0.50
0.40
0.30
25
24
12
13
0.25 MIN
5.50
REF
0.80 MAX
0.65 TYP
1.00
0.85
0.80
12° MAX
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.50 BSC
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
Figure 48. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
7 mm × 7 mm Body, Very Thin Quad
(CP-48-1)
Dimensions shown in millimeters
9.20
9.00 SQ
8.80
0.75
0.60
0.45
1.20
MAX
BOTTOM VIEW
(PINS UP)
37
36
48
37
36
48
1
1
1.00 REF
PIN 1
SEATING
PLANE
TOP VIEW
(PINS DOWN)
5.10
SQ
7.20
7.00 SQ
6.80
EXPOSED
PAD
1.05
1.00
0.95
0.20
0.09
12
25
24
25
24
12
13
13
VIEW A
7°
3.5°
0°
0.27
0.22
0.17
0.50 BSC
LEAD PITCH
0.15
0.05
0.08 MAX
COPLANARITY
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-ABC
Figure 49. 48-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
(SV-48-5)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature
Range
Package
Option
Model
Package Description
ADAU1590ACPZ1
ADAU1590ACPZ-RL1
ADAU1590ACPZ-RL71
ADAU1590ASVZ1
ADAU1590ASVZ-RL1
ADAU1590ASVZRL71
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
CP-48-1
CP-48-1
CP-48-1
SV-48-5
SV-48-5
SV-48-5
48-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 13”Tape and Reel
48-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 7”Tape and Reel
48-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
48-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP], 13”Tape and Reel
48-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP], 7”Tape and Reel
1 Z = RoHS Compliant Part.
Rev. 0 | Page 23 of 24
ADAU1590
NOTES
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06673-0-5/07(0)
Rev. 0 | Page 24 of 24
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