ADA4092-4ARUZ [ADI]
Micropower, OVP, Rail-to-Rail Input/Output Operational Amplifier; 微功耗， OVP ，轨到轨输入/输出运算放大器
| 型号： | ADA4092-4ARUZ |
| 厂家： | 
ADI |
| 描述： | Micropower, OVP, Rail-to-Rail Input/Output Operational Amplifier |
| 文件： | 总20页 (文件大小：611K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Micropower RRIO Operational Amplifier
ADA4092-4
PIN CONFIGURATION
FEATURES
Single-supply operation: 2.7 V to 36 V
Wide input voltage range
Rail-to-rail output swing
Low supply current: 200 µA/amplifier
Wide bandwidth: 1.4 MHz
High phase margin: 69°
1
2
3
4
5
6
7
14
13
12
11
10
9
OUTA
–INA
+INA
+V
OUTD
–IND
+IND
–V
ADA4092-4
TOP VIEW
(Not to Scale)
+INB
–INB
OUTB
+INC
–INC
OUTC
Slew rate: 0.4 V/µs
8
Low offset voltage: 1.50 mV maximum
No phase reversal
Figure 1. 14-Lead TSSOP (RU-14)
Overvoltage protection (OVP)
25 V above/below supply rails at 5 V
12 V above/below supply rails at 15 V
APPLICATIONS
Industrial process control
Battery-powered instrumentation
Power supply control and protection
Telecommunications
Remote sensors
Low voltage strain gage amplifiers
DAC output amplifiers
GENERAL DESCRIPTION
The ADA4092-4 quad is a micropower, single-supply, 1.4 MHz
bandwidth amplifier featuring rail-to-rail inputs and outputs. It
is guaranteed to operate from a +2.7 V to +30 V single supply as
well as from 1.35 V to 15 V dual supplies.
The ADA4092-4 is specified over the extended industrial
temperature range of −40°C to +125°C. The ADA4092-4 is
part of the growing selection of 36 V, low power op amps from
Analog Devices, Inc., see Table 1.
The ADA4092-4 features a unique input stage that allows the
input voltage to exceed either supply safely without any phase
reversal or latch-up; this is called overvoltage protection (OVP).
The ADA4092-4 is available in the 14–lead TSSOP surface-mount
package.
Table 1. Low Power, 36 V Operational Amplifiers
Applications for these amplifiers include portable telecom-
munications equipment, power supply control and protection,
and interface for transducers with wide output ranges. Sensors
requiring a rail-to-rail input amplifier include Hall effect, piezo-
electric, and resistive transducers.
RRIO
Low
Family Rail-to-Rail I/O
Precision
PJFET
Noise
OP1177
AD8682 OP2177
AD8684 OP4177
Single
Dual
Quad
ADA4091-2
ADA4091-4
ADA4092-4
The ability to swing rail-to-rail at both the input and output enables
designers, for example, to build multistage filters in single-supply
systems and to maintain high signal-to-noise ratios (SNR).
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2010 Analog Devices, Inc. All rights reserved.
ADA4092-4
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................6
Typical Performance Characteristics ..............................................7
Theory of Operation ...................................................................... 15
Input Stage................................................................................... 15
Output Stage................................................................................ 15
Input Overvoltage Protection................................................... 16
Comparator Operation.............................................................. 16
Outline Dimensions....................................................................... 17
Ordering Guide .......................................................................... 17
Applications....................................................................................... 1
Pin Configuration............................................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Specifications............................................................... 3
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
REVISION HISTORY
5/10—Rev. 0 to Rev. A
Changes to Data Sheet Title, General Description,
and Table 1......................................................................................... 1
4/10—Revision 0: Initial Version
Rev. A | Page 2 of 20
ADA4092-4
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
VSY
= 1.5 V, V CM = 0 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
−1.5
−2.5
+0.2
+1.5
+2.5
mV
mV
µV/°C
nA
nA
nA
nA
nA
nA
V
dB
dB
dB
dB
dB
dB
−40°C ≤ TA ≤ +125°C
Offset Voltage Drift
Input Bias Current
ΔVOS/ΔT
IB
3
−45
−60
−60
−275
−4
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
+60
+275
+4
+5
+75
+1.5
Input Offset Current
IOS
+1
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
−5
−75
−1.5
70
Input Voltage Range
Common-Mode Rejection Ratio
IVR
CMRR
VCM = −1.5 V to +1.5 V
−40°C ≤ TA ≤ +125°C
RL = 100 kΩ, VO = −1.2 V to +1.2 V
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ, VO = −1.2 V to +1.2 V
−40°C ≤ TA ≤ +125°C
85
68
Large Signal Voltage Gain
AVO
106
101
92
113
94
85
OUTPUT CHARACTERISTICS
Output Voltage High
VOH
RL = 100 kΩ to GND
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to GND
−40°C to +125°C
1.485
1.480
1.470
1.455
1.495
V
V
V
V
1.480
Output Voltage Low
VOL
RL = 100 kΩ to GND
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to GND
−40°C ≤ TA ≤ +125°C
Source/sink
−1.497
−1.495
−1.490
−1.480
−1.485
−1.475
V
V
V
V
mA
Ω
Short-Circuit Limit
Closed-Loop Impedance
POWER SUPPLY
ISC
ZOUT
30
130
f = 1 MHz, AV = +1
Power Supply Rejection Ratio
PSRR
ISY
VSY = 2.7 V to 36 V
−40°C ≤ TA ≤ +125°C
IO = 0 mA
98
90
112
165
dB
dB
µA
µA
Supply Current per Amplifier
200
300
−40°C ≤ TA ≤ +125°C
DYNAMIC PERFORMANCE
Slew Rate
Settling Time
SR
tS
RL = 100 kΩ, CL = 30 pF
To 0.01%
0.4
25
V/µs
µs
Gain Bandwidth Product
Phase Margin
GBP
ΦM
1.2
66
MHz
Degrees
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
en p-p
en
0.1 Hz to 10 Hz
f = 1 kHz
0.8
30
µV p-p
nV/√Hz
Rev. A | Page 3 of 20
ADA4092-4
VSY
= 5.0 V, VCM = 0 V, TA = 25°C, unless otherwise noted.
Table 3.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
−1.5
−2.5
+0.2
+1.5
+2.5
mV
mV
µV/°C
nA
nA
nA
nA
nA
nA
V
−40°C ≤ TA ≤ +125°C
Offset Voltage Drift
Input Bias Current
ΔVOS/ΔT
IB
3
−53
−60
−80
−350
−4
−7
−100
−5
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
+80
+350
+4
+7
+100
+5
Input Offset Current
IOS
+1
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
Input Voltage Range
IVR
Common-Mode Rejection Ratio
CMRR
VCM = −5.0 V to +5.0 V
−40°C ≤ TA ≤ +125°C
RL = 100 kΩ, VO = 4.7 V
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ, VO = 4.7 V
−40°C ≤ TA ≤ +125°C
82
78
113
106
98
95
dB
dB
dB
dB
dB
dB
Large Signal Voltage Gain
AVO
117
100
90
OUTPUT CHARACTERISTICS
Output Voltage High
VOH
RL = 100 kΩ to GND
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to GND
−40°C ≤ TA ≤ +125°C
RL = 100 kΩ to GND
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to GND
−40°C ≤ TA ≤ +125°C
Source/sink
4.980
4.975
4.945
4.900
4.990
V
V
V
V
V
V
V
V
4.960
Output Voltage Low
VOL
−4.997
−4.990
−4.990
−4.980
−4.980
−4.975
Short-Circuit Limit
Closed-Loop Impedance
POWER SUPPLY
ISC
ZOUT
20
90
mA
Ω
f = 1 MHz, AV = +1
Power Supply Rejection Ratio
PSRR
ISY
VSY = 2.7 V to 36 V
−40°C ≤ TA ≤ +125°C
IO = 0 mA
98
90
112
180
dB
dB
µA
µA
Supply Current per Amplifier
225
300
−40°C ≤ TA ≤ +125°C
DYNAMIC PERFORMANCE
Slew Rate
Settling Time
SR
tS
RL = 100 kΩ, CL = 30 pF
To 0.01%
0.4
25
V/µs
µs
Gain Bandwidth Product
Phase Margin
GBP
ΦM
1.3
67
MHz
Degrees
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
en p-p
en
0.1 Hz to 10 Hz
f = 1 kHz
0.8
30
µV p-p
nV/√Hz
Rev. A | Page 4 of 20
ADA4092-4
VSY
= 15.0 V, VCM = 0 V, V O = 0 V, TA = 25°C, unless otherwise noted.
Table 4.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
−1.5
−2.5
+0.2
+1.5
+2.5
mV
mV
µV/°C
nA
nA
nA
nA
nA
nA
V
dB
dB
dB
dB
dB
dB
−40°C ≤ TA ≤ +125°C
Offset Voltage Drift
Input Bias Current
ΔVOS/ΔT
IB
3
−50
−60
−80
−500
−4
−10
−140
−15
90
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
+80
+500
+4
+10
+140
+15
Input Offset Current
IOS
+1
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
Input Voltage Range
Common-Mode Rejection Ratio
IVR
CMRR
VCM = −15.0 V to +15.0 V
−40°C ≤ TA ≤ +125°C
RL = 100 kΩ, VO = 14.7 V
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ, VO = 14.7 V
−40°C ≤ TA ≤ +125°C
103
118
104
87
Large Signal Voltage Gain
AVO
116
108
102
93
OUTPUT CHARACTERISTICS
Output Voltage High
VOH
RL = 100 kΩ to GND
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to GND
−40°C ≤ TA ≤ +125°C
RL = 100 kΩ to GND
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to GND
−40°C ≤ TA ≤ +125°C
Source/sink
14.970
14.950
14.900
14.800
14.980
V
V
V
V
V
V
V
V
mA
Ω
14.915
Output Voltage Low
VOL
−14.985
−14.970
−14.980
−14.965
−14.950
−14.940
Short-Circuit Limit
Closed-Loop Impedance
POWER SUPPLY
ISC
ZOUT
20
68
f = 1 MHz, AV = +1
Power Supply Rejection Ratio
PSRR
ISY
VSY = 2.7 V to 36 V
−40°C ≤ TA ≤ +125°C
IO = 0 mA
98
90
112
200
dB
dB
µA
µA
Supply Current per Amplifier
250
350
−40°C ≤ TA ≤ +125°C
DYNAMIC PERFORMANCE
Slew Rate
Settling Time
SR
tS
RL = 100 kΩ, CL = 30 pF
To 0.01%
0.4
25
V/µs
µs
Gain Bandwidth Product
Phase Margin
Channel Separation
NOISE PERFORMANCE
Voltage Noise
GBP
ΦM
CS
1.4
69
100
MHz
Degrees
dB
f = 1 kHz
en p-p
en
0.1 Hz to 10 Hz
f = 1 kHz
0.8
30
µV p-p
nV/√Hz
Voltage Noise Density
Rev. A | Page 5 of 20
ADA4092-4
ABSOLUTE MAXIMUM RATINGS
Table 5.
THERMAL RESISTANCE
θJA is specified for the device soldered on a 4-layer JEDEC standard
printed circuit board (PCB) with zero airflow.
Parameter
Rating
Supply Voltage
Input Voltage
36 V
Refer to the Input
Overvoltage Protection
section
Table 6. Thermal Resistance
Package Type
θJA
θJC
Unit
14-Lead TSSOP (RU-14)
112
35
°C/W
Differential Input Voltage
VSY
Input Current
5 mA
ESD CAUTION
Output Short-Circuit Duration to GND
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature (Soldering, 60 sec)
Indefinite
−65°C to +150°C
−40°C to +125°C
−65°C to +150°C
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. A | Page 6 of 20
ADA4092-4
TYPICAL PERFORMANCE CHARACTERISTICS
180
40
35
30
25
20
15
10
5
ADA4092-4
= ±1.5V
ADA4092-4
= ±1.5V
160
140
120
100
80
V
SY
= 25°C
V
SY
= 25°C
T
A
T
A
60
40
20
0
0
–2
–2
–2
–1
0
1
2
3
4
5
6
6
6
7
7
7
8
8
8
TCV (μV/°C)
OS
OFFSET VOLTAGE (µV)
Figure 2. Input Offset Voltage Distribution, 3 V
Figure 5. TCVOS Distribution, 3 V
180
160
140
120
100
80
70
60
50
40
30
20
10
0
ADA4092-4
= ±5V
ADA4092-4
V
SY
= 25°C
V
= ±5V
SY
= 25°C
T
A
T
A
60
40
20
0
–1
0
1
2
3
4
5
TCV (μV/°C)
OS
OFFSET VOLTAGE (µV)
Figure 3. Input Offset Voltage Distribution, 10 V
Figure 6. TCVOS Distribution, 10 V
180
160
140
120
100
80
70
60
50
40
30
20
10
0
ADA4092-4
= ±15V
ADA4092-4
V
SY
= 25°C
V
= ±15V
SY
= 25°C
T
A
T
A
60
40
20
–1
0
1
2
3
4
5
TCV (μV/°C)
OS
OFFSET VOLTAGE (µV)
Figure 7. TCVOS Distribution, 30 V
Figure 4. Input Offset Voltage Distribution, 30 V
Rev. A | Page 7 of 20
ADA4092-4
60
40
600
500
400
300
200
100
0
ADA4092-4
= ±1.5V
V
20
SY
T = 25°C
ADA4092-4
= ±1.5V
I
OS
I
V
B–
SY
= 25°C
T
A
0
–20
I
B+
–40
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
V
(V)
V
(V)
CM
CM
Figure 8. Input Offset Voltage vs. Common-Mode Voltage, 3 V
Figure 11. Input Bias Current vs. Common-Mode Voltage, 3 V
600
500
400
60
ADA4092-4
40
V
= ±5V
SY
T = 25°C
20
0
I
300
OS
ADA4092-4
V
= ±5V
200
100
0
SY
= 25°C
T
A
I
B–
–20
I
B+
–40
–5
–5
–4
–3
–2
–1
0
1
2
3
4
5
–4
–3
–2
–1
0
1
2
3
4
5
V
(V)
CM
V
(V)
CM
Figure 12. Input Bias Current vs. Common-Mode Voltage, 10 V
Figure 9. Input Offset Voltage vs. Common-Mode Voltage, 10 V
60
600
500
40
ADA4092-4
400
I
OS
V
= ±15V
SY
T = 25°C
20
0
ADA4092-4
V
= ±15V
300
200
100
0
SY
= 25°C
T
A
I
B–
I
B+
–20
–40
–15
–10
–05
0
5
10
15
–15
–10
–5
0
5
10
15
V
(V)
V
(V)
CM
CM
Figure 10. Input Offset Voltage vs. Common-Mode Voltage, 30 V
Figure 13. Input Bias Current vs. Common-Mode Voltage, 30 V
Rev. A | Page 8 of 20
ADA4092-4
10k
1k
100
10
1
120
100
80
ADA4092-4
= ±1.5V
V
SY
= 25°C
PHASE
T
A
60
40
GAIN
20
0
V
– V
OH
DD
–20
–40
–60
–80
V
– V
SS
OL
ADA4092-4
V
T
= ±1.5V
SY
= 25°C
A
0.001
0.01
0.1
1
10
100
100
100
1k
10k
100k
1M
10M
LOAD CURRENT (mA)
FREQUENCY (Hz)
Figure 14. Dropout Voltage vs. Load Current, 3 V
Figure 17. Open-Loop Gain and Phase vs. Frequency, 3 V
120
100
80
10k
1k
100
10
1
ADA4092-4
V
= ±5V
SY
= 25°C
PHASE
T
A
60
40
GAIN
20
0
V
– V
OH
DD
–20
–40
–60
–80
–100
V
– V
SS
OL
ADA4092-4
V
= ±5V
SY
= 25°C
T
A
0.001
0.01
0.1
1
10
1k
10k
100k
1M
10M
LOAD CURRENT (mA)
FREQUENCY (Hz)
Figure 15. Dropout Voltage vs. Load Current, 10 V
Figure 18. Open-Loop Gain and Phase vs. Frequency, 10 V
10k
1k
100
10
1
140
ADA4092-4
120
100
80
V
= ±15V
SY
= 25°C
T
A
PHASE
60
40
GAIN
20
0
V
– V
OH
DD
–20
–40
–60
–80
V
1
– V
SS
OL
ADA4092-4
= ±15V
V
SY
= 25°C
T
A
0.001
0.01
0.1
10
1k
10k
100k
1M
10M
LOAD CURRENT (mA)
FREQUENCY (Hz)
Figure 16. Dropout Voltage vs. Load Current, 30 V
Figure 19. Open-Loop Gain and Phase vs. Frequency, 30 V
Rev. A | Page 9 of 20
ADA4092-4
50
1k
100
10
ADA4092-4
ADA4092-4
GAIN = +100
V
T
= ±1.5V
V
T
= ±1.5V
SY
= 25°C
40
30
SY
= 25°C
A
A
GAIN = +10
GAIN = +1
20
A
A
= +100
= +10
V
10
V
0
1
A
= +1
V
–10
–20
0.1
10
100
1k
10k
100k
z)
1M
10M
10
10
10
100
1k
10k
100k
1M
10M
10M
10M
FREQUENCY (H
FREQUENCY (Hz)
Figure 20. Closed-Loop Gain vs. Frequency, 3 V
Figure 23. Closed-Loop Output Impedance vs. Frequency, 3 V
50
40
1k
ADA4092-4
ADA4092-4
GAIN = +100
V
T
= ±5V
V
T
= ±5V
SY
= 25°C
SY
= 25°C
A
A
100
10
1
30
GAIN = +10
GAIN = +1
20
A = +100
V
10
A
= +10
V
0
A
= +1
V
–10
–20
0.1
10
100
1k
10k
100k
z)
1M
10M
100
1k
10k
100k
1M
FREQUENCY (H
FREQUENCY (Hz)
Figure 21. Closed-Loop Gain vs. Frequency, 10 V
Figure 24. Closed-Loop Output Impedance vs. Frequency, 10 V
50
40
1k
ADA4092-4
GAIN = +100
ADA4092-4
V
= ±15V
SY
= 25°C
V
= ±15V
SY
= 25°C
T
A
T
A
100
10
30
GAIN = +10
GAIN = +1
20
A
= +100
V
10
A
= +10
V
0
1
A
= +1
–10
–20
V
0.1
100
1k
10k
100k
1M
10
100
1k
10k
100k
z)
1M
10M
FREQUENCY (Hz)
FREQUENCY (H
Figure 22. Closed-Loop Gain vs. Frequency, 30 V
Figure 25. Output Impedance vs. Frequency, 30 V
Rev. A | Page 10 of 20
ADA4092-4
90
80
70
60
50
40
30
20
10
0
120
100
80
PSRR+
60
ADA4092-4
40
PSRR–
V
T
= ±1.5V
SY
= 25°C
A
20
ADA4092-4
V
T
= ±1.5V
SY
0
= 25°C
A
–20
100
1k
10k
100k
1M
10M
10M
10M
100
1k
10k
100k
1M
10M
10M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 29. PSRR vs. Frequency, 3 V
Figure 26. CMRR vs. Frequency, 3 V
120
100
80
100
90
80
70
60
50
40
30
20
10
0
PSRR+
60
ADA4092-4
= ±5V
40
PSRR–
V
SY
= 25°C
T
A
20
ADA4092-4
= ±5V
V
SY
0
T
= 25°C
A
–20
100
1k
10k
100k
1M
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 30. PSRR vs. Frequency, 10 V
Figure 27. CMRR vs. Frequency, 10 V
120
100
80
100
90
80
70
60
50
40
30
20
10
0
PSRR+
60
ADA4092-4
= ±15V
PSRR–
40
V
SY
= 25°C
T
A
20
ADA4092-4
= ±15V
V
SY
= 25°C
0
T
A
–20
100
1k
10k
100k
1M
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 31. PSRR vs. Frequency, 30 V
Figure 28. CMRR vs. Frequency, 30 V
Rev. A | Page 11 of 20
ADA4092-4
2.0
0.06
0.04
0.02
0
1.5
1.0
0.5
0
ADA4092-4
–0.5
–1.0
V
T
= ±1.5V
= 25°C
ADA4092-4
SY
–0.02
V
T
= ±1.5V
= 25°C
A
SY
R
C
= 100kΩ
= 100pF
L
L
A
R
C
= 100kΩ
= 100pF
L
L
–0.04
–0.06
–1.5
–2.0
0
0
0
10
20
30
40
50
60
70
80
0
0
0
2
4
6
8
10
12
14
16
18
18
18
TIME (µs)
TIME (µs)
Figure 32. Large Signal Transient Response, 3 V
Figure 35. Small Signal Transient Response, 3 V
6
4
0.06
0.04
0.02
0
2
0
ADA4092-4
= ±5V
= 25°C
= 100kΩ
= 100pF
V
T
R
SY
ADA4092-4
–2
–4
–6
A
–0.02
V
= ±5V
L
L
SY
C
T
= 25°C
A
R
C
= 100kΩ
= 100pF
L
L
–0.04
–0.06
20
40
60
80
100
120
140
160
2
4
6
8
10
12
14
16
TIME (µs)
TIME (µs)
Figure 33. Large Signal Transient Response, 10 V
Figure 36. Small Signal Transient Response, 10 V
2.0
0.06
0.04
0.02
0
1.5
1.0
0.5
0
ADA4092-4
= ±15V
= 25°C
= 100kΩ
= 100pF
V
T
–0.5
–1.0
SY
ADA4092-4
–0.02
A
V
= ±15V
SY
R
C
L
L
T
= 25°C
A
R
C
= 100kΩ
= 100pF
L
L
–0.04
–0.06
–1.5
–2.0
40
80
120
160
200
2
4
6
8
10
12
14
16
TIME (µs)
TIME (µs)
Figure 34. Large Signal Transient Response, 30 V
Figure 37. Small Signal Transient Response, 30 V
Rev. A | Page 12 of 20
ADA4092-4
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
–1.6
ADA4092-4
ADA4092-4
V
T
= ±1.5V
V
T
= ±1.5V
SY
= 25°C
SY
= 25°C
A
A
0
10
20
30
40
50
60
70
80
90
0
10
20
30
40
50
TIME (µs)
60
70
80
90
100
TIME (µs)
Figure 38. Positive Overload Recovery, 3 V
Figure 41. Negative Overload Recovery, 3 V
6
5
4
3
2
1
0
0
–1
–2
–3
–4
–5
–6
ADA4092-4
ADA4092-4
V
T
= ±5V
V
T
= ±5V
SY
= 25°C
SY
= 25°C
A
A
–1
0
10
20
30
40
TIME (µs)
50
60
70
90
0
10
20
30
40
50
60
70
80
90
TIME (µs)
Figure 39. Positive Overload Recovery, 10 V
Figure 42. Negative Overload Recovery, 10 V
0
–2
16
14
12
10
8
–4
–6
–8
ADA4092-4
ADA4092-4
6
V
T
= ±15V
V
T
= ±15V
SY
= 25°C
SY
= 25°C
A
–10
–12
–14
–16
A
4
2
0
–2
0
10
20
30
40
TIME (µs)
50
60
70
80
0
10
20
30
40
50
60
70
80
90
TIME (µs)
Figure 40. Positive Overload Recovery, 30 V
Figure 43. Negative Overload Recovery, 30 V
Rev. A | Page 13 of 20
ADA4092-4
0.5
1000
100
10
ADA4092-4
= ±15V
ADA4092-4
= ±15V
V
0.4
SY
V
SY
T = 25°C
T
= 25°C
A
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
0
1
2
3
4
5
6
7
8
9
10
0.01
0.10
1
10
100
1000
TIME (µs)
FREQUENCY (Hz)
Figure 44. Peak-to-Peak Voltage Noise
Figure 46. Voltage Noise Density
200
180
160
140
120
100
80
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
ADA4092-4
60
T
= 25°C
A
ADA4092-4
40
V
T
= ±1.5V, ±5V, ±15V
= 25°C
SY
A
20
0
0
4
8
12
16
20
(V)
24
28
32
36
20
100
1k
10k
50k
V
FREQUENCY (Hz)
SUPPLY
Figure 47. Channel Separation vs. Frequency
Figure 45. Supply Current vs. Supply Voltage
Rev. A | Page 14 of 20
ADA4092-4
THEORY OF OPERATION
A common practice in bipolar amplifiers to protect the input
transistors from large differential voltages is to include series
resistors and differential diodes. See Figure 49 for the full input
protection circuitry. These diodes turn on whenever the differential
voltage exceeds approximately 0.6 V. In this condition, current
flows between the input pins, limited only by the two 5 kΩ
resistors. Evaluate each application carefully to make sure that
the increase in current does not affect performance.
The ADA4092-4 is a single-supply, micropower amplifier
featuring rail-to-rail inputs and outputs. To achieve wide input
and output ranges, these amplifiers employ unique input and
output stages.
INPUT STAGE
In Figure 48, the input stage comprises two differential pairs, a
PNP pair (PNP input stage) and an NPN pair (NPN input stage).
These input stages do not work in parallel. Instead, only one
stage is on for any given input common-mode signal level. The
PNP stage (Transistor Q1 and Transistor Q2) is required to ensure
that the amplifier remains in the linear region when the input
voltage approaches and reaches the negative rail. Alternatively,
the NPN stage (Transistor Q5 and Transistor Q6) is needed for
input voltages up to, and including, the positive rail.
OUTPUT STAGE
The output stage in the ADA4092-4 device uses a PNP and an
NPN transistor, as do most output stages. However, Q32 and
Q33, the output transistors, connect with their collectors to an
output pin to achieve the rail-to-rail output swing.
As the output voltage approaches either the positive or the
negative rail, these transistors begin to saturate. Thus, the final
limit on output voltage is the saturation voltage of these transistors,
which is about 50 mV. The output stage has inherent gain arising
from the transistor output impedance, as well as any external load
impedance; consequently, the open-loop gain of the op amp is
dependent on the load resistance and decreases when the output
voltage is close to either rail.
For the majority of the input common-mode range, the PNP
stage is active, as shown in Figure 8 through Figure 13. Notice
that the VOS shifts and that the bias current switches direction at
approximately 1.5 V below the positive rail. At voltages below this
level, the bias current flows out of the ADA4092-4 input, from
the PNP input stage. However, above this voltage, the bias
current enters the device due to the NPN stage. The actual
mechanism within the amplifier for switching between the input
stages comprises Q3, Q4, and Q7. As the input common-mode
voltage increases, the emitters of Q1 and Q2 follow that voltage
plus a diode drop. Eventually, the emitters of Q1 and Q2 are
high enough to turn on Q3, which diverts the tail current away
from the PNP input stage, turning it off. The tail current of the
PNP pair is diverted to the Q4/Q7 current mirror to activate the
NPN input stage, as shown in Figure 48.
–IN
Q32
Q3
Q16
Q17
Q5 Q6
+IN
Q1 Q2
Q8
Q10
Q11
Q12
Q14
Q15
OUT
Q9
Q13
Q18
Q19
Q33
Q4
Q7
Figure 48. Simplified Schematic Without Input Protection (See Figure 49)
Rev. A | Page 15 of 20
ADA4092-4
INPUT OVERVOLTAGE PROTECTION
The ADA4092-4 has two different ESD circuits for enhanced
protection, as shown in Figure 49.
Therefore, consider two conditions to determine which case is
the limiting factor.
1. Consider, for example, that when operating on 15 V, the
inputs can go +42 V above the negative supply rail. With
the −V pin equal to −15 V, +42 V above this supply (the
negative supply) is +27 V.
2. There is a restriction on the input current of 5 mA through
a 5 kΩ resistor to the ESD structure to the positive rail. In
the first condition, +27 V through the 5 kΩ resistor to +15 V
gives a current of 2.4 mA. Thus, the DIAC is the limiting
factor. If the ADA4092-4 supply voltages are changed to 5 V,
then −5 V + 42 V = +37 V. However, +5 V + (5 kΩ × 5 mA) =
30 V. Thus, the normal resistor diode structure is the
limitation when running on lower supply voltages.
+V
D3
D1
D2
R1
D4
D7
D5
D6
R2
D8
–V
Additional resistance can be added externally in series with
each input to protect against higher peak voltages; however, the
additional thermal noise of the resistors must be considered.
The flatband voltage noise of the ADA4092-4 is approximately
25 nV/√Hz, and a 5 kΩ resistor has a noise of 9 nV/√Hz. Adding
an additional 5 kΩ resistor increases the total noise by less than
15% root sum square (rss). Therefore, maintain resistor values
below this value (5 kΩ) when overall noise performance is critical.
Figure 49. Complete Input Protection Network
One circuit is a series resistor of 5 kΩ to the internal inputs and
diodes (D1 and D2 or D5 and D6) from the internal inputs to the
supply rails. The other protection circuit is a circuit with two
DIACs (D3 and D4 or D7 and D8) to the supply rails. A DIAC
can be considered a bidirectional Zener diode with a transfer
characteristic, as shown in Figure 50.
Note that this represents input protection under abnormal
conditions only. The correct amplifier operation input voltage
range (IVR) is specified in Table 2, Table 3, and Table 4.
COMPARATOR OPERATION
Although op amps are quite different from comparators,
occasionally an unused section of a dual or a quad op amp
can be pressed into service as a comparator; however, this is not
recommended. For rail-to-rail output op amps, the output stage
is generally a ratioed current mirror with bipolar or MOSFET
transistors. With the part operating open loop, the second stage
increases the current drive to the ratioed mirror to close the loop,
but it cannot, which results in an increase in supply current. With
three of the op amps operating normally and the fourth one in
comparator mode, the supply current increases by about 200 µA
(see Figure 51).
5
4
3
2
1
0
–1
–2
–3
1000
ONE COMPARATOR, V
OUT
HIGH
900
800
700
600
500
400
300
200
100
–50 –40 –30 –20 –10
0
10
20
30
40
50
VOLTAGE (V)
ONE COMPARATOR, V
NORMAL OPERATION
LOW
OUT
Figure 50. DIAC Transfer Characteristic
For a worst-case design analysis, consider two cases. The
ADA4092-4 has a normal ESD structure from the internal op
amp inputs to the supply rails. In addition, it has 42 V DIACs
from the external inputs to the rails, as shown in Figure 48.
0
0
4
8
12
16
V
20
(V)
24
28
32
36
SY
Figure 51. Comparator Supply Current
Rev. A | Page 16 of 20
ADA4092-4
OUTLINE DIMENSIONS
5.10
5.00
4.90
14
8
7
4.50
4.40
4.30
6.40
BSC
1
PIN 1
0.65 BSC
1.05
1.00
0.80
1.20
0.20
0.09
MAX
0.75
0.60
0.45
8°
0°
0.15
0.05
COPLANARITY
0.10
SEATING
PLANE
0.30
0.19
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 52. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +125°C
−40°C to +125°C
Package Description
Package Option
RU-14
RU-14
ADA4092-4ARUZ
ADA4092-4ARUZ-RL
14-Lead Thin Shrink Small Outline Package [TSSOP]
14-Lead Thin Shrink Small Outline Package [TSSOP]
1 Z = RoHS Compliant Part.
Rev. A | Page 17 of 20
ADA4092-4
NOTES
Rev. A | Page 18 of 20
ADA4092-4
NOTES
Rev. A | Page 19 of 20
ADA4092-4
NOTES
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08803-0-5/10(A)
Rev. A | Page 20 of 20
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