ADA4091-4ARUZ-RL [ADI]
Precision Micropower, OVP, RRIO Operational Amplifier; 精密微功耗， OVP ， RRIO运算放大器
| 型号： | ADA4091-4ARUZ-RL |
| 厂家： | 
ADI |
| 描述： | Precision Micropower, OVP, RRIO Operational Amplifier |
| 文件： | 总20页 (文件大小：448K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Precision Micropower, OVP, RRIO
Operational Amplifier
ADA4091-2/ADA4091-4
FEATURES
PIN CONFIGURATIONS
Single-supply operation: 2.7 V to 36 V
Wide input voltage range
Rail-to-rail output swing
Low supply current: 200 µA/amplifier
Wide bandwidth: 1.2 MHz
OUTA
–INA
+INA
–V
1
2
3
4
8
7
6
5
+V
OUTB
–INB
+INB
ADA4091-2
TOP VIEW
(Not to Scale)
Figure 1. 8-Lead, Narrow-Body SOIC (R-8)
Slew rate: 0.46 V/µs
OUTA
–INA
+INA
–V
1
2
3
4
8
7
6
5
+V
Low offset voltage: 250 µV maximum
No phase reversal
Overvoltage protection (OVP)
25 V above/below supply rails at 5 V
12 V above/below supply rails at 15 V
OUTB
–INB
+INB
ADA4091-2
TOP VIEW
(Not to Scale)
NOTES
1. IT IS RECOMMENDED TO CONNECT THE
EXPOSED PAD TO V–.
APPLICATIONS
Figure 2. 8-Lead LFCSP (CP-8-9)
Industrial process control
Battery-powered instrumentation
Power supply control and protection
Telecommunications
Remote sensors
Low voltage strain gage amplifiers
DAC output amplifiers
1
2
3
4
5
6
7
14
13
12
11
10
9
OUTA
–INA
+INA
+V
OUTD
–IND
+IND
–V
ADA4091-4
TOP VIEW
(Not to Scale)
+INB
–INB
OUTB
+INC
–INC
OUTC
8
Figure 3. 14-Lead TSSOP (RU-14)
GENERAL DESCRIPTION
The ADA4091-2 dual and ADA4091-4 quad are micropower,
single-supply, 1.2 MHz bandwidth amplifiers featuring rail-to-
rail inputs and outputs. They are guaranteed to operate from a
+2.7 V to +30 V single supply as well as from 1.35 V to 15 V
dual supplies.
–INA
+INA
V+
1
2
3
4
12 –IND
11 +IND
10 V–
ADA4091-4
TOP
VIEW
9
+INC
+INB
The ADA4091 family features a unique input stage that allows
the input voltage to exceed either supply safely without any phase
reversal or latch-up; this is called overvoltage protection, or OVP.
Applications for these amplifiers include portable telecom-
munications equipment, power supply control and protection,
and interface for transducers with wide output ranges. Sensors
requiring a rail-to-rail input amplifier include Hall effect, piezo-
electric, and resistive transducers.
NOTES
1. NC = NO CONNECT.
2. IT IS RECOMMENDED TO CONNECT THE
EXPOSED PAD TO V–.
Figure 4. 16-Lead LFCSP (CP-16-17)
The ADA4091-2 is available in 8-lead, plastic SOIC and 8-lead
LFCSP packages. The ADA4091-4 is available in 14–lead TSSOP
and 16-lead LFCSP surface-mount packages.
The ability to swing rail-to-rail at both the input and output enables
designers, for example, to build multistage filters in single-supply
systems and to maintain high signal-to-noise ratios (SNR).
Table 1. Low Power, 36 V Operational Amplifiers
The ADA4091 family is specified over the extended industrial
temperature range of −40°C to +125°C. The ADA4091 family is
part of the growing selection of 36 V, low power op amps from
Analog Devices, Inc., (see Table 1).
Family
Single
Dual
Rail-to-Rail I/O
PJFET
Low Noise
OP1177
OP2177
OP4177
ADA4091-2
ADA4091-4
AD8682
AD8684
Quad
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2008–2010 Analog Devices, Inc. All rights reserved.
ADA4091-2/ADA4091-4
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................6
Typical Performance Characteristics ..............................................7
Theory of Operation ...................................................................... 14
Input Stage................................................................................... 14
Output Stage................................................................................ 14
Input Overvoltage Protection................................................... 15
Outline Dimensions....................................................................... 16
Ordering Guide .......................................................................... 18
Applications....................................................................................... 1
General Description ......................................................................... 1
Pin Configurations ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Specifications............................................................... 3
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
REVISION HISTORY
5/10—Rev. D. to Rev. E
7/09—Rev. 0 to Rev. A
Changes to Data Sheet Title ............................................................ 1
Changes to Table 2, Input Characteristics, Offset Voltage.......... 3
Changes to Table 3, Input Characteristics, Offset Voltage.......... 4
Changes to Table 4, Input Characteristics, Offset Voltage.......... 5
Changes to Data Sheet Title .............................................................1
Changes to Features ..........................................................................1
Changes to Table 2.............................................................................3
Changes to Table 3.............................................................................4
Changes to Table 4.............................................................................5
Added Input Current Parameter, Table 5.......................................6
Added New Figure 12 and Figure 13, Renumbered
Sequentially ........................................................................................8
Added New Figure 24 and Figure 25 ........................................... 10
Added New Figure 36 and Figure 37 ........................................... 12
Added New Figure 43 .................................................................... 13
Changes to Input Overvoltage Protection Section..................... 15
Changes to Ordering Guide.......................................................... 16
4/10—Rev. C to Rev. D
Changes to Table 2, Added LFCSP to Input Characteristics ...... 3
Changes to Table 3, Added LFCSP to Input Characteristics ...... 4
Changes to Table 4, Added LFCSP to Input Characteristics ...... 5
10/09—Rev. B to Rev. C
Added 8-Lead LFCSP and 16-Lead LFCSP.....................Universal
Change to Features Section ............................................................. 1
Updated Outline Dimensions....................................................... 16
Changes to Ordering Guide .......................................................... 18
10/08—Revision 0: Initial Version
7/09—Rev. A to Rev. B
Added New Part ADA4091-4 ...........................................Universal
Changes to Features Section, General Description Section, and
Figure 4 .............................................................................................. 1
Added Figure 2, Renumbered Sequentially .................................. 1
Changes to Table 1............................................................................ 1
Changes to Table 2............................................................................ 3
Changes to Table 3............................................................................ 4
Changes to Table 4............................................................................ 5
Changes to Table 5............................................................................ 6
Changes to Table 6............................................................................ 6
Updated Outline Dimensions....................................................... 16
Changes to Ordering Guide .......................................................... 16
Rev. E | Page 2 of 20
ADA4091-2/ADA4091-4
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
VSY
= 1.5 V, V CM = 0.0 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
−250
−400
−600
−40
−40
+250
+400
+600
µV
µV
µV
µV/°C
nA
nA
nA
nA
nA
nA
V
dB
dB
dB
dB
dB
dB
ADA4091-4 LFCSP package
−40°C ≤ TA ≤ +125°C
Offset Voltage Drift
Input Bias Current
∆VOS/∆T
IB
2.5
−44
−55
−55
−275
−3
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
+55
+275
+3
+5
+75
+1.5
Input Offset Current
IOS
0.5
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
−5
−75
−1.5
84
Input Voltage Range
Common-Mode Rejection Ratio
CMRR
AVO
VCM = −1.35 V to +1.35 V
−40°C ≤ TA ≤ +125°C
RL = 100 kΩ, VO = −1.2 V to +1.2 V
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ, VO = −1.2 V to +1.2 V
−40°C ≤ TA ≤ +125°C
100
113
94
78
Large Signal Voltage Gain
106
101
92
85
OUTPUT CHARACTERISTICS
Output Voltage High
VOH
RL = 100 kΩ to GND
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to GND
−40°C to +125°C
RL = 100 kΩ to GND
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to GND
−40°C ≤ TA ≤ +125°C
Source/sink
1.490
1.490
1.475
1.455
1.495
V
V
V
V
V
V
V
V
1.485
Output Voltage Low
VOL
−1.499
−1.495
−1.495
−1.495
−1.490
−1.490
Short-Circuit Limit
Open-Loop Impedance
POWER SUPPLY
ISC
ZOUT
31
102
mA
Ω
f = 1 MHz, AV = 1
Power Supply Rejection Ratio
PSRR
ISY
VSY = 2.7 V to 36 V
−40°C ≤ TA ≤ +125°C
IO = 0 mA
108
100
126
165
dB
dB
µA
µA
Supply Current per Amplifier
200
300
−40°C ≤ TA ≤ +125°C
DYNAMIC PERFORMANCE
Slew Rate
Settling Time
SR
tS
RL = 100 kΩ, CL = 30 pF
To 0.01%
0.46
22
V/µs
µs
Gain Bandwidth Product
Phase Margin
GBP
ΦM
1.22
69
MHz
Degrees
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
en p-p
en
0.1 Hz to 10 Hz
f = 1 kHz
0.8
24
µV p-p
nV/√Hz
Rev. E | Page 3 of 20
ADA4091-2/ADA4091-4
VSY
= 5.0 V, VCM = 0.0 V, TA = 25°C, unless otherwise noted.
Table 3.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
−250
−400
−600
−45
−40
+250
+400
+600
µV
µV
µV
µV/°C
nA
nA
nA
nA
nA
nA
V
ADA4091-4 LFCSP package
−40°C ≤ TA ≤ +125°C
Offset Voltage Drift
Input Bias Current
∆VOS/∆T
IB
2.5
−50
−60
−80
−350
−3
−7
−100
−5
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
+80
+350
+3
+7
+100
+5
Input Offset Current
IOS
0.5
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
Input Voltage Range
Common-Mode Rejection Ratio
CMRR
AVO
VCM = −4.85 V to +4.85 V
−40°C ≤ TA ≤ +125°C
RL = 100 kΩ, VO = 4.7 V
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ, VO = 4.7 V
−40°C ≤ TA ≤ +125°C
95
88
113
106
98
113
117
100
dB
dB
dB
dB
dB
dB
Large Signal Voltage Gain
90
OUTPUT CHARACTERISTICS
Output Voltage High
VOH
RL = 100 kΩ to GND
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to GND
−40°C ≤ TA ≤ +125°C
RL = 100 kΩ to GND
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to GND
−40°C ≤ TA ≤ +125°C
Source/sink
4.980
4.980
4.950
4.900
4.990
V
V
V
V
V
V
V
V
4.960
Output Voltage Low
VOL
−4.998
−4.990
−4.990
−4.980
−4.980
−4.975
Short-Circuit Limit
Open-Loop Impedance
POWER SUPPLY
ISC
ZOUT
20
77
mA
Ω
f = 1 MHz, AV = 1
Power Supply Rejection Ratio
PSRR
ISY
VSY = 2.7 V to 36 V
−40°C ≤ TA ≤ +125°C
IO = 0 mA
108
100
126
180
dB
dB
µA
µA
Supply Current per Amplifier
225
300
−40°C ≤ TA ≤ +125°C
DYNAMIC PERFORMANCE
Slew Rate
Settling Time
SR
tS
RL = 100 kΩ, CL = 30 pF
To 0.01%
0.46
22
V/µs
µs
Gain Bandwidth Product
Phase Margin
GBP
ΦM
1.22
70
MHz
Degrees
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
en p-p
en
0.1 Hz to 10 Hz
f = 1 kHz
0.8
24
µV p-p
nV/√Hz
Rev. E | Page 4 of 20
ADA4091-2/ADA4091-4
VSY
= 15.0 V, VCM = 0.0 V, VO = 0.0 V, TA = 25°C, unless otherwise noted.
Table 4.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
−250
−400
−600
−35
−40
+250
+400
+600
µV
µV
µV
µV/°C
nA
nA
nA
nA
nA
nA
V
dB
dB
dB
dB
dB
dB
ADA4091-4 LFCSP package
−40°C ≤ TA ≤ +125°C
Offset Voltage Drift
Input Bias Current
∆VOS/∆T
IB
3.0
−50
−60
−80
−510
−3
−10
−140
−15
104
95
116
108
102
93
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
+80
+510
+3
+10
+140
+15
Input Offset Current
IOS
0.5
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
Input Voltage Range
Common-Mode Rejection Ratio
CMRR
AVO
VCM = −14.85 V to +14.85 V
−40°C ≤ TA ≤ +125°C
RL = 100 kΩ, VO = 14.7 V
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ, VO = 14.7 V
−40°C ≤ TA ≤ +125°C
121
119
104
Large Signal Voltage Gain
OUTPUT CHARACTERISTICS
Output Voltage High
VOH
RL = 100 kΩ to GND
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to GND
−40°C ≤ TA ≤ +125°C
RL = 100 kΩ to GND
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to GND
−40°C ≤ TA ≤ +125°C
Source/sink
14.975
14.950
14.900
14.800
14.980
14.920
V
V
V
V
V
V
V
V
Output Voltage Low
VOL
−14.996 −14.990
−14.985
−14.975 −14.950
−14.940
Short-Circuit Limit
Open-Loop Impedance
POWER SUPPLY
ISC
ZOUT
20
71
mA
Ω
f = 1 MHz, AV = 1
Power Supply Rejection Ratio
PSRR
ISY
VSY = 2.7 V to 36 V
−40°C ≤ TA ≤ +125°C
IO = 0 mA
108
100
126
dB
dB
µA
µA
Supply Current per Amplifier
200
250
350
−40°C ≤ TA ≤ +125°C
DYNAMIC PERFORMANCE
Slew Rate
Settling Time
SR
tS
RL = 100 kΩ, CL = 30 pF
To 0.01%
0.46
22
V/µs
µs
Gain Bandwidth Product
Phase Margin
Channel Separation
NOISE PERFORMANCE
Voltage Noise
GBP
ΦM
CS
1.27
72
100
MHz
Degrees
dB
f = 1 kHz
en p-p
en
0.1 Hz to 10 Hz
f = 1 kHz
0.8
25
µV p-p
nV/√Hz
Voltage Noise Density
Rev. E | Page 5 of 20
ADA4091-2/ADA4091-4
ABSOLUTE MAXIMUM RATINGS
Table 5.
THERMAL RESISTANCE
θJA is specified for the device soldered on a 4-layer JEDEC standard
PCB with zero airflow. The exposed pad is soldered to the
application board.
Parameter
Supply Voltage
Input Voltage
Rating
36 V
Refer to the Input
Overvoltage Protection
section
VSY
5 mA
Indefinite
−65°C to +150°C
−40°C to +125°C
−65°C to +150°C
300°C
Table 6. Thermal Resistance
Package Type
θJA
155
112
75
θJC
45
35
12
14
Unit
°C/W
°C/W
°C/W
°C/W
Differential Input Voltage1
Input Current
8-Lead SOIC (R-8)
14-Lead TSSOP (RU-14)
8-Lead LFCSP (CP-8-9)
16-Lead LFCSP (CP-16-17)
Output Short-Circuit Duration to GND
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature (Soldering, 60 sec)
1 Input current should be limited to 5 mA.
55
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. E | Page 6 of 20
ADA4091-2/ADA4091-4
TYPICAL PERFORMANCE CHARACTERISTICS
200
10,000
1000
100
10
ADA4091-2
T
= 25°C
180
160
140
120
100
80
A
V
= ±1.5V
SY
V
– V
OH
DD
60
V
– V
SS
OL
40
1
20
ADA4091-2
= ±1.5V
V
SY
0
0.1
0.001
–250 –200 –150 –100 –50
0
50 100 150 200 250
0.01
0.1
1
10
100
V
(µV)
LOAD CURRENT (mA)
OS
Figure 5. Input Offset Voltage Distribution
Figure 8. Dropout Voltage vs. Load Current
300
250
200
150
100
50
100
80
60
40
20
0
100
80
60
40
20
0
ADA4091-2
PHASE
–40°C ≤ T ≤ +125°C
A
V
= ±1.5V
SY
GAIN
ADA4091-2
V
= ±1.5V
SY
R
C
= 1MΩ
= 35pF
L
L
0
–20
1k
–20
10M
–1
0
1
2
3
4
5
6
7
8
10k
100k
1M
TCV (µV/°C)
OS
FREQUENCY (Hz)
Figure 6. TCVOS Distribution
Figure 9. Open-Loop Gain and Phase vs. Frequency
350
300
250
200
150
100
50
50
ADA4091-2
= ±1.5V
V
SY
A
= 100
= 10
= 1
V
40
30
20
10
0
+125°C
A
V
+85°C
A
V
0
–50
–100
–150
ADA4091-2
–10
–20
V
= ±1.5V
= 1MΩ
SY
+25°C
0
R
C
L
L
–40°C
–1.0
= 35pF
–1.5
–0.5
0.5
1.0
1.5
10
100
1k
10k
100k
1M
10M
V
(V)
FREQUENCY (Hz)
CM
Figure 7. Input Bias Current vs. Common-Mode Voltage
Figure 10. Closed-Loop Gain vs. Frequency
Rev. E | Page 7 of 20
ADA4091-2/ADA4091-4
3.0
2.5
2.0
1.5
1.0
0.5
0
1k
100
A
= 100
V
10
1
A
= 10
V
A
= 1
V
ADA4091-2
ADA4091-2
V
V
= ±1.5V
= 2.8V p-p
= 100kΩ
SY
IN
L
T
= 25°C
A
R
V
= ±1.5V
SY
0.1
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 11. Output Impedance vs. Frequency
Figure 14. Output Swing vs. Frequency
2.0
1.5
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.0
0.5
0
ADA4091-2
V
= ±1.5V
SY
–0.5
–1.0
–1.5
–2.0
T
= 25°C
= 100kΩ
= 100pF
= +1
A
R
C
A
L
L
V
ADA4091-2
= 25°C
T
A
V
= ±1.5V
SY
–0.2
0
5
10
15
20
25
30
35
40
45
50
0
10
20
30
40
50
60
70
80
90
TIME (µs)
TIME (µs)
Figure 12. Large Signal Transient Response
Figure 15. Positive Overload Recovery
0.06
0.04
0.02
0
0
–0.2
–0.4
–0.6
–0.8
ADA4091-2
V
= ±1.5V
SY
T
= 25°C
= 100kΩ
= 100pF
= +1
A
–0.02
–0.04
–0.06
–0.08
R
C
A
L
L
V
–1.0
–1.2
–1.4
–1.6
ADA4091-2
= 25°C
T
A
V
= ±1.5V
SY
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
0
10
20
30
40
50
60
70
80
90
TIME (µs)
TIME (µs)
Figure 16. Negative Overload Recovery
Figure 13. Small Signal Transient Response
Rev. E | Page 8 of 20
ADA4091-2/ADA4091-4
225
200
175
150
125
100
75
0.06
0.04
0.02
0
ADA4091-2
T
= 25°C
= ±5V
A
V
SY
ADA4091-2
V
= ±5V
SY
T
= 25°C
= 100kΩ
= 100pF
= +1
A
R
C
A
L
L
V
–0.02
–0.04
–0.06
–0.08
50
25
0
–250 –200 –150 –100 –50
0
50 100 150 200 250
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
V
(µV)
TIME (µs)
OS
Figure 17. Input Offset Voltage Distribution
Figure 20. Small Signal Transient Response
400
350
300
250
200
150
100
50
500
400
300
200
100
0
ADA4091-2
= ±5V
ADA4091-2
V
–40°C ≤ T ≤ +125°C
SY
A
V
= ±5V
SY
+125°C
+85°C
+25°C
–100
–200
–40°C
0
–1
0
1
2
3
4
5
6
7
8
–5
–4
–3
–2
–1
0
1
2
3
4
5
TCV (µV/°C)
OS
V
(V)
CM
Figure 18. TCVOS Distribution
Figure 21. Input Bias Current vs. Common-Mode Voltage
100
80
60
40
20
0
100
80
60
40
20
0
6
4
PHASE
2
GAIN
0
ADA4091-2
V
= ±5V
SY
T
= 25°C
= 100kΩ
= 100pF
= +1
A
R
C
A
L
L
V
–2
–4
–6
ADA4091-2
V
= ±5V
= 1MΩ
= 35pF
SY
R
C
L
L
–20
1k
–20
10M
10k
100k
1M
0
5
10
15
20
25
30
35
40
45
50
TIME (µs)
FREQUENCY (Hz)
Figure 19. Large Signal Transient Response
Figure 22. Open-Loop Gain and Phase vs. Frequency
Rev. E | Page 9 of 20
ADA4091-2/ADA4091-4
50
40
1k
A
= 100
= 10
= 1
V
100
30
A
V
20
A
= 100
= 10
V
10
1
10
A
V
A
A
V
0
ADA4091-2
–10
–20
ADA4091-2
= 25°C
V
R
C
= ±5V
= 1MΩ
= 35pF
SY
= 1
V
T
L
L
A
V
= ±5V
SY
0.1
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 26. Closed-Loop Gain vs. Frequency
Figure 23. Output Impedance vs. Frequency
6
5
10
9
8
7
6
5
4
3
2
1
0
4
3
2
ADA4091-2
1
0
ADA4091-2
= 25°C
V
= ±5V
SY
IN
L
T
V
R
= 9.8V p-p
A
= 100kΩ
V
= ±5V
SY
100
1k
10k
100k
1M
0
10
20
30
40
50
60
70
80
90
TIME (µs)
FREQUENCY (Hz)
Figure 24. Output Voltage Swing vs. Frequency
Figure 27. Positive Overload Recovery
10,000
1000
100
10
1
0
–1
–2
V
– V
OH
DD
V
– V
SS
OL
–3
–4
–5
1
ADA4091-2
= 25°C
T
A
ADA4091-2
= ±5V
V
= ±5V
SY
V
SY
–6
0.1
0.001
0.01
0.1
1
10
100
0
10
20
30
40
50
60
70
80
TIME (µs)
LOAD CURRENT (mA)
Figure 28. Negative Overload Recovery
Figure 25. Dropout Voltage vs. Load Current
Rev. E | Page 10 of 20
ADA4091-2/ADA4091-4
250
200
150
100
50
100
80
60
40
20
0
100
ADA4091-2
= 25°C
SY
PHASE
T
A
V
= ±15V
80
60
40
20
0
GAIN
ADA4091-2
V
= ±15V
= 1MΩ
= 35pF
SY
R
C
L
L
0
–20
1k
–20
10M
–250 –200 –150 –100 –50
0
50 100 150 200 250
10k
100k
FREQUENCY (Hz)
1M
V
(µV)
OS
Figure 29. Input Offset Voltage Distribution
Figure 32. Open-Loop Gain and Phase vs. Frequency
350
300
250
200
150
100
50
20
15
ADA4091-2
–40°C ≤ T ≤ +125°C
A
V
= ±15V
SY
10
5
ADA4091-2
0
V
= ±15V
SY
T
= 25°C
= 100kΩ
= 100pF
= +1
A
R
C
A
–5
L
L
V
–10
–15
–20
0
–25
0
25
50
75
100
125
150
175
200
–1
0
1
2
3
4
5
6
7
8
TIME (µs)
TCV (µV/°C)
OS
Figure 30. TCVOS Distribution
Figure 33. Large Signal Transient Response
700
600
500
400
300
200
100
0
0.06
0.04
0.02
0
ADA4091-2
= ±15V
V
SY
+125°C
ADA4091-2
V
= ±15V
SY
T
= 25°C
= 100kΩ
= 100pF
= +1
A
R
C
A
L
L
V
–0.02
–0.04
–0.06
–0.08
+85°C
+25°C
–100
–200
–300
–40°C
–15
–10
–5
0
5
10
15
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
V
(V)
TIME (µs)
CM
Figure 31. Input Bias Current vs. Common-Mode Voltage
Figure 34. Small Signal Transient Response
Rev. E | Page 11 of 20
ADA4091-2/ADA4091-4
35
30
25
20
15
50
40
A
= 100
= 10
= 1
V
30
A
V
20
10
A
V
0
10
–10
–20
–30
ADA4091-2
ADA4091-2
5
V
V
= ±15V
V
= ±15V
= 1MΩ
= 35pF
SY
IN
SY
L
L
= 29.8V p-p
= 100kΩ
R
C
R
L
0
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 35. Output Voltage Swing vs. Frequency
Figure 38. Closed-Loop Gain vs. Frequency
10,000
1000
100
10
16
14
12
10
8
V
– V
OH
DD
V
– V
SS
OL
6
4
2
1
ADA4091-2
0
T
= 25°C
= ±15V
ADA4091-2
= ±15V
A
V
V
SY
SY
0.1
0.001
–2
0.01
0.1
1
10
100
0
10
20
30
40
50
60
70
80
90
LOAD CURRENT (mA)
TIME (µs)
Figure 36. Dropout Voltage vs. Load Current
Figure 39. Positive Overload Recovery
1k
2
0
–2
100
10
1
–4
–6
A
= 100
= 10
V
–8
–10
–12
–14
–16
A
V
ADA4091-2
ADA4091-2
= 25°C
A
= 1
V
T
V
= 25°C
= ±15V
T
A
A
V
= ±15V
SY
SY
0.1
10
100
1k
10k
100k
1M
10M
0
10
20
30
40
50
60
70
80
TIME (µs)
FREQUENCY (Hz)
Figure 40. Negative Overload Recovery
Figure 37. Output Impedance vs. Frequency
Rev. E | Page 12 of 20
ADA4091-2/ADA4091-4
100
80
60
40
20
0
0.5
0.4
ADA4091-2
V
= ±1.5V, ±5V, ±15V
SY
0.3
0.2
0.1
PSRR+
PSRR–
0
–0.1
–0.2
–0.3
–0.4
–0.5
ADA4091-2
= ±15V
V
SY
–20
100
1k
10k
100k
1M
10M
0
1
2
3
4
5
6
7
8
9
10
FREQUENCY (Hz)
TIME (Seconds)
Figure 44. PSRR vs. Frequency
Figure 41.Peak-to-Peak Voltage Noise
500
450
400
350
300
250
200
150
100
50
–60
–70
ADA4091-2
= 25°C
ADA4091-2
= ±15V
T
V
A
SY
–80
–90
–100
–110
–120
–130
0
0
5
10
15
20
25
30
35
10
100
1k
10k
100k
V
(V)
FREQUENCY (Hz)
SY
Figure 42. Channel Separation vs. Frequency
Figure 45. Supply Current vs. Supply Voltage
110
100
90
80
70
60
50
40
30
20
10
0
1k
ADA4091-2
V
= ±5V, ±15V
SY
V
= ±1.5V
SY
100
ADA4091-2
= 25°C
T
A
V
= ±5V
SY
10
0.01
100
1k
10k
100k
1M
10M
0.1
1
10
100
1k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 43. CMRR vs. Frequency
Figure 46. Voltage Noise Density
Rev. E | Page 13 of 20
ADA4091-2/ADA4091-4
THEORY OF OPERATION
Q1 and Q2 are high enough to turn on Q3, which diverts the
tail current away from the PNP input stage, turning it off. The
tail current of the PNP pair is diverted to the Q4/Q7 current
mirror to activate the NPN input stage.
The ADA4091 family is a single-supply, micropower amplifier
featuring rail-to-rail inputs and outputs. To achieve wide input
and output ranges, these amplifiers employ unique input and
output stages.
A common practice in bipolar amplifiers to protect the input
transistors from large differential voltages is to include series
resistors and differential diodes. See Figure 48 for the full input
protection circuitry. These diodes turn on whenever the diffe-
rential voltage exceeds approximately 0.6 V. In this condition,
current flows between the input pins, limited only by the two
5 kΩ resistors. Evaluate each application carefully to make sure
that the increase in current does not affect performance.
INPUT STAGE
In Figure 47, the input stage comprises two differential pairs, a
PNP pair (PNP input stage) and an NPN pair (NPN input
stage). These input stages do not work in parallel. Instead, only
one stage is on for any given input common-mode signal level.
The PNP stage (Transistor Q1 and Transistor Q2) is required to
ensure that the amplifier remains in the linear region when the
input voltage approaches and reaches the negative rail. Alter-
natively, the NPN stage (Transistor Q5 and Transistor Q6) is
needed for input voltages up to, and including, the positive rail.
OUTPUT STAGE
The output stage in the ADA4091-x device uses a PNP and
an NPN transistor, as do most output stages. However, Q32
and Q33, the output transistors, connect with their collectors
to the output pin to achieve the rail-to-rail output swing.
For the majority of the input common-mode range, the PNP
stage is active, as shown in Figure 7, Figure 21, and Figure 31.
Notice that the bias current switches direction at approximately
1.5 V below the positive rail. At voltages below this level, the
bias current flows out of the ADA4091-x input, from the PNP
input stage. Above this voltage, however, the bias current enters
the device, due to the NPN stage. The actual mechanism within
the amplifier for switching between the input stages comprises
Transistor Q3, Transistor Q4, and Transistor Q7. As the input
common-mode voltage increases, the emitters of Q1 and Q2
follow that voltage plus a diode drop. Eventually, the emitters of
As the output voltage approaches either the positive or negative
rail, these transistors begin to saturate. Thus, the final limit
on output voltage is the saturation voltage of these transistors,
which is about 50 mV. The output stage has inherent gain arising
from the transistor output impedance, as well as any external load
impedance; consequently, the open-loop gain of the op amp is
dependent on the load resistance and decreases when the output
voltage is close to either rail.
–IN
Q32
Q3
Q16
Q17
Q5 Q6
+IN
Q1 Q2
Q8
Q10
Q11
Q12
Q14
Q15
OUT
Q9
Q13
Q18
Q19
Q33
Q4
Q7
Figure 47. Simplified Schematic Without Input Protection (see Figure 48)
Rev. E | Page 14 of 20
ADA4091-2/ADA4091-4
INPUT OVERVOLTAGE PROTECTION
The ADA4091-x has two different ESD circuits for enhanced
protection, as shown in Figure 48.
For a worst-case design analysis, consider two cases. The
ADA4091-x has a normal ESD structure from the internal op
amp inputs to the supply rails. In addition, it has 42 V DIACs
from the external inputs to the rails, as shown in Figure 47.
Therefore, two conditions need to be considered to determine
which case is the limiting factor.
•
Condition 1. Consider, for example, that when operating
on 15 V, the inputs can go +42 V above the negative
supply rail. With the −V pin equal to −15 V, +42 V above
this supply (the negative supply) is +27 V.
+V
D3
D1
D2
R1
D4
D7
D5
D6
R2
D8
•
Condition 2. There is a restriction on the input current of
5 mA through a 5 kΩ resistor to the ESD structure to the
positive rail. In Condition 1, +27 V through the 5 kΩ
resistor to +15 V gives a current of 2.4 mA. Thus, the
DIAC is the limiting factor. If the ADA4091-x supply
voltages are changed to 5 V, th e n −5 V + 42 V = +37 V.
However, +5 V + (5 kΩ × 5 mA) = 30 V. Thus, the normal
resistor diode structure is the limitation when running on
lower supply voltages.
–V
Additional resistance can be added externally in series with
each input to protect against higher peak voltages; however, the
additional thermal noise of the resistors must be considered.
Figure 48. Complete Input Protection Network
One circuit is a series resistor of 5 kΩ to the internal inputs and
diodes (D1 and D2 or D5 and D6) from the internal inputs to
the supply rails. The other protection circuit is a circuit with
two DIACs (D3 and D4 or D7 and D8) to the supply rails. A
DIAC can be considered a bidirectional Zener diode with a
transfer characteristic, as shown in Figure 49.
The flatband voltage noise of the ADA4091-x is approximately
24 nV/√Hz, and a 5 kΩ resistor has a noise of 9 nV/√Hz. Adding
an additional 5 kΩ resistor increases the total noise by less than
15% root sum square (rss). Therefore, maintain resistor values
below this value (5 kΩ) when overall noise performance is critical.
5
Note that this represents input protection under abnormal con-
ditions only. The correct amplifier operation input voltage range
(IVR) is specified in Table 2, Table 3, and Table 4.
4
3
2
1
0
–1
–2
–3
–50 –40 –30 –20 –10
0
10
20
30
40
50
VOLTAGE (V)
Figure 49. DIAC Transfer Characteristic
Rev. E | Page 15 of 20
ADA4091-2/ADA4091-4
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 50. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
3.25
3.00 SQ
2.75
0.60 MAX
0.50
BSC
0.60 MAX
5
8
2.95
2.75 SQ
2.55
EXPOSED
PAD
1.60
1.50
1.40
PIN 1
INDICATOR
4
1
PIN 1
INDICATOR
0.50
0.40
0.30
TOP VIEW
BOTTOM VIEW
2.23
2.13
2.03
12° MAX
0.70 MAX
0.65TYP
0.90 MAX
0.85 NOM
0.05 MAX
0.01 NOM
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.30
0.23
0.18
SEATING
PLANE
SECTION OF THIS DATA SHEET.
0.20 REF
Figure 51. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD]
3 mm × 3 mm Body, Very Thin, Dual Lead
(CP-8-9)
Dimensions shown in millimeters
Rev. E | Page 16 of 20
ADA4091-2/ADA4091-4
5.10
5.00
4.90
14
8
7
4.50
4.40
4.30
6.40
BSC
1
PIN 1
0.65 BSC
1.05
1.00
0.80
1.20
MAX
0.20
0.09
0.75
0.60
0.45
8°
0°
0.15
0.05
COPLANARITY
0.10
SEATING
PLANE
0.30
0.19
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 52. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
4.10
4.00 SQ
3.90
0.35
0.30
0.25
PIN 1
INDICATOR
PIN 1
INDICATOR
13
16
1
0.65
BSC
12
EXPOSED
PAD
2.70
2.60 SQ
2.50
4
5
9
8
0.45
0.40
0.35
0.25 MIN
TOP VIEW
BOTTOM VIEW
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGC.
Figure 53. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-16-17)
Dimensions are millimeters
Rev. E | Page 17 of 20
ADA4091-2/ADA4091-4
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
R-8
R-8
Branding
ADA4091-2ARZ
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
8-Lead Standard Small Outline Package (SOIC_N)
8-Lead Standard Small Outline Package (SOIC_N)
8-Lead Standard Small Outline Package (SOIC_N)
8-Lead Frame Chip Scale Package (LFCSP_VD)
8-Lead Frame Chip Scale Package (LFCSP_VD)
8-Lead Frame Chip Scale Package (LFCSP_VD)
14-Lead Thin Shrink Small Outline Package (TSSOP)
14-Lead Thin Shrink Small Outline Package (TSSOP)
16-Lead Lead Frame Chip Scale Package (LFCSP_WQ)
16-Lead Lead Frame Chip Scale Package (LFCSP_WQ)
16-Lead Lead Frame Chip Scale Package (LFCSP_WQ)
ADA4091-2ARZ-R7
ADA4091-2ARZ-RL
ADA4091-2ACPZ-R2
ADA4091-2ACPZ-R7
ADA4091-2ACPZ-RL
ADA4091-4ARUZ
ADA4091-4ARUZ-RL
ADA4091-4ACPZ-R2
ADA4091-4ACPZ-R7
ADA4091-4ACPZ-RL
R-8
CP-8-9
CP-8-9
CP-8-9
RU-14
A1Z
A1Z
A1Z
RU-14
CP-16-17
CP-16-17
CP-16-17
1 Z = RoHS Compliant Part.
Rev. E | Page 18 of 20
ADA4091-2/ADA4091-4
NOTES
Rev. E | Page 19 of 20
ADA4091-2/ADA4091-4
NOTES
©2008–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07671-0-5/10(E)
Rev. E | Page 20 of 20
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