AD9709ASTZ1_技术文档

8-Bit, 125 MSPS, Dual TxDAC+

Digital-to-Analog Converter

AD9709

FEATURES

FUNCTIONAL BLOCK DIAGRAM

DVDD1/ DCOM1/

DVDD2 DCOM2 AVDD ACOM

8-bit dual transmit digital-to-analog converter (DAC)

125 MSPS update rate

Excellent SFDR to Nyquist @ 5 MHz output: 66 dBc

Excellent gain and offset matching: 0.1%

Fully independent or single-resistor gain control

Dual port or interleaved data

CLK1

I

OUTA1

OUTB1

1

DAC

PORT1

LATCH

REFIO

FSADJ1

FSADJ2

GAINCTRL

REFERENCE

WRT1/IQWRT

WRT2/IQSEL

DIGITAL

AD9709

INTERFACE

On-chip 1.2 V reference

BIAS

GENERATOR

SLEEP

Single 5 V or 3.3 V supply operation

Power dissipation: 380 mW @ 5 V

Power-down mode: 50 mW @ 5 V

48-lead LQFP

I

OUTA2

2

DAC

PORT2

LATCH

I

OUTB2

MODE

CLK2/IQ RESET

Figure 1.

APPLICATIONS

Communications

Base stations

Digital synthesis

Quadrature modulation

3D ultrasound

glitch energy and to maximize dynamic accuracy. Each DAC

provides differential current output, thus supporting single-

ended or differential applications. Both DACs can be

simultaneously updated and provide a nominal full-scale

current of 20 mA. The full-scale currents between each DAC

are matched to within 0.1%.

GENERAL DESCRIPTION

The AD9709¹is a dual-port, high speed, 2-channel, 8-bit CMOS

DAC. It integrates two high quality 8-bit TxDAC+® cores, a voltage

reference, and digital interface circuitry into a small 48-lead LQFP

package. The AD9709 offers exceptional ac and dc performance

while supporting update rates of up to 125 MSPS.

The AD9709 is manufactured on an advanced low-cost CMOS

process. It operates from a single supply of 3.3 V or 5 V and

consumes 380 mW of power.

The AD9709 has been optimized for processing I and Q data in

communications applications. The digital interface consists of two

double-buffered latches as well as control logic. Separate write

inputs allow data to be written to the two DAC ports independent

of one another. Separate clocks control the update rate of the DACs.

PRODUCT HIGHLIGHTS

1. The AD9709 is a member of a pin-compatible family of

dual TxDACs providing 8-, 10-, 12-, and 14-bit resolution.

2. Dual 8-Bit, 125 MSPS DACs. A pair of high performance

DACs optimized for low distortion performance provide

for flexible transmission of I and Q information.

A mode control pin allows the AD9709 to interface to two separate

data ports, or to a single interleaved high speed data port. In inter-

leaving mode, the input data stream is demuxed into its original

I and Q data and then latched. The I and Q data is then converted

by the two DACs and updated at half the input data rate.

3. Matching. Gain matching is typically 0.1% of full scale, and

offset error is better than 0.02%.

The GAINCTRL pin allows two modes for setting the full-scale

current (I_OUTFS) of the two DACs. I_OUTFSfor each DAC can be set

independently using two external resistors, or I_OUTFSfor both

DACs can be set by using a single external resistor. See the Gain

Control Mode section for important date code information on

this feature.

4. Low Power. Complete CMOS dual DAC function operates

at 380 mW from a 3.3 V or 5 V single supply. The DAC

full-scale current can be reduced for lower power operation,

and a sleep mode is provided for low power idle periods.

5. On-Chip Voltage Reference. The AD9709 includes a 1.20 V

temperature-compensated band gap voltage reference.

6. Dual 8-Bit Inputs. The AD9709 features a flexible dual-

port interface, allowing dual or interleaved input data.

The DACs utilize a segmented current source architecture

combined with a proprietary switching technique to reduce

¹Patent pending.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

AD9709

TABLE OF CONTENTS

Features .............................................................................................. 1

Analog Outputs .......................................................................... 14

Digital Inputs .............................................................................. 15

DAC Timing................................................................................ 15

Sleep Mode Operation............................................................... 18

Power Dissipation....................................................................... 18

Applying the AD9709 .................................................................... 19

Output Configurations.............................................................. 19

Differential Coupling Using a Transformer............................ 19

Differential Coupling Using an Op Amp................................ 19

Single-Ended, Unbuffered Voltage Output............................. 20

Single-Ended, Buffered Voltage Output Configuration........ 20

Power and Grounding Considerations.................................... 20

Applications Information.............................................................. 22

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

DC Specifications ......................................................................... 3

Dynamic Specifications ............................................................... 4

Digital Specifications ................................................................... 5

Absolute Maximum Ratings............................................................ 6

Thermal Resistance ...................................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Terminology .................................................................................... 11

Theory of Operation ...................................................................... 12

Functional Description.............................................................. 12

Reference Operation .................................................................. 13

Gain Control Mode.................................................................... 13

Setting the Full-Scale Current................................................... 13

DAC Transfer Function ............................................................. 14

Quadrature Amplitude Modulation (QAM) Using the

AD9709........................................................................................ 22

CDMA ......................................................................................... 23

Evaluation Board ............................................................................ 24

General Description................................................................... 24

Schematics................................................................................... 24

Evaluation Board Layout........................................................... 30

Outline Dimensions....................................................................... 32

Ordering Guide .......................................................................... 32

REVISION HISTORY

9/09—Rev. A to Rev. B

Replaced Reference Control Amplifier Section with Setting

the Full-Scale Current Section...................................................... 13

Changes to DAC Transfer Function Section............................... 14

Changes to Interleaved Mode Timing Section ........................... 16

Added Figure 28 ............................................................................. 16

Changes to Power and Grounding Considerations Section ..... 20

Changes to Figure 44...................................................................... 22

Deleted Figure 43............................................................................ 17

Changes to CDMA Section........................................................... 23

Changes to Figure 45 Caption ...................................................... 23

Changes to Figure 46...................................................................... 24

Changes to Figure 48...................................................................... 26

Updated Outline Dimensions....................................................... 30

Changes to Ordering Guide.......................................................... 30

Changes to Power and Grounding Considerations Section ..... 20

Changes to Schematics Section..................................................... 24

Changes to Evaluation Board Layout Section............................. 30

1/08—Rev. 0 to Rev. A

Updated Format..................................................................Universal

Changed Single Supply Operation to 5 V or 3.3 V ........Universal

Changes to Figure 1.......................................................................... 1

Added Timing Diagram Section .................................................... 5

Changes to Figure 3 and Table 6..................................................... 7

Change to Figure 12 ......................................................................... 9

Changes to Figure 18 to Figure 20................................................ 10

Changes to Functional Description Section ............................... 13

Changes to Reference Operation Section.................................... 13

Changes to Figure 23 and Figure 24............................................. 13

Changes to Gain Control Mode Section...................................... 13

5/00—Revision 0: Initial Version

Rev. B | Page 2 of 32

AD9709

SPECIFICATIONS

DC SPECIFICATIONS

T_MINto T_MAX, AVDD = 3.3 V or 5 V, DVDD1 = DVDD2 = 3.3 V or 5 V, I_OUTFS= 20 mA, unless otherwise noted.

Table 1.

Parameter

Min

Typ

Max

Unit

RESOLUTION

8

Bits

DC ACCURACY¹

Integral Linearity Error (INL)

Differential Nonlinearity (DNL)

ANALOG OUTPUT

−0.5

0.1

+0.5

LSB

Offset Error

−0.02

−2

−5

+0.02

+2

+5

% of FSR

Gain Error Without Internal Reference

Gain Error with Internal Reference

Gain Match

0.25

+1

T_A= 25°C

T_MINto T_MAX

Full-Scale Output Current²

Output Compliance Range

Output Resistance

−0.3

−1.6

−0.14

2.0

0.1

+0.3

+1.6

+0.14

20.0

+1.25

% of FSR

dB

mA

V

−1.0

100

5

kΩ

pF

Output Capacitance

REFERENCE OUTPUT

Reference Voltage

1.14

0.1

1.20

100

1.26

1.25

V

nA

Reference Output Current³

REFERENCE INPUT

Input Compliance Range

Reference Input Resistance

Small-Signal Bandwidth

TEMPERATURE COEFFICIENTS

Offset Drift

Gain Drift Without Internal Reference

Gain Drift with Internal Reference

Reference Voltage Drift

POWER SUPPLY

V

MΩ

MHz

1

0.5

0

ppm of FSR/°C

ppm/°C

50

100

50

Supply Voltages

AVDD

DVDD1, DVDD2

Analog Supply Current (I_AVDD

Digital Supply Current (I_DVDD

3

2.7

5

71

5

5.5

75

7

15

V

mA

)

4

)

5

Digital Supply Current (I_DVDD

)

mA

Supply Current Sleep Mode (I_AVDD

)

8

12

mA

Power Dissipation⁴(5 V, I_OUTFS= 20 mA)

Power Dissipation⁵(5 V, I_OUTFS= 20 mA)

Power Dissipation⁶(5 V, I_OUTFS= 20 mA)

Power Supply Rejection Ratio⁷—AVDD

Power Supply Rejection Ratio⁷—DVDD1, DVDD2

OPERATING RANGE

380

420

450

410

450

mW

% of FSR/V

°C

−0.4

−0.025

−40

+0.4

+0.025

+85

¹Measured at I_OUTA, driving a virtual ground.

²Nominal full-scale current, I_OUTFS, is 32 times the I_REFcurrent.

³An external buffer amplifier with input bias current <100 nA should be used to drive any external load.

⁴Measured at f_CLK= 25 MSPS and f_OUT= 1.0 MHz.

⁵Measured at f_CLK= 100 MSPS and f_OUT= 1 MHz.

⁶Measured as unbuffered voltage output with I_OUTFS= 20 mA and R_LOAD= 50 Ω at I_OUTAand I_OUTB, f_CLK= 100 MSPS, and f_OUT= 40 MHz.

7

10% power supply variation.

Rev. B | Page 3 of 32

AD9709

DYNAMIC SPECIFICATIONS

T_MINto T_MAX, AVDD = 3.3 V or 5 V, DVDD1 = DVDD2 = 3.3 V or 5 V, I_OUTFS= 20 mA, differential transformer-coupled output, 50 Ω

doubly terminated, unless otherwise noted.

Table 2.

Parameter

Min

Typ

Max

Unit

DYNAMIC PERFORMANCE

Maximum Output Update Rate (f_CLK

Output Settling Time (t_ST) to 0.1%¹

Output Propagation Delay (t_PD)

Glitch Impulse

Output Rise Time (10% to 90%)¹

Output Fall Time (90% to 10%)¹

Output Noise (I_OUTFS= 20 mA)

Output Noise (I_OUTFS= 2 mA)

AC LINEARITY

)

125

MSPS

ns

pV-s

ns

35

1

5

2.5

50

30

pA/√Hz

Spurious-Free Dynamic Range to Nyquist

f_CLK= 100 MSPS, f_OUT= 1.00 MHz

0 dBFS Output

63

68

62

56

50

68

66

60

50

63

55

dBc

–6 dBFS Output

–12 dBFS Output

–18 dBFS Output

f_CLK= 65 MSPS, f_OUT= 1.00 MHz

f_CLK= 65 MSPS, f_OUT= 2.51 MHz

f_CLK= 65 MSPS, f_OUT= 5.02 MHz

f_CLK= 65 MSPS, f_OUT= 14.02 MHz

f_CLK= 65 MSPS, f_OUT= 25 MHz

f_CLK= 125 MSPS, f_OUT= 25 MHz

f_CLK= 125 MSPS, f_OUT= 40 MHz

Signal to Noise and Distortion Ratio

f_CLK= 50 MHz, f_OUT= 1 MHz

Total Harmonic Distortion

f_CLK= 100 MSPS, f_OUT= 1.00 MHz

f_CLK= 50 MSPS, f_OUT= 2.00 MHz

f_CLK= 125 MSPS, f_OUT= 4.00 MHz

f_CLK= 125 MSPS, f_OUT= 10.00 MHz

Multitone Power Ratio (Eight Tones at 110 kHz Spacing)

f_CLK= 65 MSPS, f_OUT= 2.00 MHz to 2.99 MHz

0 dBFS Output

50

dB

−67

−63

dBc

58

51

46

41

dBc

–6 dBFS Output

–12 dBFS Output

–18 dBFS Output

Channel Isolation

f_CLK= 125 MSPS, f_OUT= 10 MHz

f_CLK= 125 MSPS, f_OUT= 40 MHz

85

77

dBc

¹Measured single-ended into 50 Ω load.

Rev. B | Page 4 of 32

AD9709

DIGITAL SPECIFICATIONS

T_MINto T_MAX, AVDD = 3.3 V or 5 V, DVDD1 = DVDD2 = 3.3 V or 5 V I_OUTFS= 20 mA, unless otherwise noted.

Table 3.

Parameter

Min

Typ

Max

Unit

DIGITAL INPUTS

Logic 1 Voltage @ DVDD1 = DVDD2 = 5 V

Logic 1 Voltage @ DVDD1 = DVDD2 = 3.3 V

Logic 0 Voltage @ DVDD1 = DVDD2 = 5 V

Logic 0 Voltage @ DVDD1 = DVDD2 = 3.3 V

Logic 1 Current

Logic 0 Current

Input Capacitance

Input Setup Time (t_S)

Input Hold Time (t_H)

3.5

2.1

5

3

0

V

μA

pF

ns

1.3

0.9

+10

0

−10

5

2.0

1.5

3.5

Latch Pulse Width (t_LPW, t_CPW

)

Timing Diagram

See Table 3 and the DAC Timing section for more information about the timing specifications.

t_S

t_H

DATA IN

(WRT2) (WRT1/IQWRT)

(CLK2) (CLK1/IQCLK)

t_LPW

t_CPW

I

OUTA

OR

OUTB

t_PD

Figure 2. Timing for Dual and Interleaved Modes

Rev. B | Page 5 of 32

AD9709

ABSOLUTE MAXIMUM RATINGS

Table 4.

THERMAL RESISTANCE

With

Parameter

AVDD

Respect To

Rating

θ_JAis specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

ACOM

−0.3 V to +6.5 V

DVDD1, DVDD2

ACOM

AVDD

DCOM1/DCOM2 −0.3 V to +6.5 V

DCOM1/DCOM2 −0.3 V to +0.3 V

Table 5. Thermal Resistance

Package Type

θ_JA

Unit

DVDD1/DVDD2

−6.5 V to +6.5 V

48-Lead LQFP

91

°C/W

MODE, CLK1/IQCLK,

CLK2/IQRESET,

WRT1/IQWRT,

DCOM1/DCOM2 −0.3 V to DVDD1/

DVDD2 + 0.3 V

ESD CAUTION

WRT2/IQSEL

Digital Inputs

DCOM1/DCOM2 −0.3 V to DVDD1/

DVDD2 + 0.3 V

I_OUTA1/I_OUTA2

I_OUTB1/I_OUTB2

REFIO, FSADJ1,

FSADJ2

GAINCTRL, SLEEP

,

ACOM

−1.0 V to AVDD + 0.3 V

−0.3 V to AVDD + 0.3 V

−0.3V to AVDD + 0.3 V

150°C

JunctionTemperature

Storage Temperature

Range

−65°C to +150°C

Lead Temperature

(10 sec)

300°C

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rev. B | Page 6 of 32

AD9709

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

48 47 46 45 44 43 42 41 40 39 38 37

1

2

36

35

34

33

32

31

30

29

DB7P1 (MSB)

DB6P1

DB5P1

DB4P1

DB3P1

DB2P1

DB1P1

DB0P1

NC

PIN 1

INDICATOR

NC

3

NC

4

NC

5

NC

AD9709

6

NC

TOP VIEW

7

(Not to Scale)

DB0P2 (LSB)

DB1P2

8

9

28 DB2P2

27 DB3P2

26 DB4P2

25 DB5P2

10

11

12

NC

13 14 15 16 17 18 19 20 21 22 23 24

NC = NO CONNECT

Figure 3. Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

DB7P1 to DB0P1

NC

Description

1 to 8

9 to 14, 31 to 36

Data Bit Pins (Port 1)

No Connection

15, 21

16, 22

17

18

19

20

23 to 30

37

DCOM1, DCOM2

DVDD1, DVDD2

WRT1/IQWRT

CLK1/IQCLK

CLK2/IQRESET

WRT2/IQSEL

DB7P2 to DB0P2

SLEEP

Digital Common

Digital Supply Voltage

Input Write Signal for Port 1 (IQWRT in Interleaving Mode)

Clock Input for DAC1 (IQCLK in Interleaving Mode)

Clock Input for DAC2 (IQRESET in Interleaving Mode)

Input Write Signal for Port 2 (IQSEL in Interleaving Mode)

Data Bit Pins (Port 2)

Power-Down Control Input

38

ACOM

Analog Common

39, 40

41

42

I_OUTA2, I_OUTB2

FSADJ2

GAINCTRL

REFIO

Port 2 Differential DAC Current Outputs

Full-Scale Current Output Adjust for DAC2

Master/Slave Resistor Control Mode.

Reference Input/Output

43

44

45, 46

47

FSADJ1

I_OUTB1, I_OUTA1

AVDD

Full-Scale Current Output Adjust for DAC1

Port 1 Differential DAC Current Outputs

Analog Supply Voltage

48

MODE

Mode Select (1 = dual port, 0 = interleaved)

Rev. B | Page 7 of 32

AD9709

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD = 3.3 V or 5 V, DVDD = 3.3 V, I_OUTFS= 20 mA, 50 Ω doubly terminated load, differential output, T_A= 25°C, SFDR up to Nyquist,

unless otherwise noted.

75

70

65

60

55

50

45

75

70

65

60

55

50

45

f_CLK= 25MSPS

0dBFS

f_CLK= 5MSPS

–6dBFS

f_CLK= 65MSPS

f_CLK= 125MSPS

–12dBFS

0

5

10

15

20

25

30

35

0.1

1

10

100

2.5

12

f_OUT(MHz)

Figure 4. SFDR vs. f_OUT@ 0 dBFS

Figure 7. SFDR vs. f_OUT@ 65 MSPS

75

70

65

60

55

50

45

75

70

65

60

55

50

45

0dBFS

–6dBFS

–12dBFS

0

10

20

30

40

50

60

70

0

0.5

1.0

1.5

2.0

f_OUT(MHz)

Figure 8. SFDR vs. f_OUT@ 125 MSPS

Figure 5. SFDR vs. f_OUT@ 5 MSPS

75

70

65

60

55

50

45

75

70

65

60

55

50

45

I

= 20mA

OUTFS

0dBFS

–6dBFS

–12dBFS

I

= 10mA

OUTFS

I

= 5mA

OUTFS

0

2

4

6

8

10

0

5

10

15

20

25

30

35

f_OUT(MHz)

Figure 6. SFDR vs. f_OUT@ 25 MSPS

Figure 9. SFDR vs. f_OUTand I_OUTFS@ 65 MSPS and 0 dBFS

Rev. B | Page 8 of 32

AD9709

75

70

65

60

55

50

45

40

70

65

60

55

50

45

40

5MSPS/0.46MHz

10MSPS/0.91MHz

I

= 20mA

OUTFS

25MSPS/2.27MHz

65MSPS/5.91MHz

I

= 5mA

OUTFS

40

125MSPS/11.37MHz

I

= 10mA

100

OUTFS

80

–25

–22

–19

–16

–13

–10

–7

–4

–1

2

0

20

60

120

140

A

(dBFS)

f_CLK(MSPS)

OUT

Figure 10. Single-Tone SFDR vs. A_OUT@ f_OUT= f_CLK/11

Figure 13. SINAD vs. f_CLKand I_OUTFS@ f_OUT= 5 MHz and 0 dBFS

75

70

65

60

55

50

45

40

0.06

0.04

5MSPS/1.0MHz

0.02

0

–0.02

–0.04

–0.06

–0.08

–0.10

125MSPS/5.0MHz

10MSPS/2.0MHz

65MSPS/13.0MHz

25MSPS/5.0MHz

–25

–20

–15

A

–10

(dBFS)

–5

0

32

64

96

128

160

192

224

256

CODE

OUT

Figure 11. Single-Tone SFDR vs. A_OUT@ f_OUT= f_CLK/5

Figure 14. Typical INL

75

70

65

60

55

50

45

40

0.07

0.06

0.05

0.04

0.03

0.02

0.01

0

0.965MHz/1.035MHz @ 7MSPS

16.9MHz/19.1MHz @ 125MSPS

8.8MHz/9.8MHz @ 65MSPS

3.3MHz/3.4MHz @ 25MSPS

–0.01

–25

–20

–15

A

–10

(dBFS)

–5

0

50

100

150

200

250

CODE

OUT

Figure 12. Dual-Tone SFDR vs. A_OUT@ f_OUT= f_CLK/7

Figure 15. Typical DNL

Rev. B | Page 9 of 32

AD9709

75

70

65

60

55

50

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

f_OUT= 10MHz

f_OUT= 25MHz

f_OUT= 40MHz

f_OUT= 60MHz

45

–50

–30

–10

10

30

50

70

90

0

10

20

30

40

50

60

TEMPERATURE (°C)

FREQUENCY (MHz)

Figure 16. SFDR vs. Temperature @ f_CLK= 125 MSPS, 0 dBFS

Figure 19. Dual-Tone SFDR @ f_CLK= 125 MSPS

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

0.05

0.03

0

1.0

0.5

0

GAIN ERROR

OFFSET ERROR

–0.03

–0.5

–1.0

–0.05

0

10

20

30

40

50

60

–40

–20

0

20

40

60

80

FREQUENCY (MHz)

TEMPERATURE (°C)

Figure 17. Gain and Offset Error vs. Temperature @ f_CLK= 125 MSPS

Figure 20. Four-Tone SFDR @ f_CLK= 125 MSPS

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

10

20

30

40

50

60

FREQUENCY (MHz)

Figure 18. Single-Tone SFDR @ f_CLK= 125 MSPS

Rev. B | Page 10 of 32

AD9709

TERMINOLOGY

Temperature Drift

Linearity Error (Integral Nonlinearity or INL)

Linearity error is defined as the maximum deviation of the

actual analog output from the ideal output, determined by a

straight line drawn from zero to full-scale.

Temperature drift is specified as the maximum change from the

ambient (25°C) value to the value at either T_MINor T_MAX. For offset

and gain drift, the drift is reported in part per million (ppm) of

full-scale range (FSR) per degree Celsius. For reference drift, the

drift is reported in ppm per degree Celsius (pm/°C).

Differential Nonlinearity (DNL)

DNL is the measure of the variation in analog value, normalized

to full scale, associated with a 1 LSB change in digital input code.

Power Supply Rejection (PSR)

PSR is the maximum change in the full-scale output as the

supplies are varied from nominal to minimum and maximum

specified voltages.

Monotonicity

A DAC is monotonic if the output either increases or remains

constant as the digital input increases.

Settling Time

Offset Error

Settling time is the time required for the output to reach and

remain within a specified error band about its final value,

measured from the start of the output transition.

Offset error is the deviation of the output current from the ideal of

zero. For I_OUTA, 0 mA output is expected when the inputs are all 0s.

For I_OUTB, 0 mA output is expected when all inputs are set to 1s.

Glitch Impulse

Gain Error

Asymmetrical switching times in a DAC give rise to undesired

output transients that are quantified by a glitch impulse. It is

specified as the net area of the glitch in picovolts per second (pV-s).

Gain error is the difference between the actual and ideal output

spans. The actual span is determined by the output when all

inputs are set to 1s minus the output when all inputs are set to 0s.

Spurious-Free Dynamic Range

Output Compliance Range

The difference, in decibels (dB), between the rms amplitude of

the output signal and the peak spurious signal over the specified

bandwidth.

The output compliance range is the range of allowable voltage at

the output of a current-output DAC. Operation beyond the

maximum compliance limits may cause either output stage

saturation or breakdown resulting in nonlinear performance.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first six harmonic

components to the rms value of the measured input signal. It is

expressed as a percentage or in decibels (dB).

Rev. B | Page 11 of 32

AD9709

THEORY OF OPERATION

5V

CLK1/IQCLK CLK2/IQRESET

SLEEP

AVDD

Mini-Circuits

T1-1T

TO HP3589A

OR EQUIVALENT

SPECTRUM/

NETWORK

CLK

AD9709

DIVIDER

FSADJ1

PMOS

CURRENT

SOURCE

ARRAY

I

OUTA1

OUTB1

50Ω

R

1

SET

2kΩ

SEGMENTED

SWITCHES FOR

DAC1

REFIO

ANALYZER

LSB

SWITCH

DAC1

LATCH

0.1µF

PMOS

CURRENT

SOURCE

ARRAY

I

OUTA2

OUTB2

FSADJ2

SEGMENTED

SWITCHES FOR

DAC2

LSB

SWITCH

R

2

DAC2

LATCH

SET

2kΩ

MODE

MULTIPLEXING LOGIC

CHANNEL 1 LATCH

CHANNEL 2 LATCH

1.2V REF

DVDD1/

DVDD2

DCOM1/

DCOM2 ACOM

5V

WRT1/

IQWRT

GAINCTRL

PORT 1

PORT 2

WRT2/

IQSEL

DVDD1/DVDD2

DCOM1/DCOM2

50Ω

DIGITAL

DATA

RETIMED CLOCK OUTPUT*

LECROY 9210

PULSE

GENERATOR

*AWG2021 CLOCK RETIMED SUCH THAT

DIGITAL DATA TRANSITIONS ON FALLING

EDGE OF 50% DUTY CYCLE CLOCK.

TEKTRONIX

AWG2021

WITH OPTION 4

Figure 21. Basic AC Characterization Test Setup for AD9709, Testing Port 1 in Dual Port Mode, Using Independent GAINCTRL Resistors on FSADJ1 and FSADJ2

5V

CLK1/IQCLK CLK2/IQRESET

AVDD

SLEEP

V

= V

A – V

V

B

OUT

DIFF

OUT

CLK

R

2kΩ

1

SET

DIVIDER

FSADJ1

REFIO

PMOS

CURRENT

SOURCE

ARRAY

V

1A

I

OUT

OUTA1

OUTB1

I

1

REF

0.1µF

SEGMENTED

SWITCHES FOR

DAC1

LSB

1B

R 1A

L

50Ω

OUT

SWITCH

DAC1

LATCH

R 1B

L

50Ω

PMOS

CURRENT

SOURCE

ARRAY

V

2A

OUT

R

2

I

SET

OUTA2

OUTB2

2kΩ

FSADJ2

SEGMENTED

SWITCHES FOR

DAC2

LSB

SWITCH

V

2B

R 2A

L

50Ω

OUT

I

2

DAC2

LATCH

REF

R 2B

L

50Ω

DVDD1/

DVDD2

5V

MULTIPLEXING LOGIC

CHANNEL 1 LATCH CHANNEL 2 LATCH

AD9709

1.2V REF

ACOM

DCOM1/

DCOM2

GAINCTRL

WRT1/

IQWRT

PORT 1

PORT 2

WRT2/ MODE

IQSEL

DIGITAL DATA INPUTS

Figure 22. Simplified Block Diagram

All of these current sources are switched to one of the two

output nodes (that is, I_OUTAor I_OUTB) via the PMOS differential

current switches. The switches are based on a new architecture

that drastically improves distortion performance. This new

switch architecture reduces various timing errors and provides

matching of complementary drive signals to the inputs of the

differential current switches.

FUNCTIONAL DESCRIPTION

Figure 22 shows a simplified block diagram of the AD9709. The

AD9709 consists of two DACs, each one with its own independent

digital control logic and full-scale output current control. Each

DAC contains a PMOS current source array capable of providing

up to 20 mA of full-scale current (I_OUTFS).

The array is divided into 31 equal currents that make up the five

most significant bits (MSBs). The next four bits, or middle bits,

consist of 15 equal current sources whose value is 1/16^thof an

MSB current source. The remaining LSB is a binary weighted

fraction of the middle bit current sources. Implementing the

middle and lower bits with current sources instead of an R-2R

ladder enhances the dynamic performance for multitone or low

amplitude signals and helps maintain the high output impedance

of each DAC (that is, >100 kΩ).

The analog and digital sections of the AD9709 have separate

power supply inputs (that is, AVDD and DVDD1/DVDD2) that

can operate independently over a 3.3 V to 5 V range. The digital

section, which is capable of operating up to a 125 MSPS clock

rate, consists of edge-triggered latches and segment decoding

logic circuitry. The analog section includes the PMOS current

sources, the associated differential switches, a 1.20 V band gap

voltage reference, and two reference control amplifiers.

Rev. B | Page 12 of 32

AD9709

The full-scale output current of each DAC is regulated by

separate reference control amplifiers and can be set from 2 mA

to 20 mA via an external network connected to the full-scale

adjust (FSADJ) pin. The external network in combination with

both the reference control amplifier and voltage reference

(V_REFIO) sets the reference current (I_REF), which is replicated to

the segmented current sources with the proper scaling factor.

GAIN CONTROL MODE

The AD9709 allows the gain of each channel to be set

independently by connecting one R_SETresistor to FSADJ1 and

another R_SETresistor to FSADJ2. To add flexibility and reduce

system cost, a single R_SETresistor can be used to set the gain of

both channels simultaneously.

When GAINCTRL is low (that is, connected to analog ground),

the independent channel gain control mode using two resistors

is enabled. In this mode, individual RSET resistors should be

connected to FSADJ1 and FSADJ2. When GAINCTRL is high

(that is, connected to AVDD), the master/slave channel gain

control mode using one network is enabled. In this mode, a

single network is connected to FSADJ1, and the FSADJ2 pin

must be left unconnected.

The full-scale current (I_OUTFS) is 32 × I_REF

.

REFERENCE OPERATION

The AD9709 contains an internal 1.20 V band gap reference.

This can easily be overridden by a low noise external reference

with no effect on performance. REFIO serves as either an input

or output depending on whether the internal or an external

reference is used. To use the internal reference, simply decouple

the REFIO pin to ACOM with a 0.1 μF capacitor. The internal

reference voltage will be present at REFIO. If the voltage at

REFIO is to be used elsewhere in the circuit, an external buffer

amplifier with an input bias current of less than 100 nA should

be used. An example of the use of the internal reference is

shown in Figure 23.

Note that only parts with a date code of 9930 or later have the

master/slave gain control function. For parts with a date code

before 9930, Pin 42 must be connected to AGND, and the part

operates in the two-resistor, independent gain control mode.

SETTING THE FULL-SCALE CURRENT

OPTIONAL

Both of the DACs in the AD9709 contain a control amplifier

that is used to regulate the full-scale output current (I_OUTFS). The

control amplifier is configured as a V-I converter, as shown in

Figure 23, so that its current output (I_REF) is determined by the ratio

EXTERNAL

REFERENCE

BUFFER

GAINCTRL

AVDD

AD9709

1.2V

REF

REFERENCE

SECTION

REFIO

CURRENT

SOURCE

ARRAY

of the V_REFIOand an external resistor, R_SET

.

ADDITIONAL

EXTERNAL

LOAD

0.1µF

FSADJ1/

FSADJ2

V_REFIO

R_SET

256Ω

I_REF

=

ACOM

I

REF

22nF

R

SET

The DAC full-scale current, I_OUTFS, is an output current 32 times

Figure 23. Internal Reference Configuration

larger than the reference current, I_REF

.

An external reference can be applied to REFIO as shown in

Figure 24. The external reference can provide either a fixed

reference voltage to enhance accuracy and drift performance or

a varying reference voltage for gain control. Note that the 0.1 μF

compensation capacitor is not required because the internal

reference is overridden and the relatively high input impedance

of REFIO minimizes any loading of the external reference.

I_OUTFS= 32× I_REF

The control amplifier allows a wide (10:1) adjustment span of

_OUTFSfrom 2 mA to 20 mA by setting I_REFbetween 62.5 ꢀA and

I

625 ꢀA. The wide adjustment range of I_OUTFSprovides several

benefits. The first relates directly to the power dissipation of

the AD9709, which is proportional to I_OUTFS(refer to the Power

Dissipation section). The second relates to the 20 dB adjustment,

which is useful for system gain control purposes.

GAINCTRL

AVDD

AD9709

AVDD

1.2V

REF

REFERENCE

SECTION

It should be noted that when the R_SETresistors are 2 kΩ or less,

the 22 nF capacitor and 256 Ω resistor shown in Figure 23 and

Figure 24 are not required and the reference current can be set

by the R_SETresistors alone. For R_SETvalues greater than 2 kΩ, the

22 nF capacitor and 256 Ω resistor networks are required to

ensure the stability of the reference control amplifier(s).

Regardless of the value of R_SET, however, if the R_SETresistor is

located more than ~10 cm away from the pin, use of the 22 nF

capacitor and 256 Ω resistor is recommended.

REFIO

EXTERNAL

CURRENT

SOURCE

ARRAY

REFERENCE

FSADJ1/

FSADJ2

256Ω

I

ACOM

REF

22nF

R

SET

Figure 24. External Reference Configuration

Rev. B | Page 13 of 32

AD9709

differential amplifier configuration. The ac performance of the

AD9709 is optimum and specified using a differential

transformer-coupled output in which the voltage swing at I_OUTA

and I_OUTBis limited to 0.5 V. If a single-ended unipolar output

is desirable, I_OUTAshould be selected.

DAC TRANSFER FUNCTION

Both DACs in the AD9709 provide complementary current out-

puts, I_OUTAand I_OUTB. I_OUTAprovides a near full-scale current

output, I_OUTFS, when all bits are high (that is, DAC CODE = 256)

while I_OUTB, the complementary output, provides no current.

The current output appearing at I_OUTAand I_OUTBis a function of

both the input code and I_OUTFSand can be expressed as

The distortion and noise performance of the AD9709 can be

enhanced when it is configured for differential operation. The

common-mode error sources of both I_OUTAand I_OUTBcan be

significantly reduced by the common-mode rejection of a

transformer or differential amplifier. These common-mode

error sources include even-order distortion products and noise.

The enhancement in distortion performance becomes more

significant as the frequency content of the reconstructed

waveform increases. This is due to the first-order cancellation of

various dynamic common-mode distortion mechanisms, digital

feedthrough, and noise.

I

_OUTA= (DAC CODE/256) × I_OUTFS

(1)

(2)

_OUTB= (255 − DAC CODE)/256 × I_OUTFS

where DAC CODE = 0 to 255 (that is, decimal representation).

I

_OUTFSis a function of the reference current (I_REF), which is

nominally set by a reference voltage (V_REFIO) and an external

resistor (R_SET). It can be expressed as

I

_OUTFS= 32 × I_REF

where

_REF= V_REFIO/R_SET

(3)

(4)

Performing a differential-to-single-ended conversion via a

transformer also provides the ability to deliver twice the

reconstructed signal power to the load (that is, assuming no

source termination). Because the output currents of I_OUTAand

I

The two current outputs typically drive a resistive load directly

or via a transformer. If dc coupling is required, I_OUTAand I_OUTB

should be connected directly to matching resistive loads, R_LOAD

that are tied to the analog common, ACOM. Note that R_LOAD

can represent the equivalent load resistance seen by I_OUTAor

I

_OUTBare complementary, they become additive when processed

,

differentially. A properly selected transformer allows the AD9709

to provide the required power and voltage levels to different loads.

The output impedance of I_OUTAand I_OUTBis determined by the

equivalent parallel combination of the PMOS switches

associated with the current sources and is typically 100 kΩ in

parallel with 5 pF. It is also slightly dependent on the output

voltage (that is, V_OUTAand V_OUTB) due to the nature of a PMOS

device. As a result, maintaining I_OUTAand/or I_OUTBat a virtual

ground via an I-V op amp configuration results in the optimum

dc linearity. Note that the INL/DNL specifications for the

AD9709 are measured with I_OUTAmaintained at a virtual ground

via an op amp.

I

_OUTB, as would be the case in a doubly terminated 50 Ω or 75 Ω

cable. The single-ended voltage output appearing at the I_OUTA

and I_OUTBnodes is

V

_OUTA= I_OUTA× R_LOAD

_OUTB= I_OUTB× R_LOAD

(5)

(6)

Note the full-scale value of V_OUTAand V_OUTBmust not exceed the

specified output compliance range to maintain the specified

distortion and linearity performance.

V

_DIFF= (I_OUTA− I_OUTB) × R_LOAD

(7)

I

_OUTAand I_OUTBalso have a negative and positive voltage

Equation 7 highlights some of the advantages of operating the

AD9709 differentially. First, the differential operation helps cancel

compliance range that must be adhered to in order to achieve

optimum performance. The negative output compliance range

of −1.0 V is set by the breakdown limits of the CMOS process.

Operation beyond this maximum limit may result in a

breakdown of the output stage and affect the reliability of the

AD9709.

common-mode error sources associated with I_OUTAand I_OUTB

,

such as noise, distortion, and dc offsets. Second, the differential

code-dependent current and subsequent voltage, V_DIFF, is twice

the value of the single-ended voltage output (that is, V_OUTAor

V_OUTB), thus providing twice the signal power to the load.

The positive output compliance range is slightly dependent on

the full-scale output current, I_OUTFS. When I_OUTFSis decreased

from 20 mA to 2 mA, the positive output compliance range

degrades slightly from its nominal 1.25 V to 1.00 V. The optimum

distortion performance for a single-ended or differential output

is achieved when the maximum full-scale signal at I_OUTAand I_OUTB

does not exceed 0.5 V. Applications requiring the AD9709 output

(that is, V_OUTAand/or V_OUTB) to extend its output compliance range

should size R_LOADaccordingly. Operation beyond this compliance

range adversely affects the linearity performance of the AD9709

and subsequently degrade its distortion performance.

Note that the gain drift temperature performance for a single-

ended (V_OUTAand V_OUTB) or differential output (V_DIFF) of the

AD9709 can be enhanced by selecting temperature tracking

resistors for R_LOADand R_SETdue to their ratiometric relationship.

ANALOG OUTPUTS

The complementary current outputs, I_OUTAand I_OUTB, in each

DAC can be configured for single-ended or differential

operation. I_OUTAand I_OUTBcan be converted into complementary

single-ended voltage outputs, V_OUTAand V_OUTB, via a load

resistor, R_LOAD, as described in Equation 5 through Equation 7.

The differential voltage, V_DIFF, existing between V_OUTAand V_OUTB

can be converted to a single-ended voltage via a transformer or

Rev. B | Page 14 of 32

AD9709

The rising edge of CLK should occur before or simultaneously

with the rising edge of WRT. If the rising edge of CLK occurs

after the rising edge of WRT, a minimum delay of 2 ns should

be maintained from rising edge of WRT to rising edge of CLK.

DIGITAL INPUTS

The digital inputs of the AD9709 consist of two independent

channels. For the dual port mode, each DAC has its own

dedicated 8-bit data port: WRT line and CLK line. In the

interleaved timing mode, the function of the digital control pins

changes as described in the Interleaved Mode Timing section.

The 8-bit parallel data inputs follow straight binary coding

where DB7P1 and DB7P2 are the most significant bits (MSBs)

and DB0P1 and DB0P2 are the least significant bits (LSBs).

Timing specifications for dual port mode are given in Figure 26

and Figure 27.

t_S

t_H

DATA IN

I

_OUTAproduces a full-scale output current when all data bits are

WRT1/WRT2

CLK1/CLK2

t_LPW

at Logic 1. I_OUTBproduces a complementary output with the

full-scale current split between the two outputs as a function of

the input code.

t_CPW

I

OUTA

OR

OUTB

The digital interface is implemented using an edge-triggered

master slave latch. The DAC outputs are updated following

either the rising edge or every other rising edge of the clock,

depending on whether dual or interleaved mode is used. The

DAC outputs are designed to support a clock rate as high as

125 MSPS. The clock can be operated at any duty cycle that

meets the specified latch pulse width. The setup and hold times

can also be varied within the clock cycle as long as the specified

minimum times are met, although the location of these transition

edges may affect digital feedthrough and distortion performance.

Best performance is typically achieved when the input data

transitions on the falling edge of a 50% duty cycle clock.

t_PD

Figure 26. Dual Port Mode Timing

DATA IN

D1

D2

D3

D4

D5

WRT1/WRT2

CLK1/CLK2

I

OUTA

D3

XX

D2

D4

OR

OUTB

D1

I

Figure 27. Dual Mode Timing

DAC TIMING

Interleaved Mode Timing

The AD9709 can operate in two timing modes, dual and

interleaved, which are described in the following sections. The

block diagram in Figure 25 represents the latch architecture in

the interleaved timing mode.

When the MODE pin is at Logic 0, the AD9709 operates in

interleaved mode (refer to Figure 25). In addition, WRT1

functions as IQWRT, CLK1 functions as IQCLK, WRT2

functions as IQSEL, and CLK2 functions as IQRESET.

PORT 1

INPUT

LATCH

DAC1

LATCH

INTERLEAVED

DATA IN, PORT 1

Data enters the device on the rising edge of IQWRT. The

logic level of IQSEL steers the data to either Channel Latch 1

(IQSEL = 1) or to Channel Latch 2 (IQSEL = 0). For proper

operation, IQSEL should only change state when IQWRT and

IQCLK are low.

DAC1

DEINTERLEAVED

DATA OUT

PORT 2

INPUT

LATCH

IQWRT

IQSEL

DAC2

LATCH

DAC2

IQCLK

IQRESET

÷2

When IQRESET is high, IQCLK is disabled. When IQRESET

goes low, the next rising edge on IQCLK updates both DAC

latches with the data present at their inputs. In the interleaved

mode, IQCLK is divided by 2 internally. Following this first

rising edge, the DAC latches are only updated on every other

rising edge of IQCLK. In this way, IQRESET can be used to

synchronize the routing of the data to the DACs.

Figure 25. Latch Structure in Interleaved Mode

Dual Port Mode Timing

When the MODE pin is at Logic 1, the AD9709 operates in dual

port mode (refer to Figure 21). The AD9709 functions as two

distinct DACs. Each DAC has its own completely independent

digital input and control lines.

Similar to the order of CLK and WRT in dual port mode,

IQCLK should occur before or simultaneously with IQWRT.

The AD9709 features a double-buffered data path. Data enters the

device through the channel input latches. This data is then trans-

ferred to the DAC latch in each signal path. After the data is loaded

into the DAC latch, the analog output settles to its new value.

For general consideration, the WRT lines control the channel

input latches, and the CLK lines control the DAC latches. Both

sets of latches are updated on the rising edge of their respective

control signals.

Rev. B | Page 15 of 32

AD9709

Timing specifications for interleaved mode are shown in Figure 28

and Figure 30.

INTERLEAVED

DATA

xx

D1

D2

D3

D4

D5

IQSEL

The digital inputs are CMOS compatible with logic thresholds,

V_THRESHOLD, set to approximately half the digital positive supply

(DVDDx) or

IQWRT

V

_THRESHOLD= DVDDx/2 ( 20%)

IQCLK

t_S

t_H

IQRESET

DATA IN

DAC OUTPUT

PORT 1

xx

D3

D4

D1

500 ps

xx

DAC OUTPUT

PORT 2

D2

IQSEL

Figure 30. Interleaved Mode Timing

The internal digital circuitry of the AD9709 is capable of operating

at a digital supply of 3.3 V or 5 V. As a result, the digital inputs

can also accommodate TTL levels when DVDD1/DVDD2 is set to

accommodate the maximum high level voltage (V_OH(MAX)) of the

TTL drivers. A DVDD1/DVDD2 of 3.3 V typically ensures proper

compatibility with most TTL logic families. Figure 31 shows the

equivalent digital input circuit for the data and clock inputs.

The sleep mode input is similar with the exception that it

contains an active pull-down circuit, thus ensuring that the

AD9709 remains enabled if this input is left disconnected.

DVDD1

t_H

*

IQWRT

t_LPW

IQCLK

500 ps

I

OUTA

OR

OUTB

t_PD

*APPLIES TO FALLING EDGE OF IQCLK/IQWRT AND IQSEL ONLY.

Figure 28. 5 V or 3.3 V Interleaved Mode Timing

At 5 V it is permissible to drive IQWRT and IQCLK together as

shown in Figure 29, but at 3.3 V the interleaved data transfer is

not reliable.

DIGITAL

INPUT

t_S

t_H

Figure 31. Equivalent Digital Input

DATA IN

Because the AD9709 is capable of being clocked up to 125 MSPS,

the quality of the clock and data input signals are important in

achieving the optimum performance. Operating the AD9709

with reduced logic swings and a corresponding digital supply

(DVDD1/DVDD2) results in the lowest data feedthrough and

on-chip digital noise. The drivers of the digital data interface

circuitry should be specified to meet the minimum setup and

hold times of the AD9709 as well as its required minimum and

maximum input logic level thresholds.

IQSEL

t_H*

IQWRT

t_LPW

IQCLK

t_PD

I

OUTA

OR

OUTB

*APPLIES TO FALLING EDGE OF IQCLK/IQWRT AND IQSEL ONLY.

Figure 29. 5 V Only Interleaved Mode Timing

Rev. B | Page 16 of 32

AD9709

Digital signal paths should be kept short, and run lengths should be

matched to avoid propagation delay mismatch. The insertion of

a low value (that is, 20 Ω to 100 Ω) resistor network between

the AD9709 digital inputs and driver outputs may be helpful in

reducing any overshooting and ringing at the digital inputs that

contribute to digital feedthrough. For longer board traces and

high data update rates, stripline techniques with proper

impedance and termination resistors should be considered to

maintain “clean” digital inputs.

Input Clock and Data Timing Relationship

SNR in a DAC is dependent on the relationship between the

position of the clock edges and the point in time at which the

input data changes. The AD9709 is rising-edge triggered and

therefore exhibits SNR sensitivity when the data transition is

close to this edge. In general, the goal when applying the AD9709 is

to make the data transition close to the falling clock edge. This

becomes more important as the sample rate increases. Figure 32

shows the relationship of SNR to clock/data placement.

60

The external clock driver circuitry provides the AD9709 with a

low-jitter clock input meeting the minimum and maximum logic

levels while providing fast edges. Fast clock edges help minimize

jitter manifesting itself as phase noise on a reconstructed waveform.

Therefore, the clock input should be driven by the fastest logic

family suitable for the application.

50

40

30

20

10

0

Note that the clock input can also be driven via a sine wave, which

is centered around the digital threshold (that is, DVDDx/2) and

meets the minimum and maximum logic threshold. This typically

results in a slight degradation in the phase noise, which becomes

more noticeable at higher sampling rates and output frequencies.

In addition, at higher sampling rates, the 20% tolerance of the

digital logic threshold should be considered because it affects

the effective clock duty cycle and, subsequently, cut into the

required data setup and hold times.

–4

–3

–2

–1

0

1

2

3

4

TIME OF DATA CHANGE RELATIVE TO

RISING CLOCK EDGE (ns)

Figure 32. SNR vs. Clock Placement @ f_OUT= 20 MHz and f_CLK= 125 MSPS

Rev. B | Page 17 of 32

AD9709

80

70

60

50

40

30

20

10

SLEEP MODE OPERATION

The AD9709 has a power-down function that turns off the

output current and reduces the supply current to less than

8.5 mA over the specified supply range of 3.3 V to 5 V and

temperature range. This mode can be activated by applying a

Logic Level 1 to the SLEEP pin. The SLEEP pin logic threshold

is equal to 0.5 × AVDD. This digital input also contains an active

pull-down circuit that ensures the AD9709 remains enabled if

this input is left disconnected. The AD9709 requires less than

50 ns to power down and approximately 5 μs to power back up.

POWER DISSIPATION

0

5

10

I

15

(mA)

20

25

0.5

The power dissipation, P_D, of the AD9709 is dependent on several

factors, including

OUTFS

Figure 33. I_AVDDvs. I_OUTFS

•

the power supply voltages (AVDD and DVDD1/DVDD2)

the full-scale current output (I_OUTFS

the update rate (f_CLK

the reconstructed digital input waveform

35

30

25

20

15

10

5

)

125MSPS

100MSPS

The power dissipation is directly proportional to the analog

supply current, I_AVDD, and the digital supply current, I_DVDD. I_AVDD

is directly proportional to I_OUTFS, as shown in Figure 33, and is

65MSPS

insensitive to f_CLK

Conversely, I_DVDDis dependent on the digital input waveform,

_CLK, and digital supply (DVDD1/DVDD2). Figure 34 and

.

25MSPS

5MSPS

f

Figure 35 show I_DVDDas a function of full-scale sine wave output

ratios (f_OUT/f_CLK) for various update rates with DVDD1 =

DVDD2 = 5 V and DVDD1 = DVDD2 = 3.3 V, respectively.

Note how I_DVDDis reduced by more than a factor of 2 when

DVDD1/DVDD2 is reduced from 5 V to 3.3 V.

0

0.1

0.2

0.3

0.4

RATIO (f_OUT

/f_CLK)

Figure 34. I_DVDDvs. Ratio @ DVDD1 = DVDD2 = 5 V

18

16

14

12

10

8

125MSPS

100MSPS

65MSPS

6

25MSPS

5MSPS

4

2

0

0.1

0.2

0.3

0.4

RATIO (f_OUT

/f_CLK)

Figure 35. I_DVDDvs. Ratio @ DVDD1 = DVDD2 = 3.3 V

Rev. B | Page 18 of 32

AD9709

APPLYING THE AD9709

R_DIFF, can be inserted in applications where the output of the

OUTPUT CONFIGURATIONS

transformer is connected to the load, R_LOAD, via a passive

reconstruction filter or cable. R_DIFFis determined by the

transformer’s impedance ratio and provides the proper source

termination that results in a low VSWR. Note that approximately

The following sections illustrate some typical output configura-

tions for the AD9709. Unless otherwise noted, it is assumed that

I

_OUTFSis set to a nominal 20 mA. For applications requiring the

optimum dynamic performance, a differential output

configuration is suggested. A differential output configuration

can consist of either an RF transformer or a differential op amp

configuration. The transformer configuration provides the

optimum high frequency performance and is recommended for

any application allowing for ac coupling. The differential op

amp configuration is suitable for applications requiring dc

coupling, bipolar output, signal gain, and/or level shifting,

within the bandwidth of the chosen op amp.

half the signal power will be dissipated across R_DIFF

.

DIFFERENTIAL COUPLING USING AN OP AMP

An op amp can also be used as shown in Figure 37 to perform a

differential-to-single-ended conversion. The AD9709 is configured

with two equal load resistors, R_LOAD, of 25 Ω each. The differential

voltage developed across I_OUTAand I_OUTBis converted to a single-

ended signal via the differential op amp configuration. An optional

capacitor can be installed across I_OUTAand I_OUTB, forming a real pole

in a low-pass filter. The addition of this capacitor also enhances the

op amp’s distortion performance by preventing the DAC’s high-

slewing output from overloading the op amp’s input.

A single-ended output is suitable for applications requiring a

unipolar voltage output. A positive unipolar output voltage results

if I_OUTAand/or I_OUTBis connected to an appropriately sized load

resistor, R_LOAD, referred to ACOM. This configuration may be

more suitable for a single-supply system requiring a dc-coupled,

ground-referred output voltage. Alternatively, an amplifier can be

configured as an I-V converter, thus converting I_OUTAor I_OUTBinto a

negative unipolar voltage. This configuration provides the best dc

linearity because I_OUTAor I_OUTBis maintained at a virtual ground.

500Ω

AD9709

225Ω

I

OUTA

AD8047

225Ω

I

OUTB

C

OPT

500Ω

25Ω

Note that I_OUTAprovides slightly better performance than I_OUTB

.

DIFFERENTIAL COUPLING USING A

TRANSFORMER

Figure 37. DC Differential Coupling Using an Op Amp

The common-mode rejection of this configuration is typically

determined by the resistor matching. In this circuit, the differential

op amp circuit using the AD8047 is configured to provide some

additional signal gain. The op amp must operate from a dual

supply because its output is approximately 1.0 V. A high speed

amplifier capable of preserving the differential performance of

the AD9709 while meeting other system level objectives (that is,

cost and power) should be selected. The op amp’s differential

gain, gain setting resistor values, and full-scale output swing

capabilities should be considered when optimizing this circuit.

An RF transformer can be used as shown in Figure 36 to perform

a differential-to-single-ended signal conversion. A differentially

coupled transformer output provides the optimum distortion

performance for output signals whose spectral content lies within

the pass band of the transformer. An RF transformer such as the

Mini-Circuits® T1-1T provides excellent rejection of common-

mode distortion (that is, even-order harmonics) and noise over

a wide frequency range. It also provides electrical isolation and

the ability to deliver twice the power to the load. Transformers

with different impedance ratios can also be used for impedance

matching purposes. Note that the transformer provides ac

coupling only.

The differential circuit shown in Figure 38 provides the

necessary level shifting required in a single-supply system. In

this case, AVDD, which is the positive analog supply for both

the AD9709 and the op amp, is used to level shift the differential

output of the AD9709 to midsupply (that is, AVDD/2). The

AD8041 is a suitable op amp for this application.

AD9709

Mini-Circuits

T1-1T

I

OUTA

R

LOAD

500Ω

I

OUTB

AD9709

OPTIONAL

DIFF

225Ω

R

I

OUTA

AD8041

Figure 36. Differential Output Using a Transformer

225Ω

I

OUTB

C

OPT

The center tap on the primary side of the transformer must be

connected to ACOM to provide the necessary dc current path

for both I_OUTAand I_OUTB. The complementary voltages appearing

at I_OUTAand I_OUTB(that is, V_OUTAand V_OUTB) swing symmetrically

around ACOM and should be maintained with the specified

output compliance range of the AD9709. A differential resistor,

1kΩ

AVDD

25Ω

500Ω

Figure 38. Single-Supply DC Differential Coupled Circuit

Rev. B | Page 19 of 32

AD9709

SINGLE-ENDED, UNBUFFERED VOLTAGE OUTPUT

POWER AND GROUNDING CONSIDERATIONS

Power Supply Rejection

Figure 39 shows the AD9709 configured to provide a unipolar

output range of approximately 0 V to 0.5 V for a doubly terminated

50 Ω cable, because the nominal full-scale current, I_OUTFS, of 20 mA

flows through the equivalent R_LOADof 25 Ω. In this case, R_LOAD

Many applications seek high speed and high performance under

less than ideal operating conditions. In these applications, the

implementation and construction of the printed circuit board is

as important as the circuit design. Proper RF techniques must

be used for device selection, placement, and routing as well as

power supply bypassing and grounding to ensure optimum

performance. Figure 52 and Figure 53 illustrate the recommended

circuit board layout, including ground, power, and signal

input/output.

represents the equivalent load resistance seen by I_OUTAor I_OUTB

.

The unused output (I_OUTAor I_OUTB) can be connected directly to

ACOM or via a matching R_LOAD. Different values of I_OUTFSand

R_LOADcan be selected as long as the positive compliance range is

adhered to. One additional consideration in this mode is the

INL (see the Analog Outputs section). For optimum INL

performance, the single-ended, buffered voltage output

configuration is suggested.

One factor that can measurably affect system performance is

the ability of the DAC output to reject dc variations or ac noise

superimposed on the analog or digital dc power distribution.

This is referred to as the power supply rejection ratio (PSRR).

For dc variations of the power supply, the resulting performance

of the DAC directly corresponds to a gain error associated with

the DAC’s full-scale current, I_OUTFS. AC noise on the dc supplies

is common in applications where the power distribution is

generated by a switching power supply. Typically, switching

power supply noise occurs over the spectrum from tens of

kilohertz to several megahertz. The PSRR vs. frequency of the

AD9709 AVDD supply over this frequency range is shown in

Figure 41.

AD9709

I

= 20mA

OUTFS

V

= 0V TO 0.5V

OUTA

I

OUTA

OUTB

50Ω

I

25Ω

Figure 39. 0 V to 0.5 V Unbuffered Voltage Output

SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT

CONFIGURATION

Figure 40 shows a buffered single-ended output configuration

in which the U1 op amp performs an I-V conversion on the

AD9709 output current. U1 maintains I_OUTA(or I_OUTB) at a

virtual ground, thus minimizing the nonlinear output

90

impedance effect on the INL performance of the DAC, as

discussed in the Analog Outputs section. Although this single-

ended configuration typically provides the best dc linearity

performance, its ac distortion performance at higher DAC

update rates may be limited by the slewing capabilities of U1.

U1 provides a negative unipolar output voltage, and its full-

scale output voltage is simply the product of R_FBand I_OUTFS. The

full-scale output should be set within U1’s voltage output swing

capabilities by scaling I_OUTFSand/or R_FB. An improvement in ac

distortion performance may result with a reduced I_OUTFSbecause

the signal current U1 has to sink will be subsequently reduced.

85

80

75

70

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

FREQUENCY (MHz)

C

OPT

Figure 41. AVDD Power Supply Rejection Ratio vs. Frequency

R

200Ω

FB

Note that the data in Figure 41 is given in terms of current out

vs. voltage in. Noise on the analog power supply has the effect

of modulating the internal current sources and therefore the

output current. The voltage noise on AVDD, therefore, is added

in a nonlinear manner to the desired I_OUT. PSRR is very code

dependent, thus producing mixing effects that can modulate

low frequency power supply noise to higher frequencies. Worst-

case PSRR for either one of the differential DAC outputs occurs

when the full-scale current is directed toward that output. As a

result, the PSRR measurement in Figure 41 represents a worst-

case condition in which the digital inputs remain static and the

full-scale output current of 20 mA is directed to the DAC

output being measured.

AD9709

I

= 10mA

OUTFS

I

OUTA

U1

V

= I

OUTFS

× R

FB

OUT

I

OUTB

200Ω

Figure 40. Unipolar Buffered Voltage Output

Rev. B | Page 20 of 32

AD9709

An example serves to illustrate the effect of supply noise on the

analog supply. Suppose a switching regulator with a switching

frequency of 250 kHz produces 10 mV of noise and, for simplicity’s

sake, all of this noise is concentrated at 250 kHz (that is, ignore

harmonics). To calculate how much of this undesired noise will

appear as current noise superimposed on the DAC full-scale

current, I_OUTFS, one must determine the PSRR in decibels using

(AVDD) to the analog common (ACOM) as close to the chip as

physically possible. Similarly, decouple DVDD1/DVDD2, the

digital supply (DVDD1/DVDD2) to the digital common

(DCOM1/DCOM2) as close to the chip as possible.

For applications that require a single 5 V or 3.3 V supply for

both the analog and digital supplies, a clean analog supply can

be generated using the circuit shown in Figure 42. The circuit

consists of a differential LC filter with separate power supply

and return lines. Lower noise can be attained by using low-ESR

type electrolytic and tantalum capacitors.

Figure 41 at 250 kHz. To calculate the PSRR for a given R_LOAD

such that the units of PSRR are converted from A/V to V/V,

,

adjust the curve in Figure 41 by the scaling factor 20 × log(R_LOAD).

For instance, if R_LOADis 50 Ω, the PSRR is reduced by 34 dB

(that is, the PSRR of the DAC at 250 kHz, which is 85 dB in

Figure 41, becomes 51 dB V_OUT/V_IN).

FERRITE

BEADS

ELECTROLYTIC

CERAMIC

AVDD

ACOM

TTL/CMOS

LOGIC

CIRCUITS

10µF

TO

100µF

0.1µF

22µF

Proper grounding and decoupling should be a primary

objective in any high speed, high resolution system. The

AD9709 features separate analog and digital supply and ground

pins to optimize the management of analog and digital ground

currents in a system. In general, decouple the analog supply

TANTALUM

5V

POWER SUPPLY

Figure 42. Differential LC Filter for Single 5 V and 3.3 V Applications

Rev. B | Page 21 of 32

AD9709

APPLICATIONS INFORMATION

QUADRATURE AMPLITUDE MODULATION (QAM)

USING THE AD9709

8

DAC

DSP

OR

0°

90°

CARRIER

TO

MIXER

QAM is one of the most widely used digital modulation

schemes in digital communications systems. This modulation

technique can be found in FDM as well as spread spectrum

(that is, CDMA) based systems. A QAM signal is a carrier

frequency that is modulated in both amplitude (that is, AM

modulation) and phase (that is, PM modulation). It can be

generated by independently modulating two carriers of identical

frequency but with a 90° phase difference. This results in an

in-phase (I) carrier component and a quadrature (Q) carrier

component at a 90° phase shift with respect to the I component.

The I and Q components are then summed to provide a QAM

signal at the specified carrier frequency.

Σ

FREQUENCY

ASIC

NYQUIST

FILTERS

QUADRATURE

MODULATOR

Figure 43. Typical Analog QAM Architecture

In this implementation, it is much more difficult to maintain

proper gain and phase matching between the I and Q channels.

The circuit implementation shown in Figure 44 helps improve

the matching between the I and Q channels, and it shows a path

for upconversion using the AD8346 quadrature modulator. The

AD9709 provides both I and Q DACs with a common reference

that will improve the gain matching and stability. R_CALcan be

used to compensate for any mismatch in gain between the two

channels. The mismatch may be attributed to the mismatch

between R_SET1and R_SET2, the effective load resistance of each

channel, and/or the voltage offset of the control amplifier in each

DAC. The differential voltage outputs of both DACs in the

AD9709 are fed into the respective differential inputs of the

AD8346 via matching networks.

A common and traditional implementation of a QAM

modulator is shown in Figure 43. The modulation is performed

in the analog domain in which two DACs are used to generate

the baseband I and Q components. Each component is then

typically applied to a Nyquist filter before being applied to a

quadrature mixer. The matching Nyquist filters shape and limit

each component’s spectral envelope while minimizing intersymbol

interference. The DAC is typically updated at the QAM symbol

rate, or at a multiple of the QAM symbol rate if an interpolating

filter precedes the DAC. The use of an interpolating filter typically

eases the implementation and complexity of the analog filter,

which can be a significant contributor to mismatches in gain

and phase between the two baseband channels. A quadrature

mixer modulates the I and Q components with the in-phase and

quadrature carrier frequencies and then sums the two outputs

to provide the QAM signal.

AVDD

ROHDE & SCHWARZ

FSEA30B

OR EQUIVALENT

0.1µF

DCOM1/ DVDD1/

DCOM2 DVDD2

ACOM AVDD

RA

RB

RA

SPECTRUM ANALYZER

RL

LA

RL

VPBF

I

A

B

BBIP

BBIN

OUT

TEKTRONIX

AWG2021

WITH

I DAC

LATCH

I

VOUT

CA

CB

DAC

RB

OPTION 4

+

OUT

LA

RL

CB

WRT1/IQWRT

AD9709

LOIP

LOIN

CLK1/IQCLK

RA

PHASE

SPLITTER

BBQP

BBQN

I

A

B

RB

OUT

Q DAC

LATCH

Q

DAC

CA

C

FILTER

RB

RL

OUT

LA

RL

WRT2/IQSEL

AD8346

VDIFF = 1.82V p-p

SLEEP

MODE FSADJ1

FSADJ2 REFIO

0.1µF

DIFFERENTIAL

RLC FILTER

ROHDE & SCHWARZ

SIGNAL GENERATOR

RL = 200Ω

RA = 2500Ω

RB = 500Ω

RP = 200Ω

CA = 280pF

CB = 45pF

LA = 10µH

256Ω

22nF

256Ω

22nF

2kΩ

20kΩ

AVDD

RA

I

= 11mA

AD976x

AD8346

OUTFS

RL

RB

NOTES

1. DAC FULL-SCALE OUTPUT CURRENT = I

2. RA, RB, AND RL ARE THIN FILM RESISTOR NETWORKS

WITH 0.1% MATCHING, 1% ACCURACY AVAILABLE

FROM OHMTEK ORNXXXXD SERIES OR EQUIVALENT.

AVDD = 5.0V

VCM = 1.2V

.

OUTFS

V

MOD

0 TO I

OUTFS

V

DAC

Figure 44. Baseband QAM Implementation Using an AD9709 and AD8346

Rev. B | Page 22 of 32

AD9709

I and Q digital data can be fed into the AD9709 in two ways. In

dual port mode, the digital I information drives one input port,

and the digital Q information drives the other input port. If no

interpolation filter precedes the DAC, the symbol rate is the rate

at which the system clock drives the CLK and WRT pins on the

AD9709. In interleaved mode, the digital input stream at Port 1

contains the I and the Q information in alternating digital words.

Using IQSEL and IQRESET, the AD9709 can be synchronized

to the I and Q data streams. The internal timing of the AD9709

routes the selected I and Q data to the correct DAC output. In

interleaved mode, if no interpolation filter precedes the AD9709,

the symbol rate is half that of the system clock driving the digital

data stream and the IQWRT and IQCLK pins on the AD9709.

Distortion in the transmit path can lead to power being transmitted

out of the defined band. The ratio of power transmitted in-band to

out-of-band is often referred to as adjacent channel power (ACP).

This is a regulatory issue due to the possibility of interference

with other signals being transmitted by air. Regulatory bodies

define a spectral mask outside of the transmit band, and the ACP

must fall under this mask. If distortion in the transmit path causes

the ACP to be above the spectral mask, filtering or different

component selection is needed to meet the mask requirements.

Figure 45 displays the results of using the application circuit shown

in Figure 44 to reconstruct a wideband CDMA (W-CDMA) test

vector using a bandwidth of 8 MHz that is centered at 2.4 GHz

and sampled at 65 MHz. The IF frequency at the DAC output is

15.625 MHz. The adjacent channel power ratio (ACPR) for the

given test vector is measured at greater than 54 dB.

–30

CDMA

Code division multiple access (CDMA) is an air transmit/receive

scheme where the signal in the transmit path is modulated with a

pseudorandom digital code (sometimes referred to as the spreading

code). The effect of this is to spread the transmitted signal across

a wide spectrum. Similar to a discrete multitone (DMT) wave-

form, a CDMA waveform containing multiple subscribers can

be characterized as having a high peak to average ratio (that is,

crest factor), thus demanding highly linear components in the

transmit signal path. The bandwidth of the spectrum is defined

by the CDMA standard being used, and in operation it is

implemented by using a spreading code with particular

characteristics.

–40

–50

–60

==

–70

–80

–90

–100

–110

c11

C0

cu1

–120

–130

cu1

C0

CENTER 2.4GHz

3MHz

SPAN 30MHz

FREQUENCY

Figure 45. CDMA Signal, 8 MHz Chip Rate Sampled at 65 MSPS,

Recreated at 2.4 GHz, Adjacent Channel Power > 54 dB

Rev. B | Page 23 of 32

AD9709

EVALUATION BOARD

This board allows the user flexibility to operate the AD9709 in

various configurations. Possible output configurations include

transformer coupled, resistor terminated, and single-ended and

differential outputs. The digital inputs can be used in dual port

or interleaved mode and are designed to be driven from various

word generators, with the on-board option to add a resistor

network for proper load termination. When operating the

AD9709, best performance is obtained when running the digital

supply (DVDD1/DVDD2) at 3.3 V and the analog supply

(AVDD) at 5 V.

GENERAL DESCRIPTION

The AD9709-EB is an evaluation board for the AD9709 8-bit

dual DAC. Careful attention to layout and circuit design,

combined with a prototyping area, allow the user to easily and

effectively evaluate the AD9709 in any application where high

resolution, high speed conversion is required.

SCHEMATICS

RED

L2

RED

L1

DVDDIN

1

DVDD

AVDDIN

3

4

AVDD

TB1

BEAD

C9

C10

DCASE

VAL

VOLT

VAL

VOLT

BLK

2

TB1

BLK

DGND

AGND

1

2

1

2

RCO M

22

22 ^R1

R2

22

R1

R2

R3

R4

R5

R6

R7

R8

R9

R1

R2

R3

R4

R5

R6

R7

R8

R9

R1

R2

R3

R4

R5

R6

R7

R8

R9

2

3

2

3

INP31

INP23

INP24

INP25

INP26

INP27

INP28

INP29

INP30

INP9

INP1

3

INP32

INP33

INP34

INP35

INP36

INP10

INP11

INP12

INP13

INP14

INP2

INP3

INP4

INP5

INP6

INP7

INP8

R3

4

R4

5

R5

6

R6

7

R7

8

R8

9

INCK2

INCK1

R9

10

RP15

RP10

RP9

RP16

Figure 46. Power Decoupling and Clocks on AD9709 Evaluation Board (1)

Rev. B | Page 24 of 32

AD9709

7 4 1 6 - 6 0 0 0

A

B

1

3

B

A

C

2

1

3

0 6 C 0 R 3

0 8 C 0 R 5

5

0 8 C 0 C

0 8 C 0 C 5

8 0 5 C R

Figure 47. Power Decoupling and Clocks on AD9709 Evaluation Board (2)

Rev. B | Page 25 of 32

AD9709

L6

DNP

R23

R21

51

C31

R22

DNP

O2N

O2P

RC0603

LC0805

DNP

C24

DNP

C23

JP19

51

CC0805

L5 DNP

DNP

RC0603

LC0805

MODULATED OUTPUT

AGND2;3,4,5

SMAEDGE

R27

0

C28

AVDD2

J1

RC0603

.1UF

C29

100PF

C20

10UF

10V

CC0603

BCASE

AVDD2

2

C27

100PF

2

TP6

RED

AVDD2

AGND2;17

2

R28

1K

AGND2

TP5

BLK

JP18

.1UF

C30

LOCAL OSC INPUT

2

CC0603

AGND2;3,4,5

SMAEDGE

R29

0

ETC1-1-13

3

4

5

J2

RC0603

S

P

2

C26

C25

100PF

1

T4

R20

50

2

JP21

JP22

2

L4

DNP

R26

51

C32

DNP

O1N

O1P

RC0603

LC0805

DNP

C22

DNP

C21

JP20

51

CC0805

L3 DNP

R25

R24

DNP

RC0603

LC0805

Figure 48. Modulator on AD9709 Evaluation Board

Rev. B | Page 26 of 32

AD9709

9

1 4 6 - 6 0 0 0

0 6 C 0 R 3

RIBBON RA

Figure 49. Digital Input Signaling (1)

Rev. B | Page 27 of 32

AD9709

5 0 1 6 - 6 0 0 0

0 6 C 0 R 3

3

0 6 C 0 R

3

RIBBON RA

Figure 50. Digital Input Signaling (2)

Rev. B | Page 28 of 32

AD9709

1

1 5 6 - 6 0 0 0

0 8 C 0 C 5

5

0 8 C 0 C

P U 0 7 C C R

U P C 7 0 R C

0 8 C 0 R 5

8 0 5 C R

Figure 51. Device Under Test/Analog Output Signal Conditioning

Rev. B | Page 29 of 32

AD9709

EVALUATION BOARD LAYOUT

Figure 52. Assembly, Top Side

Rev. B | Page 30 of 32

AD9709

Figure 53. Assembly, Bottom Side

Rev. B | Page 31 of 32

AD9709

OUTLINE DIMENSIONS

9.20

9.00 SQ

8.80

0.75

0.60

0.45

1.60

MAX

37

48

36

1

PIN 1

7.20

TOP VIEW

(PINS DOWN)

7.00 SQ

6.80

1.45

1.40

1.35

0.20

0.09

7°

3.5°

0°

25

12

0.15

0.05

13

24

SEATING

PLANE

0.08

0.27

0.22

0.17

VIEW A

0.50

BSC

LEAD PITCH

COPLANARITY

VIEW A

ROTATED 90° CCW

COMPLIANT TO JEDEC STANDARDS MS-026-BBC

Figure 54. 48-Lead Low Profile Quad Flat Package [LQFP]

(ST-48)

Dimensions shown in millimeters

ORDERING GUIDE

Model

AD9709ASTZ¹

AD9709ASTZRL¹

AD9709-EBZ¹

Temperature Range

–40°C to +85°C

Package Description

Package Option

ST-48

48-Lead Low Profile Quad Flat Package [LQFP]

Evaluation Board

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D00606-0-9/09(B)

Rev. B | Page 32 of 32


型号：	AD9709ASTZ1
厂家：	ADI
描述：	8-Bit, 125 MSPS, Dual TxDAC Digital-to-Analog Converter 8位， 125 MSPS ，双通道TxDAC数位类比转换器转换器
文件：	总32页 (文件大小：597K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD9709ASTZ1 [ADI]

相关型号：

AD9709ASTZRL

AD9709ASTZRL1

AD9709_09

AD9712

AD9712AJN

AD9712AJP

AD9712AKN

AD9712AKP

AD9712ASJ

AD9712ASQ

AD9712ATJ

AD9712ATQ