AD9571ACPZPEC [ADI]
Ethernet Clock Generator, 10 Clock Outputs;
| 型号： | AD9571ACPZPEC |
| 厂家： | 
ADI |
| 描述： | Ethernet Clock Generator, 10 Clock Outputs 驱动 逻辑集成电路 |
| 文件： | 总21页 (文件大小：301K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ethernet Clock Generator, 10 Clock Outputs
AD9571
FE ATURES
FUNCTIONAL BLOCK DIAGRAM
REFSEL
Fully integrated VCO/PLL core
0.17 ps rms jitter from 1.875 MHz to 20 MHz at 156.25 MHz
0.41 ps rms jitter from 12 kHz to 20 MHz at 125 MHz
Input crystal or clock frequency of 25 MHz
Preset divide ratios for 156.25 MHz, 33.33 MHz,100 MHz, and
125 MHz
CMOS
XTAL
OSC
6 × 25MHz
REFCLK
PFD/CP
Choice of LVPECL or LVDS output format
Integrated loop filter
3RD-ORDER
LPF
6 copies of reference clock output
Rates configured via strapping pins
Space saving 6 mm × 6 mm 40-lead LFCSP
0.48 W power dissipation (LVDS operation)
0.69 W power dissipation (LVPECL operation)
3.3 V operation
LVPECL OR
LVDS
VCO
1 × 156.25MHz
2 × 100MHz OR
125MHz
APPLICATIONS
CMOS
Ethernet line cards, switches, and routers
SCSI, SATA, and PCI-express
1 × 33.33MHz
FORCE_LOW
PCI support included
AD9571
Low jitter, low phase noise clock generation
FREQSEL
Figure 1.
GENERAL DESCRIPTION
feedback divider and output divider. By connecting an external
crystal or reference clock to the REFCLK pin, frequencies up to
156.25 MHz can be locked to the input reference.
The AD9571 provides a multioutput clock generator function
comprising a dedicated PLL core that is optimized for Ethernet
line card applications. The integer-N PLL design is based on the
Analog Devices, Inc., proven portfolio of high performance, low
jitter frequency synthesizers to maximize network performance.
Other applications with demanding phase noise and jitter
requirements also benefit from this part.
Each output divider and feedback divider ratio is prepro-
grammed for the required output rates. No external loop filter
components are required, thus conserving valuable design time
and board space.
The PLL section consists of a low noise phase frequency
detector (PFD), a precision charge pump (CP), a low phase
noise voltage controlled oscillator (VCO), and a preprogrammed
The AD9571 is available in a 40-lead 6 mm × 6 mm lead frame
chip scale package and can be operated from a single 3.3 V
supply. The operating temperature range is −40°C to +85°C.
OPTIONAL
CX-4 PHY
CPU
ISLAND
XAUI
6 × 25MHz
2 × 125MHz
48 + 2 SWITCH/MAC
AD9571
1 × 156.25MHz
1 × 33.33MHz
2 × OCTAL 2 × OCTAL 2 × OCTAL 2 × OCTAL
GbE PHY GbE PHY GbE PHY GbE PHY
Figure 2. Typical Application
Rev. 0
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AD9571* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
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EVALUATION KITS
• AD9571 Evaluation Board
DOCUMENTATION
Data Sheet
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• AD9571: Ethernet Clock Generator, 10 Clock Outputs
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• AD9571/AD9572 IBIS Model
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AD9571
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................9
Pin Configuration and Function Descriptions............................10
Typical Performance Characteristics ............................................12
Terminology .....................................................................................13
Theory of Operation .......................................................................14
Outputs.........................................................................................14
Phase Frequency Detector (PFD) and Charge Pump.............15
Power Supply................................................................................15
CMOS Clock Distribution .........................................................15
LVPECL Clock Distribution ......................................................16
LVDS Clock Distribution ...........................................................16
Reference Input............................................................................16
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
PLL Characteristics ...................................................................... 3
LVDS Clock Output Jitter............................................................ 4
LVPECL Clock Output Jitter....................................................... 5
CMOS Clock Output Jitter.......................................................... 5
Reference Input............................................................................. 5
Clock Outputs............................................................................... 6
Timing Characteristics................................................................. 6
Control Pins .................................................................................. 7
Power.............................................................................................. 7
Crystal Oscillator.......................................................................... 7
Timing Diagrams.......................................................................... 8
Absolute Maximum Ratings............................................................ 9
Thermal Resistance ...................................................................... 9
Power and Grounding Considerations and Power Supply
Rejection.......................................................................................16
Outline Dimensions ........................................................................17
Ordering Guide............................................................................17
REVISION HISTORY
8/09—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
AD9571
SPECIFICATIONS
PLL CHARACTERISTICS
Typical (typ) is given for VS = 3.3 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
PHASE NOISE CHARACTERISTICS
PLL Noise (156.25 MHz LVDS Output)
@ 1 kHz
@ 10 kHz
@ 100 kHz
@ 1 MHz
@ 10 MHz
@ 30 MHz
−120
−126
−126
−145
−151
−152
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
PLL Noise (125 MHz LVDS Output)
@ 1 kHz
@ 10 kHz
@ 100 kHz
@ 1 MHz
@ 10 MHz
@ 30 MHz
−122
−128
−128
−147
−152
−152
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
PLL Noise (100 MHz LVDS Output)
@ 1 kHz
@ 10 kHz
@ 100 kHz
@ 1 MHz
@ 10 MHz
@ 30 MHz
−122
−129
−129
−147
−150
−150
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
PLL Noise (156.25 MHz LVPECL Output)
@ 1 kHz
−120
−125
−125
−145
−151
−152
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
@ 10 kHz
@ 100 kHz
@ 1 MHz
@ 10 MHz
@ 30 MHz
Rev. 0 | Page 3 of 20
AD9571
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
PLL Noise (125 MHz LVPECL Output)
@ 1 kHz
@ 10 kHz
@ 100 kHz
@ 1 MHz
@ 10 MHz
@ 30 MHz
−121
−127
−128
−148
−152
−153
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
PLL Noise (100 MHz LVPECL Output)
@ 1 kHz
@ 10 kHz
@ 100 kHz
@ 1 MHz
@ 10 MHz
@ 30 MHz
−115
−121
−128
−148
−150
−150
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
33.33 MHz output disabled
Phase Noise (33.33 MHz CMOS Output)
@ 1 kHz
@ 10 kHz
@ 100 kHz
@ 1 MHz
−131
−138
−139
−151
−152
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
@ 5 MHz
Phase Noise (25 MHz CMOS Output)
@ 1 kHz
@ 10 kHz
@ 100 kHz
@ 1 MHz
−133
−143
−147
−148
−148
−70
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc
@ 5 MHz
Spurious Content1
PLL Figures of Merit
Dominant amplitude with all outputs active
−217.5
dBc/Hz
1 When the 33.33 MHz, 100 MHz, and 125 MHz clocks are enabled simultaneously, a worst-case −50 dBc spurious content may be presented on Pin 21 and Pin 22 only.
LVDS CLOCK OUTPUT JITTER
Typical (typ) is given for VS = 3.3 V, TA = 25°C, unless otherwise noted.
Table 2.
Jitter Integration
Bandwidth (Typ)
125 MHz1,
33.33 MHz = Off/On
100 MHz
156.25 MHz
Unit
Test Conditions/Comments
12 kHz to 20 MHz
1.875 MHz to 20 MHz
200 kHz to 10 MHz
0.50
0.41/0.77
0.41
ps rms
LVDS output frequency combinations
are 1 × 156.25 MHz, 1 × 100 MHz, 1 ×
125 MHz, 1 × 33.33 MHz
LVDS output frequency combinations
are 1 × 156.25 MHz, 1 × 100 MHz, 1 ×
125 MHz, 1 × 33.33 MHz
0.17
ps rms
ps rms
0.30
0.24/0.66
LVDS output frequency combinations
are 1 × 156.25 MHz, 1 × 100 MHz, 1 ×
125 MHz, 1 × 33.33 MHz
1 The typical 125 MHz rms jitter data collected from the differential pair of Pin 21 and Pin 22, unless otherwise noted.
Rev. 0 | Page 4 of 20
AD9571
LVPECL CLOCK OUTPUT JITTER
Typical (typ) is given for VS = 3.3 V, TA = 25°C, unless otherwise noted.
Table 3.
Jitter Integration
Bandwidth (Typ)
125 MHz1,
33.33 MHz = Off/On
100 MHz
156.25 MHz
Unit
Test Conditions/Comments
12 kHz to 20 MHz
1.875 MHz to 20 MHz
200 kHz to 10 MHz
0.54
0.42/2.0
0.25/1.9
0.45
ps rms
LVPECL output frequency combinations are
1 × 156.25 MHz, 1 × 100 MHz, 1 × 125 MHz,
1 × 33.33 MHz
LVPECL output frequency combinations are
1 × 156.25 MHz, 1 × 100 MHz, 1 × 125 MHz,
1 × 33.33 MHz
0.22
ps rms
ps rms
0.31
LVPECL output frequency combinations are
1 × 156.25 MHz, 1 × 100 MHz, 1 × 125 MHz,
1 × 33.33 MHz
1 The typical 125 MHz rms jitter data collected from the differential pair of Pin 21 and Pin 22, unless otherwise noted.
CMOS CLOCK OUTPUT JITTER
Typical (typ) is given for VS = 3.3 V, TA = 25°C, unless otherwise noted.
Table 4.
Jitter Integration Bandwidth
12 kHz to 5 MHz
200 kHz to 5 MHz
25 MHz
0.82
0.80
33.33 MHz
0.53
0.43
Unit
ps rms
ps rms
Test Conditions/Comments
N/A
N/A
REFERENCE INPUT
Typical (typ) is given for VS = 3.3 V 10%, TA = 25°C, unless otherwise noted. Minimum (min) and maximum (max) values are given
over full VS and TA (−40°C to +85°C) variation.
Table 5.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
CLOCK INPUT (REFCLK)
Input Frequency
Input High Voltage
Input Low Voltage
Input Current
25
MHz
V
V
µA
pF
2.0
0.8
+1.0
−1.0
Input Capacitance
2
Rev. 0 | Page 5 of 20
AD9571
CLOCK OUTPUTS
Typical (typ) is given for VS = 3.3 V 10%, TA = 25°C, unless otherwise noted. Minimum (min) and maximum (max) values are given
over full VS and TA (−40°C to +85°C) variation.
Table 6.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LVPECL CLOCK OUTPUTS
Output Frequency
Output High Voltage (VOH)
Output Low Voltage (VOL)
Output Differential Voltage (VOD)
Duty Cycle
156.25
VS − 0.83
VS − 1.62
950
MHz
V
V
mV
%
VS − 1.24
VS − 2.07
700
VS − 1.05
VS − 1.87
825
45
55
LVDS CLOCK OUTPUTS
Output Frequency
Differential Output Voltage (VOD)
Delta VOD
Output Offset Voltage (VOS)
Delta VOS
Short-Circuit Current (ISA, ISB)
Duty Cycle
156.25
475
25
1.375
25
MHz
mV
mV
V
mV
mA
%
250
350
1.25
14
1.125
24
55
Output shorted to GND
45
CMOS CLOCK OUTPUTS
Output Frequency
Output High Voltage (VOH)
Output Low Voltage (VOL)
Duty Cycle
33.33
MHz
V
V
VS − 0.1
42
Sourcing 1.0 mA current
Sinking 1.0 mA current
0.1
58
%
TIMING CHARACTERISTICS
Typical (typ) is given for VS = 3.3 V 10%, TA = 25°C, unless otherwise noted. Minimum (min) and maximum (max) values are given
over full VS and TA (−40°C to +85°C) variation.
Table 7.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LVPECL
Termination = 200 Ω to 0 V; CLOAD = 0 pF
20% to 80%, measured differentially
80% to 20%, measured differentially
Termination = 100 Ω differential; CLOAD = 0 pF
20% to 80%, measured differentially
80% to 20%, measured differentially
Termination = 50 Ω to 0 V; CLOAD = 5 pF
20% to 80%
Output Rise Time, tRP
Output Fall Time, tFP
LVDS
Output Rise Time, tRL
Output Fall Time, tFL
CMOS
480
480
625
625
810
810
ps
ps
160
160
350
350
540
540
ps
ps
Output Rise Time, tRC
Output Fall Time, tFC
0.25
0.25
0.50
0.70
2.5
2.5
ns
ns
80% to 20%
Rev. 0 | Page 6 of 20
AD9571
CONTROL PINS
Typical (typ) is given for VS = 3.3 V 10%, TA = 25°C, unless otherwise noted. Minimum (min) and maximum (max) values are given
over full VS and TA (−40°C to +85°C) variation.
Table 8.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
INPUT CHARACTERISTICS
REFSEL Pin
REFSEL has a 30 kΩ pull-up resistor.
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
FREQSEL Pin
2.0
V
V
µA
µA
0.8
1.0
155
FREQSEL has a 150 kΩ pull-up resistor and a
100 kΩ pull-down resistor.
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
FORCE_LOW Pin
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
2/3(VS) + 0.2
V
V
µA
µA
1/3(VS)-0.2
45
30
FORCE_LOW has a 16 kΩ pull-down resistor.
2.0
V
V
µA
µA
0.8
240
2.0
POWER
Typical (typ) is given for VS = 3.3 V 10%, TA = 25°C, unless otherwise noted. Minimum (min) and maximum (max) values are given
over full VS and TA (−40°C to +85°C) variation.
Table 9.
Parameter
Min
Typ
3.3
Max
3.6
Unit
V
Test Conditions/Comments
Power Supply
3.0
LVDS Power Dissipation
LVPECL Power Dissipation
480
690
600
860
mW
mW
CRYSTAL OSCILLATOR
Typical (typ) is given for VS = 3.3 V 10%, TA = 25°C, unless otherwise noted. Minimum (min) and maximum (max) values are given
over full VS and TA (−40°C to +85°C) variation.
Table 10.
Parameter
CRYSTAL SPECIFICATION
Frequency
Min
Typ
Max
50
Unit
Test Conditions/Comments
Fundamental mode
25
MHz
Ω
ESR
Load Capacitance
Phase Noise
Stability
14
−135
pF
dBc/Hz
ppm
@1 kHz offset
−30
+30
Rev. 0 | Page 7 of 20
AD9571
TIMING DIAGRAMS
SINGLE-ENDED
80%
DIFFERENTIAL
80%
CMOS
5pF LOAD
LVPECL
20%
20%
tRC
tFC
tRP
tFP
Figure 5. CMOS Timing, Single-Ended, 5 pF Load
Figure 3. LVPECL Timing, Differential
DIFFERENTIAL
80%
LVDS
20%
tRL
tFL
Figure 4. LVDS Timing, Differential
Rev. 0 | Page 8 of 20
AD9571
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 11.
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Thermal impedance measurements were taken on a 4-layer
board in still air in accordance with EIA/JESD51-7.
Parameter
Rating
VS to GND
−0.3 V to +3.6 V
−0.3 V to VS + 0.3 V
−0.3 V to VS + 0.3 V
−0.3 V to VS + 0.3 V
−0.3 V to VS + 0.3 V
REFCLK to GND
BYPASSx to GND
XO to GND
Table 12. Thermal Resistance
FORCE_LOW, FREQSEL, and
REFSEL to GND
Package Type
θJA
Unit
40-Lead LFCSP
27.5
°C/W
−0.3 V to VS + 0.3 V
25M, 33M, 100M/125M, and 156M
to GND
Junction Temperature1
Storage Temperature Range
1 See Table 12 for θJA.
ESD CAUTION
150°C
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 9 of 20
AD9571
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
GND
VS
25M
25M
VS
1
2
3
4
5
6
7
8
9
30 25M
29 25M
28 VS
27 FREQSEL
26 VS
25 VS
24 VS
23 33M
22 100M/125M
21 100M/125M
INDICATOR
AD9571
TOP VIEW
XO
XO
REFCLK
REFSEL
(Not to Scale)
LVPECL/
LVDS
GND 10
NOTES
1. * = SHORT TO PIN 36.
2. ** = SHORT TO PIN 14.
3. NOTE THAT THE EXPOSED PADDLE ON THIS PACKAGE IS AN ELECTRICAL
CONNECTION AS WELL AS A THERMAL ENHANCEMENT. FOR THE DEVICE TO
FUNCTION PROPERLY, THE PADDLE MUST BE ATTACHED TO GROUND (GND).
Figure 6. Pin Configuration
Table 13. Pin Function Descriptions1
Pin No.
Mnemonic
Description
2
VS
25M
Power Supply Connection for the 25M CMOS Buffer.
CMOS 25 MHz Output.
3, 4, 29, 30, 31, 32
5
6, 7
8
9
11
VS
XO
REFCLK
REFSEL
Power Supply Connection for the Crystal Oscillator.
External 25 MHz Crystal.
25 MHz Reference Clock Input. Tie low when not in use.
Logic Input. Used to select the reference source.
Power Supply Connection for the GbE PLL.
VS
1, 10, 34
14, 36
15
16
17
GND
BYPASS2, BYPASS1
VS
VS
156M
156M
100M/125M
Ground Pins. The external paddle must be attached to GND.
These pins are for bypassing each LDO to ground with a 220 nF capacitor.
Power Supply Connection for the GbE VCO.
Power Supply Connection for the 156M LVDS Output Buffer and Output Dividers.
LVPECL/LVDS Output at 156.25 MHz.
18
Complementary LVPECL/LVDS Output at 156.25 MHz.
19, 21
20, 22
23
24
25
26
27
28
LVPECL/LVDS Output at 100 MHz or 125 MHz. Selected by FREQSEL pin strapping.
Complementary LVPECL/LVDS Output at 100 MHz or 125 MHz.
CMOS 33.33 MHz Output.
Power Supply Connection for the 33M CMOS Output Buffer and Output Dividers.
Power Supply Connection for the 100M/125M LVDS Output Buffer and Output Dividers.
Power Supply Connection for the GbE PLL Feedback Divider.
Logic Input. Used to configure output drivers.
/
100M 125M
33M
VS
VS
VS
FREQSEL
VS
Power Supply Connection for the FC PLL Feedback Divider.
Rev. 0 | Page 10 of 20
AD9571
Pin No.
33
35
Mnemonic
VS
VS
Description
Power Supply Connection for the 106.25 MHz LVDS Output Buffer and Output Dividers.
Power Supply Connection for the FC VCO.
37
FORCE_LOW
Forces the 33.33 MHz output into a low state.
39
40
VS
VS
Power Supply Connection for the FC PLL.
Power Supply Connection for Miscellaneous Logic.
1 The exposed paddle on this package is an electrical connection as well as a thermal enhancement. For the device to function properly, the paddle must be attached to
ground (GND).
Rev. 0 | Page 11 of 20
AD9571
TYPICAL PERFORMANCE CHARACTERISTICS
Both 100 MHz and 125 MHz outputs enabled; 33.33 MHz output disabled.
–100
–100
–110
–120
–130
–140
–150
–160
–110
–120
–130
–140
–150
–160
1k
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 7. 125 MHz Phase Noise
Figure 9. 156.25 MHz Phase Noise
–100
–110
–120
–130
–140
–150
–160
–100
–110
–120
–130
–140
–150
–160
1k
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 8. 25 MHz Phase Noise
Figure 10. 100 MHz Phase Noise
Rev. 0 | Page 12 of 20
AD9571
TERMINOLOGY
Phase Jitter
Time Jitter
An ideal sine wave can be thought of as having a continuous
and even progression of phase with time from 0 degrees to 360
degrees for each cycle. Actual signals, however, display a certain
amount of variation from ideal phase progression over time.
This phenomenon is called phase jitter. Although many causes
can contribute to phase jitter, one major cause is random noise,
which is characterized statistically as gaussian (normal) in
distribution.
Phase noise is a frequency domain phenomenon. In the time
domain, the same effect is exhibited as time jitter. When
observing a sine wave, the time of successive zero crossings is
seen to vary. In a square wave, the time jitter is seen as a
displacement of the edges from their ideal (regular) times of
occurrence. In both cases, the variations in timing from the
ideal are the time jitter. Because these variations are random in
nature, the time jitter is specified in units of seconds root mean
square (rms) or 1 sigma of the gaussian distribution.
This phase jitter leads to a spreading out of the energy of the
sine wave in the frequency domain, producing a continuous
power spectrum. This power spectrum is usually reported as a
series of values whose units are dBc/Hz at a given offset in
frequency from the sine wave (carrier). The value is a ratio
(expressed in dB) of the power contained within a 1 Hz
bandwidth with respect to the power at the carrier frequency.
For each measurement, the offset from the carrier frequency is
also given.
Additive Phase Noise
Additive phase noise is the amount of phase noise that is
attributable to the device or subsystem being measured. The
phase noise of any external oscillators or clock sources has been
subtracted. This makes it possible to predict the degree to which
the device impacts the total system phase noise when used in
conjunction with the various oscillators and clock sources, each
of which contributes its own phase noise to the total. In many
cases, the phase noise of one element dominates the system
phase noise.
Phase Noise
When the total power contained within some interval of offset
frequencies (for example, 12 kHz to 20 MHz) is integrated, it is
called the integrated phase noise over that frequency offset
interval, and it can be readily related to the time jitter due to the
phase noise within that offset frequency interval.
Additive Time Jitter
Additive time jitter is the amount of time jitter that is attributable
to the device or subsystem being measured. The time jitter of
any external oscillators or clock sources has been subtracted.
This makes it possible to predict the degree to which the device
impacts the total system time jitter when used in conjunction
with the various oscillators and clock sources, each of which
contributes its own time jitter to the total. In many cases, the
time jitter of the external oscillators and clock sources dominates
the system time jitter.
Phase noise has a detrimental effect on error rate performance
by increasing eye closure at the transmitter output and reducing
the jitter tolerance/sensitivity of the receiver.
Rev. 0 | Page 13 of 20
AD9571
THEORY OF OPERATION
REFSEL VS
GND
25MHz
CMOS
25M
25M
25M
25M
25M
25M
XTAL
OSC
1
0
CMOS
CMOS
REFCLK
PHASE
FREQUENCY
DETECTOR
DIVIDE
BY 25
VCO
156.25MHz
156M
156M
CHARGE
PUMP
DIVIDE
BY 4
DIVIDE
BY 4
LVPECL/
LVDS
V
LDO
125MHz/
100MHz
0
1
DIVIDE
BY 5
DIVIDE
BY 4
100M/125M
100M/125M
LVPECL/
LVDS
LEVEL
DECODE
FREQSEL
125MHz/
100MHz
0
1
100M/125M
100M/125M
DIVIDE
BY 5
LVPECL/
LVDS
AD9571
33.33MHz
CMOS
DIVIDE
BY 3
33M
FORCE_LOW
Figure 11. Detailed Block Diagram
Figure 11 shows a block diagram of the AD9571. The chip
consists of a PLL core, which is configured to generate the
specific clock frequencies required for Ethernet applications,
without any user programming. This PLL is based on proven
Analog Devices synthesizer technology, noted for its exceptional
phase noise performance. The AD9571 is highly integrated and
includes loop filters, regulators for supply noise immunity, all
the necessary dividers with multiple output buffers in a choice
of formats, and a crystal oscillator. A user need only supply a
25 MHz reference clock or an external crystal to implement an
entire line card clocking solution that does not require any
processor intervention. Six copies of the 25 MHz reference
source are also available.
OUTPUTS
Table 14 provides a summary of the outputs available.
Table 14. Output Formats
Frequency
Format
Copies
25 MHz
CMOS
6
1
2
1
156.25 MHz
100 MHz or 125 MHz
33.33 MHz
LVPECL/LVDS
LVPECL/LVDS
CMOS
Note that the pins labeled 100M/125M can provide 100 MHz or
125 MHz by strapping the FREQSEL pin as shown in Table 15.
Rev. 0 | Page 14 of 20
AD9571
Table 15. FREQSEL Definition
PHASE FREQUENCY DETECTOR (PFD) AND
Frequency Available
from Pin 19 and Pin 20
FREQSEL (MHZ)
Frequency Available
from Pin 21 and Pin 22
(MHZ)
125
100
100
CHARGE PUMP
The PFD takes inputs from the reference clock and feedback
divider to produce an output proportional to the phase and
frequency difference between them. Figure 14 shows a
simplified schematic.
0
125
100
125
1
NC
3.3V
CHARGE
PUMP
3.5mA
UP
HIGH
D1 Q1
CLR1
REFCLK
OUT
OUT
CP
3.5mA
CLR2
D2 Q2
DOWN
HIGH
FEEDBACK
DIVIDER
Figure 12. LVDS Output Simplified Equivalent Circuit
The simplified equivalent circuits of the LVDS and LVPECL
GND
outputs are shown in Figure 12 and Figure 13.
Figure 14. PFD Simplified Schematic
3.3V
POWER SUPPLY
The AD9571 requires a 3.3 V 10% power supply for VS. The
Specifications section gives the performance expected from the
AD9571 with the power supply voltage within this range. The
absolute maximum range of (−0.3 V) − (+3.6 V), with respect to
GND, must never be exceeded on the VS pin.
OUT
OUT
Good engineering practice should be followed in the layout of
power supply traces and the ground plane of the PCB. Bypass
the power supply on the PCB with adequate capacitance (>10
µF). Bypass the AD9571 with adequate capacitors (0.1 µF) at all
power pins as close as possible to the part. The layout of the
AD9571 evaluation board is a good example.
GND
Figure 13. LVPECL Output Simplified Equivalent Circuit
The differential outputs are factory programmed to either LVPECL
or LVDS format, and either option can be sampled on request.
The exposed metal paddle on the AD9571 package is an electrical
connection, as well as a thermal enhancement. For the device to
function properly, the paddle must be properly attached to ground
(GND). The PCB acts as a heat sink for the AD9571; therefore,
this GND connection should provide a good thermal path to a
larger dissipation area, such as a ground plane on the PCB.
CMOS drivers tend to generate more noise than differential
outputs and, as a result, the proximity of the 33.33 MHz output
to Pin 21 and Pin 22 does affect the jitter performance when
FREQSEL = 0 (that is, when the differential output is generating
125 MHz). For this reason, the 33.33 MHz pin can be forced to
a low state by asserting the FORCE_LOW signal on Pin 37 (see
Table 16). An internal pull-down enables the 33.33 MHz output
if the pin is not connected.
CMOS CLOCK DISTRIBUTION
The AD9571 provides seven CMOS clock outputs (six 25 MHz
and one 33.33 MHz) that are dedicated CMOS levels. Whenever
single-ended CMOS clocking is used, some of the following
general guidelines should be followed.
Table 16. FORCE_LOW (Pin 37) Definition
FORCE_LOW
33.33 MHz Output (Pin 23)
0 or NC
1
33.33 MHz
0 MHz
Point-to-point nets should be designed such that a driver has
one receiver only on the net, if possible. This allows for simple
termination schemes and minimizes ringing due to possible
mismatched impedances on the net. Series termination at the
source is generally required to provide transmission line
matching and/or to reduce current transients at the driver.
Rev. 0 | Page 15 of 20
AD9571
3.3V
3.3V
The value of the resistor is dependent on the board design and
timing requirements (typically 10Ω to 100 Ω is used). CMOS
outputs are limited in terms of the capacitive load or trace
length that they can drive. Typically, trace lengths less than
6 inches are recommended to preserve signal rise/fall times
and signal integrity.
0.1nF
DIFFERENTIAL
(COUPLED)
100Ω
LVPECL
LVPECL
0.1nF
200Ω
200Ω
60.4Ω
1.0 INCH
Figure 18. LVPECL with Parallel Transmission Line
10Ω
CMOS
LVDS CLOCK DISTRIBUTION
MICROSTRIP
5pF
Low voltage differential signaling (LVDS) is a second differ-
ential output option for the AD9571. LVDS uses a current mode
output stage with a factory programmed current level. The
normal value (default) for this current is 3.5 mA, which yields a
350 mV output swing across a 100Ω resistor. The LVDS
outputs meet or exceed all ANSI/TIA/EIA-644 specifications.
GND
Figure 15. Series Termination of CMOS Output
Termination at the far end of the PCB trace is a second option.
The CMOS outputs of the AD9571 do not supply enough current
to provide a full voltage swing with a low impedance resistive,
far-end termination, as shown in Figure 16. The far-end termin-
ation network should match the PCB trace impedance and
provide the desired switching point. The reduced signal swing
may still meet receiver input requirements in some applications.
This can be useful when driving long trace lengths on less
critical nets.
A recommended termination circuit for the LVDS outputs is
shown in Figure 19.
50Ω
100Ω
LVDS
LVDS
50Ω
Figure 19. LVDS Output Termination
V
= 3.3V
PULLUP
See the AN-586 Application Note on the Analog Devices
website at www.analog.com for more information about LVDS.
100Ω
50Ω
10Ω
CMOS
5pF
100Ω
REFERENCE INPUT
By default, the crystal oscillator is enabled and used as the
reference source, which requires the connection of an external
25 MHz crystal. The REFSEL pin is pulled high internally by
about 30 kΩ to support default operation. When REFSEL is tied
low, the crystal oscillator is powered down, and the REFCLK pin
must provide a good quality 25 MHz reference clock instead.
This single-ended input can be driven by either a dc-coupled
LVCMOS level signal or an ac-coupled sine wave or square
wave, provided that an external divider is used to bias the input
at VS/2.
Figure 16. CMOS Output with Far-End Termination
LVPECL CLOCK DISTRIBUTION
The low voltage, positive emitter-coupled logic (LVPECL)
outputs of the AD9571 provide the lowest jitter clock signals
available from the AD9571. The LVPECL outputs (because they
are open emitter) require a dc termination to bias the output
transistors. The simplified equivalent circuit in Figure 13 shows
the LVPECL output stage.
In most applications, a standard LVPECL far-end termination is
recommended, as shown in Figure 17. The resistor network is
designed to match the transmission line impedance (50Ω) and
the desired switching threshold (1.3 V).
Table 17. REFSEL Definition
REFSEL
Reference Source
0
1
REFCLK input
Internal crystal oscillator
3.3V
POWER AND GROUNDING CONSIDERATIONS AND
POWER SUPPLY REJECTION
3.3V
3.3V
127Ω
127Ω
50Ω
Many applications seek high speed and performance under
less than ideal operating conditions. In these application
circuits, the implementation and construction of the PCB is as
important as the circuit design. Proper RF techniques must be
used for device selection, placement, and routing, as well as for
power supply bypassing and grounding to ensure optimum
performance.
SINGLE-ENDED
(NOT COUPLED)
LVPECL
LVPECL
50Ω
83Ω
83Ω
V
= V – 1.3V
T
CC
Figure 17. LVPECL Far-End Termination
Rev. 0 | Page 16 of 20
AD9571
OUTLINE DIMENSIONS
6.10
6.00 SQ
5.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
31
30
40
1
0.50
BSC
*
4.80
EXPOSED
PAD
4.70 SQ
4.50
21
20
10
11
0.45
0.40
0.35
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-WJJD-5
WITH EXCEPTION TO EXPOSED PAD DIMENSION.
Figure 20. 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
6 mm × 6 mm Body, Very Very Thin Quad
(CP-40-7)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
40-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Package Option
CP-40-7
CP-40-7
AD9571ACPZLVD1, 2
AD9571ACPZLVD-RL1, 2
40-Lead Lead Frame Chip Scale Package [LFCSP_WQ],
7” Tape Reel, 2,500 Pieces
40-Lead Lead Frame Chip Scale Package [LFCSP_WQ],
7” Tape Reel, 750 Pieces
AD9571ACPZLVD-R71, 2
−40°C to +85°C
CP-40-7
AD9571ACPZPEC1, 3
AD9571ACPZPEC-R71, 3
−40°C to +85°C
−40°C to +85°C
40-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
CP-40-7
CP-40-7
40-Lead Lead Frame Chip Scale Package [LFCSP_WQ],
7” Tape Reel, 750 Pieces
40-Lead Lead Frame Chip Scale Package [LFCSP_WQ],
7” Tape Reel, 2,500 Pieces
Evaluation Board
Evaluation Board
AD9571ACPZPEC-RL1, 3
−40°C to +85°C
CP-40-7
AD9571-EVALZ-LVD1, 2
AD9571-EVALZ-PEC1, 3
1Z = RoHS Compliant Part.
2LVD indicates LVDS compliant, differential clock outputs.
3PEC indicates LVPECL compliant, differential clock outputs.
Rev. 0 | Page 17 of 20
AD9571
NOTES
Rev. 0 | Page 18 of 20
AD9571
NOTES
Rev. 0 | Page 19 of 20
AD9571
NOTES
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07499-0-8/09(0)
Rev. 0 | Page 20 of 20
相关型号：
AD9572ACPZLVD1
IC 156.25 MHz, OTHER CLOCK GENERATOR, QCC40, 6 X 6 MM, ROHS COMPLIANT, MO-220WJJD-5, LFCSP-40, Clock Generator
ADI
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