AD9258-125EBZ_技术文档

14-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Dual

Analog-to-Digital Converter (ADC)

AD9258

FUNCTIONAL BLOCK DIAGRAM

FEATURES

SDIO/ SCLK/

SNR = 77.6 dBFS @ 70 MHz and 125 MSPS

SFDR = 88 dBc @ 70 MHz and 125 MSPS

Low power: 750 mW @ 125 MSPS

AVDD

CSB

DRVDD

DCS

DFS

SPI

AD9258

1.8 V analog supply operation

ORA

1.8 V CMOS or LVDS output supply

Integer 1-to-8 input clock divider

IF sampling frequencies to 300 MHz

−152.8 dBm/Hz small signal input noise with 200 Ω input

impedance @ 70 MHz and 125 MSPS

Optional on-chip dither

Programmable internal ADC voltage reference

Integrated ADC sample-and-hold inputs

Flexible analog input range: 1 V p-p to 2 V p-p

Differential analog inputs with 650 MHz bandwidth

ADC clock duty cycle stabilizer

PROGRAMMING DATA

CMOS/LVDS

D13A (MSB)

TO

D0A (LSB)

VIN+A

VIN–A

14

ADC

OUTPUT BUFFER

CLK+

CLK–

VREF

DIVIDE 1

TO 8

SENSE

DCOA

DCOB

DUTY CYCLE

STABILIZER

DCO

GENERATION

REF

SELECT

VCM

RBIAS

ORB

D13B (MSB)

TO

D0B (LSB)

VIN–B

VIN+B

14

CMOS/LVDS

OUTPUT BUFFER

ADC

95 dB channel isolation/crosstalk

Serial port control

MULTICHIP

SYNC

User-configurable, built-in self-test (BIST) capability

Energy-saving power-down modes

AGND

SYNC

PDWN

OEB

NOTES

1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY;

SEE FIGURE 7 FORLVDS PIN NAMES.

APPLICATIONS

Figure 1.

Communications

Diversity radio systems

PRODUCT HIGHLIGHTS

Multimode digital receivers (3G)

GSM, EDGE, W-CDMA, LTE,

CDMA2000, WiMAX, TD-SCDMA

I/Q demodulation systems

Smart antenna systems

General-purpose software radios

Broadband data applications

Ultrasound equipment

1. On-chip dither option for improved SFDR performance

with low power analog input.

2. Proprietary differential input that maintains excellent SNR

performance for input frequencies up to 300 MHz.

3. Operation from a single 1.8 V supply and a separate digital

output driver supply accommodating 1.8 V CMOS or

LVDS outputs.

4. Standard serial port interface (SPI) that supports various

product features and functions, such as data formatting

(offset binary, twos complement, or gray coding), enabling

the clock DCS, power-down, test modes, and voltage

reference mode.

5. Pin compatibility with the AD9268, allowing a simple

migration from 14 bits to 16 bits. The AD9258 is also pin

compatible with the AD9251, AD9231, and AD9204 family

of products for lower sample rate, low power applications.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD9258* PRODUCT PAGE QUICK LINKS

Last Content Update: 09/27/2017

COMPARABLE PARTS

View a parametric search of comparable parts.

TOOLS AND SIMULATIONS

• Visual Analog

• AD9258 IBIS Models

EVALUATION KITS

REFERENCE DESIGNS

• CN0140

• AD9258 Evaluation Board

DOCUMENTATION

REFERENCE MATERIALS

Application Notes

• AN-1142: Techniques for High Speed ADC PCB Layout

• AN-586: LVDS Outputs for High Speed A/D Converters

Technical Articles

• Improve The Design Of Your Passive Wideband ADC

Front-End Network

• AN-742: Frequency Domain Response of Switched-

Capacitor ADCs

• MS-2210: Designing Power Supplies for High Speed ADC

• AN-807: Multicarrier WCDMA Feasibility

• AN-808: Multicarrier CDMA2000 Feasibility

DESIGN RESOURCES

• AD9258 Material Declaration

• PCN-PDN Information

• Quality And Reliability

• Symbols and Footprints

• AN-812: MicroController-Based Serial Port Interface (SPI)

Boot Circuit

• AN-827: A Resonant Approach to Interfacing Amplifiers to

Switched-Capacitor ADCs

• AN-878: High Speed ADC SPI Control Software

• AN-905: Visual Analog Converter Evaluation Tool Version

1.0 User Manual

DISCUSSIONS

View all AD9258 EngineerZone Discussions.

• AN-935: Designing an ADC Transformer-Coupled Front

End

SAMPLE AND BUY

Visit the product page to see pricing options.

Data Sheet

• AD9258: 14-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Dual

Analog-to-Digital Converter (ADC) Data Sheet

TECHNICAL SUPPORT

User Guides

Submit a technical question or find your regional support

number.

• UG-003: Evaluating the AD9650/AD9268/AD9258/

AD9251/AD9231/AD9204 Analog-to-Digital Converters

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AD9258

TABLE OF CONTENTS

Features .............................................................................................. 1

Clock Input Considerations...................................................... 30

Channel/Chip Synchronization................................................ 31

Power Dissipation and Standby Mode .................................... 32

Digital Outputs ........................................................................... 32

Timing ......................................................................................... 33

Built-In Self-Test (BIST) and Output Test .................................. 34

Built-In Self-Test (BIST)............................................................ 34

Output Test Modes..................................................................... 34

Serial Port Interface (SPI).............................................................. 35

Configuration Using the SPI..................................................... 35

Hardware Interface..................................................................... 36

Configuration Without the SPI ................................................ 36

SPI Accessible Features.............................................................. 36

Memory Map .................................................................................. 37

Reading the Memory Map Register Table............................... 37

Memory Map Register Table..................................................... 38

Memory Map Register Descriptions........................................ 40

Applications Information.............................................................. 41

Design Guidelines ...................................................................... 41

Outline Dimensions....................................................................... 42

Ordering Guide .......................................................................... 42

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

General Description......................................................................... 3

Specifications..................................................................................... 4

ADC DC Specifications................................................................. 4

ADC AC Specifications ................................................................. 6

Digital Specifications ................................................................... 7

Switching Specifications ................................................................ 9

Timing Specifications ................................................................ 10

Absolute Maximum Ratings.......................................................... 12

Thermal Characteristics ............................................................ 12

ESD Caution................................................................................ 12

Pin Configurations and Function Descriptions ......................... 13

Typical Performance Characteristics ........................................... 17

Equivalent Circuits......................................................................... 25

Theory of Operation ...................................................................... 26

ADC Architecture ...................................................................... 26

Analog Input Considerations.................................................... 26

Voltage Reference ....................................................................... 29

REVISION HISTORY

9/09—Rev. 0 to Rev. A

Changes to Features List.................................................................. 1

Changes to Specifications Section.................................................. 4

Changes to Table 5............................................................................ 9

Changes to Typical Performance Characteristics Section......... 17

5/09—Revision 0: Initial Version

Rev. A | Page 2 of 44

AD9258

GENERAL DESCRIPTION

The AD9258 is a dual, 14-bit, 80 MSPS/105 MSPS/125 MSPS

analog-to-digital converter (ADC). The AD9258 is designed to

support communications applications where high performance,

combined with low cost, small size, and versatility, is desired.

The ADC output data can be routed directly to the two external

14-bit output ports. These outputs can be set to either 1.8 V CMOS

or LVDS.

Flexible power-down options allow significant power savings,

when desired.

The dual ADC core features a multistage, differential pipelined

architecture with integrated output error correction logic. Each

ADC features wide bandwidth differential sample-and-hold

analog input amplifiers that support a variety of user-selectable

input ranges. An integrated voltage reference eases design consid-

erations. A duty cycle stabilizer is provided to compensate for

variations in the ADC clock duty cycle, allowing the converters

to maintain excellent performance.

Programming for setup and control is accomplished using a 3-wire

SPI-compatible serial interface.

The AD9258 is available in a 64-lead LFCSP and is specified over

the industrial temperature range of −40°C to +85°C.

Rev. A | Page 3 of 44

AD9258

SPECIFICATIONS

ADC DC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless

otherwise noted.

Table 1.

AD9258BCPZ-80

AD9258BCPZ-105

AD9258BCPZ-125

Max

Parameter

Temperature Min Typ

Max Min Typ Max Min Typ

Unit

RESOLUTION

ACCURACY

Full

14

Bits

No Missing Codes

Offset Error

Gain Error

Full

Guaranteed

±±.1

±±.4

Guaranteed

±±.1

±±.4

Guaranteed

±±.4

±±.ꢀ

±2.ꢀ

±±.ꢀ

±2.ꢀ

±±.ꢀ

±±.ꢁꢀ % FSR

±2.ꢀ

±±.ꢀ

% FSR

LSB

Differential

Nonlinearity (DNL)¹

2ꢀ°C

±±.2ꢀ

±±.ꢀꢀ

±±.2ꢀ

±±.ꢂ

±±.2ꢀ

±±.ꢃ

LSB

Integral Nonlinearity Full

(INL)¹

±1.1

±1.3

±1.4

2ꢀ°C

LSB

MATCHING

CHARACTERISTIC

Offset Error

Gain Error

Full

±±.1

±±.3

±±.4

±1.3

±±.1

±±.3

±±.4

±1.3

±±.2

±±.3

±±.4ꢀ % FSR

±1.3

% FSR

TEMPERATURE DRIFT

Offset Error

Gain Error

Full

±2

±1ꢀ

±2

±1ꢀ

±2

±1ꢀ

ppm/°C

INTERNAL VOLTAGE

REFERENCE

Output Voltage Error Full

(1 V Mode)

±ꢀ

ꢀ

±12

±ꢀ

ꢀ

±12

±ꢀ

ꢀ

±12

mV

Load Regulation @

1.± mA

Full

INPUT REFERRED NOISE

VREF = 1.± V

2ꢀ°C

±.ꢁ2

2

±.ꢁ3

2

±.ꢂ

2

LSB

rms

ANALOG INPUT

Input Span, VREF =

1.± V

Input Capacitance²

Input Common-

Mode Voltage

Full

V p-p

Full

ꢃ

±.9

ꢃ

±.9

ꢃ

±.9

pF

V

REFERENCE INPUT

RESISTANCE

Full

ꢁ

kΩ

POWER SUPPLIES

Supply Voltage

AVDD

Full

1.ꢂ

1.ꢃ

1.9

1.ꢂ

1.ꢃ

1.9

1.ꢂ

1.ꢃ

1.9

V

DRVDD

Supply Current

IAVDD¹

IDRVDD¹(1.ꢃ V

CMOS)

Full

234

33

24±

293

43

3±±

39±

ꢀ3

4±±

mA

IDRVDD¹(1.ꢃ V

LVDS)

Full

ꢃ1

9±

mA

Rev. A | Page 4 of 44

AD9258

AD9258BCPZ-80

Temperature Min Typ Max Min Typ

AD9258BCPZ-105

AD9258BCPZ-125

Max

Parameter

Max Min Typ

Unit

POWER CONSUMPTION

DC Input

Sine Wave Input¹

(DRVDD = 1.ꢃ V

CMOS Output

Mode)

Full

4ꢁ2

4ꢃ1

4ꢃꢂ

ꢀꢁꢀ

ꢁ±ꢀ

ꢀ9±

ꢂꢀ±

ꢂ9ꢂ

ꢂꢂꢂ

mW

Sine Wave Input¹

(DRVDD = 1.ꢃ V

LVDS Output

Mode)

Full

ꢀꢁꢃ

ꢁꢂ1

ꢃꢁꢀ

mW

Standby Power³

Full

4ꢀ

±.ꢀ

4ꢀ

±.ꢀ

4ꢀ

±.ꢀ

mW

Power-Down Power

2.ꢀ

¹Measured with a low input frequency, full-scale sine wave, with approximately ꢀ pF loading on each output bit.

²Input capacitance refers to the effective capacitance between one differential input pin and AGND.

³Standby power is measured with a dc input and with the CLK pins inactive (set to AVDD or AGND).

Rev. A | Page ꢀ of 44

AD9258

ADC AC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless

otherwise noted.

Table 2.

AD9258BCPZ-80

AD9258BCPZ-105

AD9258BCPZ-125

Parameter¹

Temp

Min

Typ

Max

Min Typ

Max

Min

Typ

Max

Unit

SIGNAL-TO-NOISE-RATIO (SNR)

f_IN= 2.4 MHz

f_IN= ꢂ± MHz

2ꢀ°C

Full

2ꢀ°C

ꢂ9.±

ꢂꢃ.3

ꢂꢃ.4

ꢂꢂ.3 ꢂꢃ.2

ꢂꢁ.9

ꢂꢂ.ꢂ

ꢂꢂ.ꢁ

dBFS

ꢂꢂ.ꢂ

ꢂꢂ.4

ꢂꢁ.ꢃ

ꢂꢁ.±

ꢂꢂ.±

ꢂꢀ.3

ꢂꢁ.ꢁ

ꢂꢀ.1

f_IN= 14± MHz

f_IN= 2±± MHz

ꢂ4.9

SIGNAL-TO-NOISE AND DISTORTION (SINAD)

f_IN= 2.4 MHz

f_IN= ꢂ± MHz

2ꢀ°C

Full

2ꢀ°C

ꢂꢃ.ꢂ

ꢂꢃ.±

ꢂꢂ.ꢃ

ꢂꢂ.1 ꢂꢃ.±

ꢂꢁ.ꢂ

ꢂꢂ.3

ꢂꢂ.±

dBFS

ꢂꢂ.ꢀ

ꢂꢂ.2

ꢂꢁ.ꢀ

ꢂꢀ.ꢂ

f_IN= 14± MHz

f_IN= 2±± MHz

ꢂꢀ.1

ꢂ4.2

ꢂꢀ.ꢁ

ꢂ2.1

ꢂꢀ.3

ꢂ3.ꢁ

EFFECTIVE NUMBER OF BITS (ENOB)

f_IN= 2.4 MHz

f_IN= ꢂ± MHz

f_IN= 14± MHz

f_IN= 2±± MHz

2ꢀ°C

12.ꢃ

12.ꢂ

12.2

12.±

12.ꢁ

12.3

11.ꢂ

12.ꢀ

12.2

11.9

Bits

WORST SECOND OR THIRD HARMONIC

f_IN= 2.4 MHz

f_IN= ꢂ± MHz

2ꢀ°C

Full

2ꢀ°C

−92

−91

−ꢃꢂ

−92

−9±

−ꢃꢃ

dBc

−ꢃꢂ

−ꢃ3

f_IN= 14± MHz

f_IN= 2±± MHz

−ꢃ±

−ꢃ2

−ꢃ4

−ꢂꢁ

−ꢃ3

−ꢂ9

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

f_IN= 2.4 MHz

f_IN= ꢂ± MHz

2ꢀ°C

Full

2ꢀ°C

92

91

ꢃꢂ

92

9±

ꢃꢃ

dBc

ꢃꢂ

ꢃ3

f_IN= 14± MHz

f_IN= 2±± MHz

ꢃ±

ꢃ2

ꢃ4

ꢂꢁ

ꢃ3

ꢂ9

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

Without Dither (AIN @ −23 dBFS)

f_IN= 2.4 MHz

2ꢀ°C

93

9ꢀ

9ꢃ

1±2

1±±

9ꢁ

ꢃꢃ

ꢃ9

9±

ꢃ9

dBFS

f_IN= ꢂ± MHz

f_IN= 14± MHz

f_IN= 2±± MHz

1±±

With On-Chip Dither (AIN @ −23 dBFS)

f_IN= 2.4 MHz

f_IN= ꢂ± MHz

f_IN= 14± MHz

f_IN= 2±± MHz

2ꢀ°C

1±ꢂ

1±ꢁ

1±ꢀ

1±ꢁ

1±ꢂ

1±ꢀ

1±ꢁ

1±ꢂ

1±ꢁ

1±3

1±ꢀ

dBFS

Rev. A | Page ꢁ of 44

AD9258

AD9258BCPZ-80

AD9258BCPZ-105

AD9258BCPZ-125

Parameter¹

Temp

Min

Typ

Max

Min Typ

Max

Min

Typ

Max

Unit

WORST OTHER (HARMONIC OR SPUR)

Without Dither

f_IN= 2.4 MHz

f_IN= ꢂ± MHz

2ꢀ°C

Full

2ꢀ°C

−1±±

−1±± −9ꢁ

−9ꢁ

−9ꢂ

−9ꢀ

−1±±

−99

−9ꢃ

dBc

−94

f_IN= 14± MHz

f_IN= 2±± MHz

−9ꢂ

−9ꢀ

−9ꢂ

−9ꢀ

With On-Chip Dither

f_IN= 2.4 MHz

f_IN= ꢂ± MHz

2ꢀ°C

Full

2ꢀ°C

−1±9

−1±ꢀ −9ꢁ

−9ꢁ

−1±ꢁ

−1±2

−1±ꢂ

−1±ꢁ

−1±ꢂ

−1±ꢀ −9ꢀ

−9ꢀ

−1±3

−9ꢂ

dBc

−9ꢀ

f_IN= 14± MHz

f_IN= 2±± MHz

−1±4

TWO-TONE SFDR WITHOUT DITHER

f_IN= 29 MHz (−ꢂ dBFS ), 32 MHz (−ꢂ dBFS )

f_IN= 1ꢁ9 MHz (−ꢂ dBFS ),1ꢂ2 MHz (−ꢂ dBFS )

CROSSTALK²

2ꢀ°C

Full

93

ꢃ1

92

ꢃ±

9±

ꢃ2

dBc

dB

−9ꢀ

ꢁꢀ±

−9ꢀ

ꢁꢀ±

−9ꢀ

ꢁꢀ±

ANALOG INPUT BANDWIDTH

2ꢀ°C

MHz

¹See the AN-ꢃ3ꢀ Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.

²Crosstalk is measured at 1±± MHz with −1.± dBFS on one channel and no input on the alternate channel.

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless

otherwise noted.

Table 3.

Parameter

Temperature

Min

Typ

Max

Unit

DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)

Logic Compliance

CMOS/LVDS/LVPECL

Internal Common-Mode Bias

Differential Input Voltage

Input Voltage Range

Input Common-Mode Range

High Level Input Current

Low Level Input Current

Input Capacitance

Full

±.9

V

V p-p

V

±.3

AGND

±.9

−1±±

3.ꢁ

AVDD

1.4

+1±±

V

μA

pF

kΩ

4

1±

Input Resistance

ꢃ

12

SYNC INPUT

Logic Compliance

Internal Bias

CMOS

±.9

Full

V

Input Voltage Range

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Capacitance

AGND

1.2

AGND

−1±±

AVDD

±.ꢁ

V

+1±±

μA

pF

kΩ

1

1ꢁ

Input Resistance

12

2±

Rev. A | Page ꢂ of 44

AD9258

Parameter

LOGIC INPUT (CSB)¹

Temperature

Min

Typ

Max

Unit

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Resistance

Full

1.22

±

−1±

4±

2.1

±.ꢁ

+1±

132

V

μA

kΩ

pF

2ꢁ

2

Input Capacitance

LOGIC INPUT (SCLK/DFS)²

High Level Input Voltage

Low Level Input Voltage

High Level Input Current (VIN = 1.ꢃ V)

Low Level Input Current

Input Resistance

Full

1.22

±

−92

−1±

2.1

±.ꢁ

−13ꢀ

+1±

V

μA

kΩ

pF

2ꢁ

2

Input Capacitance

LOGIC INPUT/OUTPUT (SDIO/DCS)¹

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Resistance

Full

1.22

±

−1±

3ꢃ

2.1

±.ꢁ

+1±

12ꢃ

V

μA

kΩ

pF

2ꢁ

ꢀ

Input Capacitance

LOGIC INPUTS (OEB, PDWN)²

High Level Input Voltage

Low Level Input Voltage

High Level Input Current (VIN = 1.ꢃ V)

Low Level Input Current

Input Resistance

Full

1.22

±

−9±

−1±

2.1

±.ꢁ

−134

+1±

V

μA

kΩ

pF

2ꢁ

ꢀ

Input Capacitance

DIGITAL OUTPUTS

CMOS Mode—DRVDD = 1.ꢃ V

High Level Output Voltage

I_OH= ꢀ± μA

Full

1.ꢂ9

1.ꢂꢀ

V

I_OH= ±.ꢀ mA

Low Level Output Voltage

I_OL= 1.ꢁ mA

I_OL= ꢀ± μA

Full

±.2

±.±ꢀ

V

LVDS Mode—DRVDD = 1.ꢃ V

Differential Output Voltage (V_OD), ANSI Mode

Output Offset Voltage (V_OS), ANSI Mode

Differential Output Voltage (V_OD), Reduced Swing Mode

Output Offset Voltage (V_OS), Reduced Swing Mode

Full

29±

1.1ꢀ

1ꢁ±

1.1ꢀ

34ꢀ

1.2ꢀ

2±±

1.2ꢀ

4±±

1.3ꢀ

23±

1.3ꢀ

mV

V

mV

V

¹Pull up.

²Pull down.

Rev. A | Page ꢃ of 44

AD9258

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless

otherwise noted.

Table 4.

AD9258BCPZ-80

Temperature Min Typ Max Min Typ

AD9258BCPZ-105

AD9258BCPZ-125

Max

Parameter

Max Min Typ

Unit

CLOCK INPUT PARAMETERS

Input Clock Rate

Conversion Rate¹

DCS Enabled

DCS Disabled

CLK Period—Divide-by-1 Mode (t_CLK

Full

625

MHz

Full

20

10

12.5

80

20

10

9.5

105

20

10

8

125

MSPS

ns

)

CLK Pulse Width High (t_CH)

3.75

5.95

0.8

8.75

6.55

2.85

4.5

6.65

5.0

Divide-by-1 Mode, DCS Enabled

Divide-by-1 Mode, DCS Disabled Full

Divide-by-2 Mode Through

Divide-by-8 Mode

Full

6.25

4.75

2.4

3.8

0.8

4

5.6

4.2

ns

Full

0.8

Aperture Delay (t_A)

Aperture Uncertainty (Jitter, t_J)

Full

1.0

0.07

1.0

0.07

1.0

0.07

ns

ps

rms

DATA OUTPUT PARAMETERS

CMOS Mode

4.2

0

2.8

Data Propagation Delay (t_PD)

DCO Propagation Delay (t_DCO

Full

2.8

3.5

3.1

3.5

3.1

4.2

0

2.8

3.5

3.1

4.2

0

ns

2

)

DCO to Data Skew (t_SKEW

LVDS Mode

)

−0.6 −0.4

Data Propagation Delay (t_PD

DCO Propagation Delay (t_DCO

Full

2.9

3.7

3.9

4.5

2.9

3.7

3.9

4.5

2.9

3.7

3.9

4.5

+0.5

ns

Cycles

2

)

DCO to Data Skew (t_SKEW

)

−0.1 +0.2

12

+0.5 −0.1 +0.2

12

+0.5 −0.1 +0.2

12

CMOS Mode Pipeline Delay

(Latency)

LVDS Mode Pipeline Delay

Full

12/12.5

Cycles

(Latency) Channel A/Channel B

Wake-Up Time³

Out-of-Range Recovery Time

Full

500

2

500

2

500

2

μs

Cycles

¹Conversion rate is the clock rate after the divider.

²Additional DCO delay can be added by writing to Bit 0 through Bit 4 in SPI Register 0x17 (see Table 17).

³Wake-up time is defined as the time required to return to normal operation from power-down mode.

Rev. A | Page 9 of 44

AD9258

TIMING SPECIFICATIONS

Table 5.

Parameter

Conditions

Limit

SYNC TIMING REQUIREMENTS

t_SSYNC

t_HSYNC

SYNC to rising edge of CLK+ setup time

SYNC to rising edge of CLK+ hold time

±.3± ns typ

±.4± ns typ

SPI TIMING REQUIREMENTS

t_DS

t_DH

t_CLK

t_S

t_H

t_HIGH

t_LOW

t_{EN_SDIO}

Setup time between the data and the rising edge of SCLK

Hold time between the data and the rising edge of SCLK

Period of the SCLK

Setup time between CSB and SCLK

Hold time between CSB and SCLK

SCLK pulse width high

2 ns min

4± ns min

2 ns min

1± ns min

SCLK pulse width low

Time required for the SDIO pin to switch from an input to an output relative to the SCLK

falling edge

t_{DIS_SDIO}

Time required for the SDIO pin to switch from an output to an input relative to the SCLK

rising edge

1± ns min

Timing Diagrams

N – 1

N + 4

t_A

N + 5

N

N + 3

VIN

N + 1

N + 2

t_CH

t_CLK

CLK+

CLK–

t_DCO

DCOA/DCOB

t_SKEW

N – 12

CH A/CH B DATA

N – 13

N – 11

N – 10

N – 9

N – 8

t_PD

Figure 2. CMOS Default Output Mode Data Output Timing

N – 1

N + 4

t_A

N + 5

N

N + 3

VIN

N + 1

N + 2

t_CH

t_CLK

CLK+

CLK–

t_DCO

DCOA/DCOB

t_SKEW

t_PD

CH A CH B CH A CH B CH A CH B

CH A CH B

CH A

N – 8

CH A/CH B DATA

N – 12 N – 12 N – 11 N – 11 N – 10 N – 10 N – 9 N – 9

Figure 3. CMOS Interleaved Output Mode Data Output Timing

Rev. A | Page 1± of 44

AD9258

N – 1

N + 4

t_A

N + 5

N

N + 3

VIN

N + 1

N + 2

t_CH

t_CLK

CLK+

CLK–

t_DCO

DCOA/DCOB

t_SKEW

CH A CH B CH A CH B CH A CH B

t_PD

CH A CH B

CH A

N – 8

CH A/CH B DATA

N – 12 N – 12 N – 11 N – 11 N – 10 N – 10 N – 9 N – 9

Figure 4. LVDS Mode Data Output Timing

CLK+

SYNC

t_SSYNC

t_HSYNC

Figure 5. SYNC Input Timing Requirements

Rev. A | Page 11 of 44

AD9258

ABSOLUTE MAXIMUM RATINGS

THERMAL CHARACTERISTICS

Table 6.

The exposed paddle must be soldered to the ground plane for

the LFCSP package. Soldering the exposed paddle to the PCB

increases the reliability of the solder joints and maximizes the

thermal capability of the package.

Parameter

Rating

ELECTRICAL¹

AVDD to AGND

DRVDD to AGND

−0.3 V to +2.0 V

−0.3 V to +2.0V

VIN+A/VIN+B, VIN−A/VIN−B to AGND −0.3 V to AVDD + 0.2 V

Typical θ_JAis specified for a 4-layer PCB with a solid ground

plane. As shown in Table 7, airflow improves heat dissipation,

which reduces θ_JA. In addition, metal in direct contact with the

package leads from metal traces, through holes, ground, and

power planes, reduces θ_JA.

CLK+, CLK− to AGND

SYNC to AGND

VREF to AGND

SENSE to AGND

VCM to AGND

RBIAS to AGND

CSB to AGND

SCLK/DFS to AGND

SDIO/DCS to AGND

OEB

−0.3 V to AVDD + 0.2 V

−0.3V to AVDD + 0.2 V

−0.3 V to DRVDD + 0.2 V

Table 7. Thermal Resistance

Airflow

Velocity

(m/sec)

1, 2

1, 3

1, 4

Package Type

θ_JA

θ_JC

1.0

θ_JB

Unit

°C/W

64-Lead LFCSP

(CP-64-6)

0

18.5

16.1

14.5

1.0

2.5

9.2

PDWN

D0A/D0B through D13A/D13B to

AGND

¹Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.

2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).

3 Per MIL-Std 883, Method 1012.1.

4 Per JEDEC JESD51-8 (still air).

DCOA/DCOB to AGND

ENVIRONMENTAL

−0.3 V to DRVDD + 0.2 V

Operating Temperature Range

(Ambient)

Maximum Junction Temperature

Under Bias

−40°C to +85°C

150°C

ESD CAUTION

Storage Temperature Range

(Ambient)

−65°C to +150°C

¹The inputs and outputs are rated to the supply voltage (AVDD or DRVDD) +

0.2 V but should not exceed 2.1 V.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rev. A | Page 12 of 44

AD9258

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

CLK+

CLK–

SYNC

NC

1

2

3

4

5

6

7

8

9

48 PDWN

47 OEB

46 CSB

45 SCLK/DFS

44 SDIO/DCS

43 ORA

42 D13A (MSB)

41 D12A

40 D11A

39 D10A

38 D9A

37 DRVDD

36 D8A

35 D7A

34 D6A

33 D5A

NC

D0B (LSB)

D1B

D2B

D3B

AD9258

PARALLEL CMOS

TOP VIEW

DRVDD 10

D4B 11

D5B 12

D6B 13

D7B 14

D8B 15

D9B 16

(Not to Scale)

NOTES

1. NC = NO CONNECT.

2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE

PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED

PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.

Figure 6. LFCSP Parallel CMOS Pin Configuration (Top View)

Table 8. Pin Function Descriptions (Parallel CMOS Mode)

Pin No.

Mnemonic

Type

Description

ADC Power Supplies

1±, 19, 2ꢃ, 3ꢂ

49, ꢀ±, ꢀ3, ꢀ4, ꢀ9,

ꢁ±, ꢁ3, ꢁ4

DRVDD

AVDD

Supply

Digital Output Driver Supply (1.ꢃ V Nominal).

Analog Power Supply (1.ꢃ V Nominal).

4, ꢀ, 2ꢀ, 2ꢁ

±

NC

AGND,

Exposed Pad

Do Not Connect.

Ground

The exposed thermal pad on the bottom of the package provides the analog

ground for the part. This exposed pad must be connected to ground for proper

operation.

ADC Analog

ꢀ1

ꢀ2

ꢁ2

ꢁ1

VIN+A

VIN−A

VIN+B

VIN−B

VREF

Input

Differential Analog Input Pin (+) for Channel A.

Differential Analog Input Pin (−) for Channel A.

Differential Analog Input Pin (+) for Channel B.

Differential Analog Input Pin (−) for Channel B.

ꢀꢀ

Input/Output Voltage Reference Input/Output.

ꢀꢁ

ꢀꢃ

ꢀꢂ

1

SENSE

RBIAS

VCM

CLK+

CLK−

Input

Voltage Reference Mode Select. See Table 11 for details.

Input/Output External Reference Bias Resistor.

Output

Input

Common-Mode Level Bias Output for Analog Inputs.

ADC Clock Input—True.

ADC Clock Input—Complement.

2

Input

Digital Input

3

SYNC

Input

Digital Synchronization Pin. Slave mode only.

Digital Outputs

2ꢂ

29

3±

31

D±A (LSB)

D1A

D2A

Output

Channel A CMOS Output Data.

D3A

Rev. A | Page 13 of 44

AD9258

Pin No.

Mnemonic

D4A

Type

Description

32

Output

Channel A CMOS Output Data.

Channel A Overrange Output.

Channel B CMOS Output Data.

Channel B Overrange Output

Channel A Data Clock Output.

Channel B Data Clock Output.

33

34

3ꢀ

3ꢁ

3ꢃ

39

4±

41

42

43

ꢁ

ꢂ

ꢃ

9

11

12

13

14

1ꢀ

1ꢁ

1ꢂ

1ꢃ

2±

21

DꢀA

DꢁA

DꢂA

DꢃA

D9A

D1±A

D11A

D12A

D13A (MSB)

ORA

D±B (LSB)

D1B

D2B

D3B

D4B

DꢀB

DꢁB

DꢂB

DꢃB

D9B

D1±B

D11B

D12B

D13B (MSB)

ORB

22

24

23

DCOA

DCOB

SPI Control

4ꢀ

44

4ꢁ

SCLK/DFS

SDIO/DCS

CSB

Input

SPI Serial Clock/Data Format Select Pin in External Pin Mode.

Input/Output SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode.

Input

SPI Chip Select (Active Low).

ADC Configuration

4ꢂ

4ꢃ

OEB

PDWN

Input

Output Enable Input (Active Low) in External Pin Mode.

Power-Down Input in External Pin Mode. In SPI mode, this input can be

configured as power-down or standby.

Rev. A | Page 14 of 44

AD9258

PIN 1

INDICATOR

48

PDWN

47 OEB

46 CSB

45 SCLK/DFS

44 SDIO/DCS

43 OR+

CLK+

CLK–

SYNC

NC

1

2

3

4

5

6

7

8

9

NC

D0– (LSB)

D0+ (LSB)

DRVDD 10

D1– 11

D1+ 12

D2– 13

D2+ 14

D3– 15

D3+ 16

42 OR–

41 D13+ (MSB)

40 D13– (MSB)

39 D12+

38 D12–

37 DRVDD

36 D11+

35 D11–

34 D10+

33 D10–

AD9258

PARALLEL LVDS

TOP VIEW

(Not to Scale)

NOTES

1. NC = NO CONNECT.

2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE

PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED

PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.

Figure 7. LFCSP Interleaved Parallel LVDS Pin Configuration (Top View)

Table 9. Pin Function Descriptions (Interleaved Parallel LVDS Mode)

Pin No.

Mnemonic

Type

Description

ADC Power Supplies

1±, 19, 2ꢃ, 3ꢂ

DRVDD

AVDD

Supply

Digital Output Driver Supply (1.ꢃ V Nominal).

Analog Power Supply (1.ꢃ V Nominal).

49, ꢀ±, ꢀ3, ꢀ4, ꢀ9,

ꢁ±, ꢁ3, ꢁ4

4, ꢀ, ꢁ, ꢂ

±

NC

Do Not Connect.

AGND,

Exposed Pad

Ground

The exposed thermal pad on the bottom of the package provides the analog

ground for the part. This exposed pad must be connected to ground for proper

operation.

ADC Analog

ꢀ1

ꢀ2

ꢁ2

ꢁ1

VIN+A

VIN−A

VIN+B

VIN−B

VREF

Input

Differential Analog Input Pin (+) for Channel A.

Differential Analog Input Pin (−) for Channel A.

Differential Analog Input Pin (+) for Channel B.

Differential Analog Input Pin (−) for Channel B.

ꢀꢀ

Input/Output Voltage Reference Input/Output.

ꢀꢁ

ꢀꢃ

ꢀꢂ

1

SENSE

RBIAS

VCM

CLK+

CLK−

Input

Voltage Reference Mode Select. See Table 11 for details.

Input/Output External Reference Bias Resistor.

Output

Input

Common-Mode Level Bias Output for Analog Inputs.

ADC Clock Input—True.

ADC Clock Input—Complement.

2

Input

Digital Input

3

SYNC

Input

Digital Synchronization Pin. Slave mode only.

Digital Outputs

9

ꢃ

12

11

14

13

D±+ (LSB)

D±− (LSB)

D1+

D1−

D2+

Output

Channel A/Channel B LVDS Output Data ±—True.

Channel A/Channel B LVDS Output Data ±—Complement.

Channel A/Channel B LVDS Output Data 1—True.

Channel A/Channel B LVDS Output Data 1—Complement.

Channel A/Channel B LVDS Output Data 2—True.

Channel A/Channel B LVDS Output Data 2—Complement.

D2−

Rev. A | Page 1ꢀ of 44

AD9258

Pin No.

Mnemonic

D3+

Type

Description

1ꢁ

Output

Channel A/Channel B LVDS Output Data 3—True.

Channel A/Channel B LVDS Output Data 3—Complement.

Channel A/Channel B LVDS Output Data 4 —True.

Channel A/Channel B LVDS Output Data 4—Complement.

Channel A/Channel B LVDS Output Data ꢀ—True.

Channel A/Channel B LVDS Output Data ꢀ—Complement.

Channel A/Channel B LVDS Output Data ꢁ—True.

Channel A/Channel B LVDS Output Data ꢁ—Complement.

Channel A/Channel B LVDS Output Data ꢂ—True.

Channel A/Channel B LVDS Output Data ꢂ—Complement.

Channel A/Channel B LVDS Output Data ꢃ—True.

Channel A/Channel B LVDS Output Data ꢃ—Complement.

Channel A/Channel B LVDS Output Data 9—True.

Channel A/Channel B LVDS Output Data 9—Complement.

Channel A/Channel B LVDS Output Data 1±—True.

Channel A/Channel B LVDS Output Data 1±—Complement.

Channel A/Channel B LVDS Output Data 11—True.

Channel A/Channel B LVDS Output Data 11—Complement.

Channel A/Channel B LVDS Output Data 12—True.

Channel A/Channel B LVDS Output Data 12—Complement.

Channel A/Channel B LVDS Output Data 13—True.

Channel A/Channel B LVDS Output Data 13—Complement.

Channel A/Channel B LVDS Overrange Output—True.

Channel A/Channel B LVDS Overrange Output—Complement.

Channel A/Channel B LVDS Data Clock Output—True.

Channel A/Channel B LVDS Data Clock Output—Complement.

1ꢀ

1ꢃ

1ꢂ

21

2±

23

22

2ꢂ

2ꢁ

3±

29

32

31

34

33

3ꢁ

3ꢀ

39

3ꢃ

41

4±

43

42

2ꢀ

D3−

D4+

D4−

Dꢀ+

Dꢀ−

Dꢁ+

Dꢁ−

Dꢂ+

Dꢂ−

Dꢃ+

Dꢃ−

D9+

D9−

D1±+

D1±−

D11+

D11−

D12+

D12−

D13+ (MSB)

D13− (MSB)

OR+

OR−

DCO+

DCO−

24

SPI Control

4ꢀ

SCLK/DFS

SDIO/DCS

CSB

Input

SPI Serial Clock/Data Format Select Pin in External Pin Mode.

44

4ꢁ

Input/Output SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode.

Input

SPI Chip Select (Active Low).

ADC Configuration

4ꢂ

4ꢃ

OEB

PDWN

Input

Output Enable Input (Active Low) in External Pin Mode.

Power-Down Input in External Pin Mode. In SPI mode, this input can be configured

as power-down or standby.

Rev. A | Page 1ꢁ of 44

AD9258

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD = 1.8 V, DRVDD = 1.8 V, rated sample rate, DCS enabled, 1.0 V internal reference, 2 V p-p differential input, VIN = −1.0 dBFS, and

32k sample, T_A= 25°C, unless otherwise noted

0

–20

–40

–60

0

–20

–40

–60

80MSPS

200.3MHz @ –1dBFS

SNR = 74.3dB (75.3dBFS)

SFDR = 83dBc

2.4MHz @ –1dBFS

SNR = 78.2dB (79.2dBFS)

SFDR = 99dBc

SECOND HARMONIC

THIRD HARMONIC

SECOND HARMONIC

THIRD HARMONIC

–80

–100

–120

–100

–120

–140

20

FREQUENCY (MHz)

0

10

20

FREQUENCY (MHz)

30

40

0

10

30

40

Figure 8. AD9258-80 Single-Tone FFT with f_IN= 2.4 MHz

Figure 11. AD9258-80 Single-Tone FFT with f_IN= 200.1 MHz

0

80MSPS

70.1MHz @ –6dBFS

SNR = 71.6dB (77.6dBFS)

SFDR = 97dBc

80MSPS

70.1MHz @ –1dBFS

SNR = 77.0dB (78.0dBFS)

SFDR = 89.0dBc

–20

–40

–60

–20

–40

–60

THIRD HARMONIC

SECOND HARMONIC

–80

–100

–120

–80

–100

–120

SECOND HARMONIC

–140

0

10

20

30

40

0

10

20

30

40

FREQUENCY (MHz)

Figure 9. AD9258-80 Single-Tone FFT with f_IN= 70.1 MHz

Figure 12. AD9258-80 Single-Tone FFT with f_IN= 70.1 MHz with Dither

Enabled

120

100

80

0

80MSPS

140.1MHz @ –1dBFS

SNR = 75.5dB (76.5dBFS)

SFDR = 82.0dBc

–20

–40

–60

THIRD HARMONIC

SECOND HARMONIC

60

–80

–100

–120

40

SNR (dBFS)

SFDR (dBc)

SNR (dBc)

20

0

SFDR (dBFS)

–140

–100 –90 –80 –70 –60 –50 –40 –30 –20 –10

0

10

20

FREQUENCY (MHz)

30

40

INPUT AMPLITUDE (dBFS)

Figure 13. AD9258-80 Single-Tone SNR/SFDR vs. Input Amplitude (A_IN

)

Figure 10. AD9258-80 Single-Tone FFT with f_IN= 140.1 MHz

with f_IN= 98.12 MHz

Rev. A | Page 1ꢂ of 44

AD9258

800,000

700,000

600,000

500,000

400,000

300,000

200,000

100,000

0

120

110

100

90

SNRFS (DITHER ON)

SNRFS (DITHER OFF)

SFDRFS (DITHER ON)

SFDRFS (DITHER OFF)

80

70

N – 3

N – 2

N – 1

N

N + 1

N + 2

N + 3

–100 –90 –80 –70 –60 –50 –40 –30 –20 –10

0

OUTPUT CODE

INPUT AMPLITUDE (dBFS)

Figure 17. AD9258-80 Grounded Input Histogram

Figure 14. AD9258-80 Single-Tone SNR/SFDR vs. Input Amplitude (A_IN

)

with f_IN= 30 MHz with and without Dither Enabled

2

1

100

DITHER ENABLED

DITHER DISABLED

SNR @ –40°C

SFDR @ –40°C

SNR @ +25°C

SFDR @ +25°C

SNR @ +85°C

SFDR @ +85°C

95

90

85

80

75

70

65

0

–1

–2

0

2000 4000 6000

8000 10,000 12,000 14,000 16,000

0

50

100

150

200

250

300

OUTPUT CODE

INPUT FREQUENCY (MHz)

Figure 18. AD9258-80 INL with f_IN= 9.7 MHz

Figure 15. AD9258-80 Single-Tone SNR/SFDR vs. Input Frequency (f_IN

)

with 2 V p-p Full Scale

105

0.50

SNR, CHANNEL B

SFDR, CHANNEL B

SNR, CHANNEL A

100

SFDR, CHANNEL A

0.25

0

95

90

85

80

75

–0.25

–0.50

0

25

30

35

40

45

50

55

60

65

70

75

80

2000 4000 6000

8000 10,000 12,000 14,000 16,000

SAMPLE RATE (MSPS)

OUTPUT CODE

Figure 16. AD9258-80 Single-Tone SNR/SFDR vs. Sample Rate (f_S)

with f_IN= 70.1 MHz

Figure 19. AD9258-80 DNL with f_IN= 9.7 MHz

Rev. A | Page 1ꢃ of 44

AD9258

0

–20

–40

–60

0

–20

–40

–60

105MSPS

2.4MHz @ –1dBFS

SNR = 77.5dB (78.5dBFS)

SFDR = 90dBc

200.3MHz @ –1dBFS

SNR = 74.0dB (75.0dBFS)

SFDR = 80dBc

SECOND HARMONIC

THIRD HARMONIC

SECOND HARMONIC

–80

–100

–120

–80

–100

–120

–140

0

10

20

30

40

50

0

10

20

30

40

50

FREQUENCY (MHz)

Figure 20. AD9258-105 Single-Tone FFT with f_IN= 2.4 MHz

Figure 23. AD9258-105 Single-Tone FFT with f_IN= 200.3 MHz

0

105MSPS

70.1MHz @ –1dBFS

–20 SNR = 76.8dB (77.8dBFS)

SFDR = 93.5dBc

70.1MHz @ –6dBFS

SNR = 72.0dB (78.0dBFS)

SFDR = 97dBc

–20

–40

–60

–40

–60

SECOND

HARMONIC

SECOND

HARMONIC

THIRD HARMONIC

–80

–100

–120

–80

–100

–120

–140

0

10

20

30

40

50

0

10

20

30

40

50

FREQUENCY (MHz)

Figure 21. AD9258-105 Single-Tone FFT with f_IN= 70.1 MHz

Figure 24. AD9258-105 Single-Tone FFT with f_IN= 70.1 MHz with Dither

Enabled

120

100

80

0

105MSPS

140.1MHz @ –1dBFS

SNR = 75.5dB (76.5dBFS)

SFDR = 85.0dBc

–20

–40

–60

SECOND HARMONIC

THIRD HARMONIC

60

–80

–100

–120

40

SNR (dBFS)

SFDR (dBc)

SNR (dBc)

20

0

SFDR (dBFS)

–140

–100 –90 –80 –70 –60 –50 –40 –30 –20 –10

0

10

20

30

40

50

INPUT AMPLITUDE (dBFS)

FREQUENCY (MHz)

Figure 25. AD9258-105 Single-Tone SNR/SFDR vs. Input Amplitude (A_IN

)

Figure 22. AD9258-105 Single-Tone FFT with f_IN= 140.1 MHz

with f_IN= 98.12 MHz

Rev. A | Page 19 of 44

AD9258

700,000

120

110

100

90

600,000

500,000

400,000

SNRFS (DITHER ON)

SNRFS (DITHER OFF)

SFDRFS (DITHER ON)

SFDRFS (DITHER OFF)

300,000

200,000

100,000

0

80

70

N – 3

N – 2

N – 1

N

N + 1

N + 2

N + 3

–100 –90 –80 –70 –60 –50 –40 –30 –20 –10

0

OUTPUT CODE

INPUT AMPLITUDE (dBFS)

Figure 29. AD9258-105 Grounded Input Histogram

Figure 26. AD9258-105 Single-Tone SNR/SFDR vs. Input Amplitude (A_IN

)

with f_IN= 30 MHz with and without Dither Enabled

2

100

DITHER ENABLED

DITHER DISABLED

SNR @ –40°C

SFDR @ –40°C

95

90

85

80

75

70

65

SNR @ +25°C

SFDR @ +25°C

SNR @ +85°C

SFDR @ +85°C

1

0

–1

–2

0

50

100

150

200

250

300

2000 4000 6000

8000 10,000 12,000 14,000 16,000

INPUT FREQUENCY (MHz)

OUTPUT CODE

Figure 27. AD9258-105 Single-Tone SNR/SFDR vs. Input Frequency (f_IN

)

Figure 30. AD9258-105 INL with f_IN= 9.7 MHz

with 2 V p-p Full Scale

105

0.50

SNR, CHANNEL B

SFDR, CHANNEL B

SNR, CHANNEL A

SFDR, CHANNEL A

100

95

0.25

0

90

85

80

75

–0.25

–0.50

0

25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105

2000 4000 6000

8000 10,000 12,000 14,000 16,000

SAMPLE RATE (MSPS)

OUTPUT CODE

Figure 28. AD9258-105 Single-Tone SNR/SFDR vs. Sample Rate (f_S)

with f_IN= 70.1 MHz

Figure 31. AD9258-105 DNL with f_IN= 9.7 MHz

Rev. A | Page 2± of 44

AD9258

0

125MSPS

2.4MHz @ –1dBFS

SNR = 76.6dB (77.6dBFS)

SFDR = 89dBc

140.1MHz @ –1dBFS

SNR = 75.5dB (76.5dBFS)

SFDR = 85.0dBc

–20

–40

–60

–40

–60

SECOND HARMONIC

THIRD HARMONIC

SECOND HARMONIC

–80

THIRD HARMONIC

–100

–120

–140

–100

–120

–140

0

10

20

30

40

50

60

0

10

20

30

40

50

60

FREQUENCY (MHz)

Figure 32. AD9258-125 Single-Tone FFT with f_IN= 2.4 MHz

Figure 35. AD9258-125 Single-Tone FFT with f_IN= 140.1 MHz

0

125MSPS

30.3MHz @ –1dBFS

SNR = 76.4dB (77.4dBFS)

SFDR = 91.2dBc

200.3MHz @ –1dBFS

SNR = 74.3dB (75.3dBFS)

SFDR = 81dBc

–20

–40

–60

–40

–60

THIRD HARMONIC

SECOND HARMONIC

THIRD HARMONIC

–80

–100

–120

–140

SECOND HARMONIC

–100

–120

–140

0

10

20

30

40

50

60

0

10

20

30

40

50

60

FREQUENCY (MHz)

Figure 33. AD9258-125 Single-Tone FFT with f_IN= 30.3 MHz

Figure 36. AD9258-125 Single-Tone FFT with f_IN= 200.3 MHz

0

125MSPS

220.1MHz @ –1dBFS

SNR = 74.0dB (75.0dBFS)

70.1MHz @ –1dBFS

SNR = 76.5dB (77.5dBFS)

–20

SFDR = 79.3dBc

SFDR = 88.0dBc

–40

THIRD HARMONIC

SECOND HARMONIC

–60

–80

–60

THIRD HARMONIC

SECOND HARMONIC

–80

–100

–120

–140

–100

–120

–140

0

10

20

30

40

50

60

0

10

20

30

40

50

60

FREQUENCY (MHz)

Figure 37. AD9258-125 Single-Tone FFT with f_IN= 220.1 MHz

Figure 34. AD9258-125 Single-Tone FFT with f_IN= 70.1 MHz

Rev. A | Page 21 of 44

AD9258

0

120

100

80

125MSPS

SFDR (dBFS)

SNR (dBFS)

70.1MHz @ –6dBFS

SNR = 71.6dB (77.6dBFS)

SFDR = 97dBc

–20

–40

–60

–80

60

SFDR (dBc)

SECOND HARMONIC

THIRD HARMONIC

40

20

0

–100

–120

–140

SNR (dBc)

0

10

20

30

40

50

60

–100 –90 –80 –70 –60 –50 –40 –30 –20 –10

0

FREQUENCY (MHz)

INPUT AMPLITUDE (dBFS)

Figure 38. AD9258-125 Single-Tone FFT with f_IN= 70.1 MHz @ −6 dBFS

with Dither Enabled

Figure 41. AD9258-125 Single-Tone SNR/SFDR vs. Input Amplitude (A_IN

)

with f_IN= 2.4 MHz

0

120

125MSPS

SFDR (dBFS)

–15 70.1MHz @ –23dBFS

SNR = 56.1dB (79.1dBFS)

100

SFDR = 67.7dBc

–30

–45

–60

SNR (dBFS)

80

THIRD HARMONIC

60

–75

–90

SECOND HARMONIC

SFDR (dBc)

40

–105

–120

–135

–150

SNR (dBc)

20

0

6

12

18

24

30

36

42

48

54

60

–100 –90 –80 –70 –60 –50 –40 –30 –20 –10

0

FREQUENCY (MHz)

INPUT AMPLITUDE (dBFS)

Figure 39. AD9258-125 Single-Tone FFT with f_IN= 70.1 MHz @ −23 dBFS

with Dither Disabled, 1M Sample

Figure 42. AD9258-125 Single-Tone SNR/SFDR vs. Input Amplitude (A_IN

)

with f_IN= 98.12 MHz

0

120

125MSPS

–15 70.1MHz @ –23dBFS

SNR = 55.4dB (78.4dBFS)

SFDR (DITHER ON)

SFDR = 86.2dBc

–30

–45

–60

110

100

–75

–90

SECOND HARMONIC

THIRD HARMONIC

SFDR (DITHER 0FF)

90

–105

–120

–135

–150

SNR (DITHER 0FF)

80

SNR (DITHER ON)

70

0

6

12

18

24

30

36

42

48

54

60

–100 –90 –80 –70 –60 –50 –40 –30 –20 –10

0

FREQUENCY (MHz)

INPUT AMPLITUDE (dBFS)

Figure 40. AD9258-125 Single-Tone FFT with f_IN= 70.1 MHz @ −23 dBFS

with Dither Enabled, 1M Sample

Figure 43. AD9258-125 Single-Tone SNR/SFDR vs. Input Amplitude (A_IN

)

with f_IN= 30 MHz with and without Dither Enabled

Rev. A | Page 22 of 44

AD9258

0

–20

100

95

90

85

80

75

70

65

SNR @ –40°C

SFDR @ –40°C

SNR @ +25°C

SFDR @ +25°C

SNR @ +85°C

SFDR @ +85°C

SFDR (dBc)

–40

IMD3 (dBc)

–60

–80

SFDR (dBFS)

IMD3 (dBFS)

–78

–100

–120

–90

–66

–54

–42

–30

–18

–6

0

50

100

150

200

250

300

INPUT AMPLITUDE (dBFS)

INPUT FREQUENCY (MHz)

Figure 47. AD9258-125 Two-Tone SFDR/IMD3 vs. Input Amplitude (A_IN

)

Figure 44. AD9258-125 Single-Tone SNR/SFDR vs. Input Frequency (f_IN

)

with f_IN1= 169.1 MHz, f_IN2= 172.1 MHz, f_S= 125 MSPS

with 2 V p-p Full Scale

0

95

90

125MSPS

29.1MHz @ –7dBFS

32.1MHz @ –7dBFS

SFDR = 88.8dBc (95.8dBFS)

–20

SFDR (dBc)

–40

85

–60

–80

80

75

70

65

SNR (dBFS)

–100

–120

–140

60

0

10

20

30

40

50

60

0

50

100

150

200

250

300

FREQUENCY (MHz)

INPUT FREQUENCY (MHz)

Figure 48. AD9258-125 Two-Tone FFT with f_IN1= 29.1 MHz and f_IN2= 32.1 MHz

Figure 45. AD9258-125 Single-Tone SNR/SFDR vs. Input Frequency (f_IN

)

with 1 V p-p Full Scale

0

125MSPS

169.1MHz @ –7dBFS

172.1MHz @ –7dBFS

0

–20

SFDR = 81.7dBc (88.7dBFS)

–20

–40

SFDR (dBc)

–40

–60

–80

–60

IMD3 (dBc)

–100

–120

–140

–80

–100

SFDR (dBFS)

IMD3 (dBFS)

–30

INPUT AMPLITUDE (dBFS)

0

10

20

30

40

50

60

–120

–90

FREQUENCY (MHz)

–78

–66

–54

–42

–18

–6

Figure 49. AD9258-125 Two-Tone FFT with f_IN1= 169.1 MHz and

_IN2= 172.1 MHz

f

Figure 46. AD9258-125 Two-Tone SFDR/IMD3 vs. Input Amplitude (A_IN

)

with f_IN1= 29.1 MHz, f_IN2= 32.1 MHz, f_S= 125 MSPS

Rev. A | Page 23 of 44

AD9258

100

95

90

85

80

0.50

SFDR (dBc), CHANNEL B

0.25

0

SFDR (dBc), CHANNEL A

SNR (dBFS), CHANNEL B

–0.25

–0.50

SNR (dBFS), CHANNEL A

75 85 95 105 115 125

SAMPLE RATE (MSPS)

75

25

35

45

55

65

0

2048

4096

6144

8192 10,240 12,288 14,336 16,384

OUTPUT CODE

Figure 50. AD9258-125 Single-Tone SNR/SFDR vs. Sample Rate (f_S)

with f_IN= 70.1 MHz

Figure 53. AD9258-125 DNL with f_IN= 9.7 MHz

100

90

700,000

SFDR (dBc)

SNR (dBFS)

0.72LSB rms

600,000

80

500,000

400,000

300,000

70

60

50

40

30

200,000

100,000

0

0.75 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20

N – 3

N – 2

N – 1

N

N + 1

N + 2

N + 3

INPUT COMMON-MODE VOLTAGE (V)

OUTPUT CODE

Figure 51. AD9258-125 Grounded Input Histogram

Figure 54. SNR/SFDR vs. Input Common Mode (VCM)

with f_IN= 30 MHz

2

DITHER ENABLED

DITHER DISABLED

1

0

–1

–2

0

2048

4096

6144

8192 10,240 12,288 14,336 16,384

OUTPUT CODE

Figure 52. AD9258-125 INL with f_IN= 9.7 MHz

Rev. A | Page 24 of 44

AD9258

EQUIVALENT CIRCUITS

AVDD

VIN

350Ω

SENSE

Figure 55. Equivalent Analog Input Circuit

Figure 60. Equivalent SENSE Circuit

AVDD

DRVDD

0.9V

26kΩ

10kΩ

350Ω

CLK–

CLK+

CSB

Figure 56. Equivalent Clock Input Circuit

Figure 61. Equivalent CSB Input Circuit

DRVDD

AVDD

PAD

VREF

6kΩ

Figure 57. Digital Output

Figure 62. Equivalent VREF Circuit

DRVDD

26kΩ

350Ω

PDWN

350Ω

SDIO/DCS

26kΩ

Figure 63. Equivalent PDWN Input Circuit

Figure 58. Equivalent SDIO/DCS Circuit

DRVDD

350Ω

SCLK/DFS

OR OEB

26kΩ

Figure 59. Equivalent SCLK/DFS or OEB Input Circuit

Rev. A | Page 2ꢀ of 44

AD9258

THEORY OF OPERATION

A small resistor in series with each input can help reduce the

peak transient current required from the output stage of the

driving source. A shunt capacitor can be placed across the

inputs to provide dynamic charging currents. This passive

network creates a low-pass filter at the ADC input; therefore,

the precise values are dependent on the application.

The AD9258 dual-core analog-to-digital converter (ADC)

design can be used for diversity reception of signals, in which the

ADCs are operating identically on the same carrier but from two

separate antennae. The ADCs can also be operated with inde-

pendent analog inputs. The user can sample any f_S/2 frequency

segment from dc to 200 MHz, using appropriate low-pass or

band-pass filtering at the ADC inputs with little loss in ADC

performance. Operation to 300 MHz analog input is permitted

but occurs at the expense of increased ADC noise and distortion.

In intermediate frequency (IF) undersampling applications, any

shunt capacitors should be reduced. In combination with the

driving source impedance, the shunt capacitors limit the input

bandwidth. Refer to the AN-742 Application Note, Frequency

Domain Response of Switched-Capacitor ADCs; the AN-827

Application Note, A Resonant Approach to Interfacing Amplifiers to

Switched-Capacitor ADCs; and the Analog Dialogue article,

“Transformer-Coupled Front-End for Wideband A/D Converters,”

for more information on this subject (refer to www.analog.com).

BIAS

In nondiversity applications, the AD9258 can be used as a base-

band or direct downconversion receiver, in which one ADC is

used for I input data, and the other is used for Q input data.

Synchronization capability is provided to allow synchronized

timing between multiple devices.

Programming and control of the AD9258 are accomplished

using a 3-wire SPI-compatible serial interface.

S

C

FB

C

ADC ARCHITECTURE

S

VIN+

The AD9258 architecture consists of a dual front-end sample-

and-hold circuit, followed by a pipelined, switched-capacitor

ADC. The quantized outputs from each stage are combined into

a final 14-bit result in the digital correction logic. The pipelined

architecture permits the first stage to operate on a new input

sample and the remaining stages to operate on the preceding

samples. Sampling occurs on the rising edge of the clock.

C

PAR1

C

PAR2

H

S

C

S

VIN–

C

FB

C

PAR1

PAR2

S

BIAS

Figure 64. Switched-Capacitor Input

Each stage of the pipeline, excluding the last, consists of a low

resolution flash ADC connected to a switched-capacitor digital-

to-analog converter (DAC) and an interstage residue amplifier

(MDAC). The MDAC magnifies the difference between the recon-

structed DAC output and the flash input for the next stage in

the pipeline. One bit of redundancy is used in each stage to

facilitate digital correction of flash errors. The last stage simply

consists of a flash ADC.

For best dynamic performance, the source impedances driving

VIN+ and VIN− should be matched, and the inputs should be

differentially balanced.

An internal differential reference buffer creates positive and

negative reference voltages that define the input span of the ADC

core. The span of the ADC core is set by this buffer to 2 × VREF.

Input Common Mode

The input stage of each channel contains a differential sampling

circuit that can be ac- or dc-coupled in differential or single-

ended modes. The output staging block aligns the data, corrects

errors, and passes the data to the output buffers. The output buffers

are powered from a separate supply, allowing digital output noise to

be separated from the analog core. During power-down, the

output buffers go into a high impedance state.

The analog inputs of the AD9258 are not internally dc biased.

In ac-coupled applications, the user must provide this bias

externally. Setting the device so that VCM = 0.5 × AVDD (or

0.9 V) is recommended for optimum performance, but the

device functions over a wider range with reasonable perfor-

mance (see Figure 54). An on-board common-mode voltage

reference is included in the design and is available from the

VCM pin. Optimum performance is achieved when the

common-mode voltage of the analog input is set by the VCM

pin voltage (typically 0.5 × AVDD). The VCM pin must be

decoupled to ground by a 0.1 μF capacitor, as described in the

Applications Information section.

ANALOG INPUT CONSIDERATIONS

The analog input to the AD9258 is a differential switched-

capacitor circuit that has been designed for optimum performance

while processing a differential input signal.

The clock signal alternatively switches the input between sample

mode and hold mode (see Figure 64). When the input is switched

into sample mode, the signal source must be capable of charging

the sample capacitors and settling within ½ of a clock cycle.

Rev. A | Page 2ꢁ of 44

AD9258

Common-Mode Voltage Servo

ADC is quantizing large-signal inputs, dithering converts these

tones to noise and produces a whiter noise floor.

In applications where there may be a voltage loss between the VCM

output of the AD9258 and the analog inputs, the common-mode

voltage servo can be enabled. When the inputs are ac-coupled and

a resistance of >100 Ω is placed between the VCM output and the

analog inputs, a significant voltage drop can occur and the

common-mode voltage servo should be enabled. Setting Bit 0 in

Register 0x0F to a logic high enables the VCM servo mode. In

this mode, the AD9258 monitors the common-mode input level

at the analog inputs and adjusts the VCM output level to keep

the common-mode input voltage at an optimal level. If both

channels are operational, Channel A is monitored. However,

if Channel A is in power-down or standby mode, then the

Channel B input is monitored.

Small-Signal FFT

For small-signal inputs, the front-end sampling circuit typically

contributes very little distortion, and, therefore, the SFDR is

likely to be limited by tones caused by DNL errors due to random

component mismatches. Therefore, for small-signal inputs (typi-

cally, those below −6 dBFS), dithering can significantly improve

SFDR by converting these DNL tones to white noise.

Static Linearity

Dithering also removes sharp local discontinuities in the INL

transfer function of the ADC and reduces the overall peak-to-

peak INL.

Dither

In receiver applications, utilizing dither helps to reduce DNL

errors that cause small-signal gain errors. Often this issue is

overcome by setting the input noise 5 dB to 10 dB above the

converter noise. By utilizing dither within the converter to correct

the DNL errors, the input noise requirement can be reduced.

The AD9258 has an optional dither mode that can be selected

for one or both channels. Dithering is the act of injecting a known

but random amount of white noise, commonly referred to as

dither, into the input of the ADC. Dithering has the effect of

improving the local linearity at various points along the ADC

transfer function. Dithering can significantly improve the SFDR

when quantizing small-signal inputs, typically when the input

level is below −6 dBFS.

Differential Input Configurations

Optimum performance is achieved while driving the AD9258

in a differential input configuration. For baseband applications,

the AD8138, ADA4937-2, and ADA4938-2 differential drivers

provide excellent performance and a flexible interface to the

ADC.

As shown in Figure 65, the dither that is added to the input of

the ADC through the dither DAC is precisely subtracted out

digitally to minimize SNR degradation. When dithering is

enabled, the dither DAC is driven by a pseudorandom number

generator (PN gen). In the AD9258, the dither DAC is precisely

calibrated to result in only a very small degradation in SNR and

the SINAD. The typical SNR and SINAD degradation values,

with dithering enabled, are only 1 dB and 0.8 dB, respectively.

The output common-mode voltage of the ADA4938-2 is easily

set with the VCM pin of the AD9258 (see Figure 66), and the

driver can be configured in a Sallen-Key filter topology to

provide band limiting of the input signal.

15pF

200Ω

33Ω

5pF

15Ω

AD9258

90Ω

VIN–

VIN+

AVDD

76.8Ω

VIN

DOUT

ADC CORE

AD9258

ADA4938-2

0.1µF

33Ω

15Ω

VCM

DITHER

DAC

120Ω

15pF

200Ω

Figure 66. Differential Input Configuration Using the ADA4938-2

PN GEN

DITHER ENABLE

For baseband applications in which SNR is a key parameter,

differential transformer coupling is the recommended input

configuration. An example is shown in Figure 67. To bias the

analog input, the VCM voltage can be connected to the center

tap of the secondary winding of the transformer.

Figure 65. Dither Block Diagram

Large-Signal FFT

In most cases, dithering does not improve SFDR for large-signal

inputs close to full-scale, for example with a −1 dBFS input. For

large-signal inputs, the SFDR is typically limited by front-end

sampling distortion, which dithering cannot improve. However,

even for such large-signal inputs, dithering may be useful for

certain applications because it makes the noise floor whiter.

As is common in pipeline ADCs, the AD9258 contains small

DNL errors caused by random component mis-matches that

produce spurs or tones that make the noise floor somewhat

randomly colored part-to-part. Although these tones are

typically at very low levels and do not limit SFDR when the

C2

R2

VIN+

R1

2V p-p

49.9Ω

C1

R1

AD9258

R2

VCM

VIN–

0.1µF

C2

Figure 67. Differential Transformer-Coupled Configuration

Rev. A | Page 2ꢂ of 44

AD9258

The signal characteristics must be considered when selecting

a transformer. Most RF transformers saturate at frequencies

below a few megahertz (MHz). Excessive signal power can also

cause core saturation, which leads to distortion.

network. At higher input frequencies, good performance can be

achieved by using a ferrite bead in series with a resistor and

removing the capacitors. However, these values are dependent

on the input signal and should be used only as a starting guide.

At input frequencies in the second Nyquist zone and above, the

noise performance of most amplifiers is not adequate to achieve

the true SNR performance of the AD9258. For applications in

which SNR is a key parameter, differential double balun coupling

is the recommended input configuration (see Figure 68). In this

configuration, the input is ac-coupled, and the CML is provided

to each input through a 33 Ω resistor. These resistors compensate

for losses in the input baluns to provide a 50 Ω impedance to

the driver.

Table 10. Example RC Network

Frequency

Range

(MHz)

R1 Series C1 Differential R2 Series C2 Shunt

(Ω Each) (pF) (Ω Each) (pF Each)

± to 1±±

33

ꢀ

1ꢀ

1±

ꢁꢁ

1ꢀ

1±

Remove

1±± to 2±± 1±

1±± to 3±± 1±¹

ꢀ

Remove

¹In this configuration, R1 is a ferrite bead with a value of 1± Ω @ 1±± MHz.

An alternative to using a transformer-coupled input at

frequencies in the second Nyquist zone is to use the AD8352

differential driver. An example is shown in Figure 69. See the

AD8352 data sheet for more information.

In the double balun and transformer configurations, the value of

the input capacitors and resistors is dependent on the input fre-

quency and source impedance and may need to be reduced or

removed. Table 10 displays recommended values to set the RC

C2

0.1µF

R1

R2

VIN+

2V p-p

33Ω

P

A

S

P

C1

R1

AD9258

0.1µF

VCM

VIN–

C2

Figure 68. Differential Double Balun Input Configuration

V

CC

0.1µF

0Ω

0.1µF

16

1

8, 13

11

0.1µF

ANALOG INPUT

R

VIN+

2

200Ω

C

AD9258

AD8352

10

R

G

C

D

3

4

5

200Ω

VCM

VIN–

14

0.1µF

ANALOG INPUT

0Ω

0.1µF

Figure 69. Differential Input Configuration Using the AD8352

Rev. A | Page 2ꢃ of 44

AD9258

If a resistor divider is connected externally to the chip, as shown

in Figure 71, the switch again sets to the SENSE pin. This puts

the reference amplifier in a noninverting mode with the VREF

output, defined as follows:

VOLTAGE REFERENCE

A stable and accurate voltage reference is built into the AD9258.

The input range can be adjusted by varying the reference voltage

applied to the AD9258, using either the internal reference or an

externally applied reference voltage. The input span of the ADC

tracks reference voltage changes linearly. The various reference

modes are summarized in the sections that follow. The Reference

Decoupling section describes the best practices for PCB layout

of the reference.

R2

R1

⎛

⎝

⎞

⎟

⎠

VREF = 0.5× 1+

⎜

The input range of the ADC always equals twice the voltage at

the reference (VREF) pin for either an internal or an external

reference.

Internal Reference Connection

VIN+A/VIN+B

VIN–A/VIN–B

A comparator within the AD9258 detects the potential at the

SENSE pin and configures the reference into four possible modes,

which are summarized in Table 11. If SENSE is grounded, the

reference amplifier switch is connected to the internal resistor

divider (see Figure 70), setting VREF to 1.0 V for a 2.0 V p-p full-

scale input. In this mode, with SENSE grounded, the full scale can

also be adjusted through the SPI port by adjusting Bit 6 and Bit 7

of Register 0x18. These bits can be used to change the full scale

to 1.25 V p-p, 1.5 V p-p, 1.75 V p-p, or to the default of 2.0 V p-p,

as shown in Table 17.

ADC

CORE

VREF

1.0µF

0.1µF

R2

SELECT

LOGIC

SENSE

0.5V

R1

Connecting the SENSE pin to the VREF pin switches the reference

amplifier output to the SENSE pin, completing the loop and pro-

viding a 0.5 V reference output for a 1 V p-p full-scale input.

AD9258

Figure 71. Programmable Reference Configuration

VIN+A/VIN+B

VIN–A/VIN–B

If the internal reference of the AD9258 is used to drive multiple

converters to improve gain matching, the loading of the reference

by the other converters must be considered. Figure 72 shows

how the internal reference voltage is affected by loading.

0

ADC

CORE

VREF

–0.5

1.0µF

0.1µF

SELECT

LOGIC

VREF = 0.5V

–1.0

SENSE

VREF = 1V

0.5V

–1.5

AD9258

–2.0

Figure 70. Internal Reference Configuration

–2.5

–3.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

LOAD CURRENT (mA)

Figure 72. Reference Voltage Accuracy vs. Load Current

Table 11. Reference Configuration Summary

Selected Mode

SENSE Voltage

Resulting VREF (V)

Resulting Differential Span (V p-p)

External Reference

Internal Fixed Reference

Programmable Reference

AVDD

VREF

±.2 V to VREF

N/A

±.ꢀ

2 × external reference

1.±

2 × VREF

R2

R1

⎛

⎞

⎟

(see Figure ꢂ1)

±.ꢀ × 1+

⎜

⎝

⎠

Internal Fixed Reference

AGND to ±.2 V

1.±

2.±

Rev. A | Page 29 of 44

AD9258

External Reference Operation

The RF balun configuration is recommended for clock frequencies

between 125 MHz and 625 MHz, and the RF transformer is recom-

mended for clock frequencies from 10 MHz to 200 MHz. The

back-to-back Schottky diodes across the transformer/balun

secondary limit clock excursions into the AD9258 to

approximately 0.8 V p-p differential.

The use of an external reference may be necessary to enhance

the gain accuracy of the ADC or improve thermal drift charac-

teristics. Figure 73 shows the typical drift characteristics of the

internal reference in 1.0 V mode.

When the SENSE pin is tied to AVDD, the internal reference is

disabled, allowing the use of an external reference. An internal

reference buffer loads the external reference with an equivalent

6 kΩ load (see Figure 62). The internal buffer generates the positive

and negative full-scale references for the ADC core. Therefore,

the external reference must be limited to a maximum of 1.0 V.

2.0

This limit helps prevent the large voltage swings of the clock

from feeding through to other portions of the AD9258 while

preserving the fast rise and fall times of the signal that are critical

to a low jitter performance.

®

Mini-Circuits

ADC

ADT1-1WT, 1:1Z

AD9258

0.1µF

XFMR

CLOCK

INPUT

1.5

CLK+

CLK–

100Ω

VREF = 1.0V

1.0

50Ω

0.1µF

SCHOTTKY

DIODES:

HSMS2822

0.5

0

0.1µF

Figure 75. Transformer-Coupled Differential Clock (Up to 200 MHz)

–0.5

–1.0

ADC

AD9258

1nF

50Ω

1nF

0.1µF

CLOCK

INPUT

CLK+

–1.5

–2.0

CLK–

–40

–20

0

20

40

60

80

TEMPERATURE (°C)

SCHOTTKY

DIODES:

HSMS2822

Figure 73. Typical VREF Drift

Figure 76. Balun-Coupled Differential Clock (Up to 625 MHz)

CLOCK INPUT CONSIDERATIONS

If a low jitter clock source is not available, another option is to

ac couple a differential PECL signal to the sample clock input

pins, as shown in Figure 77. The AD9510/AD9511/AD9512/

AD9513/AD9514/AD9515/AD9516/AD9517/AD9518 clock

drivers offer excellent jitter performance.

For optimum performance, the AD9258 sample clock inputs,

CLK+ and CLK−, should be clocked with a differential signal.

The signal is typically ac-coupled into the CLK+ and CLK− pins

via a transformer or capacitors. These pins are biased internally

(see Figure 74) and require no external bias. If the inputs are

floated, the CLK− pin is pulled low to prevent spurious clocking.

AVDD

0.1µF

CLOCK

INPUT

CLK+

ADC

AD9258

AD951x

PECL DRIVER

100Ω

0.9V

0.1µF

CLOCK

INPUT

CLK–

CLK+

CLK–

240Ω

50kΩ

4pF

Figure 77. Differential PECL Sample Clock (Up to 625 MHz)

A third option is to ac couple a differential LVDS signal to the

sample clock input pins, as shown in Figure 78. The AD9510/

AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517/

AD9518 clock drivers offer excellent jitter performance.

Figure 74. Equivalent Clock Input Circuit

Clock Input Options

The AD9258 has a very flexible clock input structure. Clock input

can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of

the type of signal being used, clock source jitter is of the most

concern, as described in the Jitter Considerations section.

0.1µF

CLOCK

INPUT

CLK+

ADC

AD9258

AD951x

LVDS DRIVER

100Ω

0.1µF

Figure 75 and Figure 76 show two preferred methods for clocking

the AD9258 (at clock rates up to 625 MHz). A low jitter clock

source is converted from a single-ended signal to a differential

signal using either an RF balun or an RF transformer.

0.1µF

CLOCK

INPUT

CLK–

50kΩ

Figure 78. Differential LVDS Sample Clock (Up to 625 MHz)

Rev. A | Page 3± of 44

AD9258

In some applications, it may be acceptable to drive the sample

clock inputs with a single-ended CMOS signal. In such applica-

tions, the CLK+ pin should be driven directly from a CMOS gate,

and the CLK− pin should be bypassed to ground with a 0.1 ꢀF

capacitor (see Figure 79).

Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality

of the clock input. For inputs near full scale, the degradation in

SNR from the low frequency SNR (SNR_LF) at a given input

frequency (f_INPUT) due to jitter (t_JRMS) can be calculated by

SNR_HF= −10 log[(2π × f_INPUT× t_JRMS)²+ 10 ^{(−SNR /10)}

]

LF

V

CC

OPTIONAL

100Ω

0.1µF

1

0.1µF

1kΩ

AD951x

CMOS DRIVER

In the equation, the rms aperture jitter represents the clock input

jitter specification. IF undersampling applications are particularly

sensitive to jitter, as illustrated in Figure 80. The measured curve in

Figure 80 was taken using an ADC clock source with approxi-

mately 65 fs of jitter, which combines with the 70 fs of jitter

inherent in the AD9258 to produce the result shown.

80

CLOCK

INPUT

CLK+

ADC

AD9258

50Ω

CLK–

0.1µF

1

50Ω RESISTOR IS OPTIONAL.

Figure 79. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)

0.05ps

Input Clock Divider

75

The AD9258 contains an input clock divider with the ability to

divide the input clock by integer values between 1 and 8. For

divide ratios of 1, 2, or 4, the duty cycle stabilizer (DCS) is

optional. For other divide ratios, divide by 3, 5, 6, 7, and 8, the

duty cycle stabilizer must be enabled for proper part operation.

MEASURED

70

0.20ps

65

0.50ps

60

55

50

The AD9258 clock divider can be synchronized using the external

SYNC input. Bit 1 and Bit 2 of Register 0x100 allow the clock

divider to be resynchronized on every SYNC signal or only on

the first SYNC signal after the register is written. A valid SYNC

causes the clock divider to reset to its initial state. This synchro-

nization feature allows multiple parts to have their clock dividers

aligned to guarantee simultaneous input sampling.

1.00ps

1.50ps

1

10

100

1k

INPUT FREQUENCY (MHz)

Figure 80. SNR vs. Input Frequency and Jitter

The clock input should be treated as an analog signal in cases in

which aperture jitter may affect the dynamic range of the AD9258.

Power supplies for clock drivers should be separated from the

ADC output driver supplies to avoid modulating the clock signal

with digital noise. Low jitter, crystal-controlled oscillators make

the best clock sources. If the clock is generated from another type of

source (by gating, dividing, or another method), it should be

retimed by the original clock at the last step.

Clock Duty Cycle

Typical high speed ADCs use both clock edges to generate

a variety of internal timing signals and, as a result, may be

sensitive to clock duty cycle. The AD9258 requires a tight

tolerance on the clock duty cycle to maintain dynamic

performance characteristics.

The AD9258 contains a duty cycle stabilizer (DCS) that retimes

the nonsampling (falling) edge, providing an internal clock signal

with a nominal 50% duty cycle. This allows the user to provide

a wide range of clock input duty cycles without affecting the perfor-

mance of the AD9258. Noise and distortion performance are

nearly flat for a wide range of duty cycles with the DCS enabled.

Refer to the AN-501 Application Note and the AN-756 Application

Note (visit www.analog.com) for more information about jitter

performance as it relates to ADCs.

CHANNEL/CHIP SYNCHRONIZATION

Jitter in the rising edge of the input is still of paramount concern

and is not easily reduced by the internal stabilization circuit. The

duty cycle control loop does not function for clock rates of less

than 20 MHz, nominally. The loop has a time constant associated

with it that must be considered in applications in which the clock

rate can change dynamically. A wait time of 1.5 μs to 5 μs is

required after a dynamic clock frequency increase or decrease

before the DCS loop is relocked to the input signal. During the

time period that the loop is not locked, the DCS loop is bypassed,

and internal device timing is dependent on the duty cycle of the

input clock signal. In such applications, it may be appropriate to

disable the duty cycle stabilizer. In all other applications, enabling

the DCS circuit is recommended to maximize ac performance.

The AD9258 has a SYNC input that offers the user flexible

synchronization options for synchronizing the clock divider.

The clock divider sync feature is useful for guaranteeing synchro-

nized sample clocks across multiple ADCs. The input clock

divider can be enabled to synchronize on a single occurrence of

the SYNC signal or on every occurrence.

The SYNC input is internally synchronized to the sample clock;

however, to ensure that there is no timing uncertainty between

multiple parts, the SYNC input signal should be externally

synchronized to the input clock signal, meeting the setup and

hold times shown in Table 5. The SYNC input should be driven

using a single-ended CMOS-type signal.

Rev. A | Page 31 of 44

AD9258

1.0

0.25

POWER DISSIPATION AND STANDBY MODE

I

AVDD

As shown in Figure 81, the power dissipated by the AD9258

varies with its sample rate. In CMOS output mode, the digital

power dissipation is determined primarily by the strength of the

digital drivers and the load on each output bit.

0.8

0.6

0.4

0.2

0

0.20

0.15

0.10

0.05

0

TOTAL POWER

The maximum DRVDD current (IDRVDD) can be calculated as

IDRVDD = VDRVDD × C_LOAD× f_CLK× N

where N is the number of output bits (28 plus two DCO

outputs, in the case of the AD9258).

I

DRVDD

This maximum current occurs when every output bit switches on

every clock cycle, that is, a full-scale square wave at the Nyquist

frequency of f_CLK/2. In practice, the DRVDD current is

established by the average number of output bits switching,

which is determined by the sample rate and the characteristics

of the analog input signal.

25

35

45

55

65

75

ENCODE FREQUENCY (MSPS)

Figure 83. AD9258-80 Power and Current vs. Encode Frequency (LVDS

Output Mode)

By asserting PDWN (either through the SPI port or by asserting

the PDWN pin high), the AD9258 is placed in power-down

mode. In this state, the ADC typically dissipates 2.5 mW.

During power-down, the output drivers are placed in a high

impedance state. Asserting the PDWN pin low returns the

AD9258 to its normal operating mode.

Reducing the capacitive load presented to the output drivers

reduces digital power consumption. The data in Figure 81 was

taken in LVDS output mode, using the same operating conditions

as those used for the Typical Performance Characteristics section.

1.25

0.5

Low power dissipation in power-down mode is achieved by

shutting down the reference, reference buffer, biasing networks,

and clock. Internal capacitors are discharged when entering power-

down mode and then must be recharged when returning to normal

operation.

1.00

0.75

0.50

0.25

0

0.4

0.3

0.2

0.1

0

IAVDD

TOTAL POWER

When using the SPI port interface, the user can place the ADC

in power-down mode or standby mode. Standby mode allows

the user to keep the internal reference circuitry powered when

faster wake-up times are required.

IDRVDD

DIGITAL OUTPUTS

The AD9258 output drivers can be configured to interface with

1.8 V CMOS logic families. The AD9258 can also be configured

for LVDS outputs (standard ANSI or reduced output swing mode),

using a DRVDD supply voltage of 1.8 V.

25

50

75

100

125

ENCODE FREQUENCY (MHz)

Figure 81. AD9258-125 Power and Current vs. Encode Frequency (LVDS

Output Mode)

1.0

0.5

In CMOS output mode, the output drivers are sized to provide

sufficient output current to drive a wide variety of logic families.

However, large drive currents tend to cause current glitches on

the supplies that may affect converter performance.

0.8

0.6

0.4

0.2

0

0.4

0.3

0.2

0.1

0

TOTAL POWER

Applications requiring the ADC to drive large capacitive loads

or large fanouts may require external buffers or latches.

The default output mode is CMOS, with each channel output

on separate busses as shown in Figure 2. The output can also be

configured for interleaved CMOS via the SPI port. In interleaved

CMOS mode, the data for both channels is output through the

Channel A output bits, and the Channel B output is placed into

high impedance mode. The timing diagram for interleaved CMOS

output mode is shown in Figure 3.

I

AVDD

I

DRVDD

25

35

45

55

65

75

85

95

105

ENCODE FREQUENCY (MSPS)

Figure 82. AD9258-105 Power and Current vs. Encode Frequency (LVDS

Output Mode)

The output data format can be selected for either offset binary

or twos complement by setting the SCLK/DFS pin when operating

in the external pin mode (see Table 12).

Rev. A | Page 32 of 44

AD9258

As detailed in the AN-877 Application Note, Interfacing to High

Speed ADCs via SPI, the data format can be selected for offset

binary, twos complement, or gray code when using the SPI control.

TIMING

The AD9258 provides latched data with a pipeline delay of

12 clock cycles. Data outputs are available one propagation

delay (t_PD) after the rising edge of the clock signal.

Table 12. SCLK/DFS Mode Selection (External Pin Mode)

The length of the output data lines and loads placed on them

should be minimized to reduce transients within the AD9258.

These transients can degrade converter dynamic performance.

Voltage at Pin

SCLK/DFS

SDIO/DCS

AGND

Offset binary

(default)

Twos complement

DCS disabled

AVDD

DCS enabled

(default)

The lowest typical conversion rate of the AD9258 is 10 MSPS.

At clock rates below 10 MSPS, dynamic performance can degrade.

Data Clock Output (DCO)

Digital Output Enable Function (OEB)

The AD9258 provides two data clock output (DCO) signals

intended for capturing the data in an external register. In CMOS

output mode, the data outputs are valid on the rising edge of DCO,

unless the DCO clock polarity has been changed via the SPI. In

LVDS output mode, the DCO and data output switching edges

are closely aligned. Additional delay can be added to the DCO

output using SPI Register 0x17 to increase the data setup time.

In this case, the Channel A output data is valid on the rising

edge of DCO, and the Channel B output data is valid on the

falling edge of DCO. See Figure 2, Figure 3, and Figure 4 for

a graphical timing description of the output modes.

The AD9258 has a flexible three-state ability for the digital output

pins. The three-state mode is enabled using the OEB pin or

through the SPI. If the OEB pin is low, the output data drivers and

DCOs are enabled. If the OEB pin is high, the output data drivers

and DCOs are placed in a high impedance state. This OEB

function is not intended for rapid access to the data bus. Note

that OEB is referenced to the digital output driver supply

(DRVDD) and should not exceed that supply voltage.

When using the SPI, the data outputs and DCO of each channel

can be independently three-stated by using the output enable

bar bit (Bit 4) in Register 0x14.

Table 13. Output Data Format

Input (V)

Condition (V)

< −VREF − ±.ꢀ LSB

= −VREF

Offset Binary Output Mode

±± ±±±± ±±±± ±±±±

1± ±±±± ±±±± ±±±±

11 1111 1111 1111

Twos Complement Mode

1± ±±±± ±±±± ±±±±

±± ±±±± ±±±± ±±±±

±1 1111 1111 1111

OR

1

±

VIN+ − VIN−

= ±

= +VREF − 1.± LSB

> +VREF − ±.ꢀ LSB

1

Rev. A | Page 33 of 44

AD9258

BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST

The AD9258 includes built-in test features designed to enable

verification of the integrity of each channel as well as facilitate

board level debugging. A BIST (built-in self-test) feature is included

that verifies the integrity of the digital datapath of the AD9258.

Various output test options are also provided to place predictable

values on the outputs of the AD9258.

The outputs are not disconnected during this test, so the PN

sequence can be observed as it runs. The PN sequence can be

continued from its last value or reset from the beginning, based

on the value programmed in Register 0x0E, Bit 2. The BIST

signature result varies based on the channel configuration.

OUTPUT TEST MODES

BUILT-IN SELF-TEST (BIST)

The output test options are shown in Table 17. When an output

test mode is enabled, the analog section of the ADC is discon-

nected from the digital back end blocks, and the test pattern is run

through the output formatting block. Some of the test patterns are

subject to output formatting, and some are not. The seed value for

the PN sequence tests can be forced if the PN reset bits are used

to hold the generator in reset mode by setting Bit 4 or Bit 5 of

Register 0x0D. These tests can be performed with or without

an analog signal (if present, the analog signal is ignored), but

they do require an encode clock. For more information, see the

AN-877 Application Note, Interfacing to High Speed ADCs via SPI.

The BIST is a thorough test of the digital portion of the selected

AD9258 signal path. When enabled, the test runs from an internal

pseudorandom noise (PN) source through the digital datapath

starting at the ADC block output. The BIST sequence runs for

512 cycles and stops. The BIST signature value for Channel A or

Channel B is placed in Register 0x24 and Register 0x25. If one

channel is chosen, its BIST signature is written to the two registers.

If both channels are chosen, the results from Channel A are placed

in the BIST signature registers.

Rev. A | Page 34 of 44

AD9258

SERIAL PORT INTERFACE (SPI)

The AD9258 serial port interface (SPI) allows the user to

configure the converter for specific functions or operations

through a structured register space provided inside the ADC.

The SPI gives the user added flexibility and customization,

depending on the application. Addresses are accessed via the

serial port and can be written to or read from via the port.

Memory is organized into bytes that can be further divided into

fields, which are documented in the Memory Map section. For

detailed operational information, see the AN-877 Application

Note, Interfacing to High Speed ADCs via SPI.

The falling edge of the CSB, in conjunction with the rising edge

of the SCLK, determines the start of the framing. An example of

the serial timing and its definitions can be found in Figure 84

and Table 5.

Other modes involving the CSB are available. When the CSB is

held low indefinitely, which permanently enables the device,

this is called streaming. The CSB can stall high between bytes to

allow for additional external timing. When CSB is tied high, SPI

functions are placed in high impedance mode. This mode turns

on any SPI pin secondary functions.

CONFIGURATION USING THE SPI

During an instruction phase, a 16-bit instruction is transmitted.

Data follows the instruction phase, and its length is determined

by the W0 and W1 bits.

Three pins define the SPI of this ADC: the SCLK/DFS pin, the

SDIO/DCS pin, and the CSB pin (see Table 14). The SCLK/DFS

(a serial clock) is used to synchronize the read and write data

presented from and to the ADC. The SDIO/DCS (serial data

input/output) is a dual-purpose pin that allows data to be sent

to and read from the internal ADC memory map registers. The

CSB (chip select bar) is an active-low control that enables or

disables the read and write cycles.

In addition to word length, the instruction phase determines

whether the serial frame is a read or write operation, allowing

the serial port to be used both to program the chip and to read

the contents of the on-chip memory. The first bit of the first byte in

a multibyte serial data transfer frame indicates whether a read

command or a write command is issued. If the instruction is a

readback operation, performing a readback causes the serial

data input/output (SDIO) pin to change direction from an input to

an output at the appropriate point in the serial frame.

Table 14. Serial Port Interface Pins

Function

SCLK Serial Clock. The serial shift clock input, which is used to

synchronize serial interface reads and writes.

SDIO Serial Data Input/Output. A dual-purpose pin that

typically serves as an input or an output, depending on

the instruction being sent and the relative position in the

timing frame.

All data is composed of 8-bit words. Data can be sent in MSB-

first mode or in LSB-first mode. MSB first is the default on

power-up and can be changed via the SPI port configuration

register. For more information about this and other features,

see the AN-877 Application Note, Interfacing to High Speed

ADCs via SPI.

CSB

Chip Select Bar. An active-low control that gates the read

and write cycles.

t_HIGH

t_DS

t_CLK

t_H

t_S

t_DH

t_LOW

CSB

SCLK DON’T CARE

SDIO DON’T CARE

DON’T CARE

R/W

W1

W0

A12

A11

A10

A9

A8

A7

D5

D4

D3

D2

D1

D0

DON’T CARE

Figure 84. Serial Port Interface Timing Diagram

Rev. A | Page 3ꢀ of 44

AD9258

When the device is in SPI mode, the PDWN and OEB pins

remain active. For SPI control of output enable and power-down,

the OEB and PDWN pins should be set to their default states.

HARDWARE INTERFACE

The pins described in Table 14 comprise the physical interface

between the user programming device and the serial port of the

AD9258. The SCLK pin and the CSB pin function as inputs

when using the SPI. The SDIO pin is bidirectional, functioning

as an input during write phases and as an output during

readback.

Table 15. Mode Selection

External

Voltage

Configuration

SDIO/DCS

AVDD (default) Duty cycle stabilizer enabled

AGND

AVDD

Duty cycle stabilizer disabled

Twos complement enabled

The SPI is flexible enough to be controlled by either FPGAs or

microcontrollers. One method for SPI configuration is

described in detail in the AN-812 Application Note, Micro-

controller-Based Serial Port Interface (SPI) Boot Circuit.

SCLK/DFS

OEB

AGND (default) Offset binary enabled

AVDD Outputs in high impedance

AGND (default) Outputs enabled

AVDD

Chip in power-down or

standby

AGND (default) Normal operation

The SPI port should not be active during periods when the full

dynamic performance of the converter is required. Because the

SCLK signal, the CSB signal, and the SDIO signal are typically

asynchronous to the ADC clock, noise from these signals can

degrade converter performance. If the on-board SPI bus is used for

other devices, it may be necessary to provide buffers between

this bus and the AD9258 to prevent these signals from transi-

tioning at the converter inputs during critical sampling periods.

PDWN

SPI ACCESSIBLE FEATURES

Table 16 provides a brief description of the general features that

are accessible via the SPI. These features are described in detail

in the AN-877 Application Note, Interfacing to High Speed ADCs

via SPI. The AD9258 part-specific features are described in detail

following Table 17, the external memory map register table.

Some pins serve a dual function when the SPI is not being used.

When the pins are strapped to AVDD or ground during device

power-on, they are associated with a specific function. The

Digital Outputs section describes the strappable functions

supported on the AD9258.

Table 16. Features Accessible Using the SPI

Feature Name

Description

Mode

Allows the user to set either power-down mode

or standby mode

Allows the user to access the DCS, set the

clock divider, set the clock divider phase, and

enable the sync

Allows the user to digitally adjust the

converter offset

Allows the user to set test modes to have

known data on output bits

Allows the user to set the output mode

including LVDS

Allows the user to set the output clock polarity

Allows the user to vary the DCO delay

CONFIGURATION WITHOUT THE SPI

Clock

In applications that do not interface to the SPI control registers,

the SDIO/DCS pin, the SCLK/DFS pin, the OEB pin, and the

PDWN pin serve as standalone CMOS-compatible control pins.

When the device is powered up, it is assumed that the user intends

to use the pins as static control lines for the duty cycle stabilizer,

output data format, output enable, and power-down feature

control. In this mode, the CSB chip select bar should be con-

nected to AVDD, which disables the serial port interface.

Offset

Test I/O

Output Mode

Output Phase

Output Delay

VREF

Allows the user to set the reference voltage

Rev. A | Page 3ꢁ of 44

AD9258

MEMORY MAP

READING THE MEMORY MAP REGISTER TABLE

Logic Levels

An explanation of logic level terminology follows:

Each row in the memory map register table has eight bit locations.

The memory map is roughly divided into four sections: the chip

configuration registers (Address 0x00 to Address 0x02); the

channel index and transfer registers (Address 0x05 and

Address 0xFF); the ADC functions registers, including setup,

control, and test (Address 0x08 to Address 0x30); and the digital

feature control register (Address 0x100).

•

“Bit is set” is synonymous with “bit is set to Logic 1” or

“writing Logic 1 for the bit.”

•

“Clear a bit” is synonymous with “bit is set to Logic 0” or

“writing Logic 0 for the bit.”

Transfer Register Map

Address 0x08 through Address 0x18 and Address 0x30 are

shadowed. Writes to these addresses do not affect part operation

until a transfer command is issued by writing 0x01 to Address

0xFF, setting the transfer bit. This allows these registers to be

updated internally and simultaneously when the transfer bit is

set. The internal update takes place when the transfer bit is set,

and the bit autoclears.

The memory map register table (see Table 17) lists the default

hexadecimal value for each hexadecimal address shown. The

column with the heading Bit 7 (MSB) is the start of the default

hexadecimal value given. For example, Address 0x18, the VREF

select register, has a hexadecimal default value of 0xC0. This means

that Bit 7 = 1, Bit 6 = 1, and the remaining bits are 0s. This setting

is the default reference selection setting. The default value uses a

2.0 V p-p reference. For more information on this function and

others, see the AN-877 Application Note, Interfacing to High Speed

ADCs via SPI. This application note details the functions con-

trolled by Register 0x00 to Register 0xFF. The remaining

register, Register 0x100 is documented in the Memory Map

Register Table section.

Channel-Specific Registers

Some channel setup functions, such as the signal monitor

thresholds, can be programmed differently for each channel. In

these cases, channel address locations are internally duplicated for

each channel. These registers and bits are designated in Table 17

as local. These local registers and bits can be accessed by setting

the appropriate Channel A or Channel B bits in Register 0x05.

If both bits are set, the subsequent write affects the registers of

both channels. In a read cycle, only Channel A or Channel B

should be set to read one of the two registers. If both bits are set

during an SPI read cycle, the part returns the value for Channel A.

Registers and bits designated as global in Table 17 affect the entire

part or the channel features for which independent settings are not

allowed between channels. The settings in Register 0x05 do not

affect the global registers and bits.

Open Locations

All address and bit locations that are not included in Table 17

are not currently supported for this device. Unused bits of a

valid address location should be written with 0s. Writing to these

locations is required only when part of an address location is

open (for example, Address 0x18). If the entire address location

is open (for example, Address 0x13), this address location should

not be written.

Default Values

After the AD9258 is reset, critical registers are loaded with

default values. The default values for the registers are given in

the memory map register table, Table 17.

Rev. A | Page 3ꢂ of 44

AD9258

MEMORY MAP REGISTER TABLE

All address and bit locations that are not included in Table 17 are not currently supported for this device.

Table 17. Memory Map Registers

Default Default

Address Register

(Hex) Name

Chip Configuration Registers

Bit 7

(MSB)

Bit 0

(LSB)

Value

(Hex)

Notes/

Comments

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

±x±±

SPI port

configuration

(global)

±

LSB first

Soft reset

1

Soft reset

LSB first

±

±x1ꢃ

The nibbles

are mirrored

so LSB-first

mode or MSB-

first mode

registers

correctly,

regardless of

shift mode

±x±1

±x±2

Chip ID

(global)

ꢃ-bit chip ID[ꢂ:±]

(AD92ꢀꢃ = ±x33)

(default)

±x33

Read only

Chip grade

(global)

Open

Speed grade ID

±1 = 12ꢀ MSPS

Open

Speed grade

ID used to

differentiate

devices; read

only

1± = 1±ꢀ MSPS

11 = ꢃ± MSPS

Channel Index and Transfer Registers

±x±ꢀ

Channel

index

Open

Data

Channel

B

Data

Channel A

(default)

±x±3

Bits are set

to determine

which device

on the chip

receives the

next write

(default)

command;

applies to local

registers only

±xFF

Transfer

Open

Transfer

±x±±

±xꢃ±

Synchronously

transfers data

from the

master shift

register to the

slave

ADC Functions

±x±ꢃ

Power modes

(local)

1

External

power-

down pin

function

(local)

± = pdwn

1 = stndby

Open

Internal power-down

mode (local)

±± = normal operation

±1 = full power-down

1± = standby

Determines

various generic

modes of chip

operation

11 = normal operation

±x±9

±x±B

Global clock

(global)

Open

Duty cycle

stabilizer

(default)

±x±1

±x±±

Clock divide

(global)

Open

Clock divide ratio

±±± = divide by 1

±±1 = divide by 2

±1± = divide by 3

±11 = divide by 4

1±± = divide by ꢀ

1±1 = divide by ꢁ

11± = divide by ꢂ

111 = divide by ꢃ

Clock divide

values other

than ±±±

automatically

cause the duty

cycle stabilizer

to become

active

±x±D

Test mode

(local)

Open

Reset PN

long gen

Reset PN

short gen

Open

Output test mode

±±± = off (default)

±±1 = midscale short

±1± = positive FS

±11 = negative FS

±x±±

When this

register is set,

the test data

is placed on

the output

pins in place of

normal data

1±± = alternating checkerboard

1±1 = PN long sequence

11± = PN short sequence

111 = one/zero word toggle

Rev. A | Page 3ꢃ of 44

AD9258

Default Default

Address Register

Bit 7

(MSB)

Bit 0

(LSB)

Value

(Hex)

Notes/

Comments

(Hex)

Name

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

±x±E

BIST enable

(global)

Open

Reset BIST

sequence

Open

BIST

enable

±x±4

±x±F

ADC input

(global)

Open

Common-

mode

±x±±

servo

enable

±x1±

±x14

Offset adjust

(local)

Offset adjust in LSBs from +12ꢂ to −12ꢃ

(twos complement format)

±x±±

Output mode

Drive

Output

type

± = CMOS

1 = LVDS

(global)

CMOS

Output

enable

bar

Open

Output

invert

(local)

Output format

Configures the

outputs and

the format of

the data

strength

± = ANSI

LVDS;

output

Interleave

enable

(global)

(must be

written

low)

±± = offset binary

±1 = twos complement

±1 = gray code

11 = offset binary

(local)

1 =

(global)

reduced

swing

LVDS

(global)

±x1ꢁ

Clock phase

control

(global)

Invert

DCO clock

Open

Input clock divider phase adjust

±±± = no delay

±x±±

Allows

selection of

clock delays

into the input

clock divider

±±1 = 1 input clock cycle

±1± = 2 input clock cycles

±11 = 3 input clock cycles

1±± = 4 input clock cycles

1±1 = ꢀ input clock cycles

11± = ꢁ input clock cycles

111 = ꢂ input clock cycles

±x1ꢂ

DCO output

Open

DCO clock delay

±x±±

delay (global)

(delay = 2ꢀ±± ps × register value/31)

±±±±± = ± ps

±±±±1 = ꢃ1 ps

±±±1± = 1ꢁ1 ps

…

1111± = 2419 ps

11111 = 2ꢀ±± ps

±x1ꢃ

VREF select

(global)

Reference voltage

Open

±xC±

selection

±± = 1.2ꢀ V p-p

±1 = 1.ꢀ V p-p

1± = 1.ꢂꢀ V p-p

11 = 2.± V p-p (default)

±x24

±x2ꢀ

±x3±

BIST signature

LSB (local)

BIST signature[ꢂ:±]

BIST signature[1ꢀ:ꢃ]

±x±±

Read only

BIST signature

MSB (local)

Dither enable

(local)

Open

Dither

Enable

Open

Digital Feature Control

±x1±±

Sync control

(global)

Open

Clock

divider

sync

Master

sync

enable

±x±±

divider

next sync

only

enable

Rev. A | Page 39 of 44

AD9258

ignore the rest. The clock divider sync enable bit (Address 0x100,

Bit 1) resets after it syncs.

MEMORY MAP REGISTER DESCRIPTIONS

For additional information about functions controlled in

Register 0x00 to Register 0xFF, see the AN-877 Application

Note, Interfacing to High Speed ADCs via SPI.

Bit 1—Clock Divider Sync Enable

Bit 1 gates the sync pulse to the clock divider. The sync signal is

enabled when Bit 1 is high and Bit 0 is high. This is continuous

sync mode.

Sync Control (Register 0x100)

Bits[7:3]—Reserved

Bit 0—Master Sync Enable

Bit 2—Clock Divider Next Sync Only

Bit 0 must be high to enable any of the sync functions. If the

sync capability is not used this bit should remain low to

conserve power.

If the master sync enable bit (Address 0x100, Bit0) and the clock

divider sync enable bit (Address 0x100, Bit 1) are high, Bit 2 allows

the clock divider to sync to the first sync pulse it receives and to

Rev. A | Page 4± of 44

AD9258

APPLICATIONS INFORMATION

The copper plane should have several vias to achieve the lowest

possible resistive thermal path for heat dissipation to flow through

the bottom of the PCB. These vias should be filled or plugged to

prevent solder wicking through the vias, which can compromise

the connection.

DESIGN GUIDELINES

Before starting design and layout of the AD9258 as a system,

it is recommended that the designer become familiar with these

guidelines, which discuss the special circuit connections and

layout requirements that are needed for certain pins.

To maximize the coverage and adhesion between the ADC and

the PCB, a silkscreen should be overlaid to partition the continuous

plane on the PCB into several uniform sections. This provides

several tie points between the ADC and the PCB during the reflow

process. Using one continuous plane with no partitions guarantees

only one tie point between the ADC and the PCB. For detailed

information about packaging and PCB layout of chip scale

packages, see the AN-772 Application Note, A Design and

Manufacturing Guide for the Lead Frame Chip Scale Package

(LFCSP), at www.analog.com.

Power and Ground Recommendations

When connecting power to the AD9258, it is recommended that

two separate 1.8 V supplies be used. Use one supply for analog

(AVDD); use a separate supply for the digital outputs (DRVDD).

For both AVDD and DRVDD several different decoupling capa-

citors should be used to cover both high and low frequencies.

Place these capacitors close to the point of entry at the PCB level

and close to the pins of the part, with minimal trace length.

A single PCB ground plane should be sufficient when using the

AD9258. With proper decoupling and smart partitioning of the

PCB analog, digital, and clock sections, optimum performance

is easily achieved.

VCM

The VCM pin should be decoupled to ground with a 0.1 ꢀF

capacitor, as shown in Figure 67.

LVDS Operation

RBIAS

The AD9258 defaults to CMOS output mode on power-up.

If LVDS operation is desired, this mode must be programmed,

using the SPI configuration registers after power-up. When the

AD9258 powers up in CMOS mode with LVDS termination

resistors (100 Ω) on the outputs, the DRVDD current can be

higher than the typical value until the part is placed in LVDS

mode. This additional DRVDD current does not cause damage

to the AD9258, but it should be taken into account when consid-

ering the maximum DRVDD current for the part.

The AD9258 requires that a 10 kΩ resistor be placed between

the RBIAS pin and ground. This resistor sets the master current

reference of the ADC core and should have at least a 1% tolerance.

Reference Decoupling

The VREF pin should be externally decoupled to ground with

a low ESR, 1.0 ꢀF capacitor in parallel with a low ESR, 0.1 ꢀF

ceramic capacitor.

SPI Port

To avoid this additional DRVDD current, the AD9258 outputs

can be disabled at power-up by taking the OEB pin high. After

the part is placed into LVDS mode via the SPI port, the OEB

pin can be taken low to enable the outputs.

The SPI port should not be active during periods when the full

dynamic performance of the converter is required. Because the

SCLK, CSB, and SDIO signals are typically asynchronous to the

ADC clock, noise from these signals can degrade converter

performance. If the on-board SPI bus is used for other devices,

it may be necessary to provide buffers between this bus and the

AD9258 to keep these signals from transitioning at the converter

inputs during critical sampling periods.

Exposed Paddle Thermal Heat Slug Recommendations

It is mandatory that the exposed paddle on the underside of the

ADC be connected to analog ground (AGND) to achieve the

best electrical and thermal performance. A continuous, exposed

(no solder mask) copper plane on the PCB should mate to the

AD9258 exposed paddle, Pin 0.

Rev. A | Page 41 of 44

AD9258

OUTLINE DIMENSIONS

0.60 MAX

9.00

BSC SQ

0.60

MAX

PIN 1

INDICATOR

64

49

1

48

PIN 1

INDICATOR

0.50

BSC

7.65

7.50 SQ

7.35

8.75

BSC SQ

TOP VIEW

EXPOSED PAD

(BOTTOM VIEW)

0.50

0.40

0.30

16

17

33

32

0.25 MIN

7.50

REF

0.80 MAX

0.65 TYP

12° MAX

1.00

0.85

0.80

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

SECTION OF THIS DATA SHEET.

0.30

0.23

0.18

SEATING

PLANE

0.20 REF

COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4

Figure 85. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

9 mm × 9 mm Body, Very Thin Quad

(CP-64-6)

Dimensions shown in millimeters

ORDERING GUIDE

Model

Temperature Range

Package Description

Package Option

CP-ꢁ4-ꢁ

AD92ꢀꢃBCPZ-ꢃ±¹

AD92ꢀꢃBCPZRLꢂ-ꢃ±¹

AD92ꢀꢃBCPZ-1±ꢀ¹

AD92ꢀꢃBCPZRLꢂ-1±ꢀ¹−4±°C to +ꢃꢀ°C

AD92ꢀꢃBCPZ-12ꢀ¹

−4±°C to +ꢃꢀ°C

AD92ꢀꢃBCPZRLꢂ-12ꢀ¹−4±°C to +ꢃꢀ°C

AD92ꢀꢃ-ꢃ±EBZ¹

−4±°C to +ꢃꢀ°C

ꢁ4-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

Evaluation Board

CP-ꢁ4-ꢁ

AD92ꢀꢃ-1±ꢀEBZ¹

AD92ꢀꢃ-12ꢀEBZ¹

Evaluation Board

¹Z = RoHS Compliant Part.

Rev. A | Page 42 of 44

AD9258

NOTES

Rev. A | Page 43 of 44

AD9258

NOTES

registered trademarks are the property of their respective owners.

D08124-0-9/09(A)

Rev. A | Page 44 of 44


型号：	AD9258-125EBZ
厂家：	ADI
描述：	Analog-to-Digital Converter (ADC)
文件：	总45页 (文件大小：2152K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD9258-125EBZ [ADI]

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