AD8542ARU-REEL [ADI]
General Purpose CMOS Rail-to-Rail Amplifiers; 通用CMOS轨到轨放大器
| 型号： | AD8542ARU-REEL |
| 厂家： | 
ADI |
| 描述： | General Purpose CMOS Rail-to-Rail Amplifiers |
| 文件： | 总16页 (文件大小：232K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
General-Purpose CMOS
Rail-to-Rail Amplifiers
a
AD8541/AD8542/AD8544
FEATURES
PIN CONFIGURATIONS
Single-Supply Operation: 2.7 V to 5.5 V
Low Supply Current: 45 A/Amplifier
Wide Bandwidth: 1 MHz
No Phase Reversal
5-Lead SC70 and SOT-23
(KS and RT Suffixes)
Low Input Currents: 4 pA
Unity Gain Stable
Rail-to-Rail Input and Output
AD8541
V+
OUT A
V؊
1
2
5
4
+IN A
3
؊IN A
APPLICATIONS
ASIC Input or Output Amplifier
Sensor Interface
Piezo Electric Transducer Amplifier
Medical Instrumentation
Mobile Communication
Audio Output
8-Lead SOIC
(R Suffix)
1
8
NC
V+
NC
AD8541
Portable Systems
2
7
–IN A
OUT A
NC
3
4
6
5
+IN A
V–
GENERAL DESCRIPTION
The AD8541/AD8542/AD8544 are single, dual, and quad rail-
to-rail input and output single-supply amplifiers featuring very
low supply current and 1 MHz bandwidth. All are guaranteed to
operate from a 2.7 V single supply as well as a 5 V supply. These
parts provide 1 MHz bandwidth at a low current consumption
of 45 mA per amplifier.
NC = NO CONNECT
8-Lead SOIC, MSOP, and TSSOP
(R, RM, and RU Suffixes)
AD8542
OUT A
–IN A
+IN A
V–
8
7
6
5
1
2
3
4
V+
Very low input bias currents enable the AD8541/AD8542/AD8544
to be used for integrators, photodiode amplifiers, piezo electric
sensors, and other applications with high source impedance. Sup-
ply current is only 45 mA per amplifier, ideal for battery operation.
OUT B
–IN B
+IN B
Rail-to-rail inputs and outputs are useful to designers buffering
ASICs in single-supply systems. The AD8541/AD8542/AD8544
are optimized to maintain high gains at lower supply voltages,
making them useful for active filters and gain stages.
14-Lead SOIC and TSSOP
(R and RU Suffixes)
The AD8541/AD8542/AD8544 are specified over the extended
industrial temperature range (–40∞C to +125∞C). The AD8541
is available in 8-lead SOIC, 5-lead SC70, and 5-lead SOT-23
packages. The AD8542 is available in 8-lead SOIC, 8-lead
MSOP, and 8-lead TSSOP surface-mount packages. The AD8544
is available in 14-lead narrow SOIC and 14-lead TSSOP surface-
mount packages. All MSOP, SC70, and SOT versions are available
in tape and reel only.
14
13
12
11
10
9
OUT D
–IN D
OUT A
–IN A
1
2
3
4
5
6
7
+IN D
V–
+IN A
V+
AD8544
+IN C
+IN B
–IN B
–IN C
8
OUT C
OUT B
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
AD8541/AD8542/AD8544–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (VS = 2.7 V, VCM = 1.35 V, TA = 25؇C, unless otherwise noted.)
Parameter
Symbol
Conditions
Min
Typ Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
IB
1
4
6
7
60
100
1,000
30
mV
mV
pA
pA
pA
pA
–40∞C £ TA £ +125∞C
Input Bias Current
Input Offset Current
–40∞C £ TA £ +85∞C
–40∞C £ TA £ +125∞C
IOS
0.1
–40∞C £ TA £ +85∞C
–40∞C £ TA £ +125∞C
50
500
2.7
pA
pA
V
Input Voltage Range
0
Common-Mode Rejection Ratio
CMRR
AVO
V
CM = 0 V to 2.7 V
40
38
100
50
2
45
dB
dB
–40∞C £ TA £ +125∞C
RL = 100 kW , VO = 0.5 V to 2.2 V
–40∞C £ TA £ +85∞C
–40∞C £ TA £ +125∞C
–40∞C £ TA £ +125∞C
–40∞C £ TA £ +85∞C
–40∞C £ TA £ +125∞C
–40∞C £ TA £ +125∞C
Large Signal Voltage Gain
500
V/mV
V/mV
V/mV
mV/∞C
fA/∞C
fA/∞C
fA/∞C
Offset Voltage Drift
Bias Current Drift
DVOS/DT
DIB/DT
4
100
2,000
25
Offset Current Drift
DIOS/DT
OUTPUT CHARACTERISTICS
Output Voltage High
VOH
VOL
IL = 1 mA
–40∞C £ TA £ +125∞C
IL = 1 mA
–40∞C £ TA £ +125∞C
VOUT = VS – 1 V
2.575 2.65
2.550
V
V
Output Voltage Low
35
100
125
mV
mV
mA
mA
W
Output Current
IOUT
± ISC
ZOUT
15
± 20
50
Closed-Loop Output Impedance
f = 200 kHz, AV = 1
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
ISY
VS = 2.5 V to 6 V
–40∞C £ TA £ +125∞C
VO = 0 V
65
60
76
38
dB
dB
mA
mA
Supply Current/Amplifier
55
75
–40∞C £ TA £ +125∞C
DYNAMIC PERFORMANCE
Slew Rate
Settling Time
Gain Bandwidth Product
Phase Margin
SR
tS
GBP
Fo
RL = 100 kW
To 0.1% (1 V Step)
0.4
0.75
5
980
63
V/ms
ms
kHz
Degrees
NOISE PERFORMANCE
Voltage Noise Density
en
en
in
f = 1 kHz
f = 10 kHz
40
38
<0.1
nV/÷Hz
nV/÷Hz
pA/÷Hz
Current Noise Density
Specifications subject to change without notice.
REV. D
–2–
AD8541/AD8542/AD8544
ELECTRICAL CHARACTERISTICS (VS = 3.0 V, VCM = 1.5 V, TA = 25؇C, unless otherwise noted.)
Parameter
Symbol
Conditions
Min
Typ Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
IB
1
4
6
7
mV
mV
pA
pA
pA
pA
pA
pA
–40∞C £ TA £ +125∞C
Input Bias Current
Input Offset Current
60
100
1,000
30
50
500
3
–40∞C £ TA £ +85∞C
–40∞C £ TA £ +125∞C
IOS
0.1
–40∞C £ TA £ +85∞C
–40∞C £ TA £ +125∞C
Input Voltage Range
0
V
Common-Mode Rejection Ratio
CMRR
AVO
VCM = 0 V to 3 V
40
38
100
50
2
45
dB
dB
–40∞C £ TA £ +125∞C
RL = 100 kW , VO = 0.5 V to 2.2 V
–40∞C £ TA £ +85∞C
–40∞C £ TA £ +125∞C
–40∞C £ TA £ +125∞C
–40∞C £ TA £ +85∞C
–40∞C £ TA £ +125∞C
–40∞C £ TA £ +125∞C
Large Signal Voltage Gain
500
V/mV
V/mV
V/mV
mV/∞C
fA/∞C
fA/∞C
fA/∞C
Offset Voltage Drift
Bias Current Drift
DVOS/DT
DIB/DT
4
100
2,000
25
Offset Current Drift
DIOS/DT
OUTPUT CHARACTERISTICS
Output Voltage High
VOH
VOL
IL = 1 mA
–40∞C £ TA £ +125∞C
IL = 1 mA
–40∞C £ TA £ +125∞C
VOUT = VS – 1 V
2.875 2.955
2.850
32
V
V
Output Voltage Low
100
125
mV
mV
mA
mA
W
Output Current
IOUT
± ISC
ZOUT
18
± 25
50
Closed-Loop Output Impedance
f = 200 kHz, AV = 1
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
ISY
VS = 2.5 V to 6 V
–40∞C £ TA £ +125∞C
VO = 0 V
65
60
76
40
dB
dB
mA
mA
Supply Current/Amplifier
60
75
–40∞C £ TA £ +125∞C
DYNAMIC PERFORMANCE
Slew Rate
Settling Time
Gain Bandwidth Product
Phase Margin
SR
tS
GBP
Fo
RL = 100 kW
To 0.01% (1 V Step)
0.4
0.8
5
980
64
V/ms
ms
kHz
Degrees
NOISE PERFORMANCE
Voltage Noise Density
en
en
in
f = 1 kHz
f = 10 kHz
42
38
<0.1
nV/÷Hz
nV/÷Hz
pA/÷Hz
Current Noise Density
Specifications subject to change without notice.
REV. D
–3–
AD8541/AD8542/AD8544–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (VS = 5.0 V, VCM = 2.5 V, TA = 25؇C, unless otherwise noted.)
Parameter
Symbol
Conditions
Min
Typ Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
IB
1
4
6
7
mV
mV
pA
pA
pA
pA
pA
pA
–40∞C £ TA £ +125∞C
Input Bias Current
60
100
1,000
30
50
500
5
–40∞C £ TA £ +85∞C
–40∞C £ TA £ +125∞C
Input Offset Current
IOS
0.1
–40∞C £ TA £ +85∞C
–40∞C £ TA £ +125∞C
Input Voltage Range
0
V
Common-Mode Rejection Ratio
CMRR
AVO
VCM = 0 V to 5 V
40
38
20
10
2
48
40
dB
dB
–40∞C £ TA £ +125∞C
RL = 100 kW , VO = 0.5 V to 2.2 V
–40∞C £ TA £ +85∞C
–40∞C £ TA £ +125∞C
–40∞C £ TA £ +125∞C
–40∞C £ TA £ +85∞C
–40∞C £ TA £ +125∞C
–40∞C £ TA £ +125∞C
Large Signal Voltage Gain
V/mV
V/mV
V/mV
mV/∞C
fA/∞C
fA/∞C
fA/∞C
Offset Voltage Drift
Bias Current Drift
DVOS/DT
DIB/DT
4
100
2,000
25
Offset Current Drift
DIOS/DT
OUTPUT CHARACTERISTICS
Output Voltage High
VOH
VOL
IL = 1 mA
–40∞C £ TA £ +125∞C
IL = 1 mA
–40∞C £ TA £ +125∞C
VOUT = VS – 1 V
4.9
4.875
4.965
25
V
V
Output Voltage Low
100
125
mV
mV
mA
mA
W
Output Current
IOUT
± ISC
ZOUT
30
± 60
45
Closed-Loop Output Impedance
f = 200 kHz, AV = 1
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
ISY
VS = 2.5 V to 6 V
–40∞C £ TA £ +125∞C
VO = 0 V
65
60
76
45
dB
dB
mA
mA
Supply Current/Amplifier
65
85
–40∞C £ TA £ +125∞C
DYNAMIC PERFORMANCE
Slew Rate
Full-Power Bandwidth
Settling Time
Gain Bandwidth Product
Phase Margin
SR
BWP
tS
GBP
Fo
RL = 100 kW, CL = 200 pF
1% Distortion
To 0.1% (1 V Step)
0.45
0.92
70
6
1,000
67
V/ms
kHz
ms
kHz
Degrees
NOISE PERFORMANCE
Voltage Noise Density
en
en
in
f = 1 kHz
f = 10 kHz
42
38
<0.1
nV/÷Hz
nV/÷Hz
pA/÷Hz
Current Noise Density
Specifications subject to change without notice.
REV. D
–4–
AD8541/AD8542/AD8544
PACKAGE INFORMATION
ABSOLUTE MAXIMUM RATINGS1
Supply Voltage (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND to VS
Differential Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . ± 6 V
Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C
Operating Temperature Range . . . . . . . . . . –40∞C to +125∞C
Junction Temperature Range . . . . . . . . . . . . –65∞C to +150∞C
Lead Temperature Range (Soldering, 60 sec) . . . . . . . 300∞C
Package Type
JA*
Unit
JC
5-Lead SC70 (KS)
5-Lead SOT-23 (RT)
8-Lead SOIC (R)
8-Lead MSOP (RM)
8-Lead TSSOP (RU)
14-Lead SOIC (R)
14-Lead TSSOP (RU)
376
230
158
210
240
120
240
126
146
43
45
43
∞C/W
∞C/W
∞C/W
∞C/W
∞C/W
∞C/W
∞C/W
NOTES
36
43
1 Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2 For supplies less than 6 V, the differential input voltage is equal to ± VS.
*qJA is specified for worst-case conditions, i.e., JA is specified for device soldered
onto a circuit board for surface mount packages.
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Option
Branding
Information
Model
AD8541AKS-R2
–40∞C to +125∞C
–40∞C to +125∞C
–40∞C to +125∞C
–40∞C to +125∞C
–40∞C to +125∞C
–40∞C to +125∞C
–40∞C to +125∞C
–40∞C to +125∞C
–40∞C to +125∞C
–40∞C to +125∞C
–40∞C to +125∞C
–40∞C to +125∞C
–40∞C to +125∞C
–40∞C to +125∞C
–40∞C to +125∞C
–40∞C to +125∞C
–40∞C to +125∞C
–40∞C to +125∞C
–40∞C to +125∞C
–40∞C to +125∞C
–40∞C to +125∞C
–40∞C to +125∞C
–40∞C to +125∞C
–40∞C to +125∞C
–40∞C to +125∞C
–40∞C to +125∞C
–40∞C to +125∞C
–40∞C to +125∞C
–40∞C to +125∞C
–40∞C to +125∞C
–40∞C to +125∞C
–40∞C to +125∞C
–40∞C to +125∞C
5-Lead SC70
5-Lead SC70
5-Lead SC70
KS-5
KS-5
KS-5
R-8
R-8
R-8
RT-5
RT-5
RT-5
RT-5
RT-5
R-8
A4B
A4B
A4B
AD8541AKS-REEL7
AD8541AKSZ-REEL7*
AD8541AR
AD8541AR-REEL
AD8541AR-REEL7
AD8541ART-R2
AD8541ART-REEL
AD8541ART-REEL7
AD8541ARTZ-REEL*
AD8541ARTZ-REEL7*
AD8542AR
AD8542AR-REEL
AD8542AR-REEL7
AD8542ARZ*
AD8542ARZ-REEL*
AD8542ARZ-REEL7*
AD8542ARM-R2
AD8542ARM-REEL
AD8542ARU
AD8542ARU-REEL
AD8542ARUZ*
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
5-Lead SOT-23
5-Lead SOT-23
5-Lead SOT-23
5-Lead SOT-23
5-Lead SOT-23
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead MSOP
8-Lead MSOP
8-Lead TSSOP
8-Lead TSSOP
8-Lead TSSOP
8-Lead TSSOP
14-Lead SOIC
14-Lead SOIC
14-Lead SOIC
14-Lead SOIC
14-Lead SOIC
14-Lead SOIC
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
A4A
A4A
A4A
A4A
A4A
R-8
R-8
R-8
R-8
R-8
RM-8
RM-8
RU-8
RU-8
RU-8
RU-8
R-14
R-14
R-14
R-14
R-14
R-14
RU-14
RU-14
RU-14
RU-14
AVA
AVA
AD8542ARUZ-REEL*
AD8544AR
AD8544AR-REEL
AD8544AR-REEL7
AD8544ARZ*
AD8544ARZ-REEL*
AD8544ARZ-REEL7*
AD8544ARU
AD8544ARU-REEL
AD8544ARUZ*
AD8544ARUZ-REEL*
*Z = Pb-free part.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8541/AD8542/AD8544 feature proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. D
–5–
–Typical Performance Characteristics
AD8541/AD8542/AD8544
180
1.0
9
8
7
6
5
4
3
2
1
0
V
V
= 5V
V
V
= 2.7V AND 5V
= V /2
V
V
= 2.7V AND 5V
= V /2
S
S
S
0.5
= 2.5V
160
140
120
100
80
CM
CM
S
CM
S
T
= 25؇C
A
0.0
؊0.5
؊1.0
؊1.5
؊2.0
؊2.5
؊3.0
؊3.5
؊4.0
60
40
20
0
؊4.5 ؊3.5 ؊2.5 ؊1.5
؊0.5 0.5 1.5 2.5 3.5 4.5
INPUT OFFSET VOLTAGE – mV
؊55 ؊35 ؊15
5
25 45 65 85 105 125 145
؊0.5
0.5
1.5
2.5
3.5
4.5
5.5
TEMPERATURE – ؇C
COMMON-MODE VOLTAGE – V
TPC 1. Input Offset Voltage
Distribution
TPC 2. Input Offset Voltage
vs. Temperature
TPC 3. Input Bias Current vs.
Common-Mode Voltage
400
350
300
250
200
150
100
50
7
160
V
V
= 2.7V AND 5V
= V /2
V
V
= 2.7V AND 5V
= V /2
S
S
V
T
= 2.7V
= 25؇C
CM
S
CM
S
S
A
140
120
100
80
6
5
4
؊PSRR
+PSRR
3
60
40
2
20
1
0
0
؊20
؊40
0
؊1
؊40 ؊20
0
20 40 60 80 100 120 140
؊55 ؊35 ؊15
5
25 45 65 85 105 125 145
100
1k
10k
100k
1M
10M
TEMPERATURE – ؇C
TEMPERATURE – ؇C
FREQUENCY – Hz
TPC 5. Input Offset Current vs.
Temperature
TPC 4. Input Bias Current vs.
Temperature
TPC 6. Power Supply Rejection
Ratio vs. Frequency
3.0
10k
60
V
T
= 2.7V
= 25؇C
V
V
= 2.7V
= 2.5V p-p
= 2k⍀
S
S
V
= 2.7V
=
= 25؇C
S
A
IN
2.5
2.0
1.5
1.0
0.5
0
1k
100
10
50
40
30
20
R
T
R
T
L
L
= 25؇C
A
A
+OS
SOURCE
SINK
؊OS
1
0.1
10
0
0.01
0.001
1k
10k
100k
1M
10M
10
100
1k
10k
0.01
0.1
1
10
100
FREQUENCY – Hz
CAPACITANCE – pF
LOAD CURRENT – mA
TPC 9. Small Signal Overshoot vs.
Load Capacitance
TPC 8. Closed-Loop Output
Voltage Swing vs. Frequency
TPC 7. Output Voltage to Supply
Rail vs. Load Current
REV. D
–6–
AD8541/AD8542/AD8544
60
50
40
30
20
10
0
60
50
40
30
20
V
= 2.7V
= 100kV
= 300pF
= 1
S
V
R
= 2.7V
= 10k⍀
= 25؇C
V
R
= 2.7V
= 2k⍀
= 25؇C
S
S
R
C
A
T
L
L
V
L
L
T
T
A
A
= 25 C
A
+OS
+OS
؊OS
1.35V
؊OS
10
0
10s
50mV
10
100
1k
10k
10
100
1k
10k
CAPACITANCE – pF
CAPACITANCE – pF
TPC 10. Small Signal Overshoot vs.
Load Capacitance
TPC 11. Small Signal Overshoot
vs. Load Capacitance
TPC 12. Small Signal Transient
Response
160
V
= 2.7V
S
V
T
= 5V
= 25؇C
S
A
140
120
100
80
R
= NO LOAD
= 25؇C
L
T
A
80
60
40
20
0
45
90
؊PSRR
+PSRR
135
180
60
1.35V
40
V
= 2.7V
= 2k⍀
= 1
S
20
R
A
L
V
A
0
T
= 25؇C
؊20
؊40
10s
500mV
1k
10k
100k
FREQUENCY – Hz
1M
10M
100
1k
10k
100k
1M
10M
FREQUENCY – Hz
TPC 14. Open-Loop Gain and
Phase vs. Frequency
TPC 13. Large Signal Transient
Response
TPC 15. Power Supply Rejection
Ratio vs. Frequency
10k
5.0
90
V
T
= 5V
= 25؇C
V
V
R
= 5V
S
V
T
= 5V
= 25؇C
S
S
4.5
80
70
60
50
= 4.9V p-p
= NO LOAD
= 25؇C
A
IN
A
1k
100
10
L
4.0
3.5
T
A
3.0
2.5
SOURCE
40
30
20
SINK
2.0
1.5
1
1.0
0.5
0
10
0.1
0
0.01
0.001
؊10
0.01
0.1
1
10
100
1k
10k
100k
FREQUENCY – Hz
1M
10M
1k
10k
100k
FREQUENCY – Hz
1M
10M
LOAD CURRENT – mA
TPC 17. Output Voltage to Supply
Rail vs. Frequency
TPC 16. Common-Mode Rejection
Ratio vs. Frequency
TPC 18. Closed-Loop Output
Voltage Swing vs. Frequency
REV. D
–7–
AD8541/AD8542/AD8544
60
50
40
30
20
60
5.0
V
V
R
= 5V
= 4.9V p-p
= 2k⍀
S
4.5
V
= 5V
= 10k⍀
= 25؇C
V
= 5V
S
S
IN
R
T
50
40
30
20
10
0
R
T
= 2k⍀
= 25؇C
L
L
L
4.0
3.5
A
T
= 25؇C
A
A
3.0
2.5
+OS
+OS
؊OS
؊OS
2.0
1.5
1.0
0.5
0
10
0
10
100
1k
10k
1k
10k
100k
FREQUENCY – Hz
1M
10M
10
100
1k
10k
CAPACITANCE – pF
CAPACITANCE – pF
TPC 19. Closed-Loop Output
Voltage Swing vs. Frequency
TPC 20. Small Signal Overshoot vs.
Load Capacitance
TPC 21. Small Signal Overshoot vs.
Load Capacitance
60
V
= 5V
S
V
R
= 5V
=
= 25؇C
S
R
C
A
= 100k⍀
= 300pF
= 1
L
L
50
40
30
20
10
0
L
T
A
V
A
T
= 25؇C
+OS
2.5V
2.5V
؊OS
V
= 5V
= 2k⍀
= 1
S
R
A
L
V
A
T
= 25؇C
10s
50mV
10s
1V
10
100
1k
10k
CAPACITANCE – pF
TPC 22. Small Signal Overshoot vs.
Load Capacitance
TPC 23. Small Signal Transient
Response
TPC 24. Large Signal Transient
Response
60
V
= 5V
= 10k⍀
= 1
S
V
R
= 5V
= NO LOAD
= 25؇C
S
T
= 25؇C
A
R
A
L
V
A
L
V
IN
50
40
30
20
10
0
T
A
T
= 25؇C
80
60
40
20
0
45
V
90
OUT
135
180
2.5V
20s
1V
1k
10k
100k
FREQUENCY – Hz
1M
10M
0
1
2
3
4
5
6
SUPPLY VOLTAGE – V
TPC 25. Open-Loop Gain and Phase
vs. Frequency
TPC 26. No Phase Reversal
TPC 27. Supply Current per
Amplifier vs. Supply Voltage
REV. D
–8–
AD8541/AD8542/AD8544
55
50
45
40
35
30
25
20
1,000
900
800
700
600
500
400
300
200
100
0
V
= 2.7V AND 5V
= 1
= 25؇C
V
A
= 5V
= 1
S
S
A
T
V
V
MARKER SET @ 10kHz
V
= 5V
A
S
MARKER READING: 37.6V/ Hz
T
= 25؇C
A
V
= 2.7V
S
؊55 ؊35؊15
5
25 45 65 85 105 125 145
0
5
10
15
20
25
1k
10k
100k
1M
10M
100M
TEMPERATURE – ؇C
FREQUENCY – Hz
FREQUENCY – kHz
TPC 28. Supply Current per
Amplifier vs. Temperature
TPC 29. Closed-Loop Output
Impedance vs. Frequency
TPC 30. Voltage Noise
NOTES ON THE AD854x AMPLIFIERS
drift will cause the circuit to no longer attenuate at the ideal
notch frequency. To achieve desired performance, 1% or
better component tolerances or special component screens
are usually required. One method to desensitize the circuit-
to-component mismatch is to increase R2 with respect to
R1, which lowers Q. A lower Q increases attenuation over a
wider frequency range but reduces attenuation at the peak
notch frequency.
The AD8541/AD8542/AD8544 amplifiers are improved perfor-
mance general-purpose operational amplifiers. Performance has
been improved over previous amplifiers in several ways.
Lower Supply Current for 1 MHz Gain Bandwidth
The AD854x series typically uses 45 mA of current per amplifier.
This is much less than the 200 mA to 700 mA used in earlier
generation parts with similar performance. This makes the
AD854x series a good choice for upgrading portable designs for
longer battery life. Alternatively, additional functions and per-
formance can be added at the same current drain.
5.0V
R
R
8
100k⍀
100k⍀
1/2 AD8542
3
2
U1
VOUT
C2
1
Higher Output Current
4
53.6F
At 5 V single supply, the short-circuit current is typically 60 mA.
Even 1 V from the supply rail, the AD854x amplifiers can provide
30 mA, sourcing or sinking.
R/2
50k⍀
R2
2.5k⍀
2.5V
REF
C
C
Sourcing and sinking are strong at lower voltages, with 15 mA
available at 2.7 V and 18 mA at 3.0 V. For even higher output
currents, please see the Analog Devices AD8531/AD8532/AD8534
parts, with output currents to 250 mA. Information on these
parts is available from your Analog Devices representative,
and data sheets are available at the Analog Devices website at
www.analog.com.
1/2 AD8542
26.7nF
26.7nF
5
6
7
U2
R1
97.5k⍀
1
f
=
0
2pRC
1
2.5V
REF
f
=
0
R1
1 ؊
4
[
]
R1+R2
Better Performance at Lower Voltages
Figure 1. 60 Hz Twin-T Notch Filter, Q = 10
The AD854x family of parts has been designed to provide better
ac performance, at 3.0 V and 2.7 V, than previously available
parts. Typical gain-bandwidth product is close to 1 MHz at 2.7 V.
Voltage gain at 2.7 V and 3.0 V is typically 500,000. Phase margin
is typically over 60∞C, making the part easy to use.
5.0V
7
AD8541
R
R
3
2
VOUT
6
4
2C
V
IN
APPLICATIONS
Notch Filter
R/2
The AD8542 has very high open-loop gain (especially with a
supply voltage below 4 V), which makes it useful for active filters
of all types. For example, Figure 1 illustrates the AD8542 in the
classic Twin-T Notch Filter design. The Twin-T Notch is desired
for simplicity, low output impedance, and minimal use of op
amps. In fact, this notch filter may be designed with only one op
amp if Q adjustment is not required. Simply remove U2 as illus-
trated in Figure 2. However, a major drawback to this circuit
topology is ensuring that all the Rs and Cs closely match. The
components must closely match or notch frequency offset and
2.5V
REF
C
C
=
Figure 2. 60 Hz Twin-T Notch Filter, Q • (Ideal)
Figure 3 shows another example of the AD8542 in a notch
filter circuit. The FNDR notch filter has fewer critical
matching requirements than the Twin-T Notch and for the
FNDR Q is directly proportional to a single resistor R1.
While matching component values is still important, it is also
REV. D
–9–
AD8541/AD8542/AD8544
much easier and/or less expensive to accomplish in the FNDR
circuit. For example, the Twin-T notch uses three capacitors
with two unique values, whereas the FNDR circuit uses only two
capacitors, which may be of the same value. U3 is simply a buffer
that is added to lower the output impedance of the circuit.
Photodiode Application
The AD854x family has very high impedance with input bias
current typically around 4 pA. This characteristic allows the
AD854x op amps to be used in photodiode applications and
other applications that require high input impedance. Note that
the AD854x has significant voltage offset, which can be removed
by capacitive coupling or software calibration.
1/4 AD8544
R1
Q ADJUST
200⍀
9
8
Figure 5 illustrates a photodiode or current measurement
application. The feedback resistor is limited to 10 MW to avoid
excessive output offset. Also, note that a resistor is not needed
on the noninverting input to cancel bias current offset because
the bias current related output offset is not significant when
compared to the voltage offset contribution. For the best
performance follow the standard high impedance layout
techniques including:
U3
VOUT
10
C1
1F
R
2.5V
REF
2.61k⍀
1/4 AD8544
1
4
3
C2
1F
U1
1/4 AD8544
2
6
11
7
U2
R
5
∑ Shield the circuit.
2.61k⍀
∑ Clean the circuit board.
R
2.61k⍀
∑ Put a trace connected to the noninverting input around the
inverting input.
1/4 AD8544
R
13
1
f =
14
2.61k⍀
2p
LC1
U4
NC
∑ Use separate analog and digital power supplies.
12
2.5V
REF
SPARE
2
L =
R C2
C
100pF
2.5V
REF
R
10M⍀
Figure 3. FNDR 60 Hz Notch Filter with Output Buffer
Comparator Function
V+
A comparator function is a common application for a spare op
amp in a quad package. Figure 4 illustrates 1/4 of the AD8544
as a comparator in a standard overload detection application.
Unlike many op amps, the AD854x family can double as
comparators because this op amp family has rail-to-rail differential
input range, rail-to-rail output, and a great speed versus power
ratio. R2 is used to introduce hysteresis. The AD854x, when
used as comparators, have 5 ms propagation delay at 5 V and 5 ms
overload recovery time.
7
OR
2
3
6
V
OUT
4
D
AD8541
2.5V
REF
2.5V
REF
Figure 5. High Input Impedance Application–Photodiode
Amplifier
R2
1M⍀
R1
1k⍀
VOUT
V
IN
1/4 AD8544
2.5V
DC
2.5V
REF
Figure 4. AD854x Comparator Application–Overload Detector
REV. D
–10–
AD8541/AD8542/AD8544
* AD8542 SPICE Macro-model Typical Values
VN1 80 0 0
* 6/98, Ver. 1
RN1 80 0 16.45E-3
* TAM / ADSC
HN 81 0 VN1 35
*
RN2 81 0 1
* Copyright 1998 by Analog Devices
*
*
* INTERNAL VOLTAGE REFERENCE
*
VFIX 90 98 DC 1
S1 90 91 (50,99) VSY_SWITCH
VSN1 91 92 DC 0
RSY 92 98 1E3
EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5
GSY 99 50 POLY(1) (99,50) 0 3.7E-6
*
* ADAPTIVE GAIN STAGE
* AT Vsy>+4.2, AVol=45 V/mv
* AT Vsy<+3.8, AVol=450 V/mv
*
G1 98 30 POLY(2) (4,6) (11,12) 0 2.5E-5 2.5E-5
VR1 30 31 DC 0
H1 31 98 POLY(2) VR1 VSN1 0 5.45E6 0 0 49.05E9
CF 45 30 10E-12
D3 30 99 DX
D4 50 30 DX
* Refer to “README.DOC” file for License
* Statement. Use of this model indicates your
* acceptance of the terms and provisions in
* the License Statement.
*
* Node Assignments
*
noninverting input
*
|
|
|
|
|
|
1
inverting input
*
|
|
|
|
|
2
positive supply
*
|
|
|
|
negative supply
*
|
|
|
output
*
|
|
*
.SUBCKT AD8542
99 50 45
*
* INPUT STAGE
*
M1 4 1 8 8 PIX L=0.6E-6 W=16E-6
M2 6 7 8 8 PIX L=0.6E-6 W=16E-6
*
M3 11 1 10 10 NIX L=0.6E-6 W=16E-6
* OUTPUT STAGE
M4 12 7 10 10 NIX L=0.6E-6 W=16E-6
*
RC1 4 50 20E3
M5 45 46 99 99 POX L=0.6E-6 W=375E-6
M6 45 47 50 50 NOX L=0.6E-6 W=500E-6
EG1 99 46 POLY(1) (98,30) 1.05 1
EG2 47 50 POLY(1) (30,98) 1.04 1
*
RC2 6 50 20E3
RC3 99 11 20E3
RC4 99 12 20E3
C1 4 6 1.5E-12
C2 11 12 1.5E-12
I1 99 8 1E-5
* MODELS
*
I2 10 50 1E-5
.MODEL POX PMOS (LEVEL=2,KP=20E-6,VTO=-
+1,LAMBDA=0.067)
V1 99 9 0.2
V2 13 50 0.2
D1 8 9 DX
D2 13 10 DX
.MODEL NOX NMOS (LEVEL=2,KP=20E-
+6,VTO=1,LAMBDA=0.067)
.MODEL PIX PMOS (LEVEL=2,KP=20E-6,VTO=-
+0.7,LAMBDA=0.01,KF=1E-31)
.MODEL NIX NMOS (LEVEL=2,KP=20E-
+6,VTO=0.7,LAMBDA=0.01,KF=1E-31)
.MODEL DX D(IS=1E-14)
.MODEL VSY_SWITCH VSWITCH(ROFF=100E3,RON=1,VOFF=-
+4.2,VON=-3.5)
EOS 7 2 POLY(3) (22,98) (73,98) (81,0) 1E-3 1 1 1
IOS 1 2 2.5E-12
*
* CMRR 64dB, ZERO AT 20kHz
*
ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5
RCM1 21 22 79.6E3
.ENDS AD8542
CCM1 21 22 100E-12
RCM2 22 98 50
*
* PSRR=90dB, ZERO AT 200Hz
*
RPS1 70 0 1E6
RPS2 71 0 1E6
CPS1 99 70 1E-5
CPS2 50 71 1E-5
EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1
RPS3 72 73 1.59E6
CPS3 72 73 500E-12
RPS4 73 98 25
*
* VOLTAGE NOISE REFERENCE OF 35nV/rt(Hz)
*
REV. D
–11–
AD8541/AD8542/AD8544
OUTLINE DIMENSIONS
8-Lead Thin Shrink Small Outline Package [TSSOP]
14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
(RU-8)
Dimensions shown in millimeters
Dimensions shown in millimeters
3.10
3.00
2.90
5.10
5.00
4.90
8
5
4
14
8
7
4.50
4.40
4.30
4.50
4.40
4.30
6.40 BSC
6.40
BSC
1
1
PIN 1
PIN 1
0.65
BSC
1.05
1.00
0.80
0.65
BSC
0.15
0.05
0.20
0.09
1.20
1.20
MAX
0.75
0.60
0.45
MAX
8؇
0؇
8؇
0؇
0.15
0.05
0.30
0.19
0.75
0.60
0.45
0.30
0.19
SEATING
PLANE
0.20
0.09
COPLANARITY
0.10
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153AA
COMPLIANT TO JEDEC STANDARDS MO-153AB-1
8-Lead Standard Small Outline Package [SOIC]
14-Lead Standard Small Outline Package [SOIC]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
Narrow Body
(R-14)
Dimensions shown in millimeters and (inches)
5.00 (0.1968)
4.80 (0.1890)
8.75 (0.3445)
8.55 (0.3366)
8
1
5
4
14
1
8
7
4.00 (0.1575)
3.80 (0.1496)
6.20 (0.2441)
5.80 (0.2283)
6.20 (0.2440)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
0.50 (0.0197)
0.25 (0.0098)
0.50 (0.0196)
0.25 (0.0099)
1.75 (0.0689)
1.35 (0.0531)
1.27 (0.0500)
BSC
؋
45؇ ؋
45؇ 1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0039)
0.25 (0.0098)
0.10 (0.0040)
8؇
0؇
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
8؇
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
0؇ 1.27 (0.0500)
COPLANARITY
0.10
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012AB
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-012AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
REV. D
–12–
AD8541/AD8542/AD8544
OUTLINE DIMENSIONS
8-Lead Mini Small Outline Package [MSOP]
(RM-8)
5-Lead Small Outline Transistor Package [SOT-23]
(RT-5)
Dimensions shown in millimeters
Dimensions shown in millimeters
3.00
BSC
2.90 BSC
8
5
4
5
1
4
3
4.90
BSC
3.00
BSC
2.80 BSC
1.60 BSC
1
2
PIN 1
PIN 1
0.95 BSC
0.65 BSC
1.90
BSC
1.30
1.15
0.90
1.10 MAX
0.15
0.00
0.80
0.60
0.40
8؇
0؇
1.45 MAX
0.22
0.08
0.38
0.22
0.23
0.08
10؇
5؇
0؇
SEATING
PLANE
COPLANARITY
0.10
0.15 MAX
0.60
0.45
0.30
0.50
0.30
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-187AA
COMPLIANT TO JEDEC STANDARDS MO-178AA
5-Lead Thin Shrink Small Outline Transistor Package [SC70]
(KS-5)
Dimensions shown in millimeters
2.00 BSC
5
1
4
3
1.25 BSC
PIN 1
2.10 BSC
2
0.65 BSC
1.10 MAX
1.00
0.90
0.70
0.22
0.08
0.46
0.36
0.26
0.30
0.15
0.10 MAX
SEATING
PLANE
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-203AA
REV. D
–13–
AD8541/AD8542/AD8544
Revision History
Location
Page
8/04—Data Sheet changed from REV. C to REV. D.
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Change to Figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1/03—Data Sheet changed from REV. B to REV. C.
Updated format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal
Change to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Changes to OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
REV. D
–14–
–15–
–16–
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SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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