AD830JR [ADI]
High Speed, Video Difference Amplifier; 高速视频差动放大器
| 型号： | AD830JR |
| 厂家： | 
ADI |
| 描述： | High Speed, Video Difference Amplifier |
| 文件： | 总16页 (文件大小：336K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Speed, Video
Difference Amplifier
a
AD830
CO NNECTIO N D IAGRAM
FEATURES
Differential Am plification
8-P in P lastic Mini-D IP (N),
Wide Com m on-Mode Voltage Range: +12.8 V, –12 V
Differential Voltage Range: ؎2 V
High CMRR: 60 dB @ 4 MHz
Built-in Differential Clipping Level: ؎2.3 V
Fast Dynam ic Perform ance
85 MHz Unity Gain Bandw idth
35 ns Settling Tim e to 0.1%
360 V/ s Slew Rate
Sym m etrical Dynam ic Response
Excellent Video Specifications
Differential Gain Error: 0.06%
Differential Phase Error: 0.08؇
15 MHz (0.1 dB) Bandw idth
Cerdip (Q) and SO IC (R) P ackages
AD830
V
X1
X2
Y1
Y2
1
2
3
4
8
7
6
5
P
V→1
V→1
OUT
NC
A=1
V
N
NC = NO CONNECT
Flexible Operation
High Output Drive of ؎50 m A m in
Specified w ith Both ؎5 V and ؎15 V Supplies
Low Distortion: THD = –72 dB @ 4 MHz
Excellent DC Perform ance: 3 m V m ax Input Offset
Voltage
input and produces an output voltage referred to a user-chosen
level. T he undesired common-mode signal is rejected, even at
high frequencies. High impedance inputs ease interfacing to fi-
nite source impedances and thus preserve the excellent
common-mode rejection. In many respects, it offers significant
improvements over discrete difference amplifier approaches, in
particular in high frequency common-mode rejection.
APPLICATIONS
Differential Line Receiver
High Speed Level Shifter
High Speed In-Am p
Differential to Single Ended Conversion
Resistorless Sum m ation and Subtraction
High Speed A/ D Driver
T he wide common-mode and differential-voltage range of the
AD830 make it particularly useful and flexible in level shifting
applications, but at lower power dissipation than discrete solu-
tions. Low distortion is preserved over the many possible differ-
ential and common-mode voltages at the input and output.
P RO D UCT D ESCRIP TIO N
Good gain flatness and excellent differential gain of 0.06% and
phase of 0.08° make the AD830 suitable for many video system
applications. Furthermore, the AD830 is suited for general pur-
pose signal processing from dc to 10 MHz.
T he AD830 is a wideband, differencing amplifier designed for
use at video frequencies but also useful in many other applica-
tions. It accurately amplifies a fully differential signal at the
110
100
90
9
V
= ±5V
S
6
3
R
= 150Ω
L
C
= 33pF
L
0
80
V
= ±15V
–3
S
C
= 4.7pF
L
70
60
50
40
30
–6
–9
V
= ±5V
S
–12
–15
–18
–21
C
= 15pF
L
10k
100k
1M
10M
100M
1G
1k
10k
100k
1M
10M
FREQUENCY – Hz
FREQUENCY – Hz
Com m on-Mode Rejection Ratio vs. Frequency
Closed-Loop Gain vs. Frequency, Gain = +1
REV. A
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700 Fax: 617/ 326-8703
AD830–SPECIFICATIONS (V = ؎15 V, R
LOAD = 150 ⍀, CLOAD = 5 pF, T = +25؇C unless otherwise noted)
S
A
AD 830J/A
Typ
AD 830S1
Typ
P aram eter
Conditions
Min
Max
Min
Max
Units
DYNAMIC CHARACT ERIST ICS
3 dB Small Signal Bandwidth
0.1 dB Gain Flatness Frequency Gain = 1, VOUT = 100 mV rms
Differential Gain Error
Differential Phase Error
Slew Rate
Gain = 1, VOUT = 100 mV rms
75
11
85
15
75
11
85
15
MHz
MHz
%
Degrees
V/µs
V/µs
MHz
ns
ns
dBc
dBc
nV/√Hz
pA/√Hz
0 to +0.7 V, Frequency = 4.5 MHz
0 to +0.7 V, Frequency = 4.5 MHz
2 V Step, RL = 500 Ω
0.06
0.08
360
350
45
25
35
–82
–72
27
0.09
0.12
0.06
0.08
360
350
45
25
35
–82
–72
27
0.09
0.12
4 V Step, RL = 500 Ω
3 dB Large Signal Bandwidth
Settling T ime, Gain = 1
Gain = 1, VOUT = 1 V rms
VOUT = 2 V Step, to 0.1%
VOUT = 4 V Step, to 0.1%
2 V p-p, Frequency = 1 MHz
2 V p-p, Frequency = 4 MHz
Frequency = 10 kHz
38
38
Harmonic Distortion
Input Voltage Noise
Input Current Noise
1.4
1.4
DC PERFORMANCE
Offset Voltage
Gain = 1
Gain = 1, T MIN–T MAX
DC
RL = 1 kΩ, G = ±1
–1 V ≤ X ≤ +1 V
–1.5 V ≤ X ≤ +1.5 V
–2 V ≤ X ≤ +2 V
VIN = 0 V, +25°C to T MAX
VIN = 0 V, TMIN
VIN = 0 V, T MIN–T MAX
±1.5
±3
±5
±1.5
±3
±7
mV
mV
dB
Open Loop Gain
Gain Error
Peak Nonlinearity, RL= 1 kΩ,
Gain = 1
64
69
64
69
±0.1
0.01
0.035
0.15
5
±0.6
0.03
0.07
0.4
10
±0.1
0.01
0.035
0.15
5
±0.6
0.03
0.07
0.4
10
%
% FS
% FS
% FS
µA
µA
µA
Input Bias Current
Input Offset Current
7
0.1
13
1
8
0.1
17
1
INPUT CHARACT ERIST ICS
Differential Voltage Range
Differential Clipping Level2
Common-Mode Voltage Range
CMRR
VCM = 0
Pins 1 and 2 Inputs Only
VDM = ±1 V
DC, Pins 1, 2, ±10 V
DC, Pins 1, 2, ±10 V, T MIN–T MAX 88
±2.0
±2.3
±2.0
±2.3
V
V
V
dB
dB
dB
kΩ
pF
±2.1
–12.0
90
±2.1
–12.0
90
86
55
+12.8
+12.8
100
100
Frequency = 4 MHz
55
60
370
2
60
370
2
Input Resistance
Input Capacitance
OUT PUT CHARACT ERIST ICS
Output Voltage Swing
RL ≥ 1 kΩ
±12
±13
+13.8, –13.8
+15.3, –14.7
±80
±12
±13
+13.8, –13.8
+15.3, –14.7
±80
V
V
mA
mA
RL ≥ 1 kΩ, ±16.5 VS
Short to Ground
RL = 150 Ω
Short Circuit Current
Output Current
±50
±4
±50
±4
POWER SUPPLIES
Operating Range
Quiescent Current
+ PSRR (to VP)
– PSRR (to VN)
PSRR
±16.5
17
±16.5
17
V
T
MIN–T MAX
14.5
86
14.5
86
mA
dB
dB
dB
DC, G = 1
DC, G = 1
DC, G = 1, ±5 to ±15 VS
DC, G = 1, ±5 to ±15 VS,
T MIN–T MAX
68
71
68
71
66
62
66
60
PSRR
68
68
dB
NOT ES
1See Standard Military Drawing 5962-9313001MPA for specifications.
2Clipping level function on X channel only.
Specifications subject to change without notice.
–2–
REV. A
AD830
(V = ؎5 V, RLOAD = 150 ⍀, CLOAD = 5 pF, T = +25؇C unless otherwise noted)
S
A
AD 830J/A
Typ
AD 830S1
Typ
P aram eter
Conditions
Min
Max
Min
Max
Units
DYNAMIC CHARACT ERIST ICS
3 dB Small Signal Bandwidth
0.1 dB Gain Flatness Frequency Gain = 1, VOUT = 100 mV rms
Gain = 1, VOUT = 100 mV rms
35
5
40
6.5
35
5
40
6.5
MHz
MHz
Differential Gain Error
Differential Phase Error
Slew Rate, Gain = 1
0 to +0.7 V, Frequency = 4.5 MHz,
G = +2
0 to +0.7 V, Frequency = 4.5 MHz,
G = +2
2 V Step, RL = 500 Ω
4 V Step, RL = 500 Ω
Gain = 1, VOUT = 1 V rms
VOUT = 2 V Step, to 0.1%
VOUT = 4 V Step, to 0.1%
2 V p-p, Frequency = 1 MHz
2 V p-p, Frequency = 4 MHz
Frequency = 10 kHz
0.14
0.18
0.4
0.14
0.18
0.4
%
0.32
210
240
36
35
48
–69
–56
27
0.32
210
240
36
35
48
–69
–56
27
Degrees
V/µs
V/µs
MHz
ns
ns
dBc
dBc
nV/√Hz
pA/√Hz
3 dB Large Signal Bandwidth
Settling T ime
30
30
Harmonic Distortion
Input Voltage Noise
Input Current Noise
1.4
1.4
DC PERFORMANCE
Offset Voltage
Gain = 1
Gain = 1, T MIN–T MAX
DC
±1.5
±3
±4
±1.5
±3
±5
mV
mV
dB
Open Loop Gain
60
65
60
65
Unity Gain Accuracy
Peak Nonlinearity, RL= 1 kΩ
RL = 1 kΩ
±0.1
0.01
0.045
0.23
5
±0.6
0.03
0.07
0.4
10
±0.1
0.01
0.045
0.23
5
±0.6
0.03
0.07
0.4
10
%
–1 V ≤ X ≤ +1 V
–1.5 V ≤ X ≤ +1.5 V
–2 V ≤ X ≤ +2 V
VIN = 0 V, +25°C to T MAX
VIN = 0 V, TMIN
VIN = 0 V, T MIN–T MAX
% FS
% FS
% FS
µA
µA
µA
Input Bias Current
Input Offset Current
7
0.1
13
1
8
0.1
17
1
INPUT CHARACT ERIST ICS
Differential Voltage Range
Differential Clipping Level2
Common-Mode Voltage Range
CMRR
VCM = 0
Pins 1 and 2 Inputs Only
VDM = ±1 V
DC, Pins 1, 2, +4 V to –2 V
DC, Pins 1, 2, +4 V to –2 V,
±2.0
±2.2
±2.0
±2.2
V
V
V
dB
±2.0
–2.0
90
±2.0
–2.0
90
+2.9
+2.9
100
100
T
MIN–T MAX
88
55
86
55
dB
dB
kΩ
pF
Frequency = 4 MHz
60
370
2
60
370
2
Input Resistance
Input Capacitance
OUT PUT CHARACT ERIST ICS
Output Voltage Swing
RL ≥ 150 Ω
RL ≥ 150 Ω, ±4 VS
Short to Ground
±3.2
±2.2
±3.5
+2.7, –2.4
–55, +70
±3.2
±2.2
±3.5
+2.7, –2.4
–55, +70
V
V
mA
mA
Short Circuit Current
Output Current
±40
±4
±40
±4
POWER SUPPLIES
Operating Range
Quiescent Current
+ PSRR (to VP)
– PSRR (to VN)
PSRR (Dual Supply)
PSRR (Dual Supply)
±16.5
16
±16.5
16
V
T
MIN–T MAX
13.5
86
68
13.5
86
68
mA
dB
dB
dB
DC, G = 1, Offset
DC, G = 1, Offset
DC, G = 1, ±5 to ±15 VS
DC, G = 1, ±5 to ±15 VS,
T MIN–T MAX
66
62
71
66
60
71
68
68
dB
NOT ES
1See Standard Military Drawing 5962-9313001MPA for specifications.
2Clipping level function on X channel only.
Specifications subject to change without notice.
REV. A
–3–
AD830
ABSO LUTE MAXIMUM RATINGS1
MAXIMUM P O WER D ISSIP ATIO N
T he maximum power that can be safely dissipated by the
AD830 is limited by the associated rise in junction temperature.
For the plastic packages, the maximum safe junction tempera-
ture is 145°C. For the cerdip, the maximum junction tempera-
ture is 175°C. If these maximums are exceeded momentarily,
proper circuit operation will be restored as soon as the die tem-
perature is reduced. Leaving the AD830 in the “overheated”
condition for an extended period can result in permanent dam-
age to the device. T o ensure proper operation, it is important to
observe the recommended derating curves.
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Internal Power Dissipation2 . . . . . . . Observe Derating Curves
Output Short Circuit Duration . . . . Observe Derating Curves
Common-Mode Input Voltage . . . . . . . . . . . . . . . . . . . . . . ±VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . ±VS
Storage T emperature Range (Q) . . . . . . . . . –65°C to +150°C
Storage T emperature Range (N) . . . . . . . . . –65°C to +125°C
Storage T emperature Range (R) . . . . . . . . . –65°C to +125°C
Operating T emperature Range
AD830J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
AD830A . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
AD830S . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Lead T emperature Range (Soldering 60 seconds) . . . +300°C
NOT ES
While the AD830 output is internally short circuit protected,
this may not be sufficient to guarantee that the maximum junc-
tion temperature is not exceeded under all conditions. If the
output is shorted to a supply rail for an extended period, then
the amplifier may be permanently destroyed.
1Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
28-Pin Plastic Package: θJA = 90°C/Watt
ESD SUSCEP TIBILITY
ESD (electrostatic discharge) sensitive device. Electrostatic
charges as high as 4000 volts, which readily accumulate on the
human body and on test equipment, can discharge without de-
tection. Although the AD830 features proprietary ESD protec-
tion circuitry, permanent damage may still occur on these
devices if they are subjected to high energy electrostatic dis-
charges. T herefore, proper ESD precautions are recommended
to avoid any performance degradation or loss of functionality.
8-Pin SOIC Package: θJA = 155°C/Watt
8-Pin Cerdip Package: θJA = 110°C/Watt
O RD ERING GUID E
Model
Tem perature Range
P ackage D escription
P ackage O ption
AD830AN
AD830JR
5962-9313001MPA*
–40°C to +85°C
0°C to +70°C
–55°C to +125°C
8-Pin Plastic Mini-DIP
8-Pin SOIC
8-Pin Cerdip
N-8
R-8
Q-8
*See Standard Military Drawing for specifications.
2.5
2.0
1.5
1.0
0.5
0
3.0
2.8
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
TJ MAX = 175°C
T
MAX = 145°C
J
8-PIN MINI-DIP
8-PIN CERDIP
0.8
0.6
0.4
0.2
8-PIN SOIC
–50
–30
–10
10
30
50
70
90
–60 –40 –20
0
20
40
60
80
100 120 140
AMBIENT TEMPERATURE – °C
AMBIENT TEMPERATURE – °C
Maxim um Power Dissipation vs. Tem perature,
Mini-DlP and SOIC Packages
Maxim um Power Dissipation vs. Tem perature,
Cerdip Package
–4–
REV. A
Typical Characteristics–
AD830
100
90
80
70
60
50
40
30
20
10
110
100
90
TO V @ ±15V
P
TO V @ ±5V
P
TO V @ ±15V
N
80
V
= ±15V
S
TO V @ ±5V
70
N
60
V
= ±5V
S
50
40
30
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
FREQUENCY – Hz
FREQUENCY – Hz
Figure 4. Power Supply Rejection Ratio vs. Frequency
Figure 1. Com m on-Mode Rejection Ratio vs. Frequency
3
0
–50
VOUT = 2V p-p
RL = 150Ω
GAIN = +1
±15V
–3
R
C
= 150Ω
L
±5V SUPPLIES
2ND HARMONIC
3RD HARMONIC
–60
–70
–80
–90
= 4.7pF
–6
–9
L
±10V
–12
–15
–18
–21
–24
–27
±15V SUPPLIES
2ND HARMONIC
3RD HARMONIC
±5V
10k
100k
1M
10M
100M
1G
1k
10k
100k
FREQUENCY – Hz
1M
10M
FREQUENCY – Hz
Figure 5. Closed-Loop Gain vs. Frequency G = +1
Figure 2. Harm onic Distortion vs. Frequency
3
9
8
7
6
5
4
3
±5VS
2
1
±10VS
0
–1
–2
–3
–4
±15VS
–60 –40 –20
0
20
40
60
80
100 120 140
–60 –40 –20
0
20
40
60
80
100 120 140
JUNCTION TEMPERATURE – °C
JUNCTION TEMPERATURE – °C
Figure 3. Input Bias Current vs. Tem perature
Figure 6. Input Offset Voltage vs. Tem perature
REV. A
–5–
AD830
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0.20
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0.40
0.36
0.32
0.28
0.24
0.20
0.16
0.12
0.08
0.04
GAIN = +2
= 500Ω
GAIN = +2
R = 150Ω
L
R
L
FREQ = 4.5MHz
FREQ = 4.5MHz
PHASE
GAIN
GAIN
PHASE
5
6
7
8
9
10
11
12
13
14
15
5
6
7
8
9
10
11
12
13
14
15
SUPPLY VOLTAGE – ±Volts
SUPPLY VOLTAGE – ±Volts
Figure 7. Differential Gain and Phase vs. Supply Voltage,
Figure 10. Differential Gain and Phase vs. Supply Voltage,
RL = 500 Ω
RL = 150 Ω
–40
–50
–60
–40
–50
HD2 (±5V)
4MHz
–60
HD3 (±5V)
HD3 (±5V)
100kHz
4MHz
–70
–70
HD2 (±15V)
4MHz
HD3 (±15V)
100kHz
–80
–80
–90
–90
HD3 (±15V)
4MHz
HD2 (±5V)
100kHz
HD2 (±15V)
100kHz
–100
0.25
–100
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
0.50
0.75
1.00
1.25
1.50
1.75
2.00
PEAK AMPLITUDE – Volts
PEAK AMPLITUDE – Volts
Figure 8. Harm onic Distortion vs. Peak Am plitude,
Frequency = 100 kHz
Figure 11. Harm onic Distortion vs. Peak Am plitude,
Frequency = 4 MHz
50
40
30
20
10
15.00
14.75
±16.5V
14.50
14.25
14.00
13.75
13.50
13.25
13.00
12.75
12.50
12.25
S
±5V
S
1k
10k
100k
1M
10M
–60 –40 –20
0
20
40
60
80
100 120 140
100
JUNCTION TEMPERATURE – °C
FREQUENCY – Hz
Figure 9. Noise Spectral Density
Figure 12. Supply Current vs. J unction Tem perature
–6–
REV. A
Typical Characteristics–AD830
3
0
9
AD830
V
8
1
V
1
P
G
M
6
2
A=1
7
6
5
±15V
OUT
R
C
= 150Ω
–3
3
L
3
4
= 0pF
L
G
C
M
–6
0
V
N
–9
–3
–6
–9
–12
–15
–18
–21
±5V
V
= 2V
1
–12
–15
–18
–21
–24
–27
OUT
(a)
RESISTOR LESS GAIN OF 2
AD830
8
1
2
V
V
P
N
G
M
A=1
7
6
5
OUT
3
4
V
1
G
C
M
100k
1M
10M
100M
1G
FREQUENCY – Hz
V
= V
OUT
1
(b)
Figure 13. Closed-Loop Gain vs. Frequency for the
Three Com m on Connections of Figure 16
OP-AMP CONNECTION
AD830
V
8
1
2
V
V
1
P
N
G
M
A=1
7
6
5
OUT
100mV
3
4
G
C
VS = ± 5V
M
100
90
V
= V
OUT
1
(c)
GAIN OF 1
Figure 16. Connection Diagram s
VS = ± 15V
10
1V
0%
VS = ± 5V
100
90
20ns
Figure 14. Sm all Signal Pulse Response,
RL = 150 Ω, CL = 4.7 pF, G = +1
VS = ± 15V
10
0%
20ns
9
V
= ±5V
S
6
3
R
= 150Ω
L
Figure 17. Large Signal Pulse Response,
RL = 150 Ω, CL = 4.7 pF, G = +1
C
= 33pF
= 15pF
L
0
C
L
9
6
–3
C
= 4.7pF
V
= +15V
L
S
–6
C = 33pF
L
R
= 150Ω
L
3
C
= 15pF
–9
L
0
–12
–15
–18
–21
–3
C = 4.7pF
L
–6
–9
10k
100k
1M
10M
100M
1G
–12
–15
–18
–21
FREQUENCY – Hz
Figure 15. Closed-Loop Gain vs. Frequency vs.
CL, G = +1. VS = ±5 V
10k
100k
1M
10M
100M
1G
FREQUENCY – Hz
Figure 18. Closed-Loop Gain vs. Frequency, vs.
CL, G = +1. VS = ±15 V
REV. A
–7–
AD830
TRAD ITIO NAL D IFFERENTIAL AMP LIFICATIO N
In the past, when differential amplification was needed to reject
common-mode signals superimposed with a desired signal; most
often the solution used was the classic op amp based difference
amplifier shown in Figure 19. T he basic function VO = V1–V2 is
simply achieved, but the overall performance is poor and the cir-
cuit possesses many serious problems that make it difficult to re-
alize a robust design with moderate to high levels of
performance.
AD 830 FO R D IFFERENTIAL AMP LIFICATIO N
T he AD830 amplifier was specifically developed to solve the
listed problems with the discrete difference amplifier approach.
Its topology, discussed in detail in a later section, by design acts
as a difference amplifier. T he circuit of Figure 20 shows how
simply the AD830 is configured to produce the difference of two
signals V1 and V2, in which the applied differential signal is
exactly reproduced at the output relative to a separate output
common. Any common-mode voltage present at the input is
removed by the AD830.
R
R
1
2
V
2
V
1
2
V→ I
V
R
I
3
V
X
Y
OUT
V
1
A=1
V
OUT
ONLY IF R = R = R = R
R
1
2
3
4
4
DOES
V
= V – V
OUT 1 2
I
V→ I
Figure 19. Op Am p Based Difference Am plifier
V
= V – V
1 2
OUT
P RO BLEMS WITH TH E O P AMP BASED AP P RO ACH
• Low Common-Mode Rejection Ratio (CMRR)
• Low Impedance Inputs
Figure 20. AD830 as a Difference Am plifier
• CMRR Highly Sensitive to the Value of Source R
• Different Input Impedance for the + and – Input
• Poor High Frequency CMRR
• Requires Very Highly Matched Resistors R1–R4 to Achieve
High CMRR
• Halves the Bandwidth of the Op Amp
• High Power Dissipation in the Resistors for Large Common-
Mode Voltage
AD VANTAGEO US P RO P ERTIES O F TH E AD 830
• High Common-Mode Rejection Ratio (CMRR)
• High Impedance Inputs
• Symmetrical Dynamic Response for +1 and –1 Gain
• Low Sensitivity to the Value of Source R
• Equal Input Impedance for the + and – Input
• Excellent High Frequency CMRR
• No Halving of the Bandwidth
• Constant Power Distortion vs. Common-Mode Voltage
• Highly Matched Resistors Not Needed
–8–
REV. A
AD830
UND ERSTAND ING TH E AD 830 TO P O LO GY
V
V
X1
T he AD830 represents Analog Devices’ first amplifier product
to embody a powerful alternative amplifier topology. Referred to
as active feedback, the topology used in the AD830 provides in-
herent advantages in the handling of differential signals, differ-
ing system commons, level shifting and low distortion, high
frequency amplification. In addition, it makes possible the
implementation of many functions not realizable with single op
amp circuits or is superior to op amp based equivalent circuits.
With this in mind, it is important to understand the internal
structure of the AD830.
G
M
X2
I
I
X
A=1
V
OUT
Y
C
C
V
V
Y1
G
M
Y2
T he topology, reduced to its elemental form, is shown below in
Figure 21. Nonideal effects such as nonlinearity, bias currents
and limited full scale are omitted from this model for simplicity,
but are discussed later. T he key feature of this topology is the
use of two, identical voltage-to-current converters, GM, that
make up input and feedback signal interfaces. T hey are labeled
with inputs VX and VY, respectively. T hese voltage to current
converters possess fully differential inputs, high linearity, high
input impedance and wide voltage range operation. T his enables
the part to handle large amplitude differential signals; they also
provide high common-mode rejection, low distortion and negli-
gible loading on the source. T he label, GM, is meant to convey
that the transconductance is a large signal quantity, unlike in the
front-end of most op amps. T he two GM stage current outputs
IX and IY, sum together at a high impedance node which is char-
acterized by an equivalent resistance and capacitance connected
to an “ac common.” A unity voltage gain stage follows the high
impedance node to provide buffering from loads. Relative to
either input, the open loop gain, AOL, is set by the
V
– V = V – V
X2 Y Y1
2
X1
FOR V = V
Y2
OUT
1
1 + S(C /G
V
= (V – V + V
)
Y1
OUT
X1
X2
)
M
C
Figure 22. Closed-Loop Connection
Precise amplification is accomplished through closed-loop op-
eration of this topology. Voltage feedback is implemented via
the Y GM stage in which where the output is connected to the
–Y input for negative feedback as shown in Figure 22. An input
signal is applied across the X GM stage, either fully differentially
or single-ended referred to common. It produces a current sig-
nal which is summed at the high impedance node with the out-
put current from the Y GM stage. Negative feedback nulls this
sum to a small error current necessary to develop the output
voltage at the high impedance node. T he error current is usually
negligible, so the null condition essentially forces the Y GM
output stage current to exactly equal the X GM output current.
Since the two transconductances are identical, the differential
voltage across the Y inputs equals the negative of the differential
voltage across the X input; VY = –VX or more precisely
transconductance, GM, working into the resistance, RP; AOL
=
GM ϫ RP. T he unity gain frequency ω0 dB for the open loop gain
is established by the transconductance, GM, working into the
capacitance, CC; ω0 dB = GM/CC. T he open loop description of
the AD830 is shown below for completeness.
V
Y2–VY1 = VX1–VX2. T his simple relation provides the basis to
easily analyze any function possible to synthesize with the
AD830, including any feedback situation.
T he bandwidth of the circuit is defined by the GM and the
capacitor CC. T he highly linear GM stages give the amplifier a
single pole response, excluding the output amplifier and loading
effects. It is important to note that the bandwidth and general dy-
namic behavior is symmetrical (identical) for the noninverting and
the inverting connections of the AD830. In addition, the input im-
pedance and CMRR are the same for either connections. T his is
very advantageous and unlike in a voltage or current feedback
amplifier, where there is a distinct difference in performance be-
tween the inverting and noninverting gain. T he practical impor-
tance of this cannot be overemphasized and is a key feature
offered by the AD830 amplifier topology.
V
X1
X2
G
M
V
I
I
X
Y
I
Z
A=1
V
OUT
I
I
I
= (V – V ) G
X1 X2 M
X
Y
Z
V
V
Y1
= (V – V ) G
Y1
Y2
M
C
R
G
C
P
M
= I + I
X
Y
Y2
G
R
M
P
A
=
OLS
1 + S (C R )
C
P
Figure 21. Topology Diagram
REV. A
–9–
AD830
INTERFACING TH E INP UT
D iffer ential Voltage Range
Com m on-Mode Voltage Range
T he maximum applied differential voltage is limited by the clip-
ping range of the input stages. T his is nominally set at 2.4 volts
magnitude and depicted in the crossplot (X-Y) photo of Figure
25. T he useful linear range of the input stages is set at 2 volts,
but is actually a function of the distortion required for a particu-
lar application. T he distortion increases for larger differential
input voltages. A plot of relative distortion versus input differen-
tial voltage is shown in Figures 8 and 11 in the T ypical Charac-
teristics section. T he distortion characteristics could impose a
secondary limit to the differential input voltage for high accu-
racy applications.
T he common-mode range of the AD830 is defined by the am-
plitude of the differential input signal and the supply voltage.
T he general definition of common-mode voltage, VCM, is usu-
ally applied to a symmetrical differential signal centered about a
particular voltage as illustrated by the diagram in Figure 23.
T his is the meaning implied here for common-mode voltage.
T he internal circuitry establishes the maximum allowable volt-
age on the input or feedback pins for a given supply voltage.
T his constraint and the differential input voltage sets the
common-mode voltage limit. Figure 24 shows a curve of the
common-mode voltage range vs. differential voltage for three
supply voltage settings.
1V
1V
V
MAX
100
90
V
CM
V
PEAK
Figure 23. Com m on-Mode Definition
10
0%
15
+VCM
±15V = VS
12
–VCM
Figure 25. Clipping Behavior
+VCM
9
15
±10V = VS
V
P
6
–VCM
12
9
+VCM
±5V = VS
3
V
N
–VCM
0
6
3
0
0.4
0.8
1.2
1.6
2.0
DIFFERENTIAL INPUT VOLTAGE – VPEAK
Figure 24. Input Com m on-Mode Voltage Range vs.
Differential Input Voltage
0
0
4
8
12
16
20
SUPPLY VOLTAGE – Volts
Figure 26. Maxim um Output Swing vs. Supply
–10–
REV. A
AD830
Choice of P olar ity
the peak output differential voltage can be easily derived from
T he sign of the gain is easily selected by choosing the polarity of
the connections to the + and – inputs of the X GM stage. Swap-
ping between inverting and noninverting gain is possible simply
by reversing the input connections. T he response of the ampli-
fier is identical in either connection, except for the sign change.
T he bandwidth, high impedance, transient behavior, etc., of the
AD830, is symmetrical for both polarities of gain. T his is very
advantageous and unlike an op amp.
the maximum output swing as VOCM = VMAX–VPEAK.
O utput Cur r ent
T he absolute peak output current is set by the short circuit cur-
rent limiting, typically greater that 60 mA. T he maximum drive
capability is rated at 50 mA, but without a guarantee of distor-
tion performance. Best distortion performance is obtained by
keeping the output current ≤20 mA. Attempting to drive large
voltages into low valued resistances (e.g., 10 V into 150 Ω) will
cause an apparent lowering of the limit for output signal swing,
but is just the current limiting behavior.
Input Im pedance
T he relatively high input impedance of the AD830, for a differ-
ential receiver amplifier, permits connections to modest imped-
ance sources without much loading or loss of common-mode
rejection. T he nominal input resistance is 300 kΩ. T he real limit
to the upper value of the source resistance is in its effect on
common-mode rejection and bandwidth. If the source resistance
is in only one input, then the low frequency common-mode re-
jection will be lowered to ≈ RIN/RS. T he source resistance/input
1
D r iving Cap Loads
T he AD830 is capable of driving modest sized capacitive loads
while maintaining its rated performance. Several curves of band-
width versus capacitive load are given in Figures 15 and 18. T he
AD830 was designed primarily as a low distortion video speed
amplifier, but with a tradeoff, giving up very large capacitive
load driving capability. If very large capacitive loads must be
driven, then the network shown in Figure 27 should be used to
insure stable operation. If the loss of gain caused by the resistor
RS in series with the load is objectionable, then the optional
feedback network shown may be added to restore the lost gain.
f =
× RS × CIN
capacitance pole
limits the bandwidth.
2π
Furthermore, the high frequency common-mode rejection will
be additionally lowered by the difference in the frequency re-
sponse caused by the RS ϫ CIN pole. T herefore, to maintain
good low and high frequency common-mode rejection, it is rec-
ommended that the source resistances of the + and – inputs be
matched and of modest value (≤10 kΩ).
+V
S
8
7
6
5
1
AD830
+
V
0.1µF
CM
INPUT
SIGNAL
H andling Bias Cur r ents
G
R
S
M
36.5Ω
T he bias currents are typically 4 µA flowing into each pin of the
GM stages of the AD830. Since all applications possess some fi-
nite source resistance, the bias current through this resistor will
create a voltage drop (IBIAS ϫ RS). T he relatively high input im-
pedance of the AD830 permits modest values of RS, typically
≤10 kΩ. If the source resistance is in only one terminal, then an
objectional offset voltage may result (e.g., 4 µA ϫ 5 kΩ =
20 mV). Placement of an equal value resistor in series with the
other input will cancel the offset to first order. However, due to
mismatches in the resistances, a residual offset will remain and
likely be greater than bias current (offset current) mismatches.
V
–
OUT
2
3
4
Z
CM
R
1
C
1
A=1
C
1kΩ
100pF
G
M
* OPTIONAL
FEEDBACK
NETWORK
0.1µF
–V
R
S
S
Applying Feedback
R
1
T he AD830 is intended for use with gain from 1 to 100. Gains
greater than one are simply set by a pair of resistors connected
as shown in the difference amplifier (Figure 35) with gain >1.
T he value of the bottom resistor R2, should be kept less than
1 kΩ to insure that the pole formed by CIN and the parallel con-
nection of R1 and R2 is sufficiently high in frequency so that it
does not introduce excessive phase shift around the loop and de-
stabilizes the amplifier. A compensating resistor, equal to the
parallel combination of R1 and R2, should be placed in series
with the other Y GM stage input to preserve the high frequency
common-mode rejection and to lower the offset voltage induced
by the input bias current.
Figure 27. Circuit for Driving Large Capacitive Loads
3
±15V
0
–3
±5V
–6
–9
–12
–15
–18
–21
–24
–27
O utput Com m on Mode
T he output swing of the AD830 is defined by the differential in-
put voltage, the gain and the output common. Depending on
the anticipated signal span, the output common (or ground)
may be set anywhere between the allowable peak output voltage
in a manner similar to that described for input voltage common
mode. A plot of the peak output voltage versus supply is shown
in Figure 26. A prediction of the common-mode range versus
10k
100k
1M
10M
100M
FREQUENCY – Hz
Figure 28. Closed-Loop Response vs. Frequency with
100 pF Load and Series Resistor Com pensation
REV. A
–11–
AD830
V
SUP P LIES, BYP ASSING AND GRO UND ING (FIGURE 29)
T he AD830 is capable of operating over a wide range of supply
voltages, both single and dual supplies. T he coupling may be dc
or ac provided the input and output voltages stay within the
specified common-mode voltage limits. For dual supplies, the
device works from ±4 V to ±16.5 V. Single supply operation is
possible over +8 V to +33 V. It is also possible to operate the
part with split supply voltages (e.g., +24 V, –5 V) for special
applications such as level shifting. T he primary constraint is that
the total potential between the two supplies does not exceed
33 V.
P
+
8
7
6
5
1
2
3
4
AD830
V
IN
G
G
M
V
–
OUT
+
A=1
V
ICM
–
M
C
Inclusion of power supply bypassing capacitors is necessary to
achieve stable behavior and the specified performance. It is es-
pecially important when driving low resistance loads. At a mini-
mum, connect a 0.1 µF ceramic capacitor at the supply lead of
the AD830 package. In addition, for the best by passing, we rec-
ommend connecting a 0.01 µF ceramic capacitor and 4.7 µF
tantalum capacitor to the supply lead going to the AD830.
+
–
V
OCM
V
= (V – V
) + V
OCM
OUT
IN
ICM
Figure 30. General Single Supply Connection
V
P
V
30
28
P
AND
AND
V
N
V
N
0.01µF
0.1µF
24
20
VP = +30V
4.7µF
LOAD
GND
LEAD
LOAD
GND
LEAD
VP = +15V
VP = +10V
16
12
8
(a)
(b)
Figure 29. Supply Decoupling Options
TO GND
0.4
4
T he AD830 is designed by its functionality to be capable of
rejecting noise and dissimilar potentials in the ground lines.
T herefore, proper care is necessary to realize the benefits of the
differential amplification of the part. Separation of the input and
output grounds is crucial in rejection of the common mode
noise at the inputs and eliminating any ground drops on the in-
put signal line. For example, connecting the ground of a coaxial
cable to the AD830 output common (board ground) could de-
grade the CMR and also introduce power-down loading on
cable grounds. However, it is also necessary as in any electronic
system, to provide a return path for bias currents back to their
original power supply. T his is accomplished by providing a con-
nection between the differing grounds through a modest imped-
ance labeled ZCM (e.g., 100 Ω).
0
0
0.8
1.2
1.6
2.0
DIFFERENTIAL INPUT VOLTAGE – VPEAK
Figure 31. Input Com m on-Mode Range for Single Supply
28
TO VP
24
20
16
Single Supply O per ation
12
8
T he AD830 is capable of operating in single power supply appli-
cations down to a voltage of +8 V, with the generalized connec-
tion shown in Figure 30. T here is a constraint on the
common-mode voltage at the input and output which estab-
lishes the range for these voltages. Direct coupling may be used
for input and output voltages which lie in these ranges. Any gain
network applied needs to be referred to the output common
connection or have an appropriate offset voltage. In situations
where the signal lies at a common voltage outside the common
mode range of the AD830 direct coupling will not work, so ac
coupling should be used. A tested application included later in
this data sheet (Figure 42), shows how to easily accomplish cou-
pling to the AD830. For single supply operation where direct
coupling is desired the input and output common-mode curves
(Figures 31 and 32) should be used.
TO GND
4
0
10
14
18
22
26
30
SUPPLY VOLTAGE – Volts
Figure 32. Output Swing Lim it for Single Supply
–12–
REV. A
AD830
D iffer ential Line Receiver
D iffer ence Am plifier with Gain > 1
T he AD830 was specifically designed to perform as a differen-
tial line receiver. T he circuit in Figure 33 shows how simple it is
to configure the AD830 for this function. T he signal from sys-
tem “A” is received differentially relative to A’s common, and
that voltage is exactly reproduced relative to the common in sys-
tem B. T he common-mode rejection versus frequency, shown in
Figure 1, is excellent, typically 100 dB at low frequencies. T he
high input impedance permits the AD830 to operate as a bridg-
ing amplifier across low impedance terminations with negligible
loading. T he differential gain and phase specifications are very
good as shown in Figure 7 for 500 Ω and Figure 10 for 150 Ω.
T he input and output common should be separated to achieve
the full CMR performance of the AD830 as a differential ampli-
fier. However, a common return path is necessary between sys-
tems A and B.
T he AD830 can provide instrumentation amplifier style differ-
ential amplification at gains greater than 1. T he input signal is
connected differentially and the gain is set via feedback resistors
as shown in Figure 35. T he gain, G = (R2 + R1)/R2. T he AD830
can provide either inverting or noninverting differential amplifi-
cation. T he polarity of the gain is established by the polarity of
the connection at the input. Feedback resistors R2 should gener-
ally be R2 ≤ 1 kΩ to maintain closed-loop stability and also keep
bias current induced offsets low. Highest CMRR and lowest dc
offsets are preserved by including a compensating resistor in
series with Pin 3. T he gain may be as high as 100.
V
P
0.1µF
AD830
8
V
1
2
3
4
1
V
G
G
CM
M
V
P
INPUT
SIGNAL
V
OUT
0.1µF
7
6
5
V
2
AD830
V
8
1
A=1
1
V
G
G
CM
Z
M
CM
INPUT
SIGNAL
R
R
2
1
V
OUT
C
2
3
4
7
6
5
V
2
M
A=1
0.1µF
COMMON IN
SYSTEM A
Z
CM
C
R1
M
V
N
0.1µF
R2
V
N
V
= (V – V ) (1+R /R )
1 2 1 2
OUT
V
= V – V
1
2
COMMON IN
SYSTEM
OUT
B
Figure 35. Gain of G Differential Am plifier, G > 1
O ffsetting the O utput with Gain
Figure 33. Differential Line Receiver
Wide Range Level Shifter
Some applications, such as A/D drivers, require that the signal
be amplified and also offset, typically to accommodate the input
range of the device. T he AD830 can offset the output signal
very simply through Pin 3 even with gain > 1. T he voltage ap-
plied to Pin 3 must be attenuated by an appropriate factor so
that V3 ϫ G = desired offset. In Figure 36, a resistive divider
from a voltage reference is used to produce the attenuated offset
voltage.
T he wide common-mode range and accuracy of the AD830 al-
lows easy level shifting of differential signals referred to an input
common-mode voltage to any new voltage defined at the out-
put. T he inputs may be referenced to levels as high as 10 V at
the inputs with a ±2 V swing about 10 V. In the circuit of Fig-
ure 34, the output voltage, VOUT , is defined by the simple equa-
tion shown below. T he excellent linearity and low distortion are
preserved over the full input and output common-mode range.
T he voltage sources need not be of low impedance, since the
high input resistance and modest input bias current of the
AD830 V-to-I converters permit the use of resistive voltage di-
viders as reference voltages.
V
P
0.1µF
AD830
V
1
8
7
1
V
G
CM
M
INPUT
SIGNAL
V
OUT
2
3
4
V
2
A=1
V
P
Z
CM
R
R
2
1
0.1µF
6
5
AD830
C
G
V
1
8
7
6
5
1
M
G
G
M
INPUT
SIGNAL
0.1µF
V
OUT
2
3
4
V
2
V
REF
R
A=1
1
INPUT
COMMON
V
N
R
C
2
M
R
3
0.1µF
V
3
V
= (V – V ) (1+R /R )
1 2 1 2
OUT
R
4
V
N
V
3
V
= V – V + V
1 2 3
OUT
OUTPUT
Figure 36. Offsetting the Output with Differential Gain > 1
COMMON
Figure 34. Differential Am plification with Level Shifting
REV. A
–13–
AD830
Loop Thr ough or Line Br idging Am plifier (Figur e 37)
T he AD830 is ideally suited for use as a video line bridging am-
plifier. T he video signal is tapped from the conductor of the
cable relative to its shield. T he high input impedance of the
AD830 provides negligible loading on the cable. More signifi-
cantly, the benign loading is maintained while the AD830 is
powered-down. Coupled with its good video load driving per-
formance, the AD830 is well suited to video cable monitoring
applications.
inputs VX1 and VY1 together and applying the input, VIN, to this
wired connection. T he output is exactly twice the applied volt-
age, VIN; VOUT = 2 ϫ VIN. Figure 39 below shows the connec-
tions for this highly useful application. T he most notable
characteristic of this alternative gain of two is that there is no
loss of bandwidth as in a voltage feedback op amp based gain of
+2 where the bandwidth is halved, therefore, the gain band-
width is doubled. Also, this circuit is accurate without the need
for any precise valued resistors, as in the op amp equivalents,
and it possess excellent differential gain and phase performance
as shown in Figures 40 and 41.
V
P
V
P
0.1µF
AD830
1
8
7
6
5
0.1µF
AD830
G
G
M
1
8
7
6
5
G
G
V
M
75Ω
OUT
V
R
2
3
4
IN
G
V
75Ω
OUT
A=1
2
3
4
A=1
249Ω
75Ω
M
75Ω
C
0.1µF
M
C
0.1µF
499Ω
499Ω
V
N
V
N
OPTIONAL C
C
Figure 39. Full Bandwidth Line Driver (G = +2)
.10
.20
Figure 37. Cable Tap Am plifier
Resistor less Sum m ing
GAIN = +2
= 150Ω
.09
.08
.07
.06
.05
.04
.03
.02
.01
.18
.16
.14
.12
.10
.08
.06
.04
.02
R
L
FREQ = 3.58MHz
0 TO 0.7V
Direct, two input, resistorless summing is easily realized from
the general unity gain mode. By grounding VX2 and applying the
two inputs to VX1 and VY1, the output is the exact sum of the
applied voltages V1 and V3, relative to common; VOUT = V1 +
V3. A diagram of this simple, but potent application is shown
below in Figure 38. T he AD830 summing circuit possesses sev-
eral virtues not present in the classic op amp based summing
circuits. It has high impedance inputs, no resistors, very precise
summing, high reverse isolation and noninverting gain. Achiev-
ing this function and performance with op amps requires signifi-
cantly more components.
PHASE
GAIN
5
6
7
8
9
10
11
12
13
14
15
SUPPLY VOLTAGE – ±Volts
V
P
AD830
Figure 40. Differential Gain and Phase for the Circuit of
Figure 39
1
8
G
G
M
V
1
OUT
0.2
0.1
2
3
4
7
6
5
A=1
V
= ±15V
S
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
M
C
V
3
R
= 150Ω
L
GAIN = +2
V
N
V
= V + V
1 3
OUT
V
= ±10V
S
Figure 38. Resistorless Sum m ing Am plifier
2
؋
Gain Bandwidth Line D r iver A gain of two, without the use of resistors, is possible with the
AD830. T his is accomplished by grounding VX2, tying the two
V
= ±5V
S
10k
100k
1M
10M
100M
FREQUENCY – Hz
Figure 41. 0.1 dB Gain Flatness for the Circuit of Figure 39
–14–
REV. A
AD830
AC CO UP LED LINE RECEIVER
becomes troublesome. For dual supply operation, the 10 kΩ
resistors may go directly to ground. T he output common is con-
veniently set by a Zener diode for a low impedance reference to
preserve the high frequency CMR. However, a simple resistive
divider will work fine and good high frequency CMR can be
maintained by placing a compensating resistor in series with the
+Y input. T he excellent CMRR response of the circuit is shown
in Figure 43. A plot of the 0.1 dB flatness from 10 Hz is also
shown. With the use of 10 µF capacitors, the CMR is >90 dB
down to a few tens of hertz. T his level of performance is almost
impossible to achieve with discrete solutions.
T he AD830 is configurable as an ac coupled differential ampli-
fier on a single or bipolar supply voltages. All that is needed is
inclusion of a few noncritical passive components as illustrated
below in Figure 42. A simple resistive network at the X GM
input establishes a common-mode bias. Here, the common
mode is centered at 6 volts, but in principle can be any voltage
within the common-mode limits of the AD830. T he 10 kΩ re-
sistors to each input bias the X GM stage with sufficiently high
impedance to keep the input coupling corner frequency low, but
not too large so that residual bias current induced offset voltage
+12V
INPUT
10µF
0.1µF
AD830
SIGNAL
8
1
75Ω
COAX
G
M
R
T
V
CABLE
75Ω
OUT
2
3
4
7
6
5
Z
CM
A=1
10µF
1000µF
10kΩ
10kΩ
2kΩ*
75Ω
+V
S
G
M
C
10kΩ
+12V
4.7kΩ
10kΩ
*OPTIONAL TUNING FOR
IMPROVING VERY LOW
FREQUENCY CMR.
6.8V
1N4736
Figure 42. AC Coupled Line Receiver
120
100
80
1
0
WITH CIRCUIT TRIMMED
USING EXTERNAL 2kΩ
POTENTIOMETER
–0.1
–0.2
–0.3
–0.4
–0.5
WITHOUT EXTERNAL
2kΩ POTENTIOMETER
60
–0.6
–0.7
–0.8
40
–0.9
10
20
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY – Hz
FREQUENCY – Hz
Figure 44. Am plitude Response vs. Frequency for Line
Receiver
Figure 43. Com m on-Mode Rejection vs. Frequency for
Line Receiver
REV. A
–15–
AD830
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
Cerdip (Q) P ackage
0.005 (0.13) MIN
0.055 (1.4) MAX
8
5
0.310 (7.87)
PIN 1
0.220 (5.59)
1
4
0.320 (8.13)
0.290 (7.37)
0.405 (10.29) MAX
0.060 (1.52)
0.015 (0.38)
0.200
(5.08)
MAX
0.150
(3.81)
MIN
0.015 (0.38)
0.008 (0.20)
0.200 (5.08)
0.125 (3.18)
15
°
0°
0.023 (0.58) 0.100
0.070 (1.78)
0.030 (0.76)
SEATING
PLANE
(2.54)
BSC
0.014 (0.36)
P lastic Mini-D IP (N) P ackage
8
5
0.280 (7.11)
0.240 (6.10)
PIN 1
1
4
0.325 (8.25)
0.300 (7.62)
0.430 (10.92)
0.348 (8.84)
0.060 (1.52)
0.015 (0.38)
0.195 (4.95)
0.115 (2.93)
0.210
(5.33)
MAX
0.130
(3.30)
MIN
0.015 (0.381)
0.008 (0.204)
0.160 (4.06)
0.115 (2.93)
SEATING
PLANE
0.100
(2.54)
0.022 (0.558)
0.014 (0.356)
0.070 (1.77)
0.045 (1.15)
BSC
8-P in SO IC (R) P ackage
0.198 (5.00)
0.188 (4.75)
5
8
0.158 (4.00)
0.150 (3.80)
0.244 (6.200)
0.228 (5.80)
1
4
0.050
(1.27)
TYP
0.018 (0.46)
0.014 (0.36)
0.205 (5.20)
0.181 (4.60)
0.102 (2.59)
0.094 (2.39)
0.010 (0.25)
0.004 (0.10)
0.045 (1.15)
0.020 (0.50)
0.015 (0.38)
0.007 (0.18)
All brand or product names mentioned are trademarks or registered trademarks of their respective holders.
–16–
REV. A
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