AD8203YCSURF [ADI]
High Common-Mode Voltage, Single-Supply Difference Amplifier; 高共模电压，单电源差动放大器
| 型号： | AD8203YCSURF |
| 厂家： | 
ADI |
| 描述： | High Common-Mode Voltage, Single-Supply Difference Amplifier |
| 文件： | 总20页 (文件大小：311K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Common-Mode Voltage,
Single-Supply Difference Amplifier
AD8203
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
High common-mode voltage range
−6 V to +30 V at a 5 V supply voltage
Operating temperature range: −40°C to +125°C
Supply voltage range: 3.5 V to 12 V
Low-pass filter (1-pole or 2-pole)
Excellent ac and dc performance
1 mV voltage offset (8-lead SOIC)
1 ppmꢀ°C typical gain drift
NC
6
A1
3
A2
4
+V
S
7
AD8203
100kΩ
G = ×7
+IN
A1
–IN
G = ×2
+IN
A2
–IN
8
1
+IN
–IN
5
OUT
10kΩ
200kΩ
200kΩ
10kΩ
80 dB CMRR minimum dc to 10 kHz
APPLICATIONS
2
NC = NO CONNECT
GND
Transmission control
Diesel injection control
Engine management
Figure 1. Functional Block Diagram
Adaptive suspension control
Vehicle dynamics control
INDUCTIVE
LOAD
5V
CLAMP
DIODE
OUTPUT
+IN +V
NC OUT
S
GENERAL DESCRIPTION
BATTERY
14V
The AD8203 is a single-supply difference amplifier for amplify-
ing and low-pass filtering small differential voltages in the
presence of a large common-mode voltage (CMV). The input
CMV range extends from −6 V to +30 V at a typical supply
voltage of 5 V.
4-TERM
SHUNT
AD8203
–IN GND A1
A2
POWER
DEVICE
The AD8203 is available in die and packaged form. The MSOP
and SOIC packages are specified over a wide temperature range,
from −40°C to +125°C, while the die is specified over a wider
temperature range, from −40°C to +150°C, making the AD8203
well-suited for use in many automotive platforms.
COMMON
NC = NO CONNECT
Figure 2. High Line Current Sensor
POWER
DEVICE
5V
Automotive platforms demand precision components for better
system control. The AD8203 provides excellent ac and dc
performance keeping errors to a minimum in the user’s system.
Typical offset and gain drift in the SOIC package are 0.3 μV/°C and
1 ppm/°C, respectively. Typical offset and gain drift in the MSOP
package are 2 ꢀV/°C and 1 ppm/°C, respectively. The device also
delivers a minimum CMRR of 80 dB from dc to 10 kHz.
OUTPUT
+IN +V
NC OUT
S
BATTERY
14V
4-TERM
SHUNT
AD8203
–IN GND A1
A2
CLAMP
DIODE
The AD8203 features an externally accessible 100 kΩ resistor at
the output of the Preamp A1, which can be used for low-pass
filter applications and for establishing gains other than 14.
INDUCTIVE
LOAD
COMMON
NC = NO CONNECT
Figure 3. Low Line Current Sensor
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
AD8203
TABLE OF CONTENTS
Features .............................................................................................. 1
Current Sensing.......................................................................... 14
Gain Adjustment ........................................................................ 14
Gain Trim .................................................................................... 15
Low-Pass Filtering...................................................................... 15
Applications....................................................................................... 1
Functional Block Diagrams............................................................. 1
Specifications..................................................................................... 3
Single Supply ................................................................................. 3
Absolute Maximum Ratings............................................................ 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Typical Performance Characteristics ............................................. 6
Theory of Operation ...................................................................... 12
Applications..................................................................................... 14
High Line Current Sensing with LPF and
Gain Adjustment ........................................................................ 16
Driving Charge Redistribution ADCs..................................... 16
Outline Dimensions....................................................................... 17
Ordering Guide .......................................................................... 17
REVISION HISTORY
10/05—Rev. A to Rev. B
Added SOIC Package .........................................................Universal
Replaced Figure 23 ........................................................................... 8
Added Figure 24 to Figure 29.......................................................... 9
Changes to Theory of Operation Section ................................... 12
Added Figure 41.............................................................................. 12
Updated Outline Dimensions....................................................... 17
Changes to Ordering Guide .......................................................... 17
2/05—Rev. 0 to Rev. A
Changes to Specifications Table...................................................... 3
Changes to Caption on Figure 6 and Figure 8 .............................. 6
Changes to Figure 12........................................................................ 7
Added Figure 14 to Figure 23.......................................................... 7
Changes to Figure 26 and Figure 27............................................. 10
Changes to Figure 29...................................................................... 11
Changes to Figure 32 and Figure 33............................................. 12
Changes to Ordering Guide .......................................................... 13
10/04—Revision 0: Initial Version
Rev. B | Page 2 of 20
AD8203
SPECIFICATIONS
SINGLE SUPPLY
TA = operating temperature range, VS = 5 V, unless otherwise noted.
Table 1.
AD8203 SOIC
AD8203 MSOP
AD8203 Die
Typ
Parameter
Conditions
Min
Typ
14
1
Max
Min
Typ
14
1
Max
Min
Max
Unit
SYSTEM GAIN
Initial
14
V/V
Error
0.02 ≤ VOUT ≤ 4.8 V dc @ 25°C
−0.3
+0.3
20
−0.3
+0.3
25
−0.3
+0.3
%
vs. Temperature
VOLTAGE OFFSET
Input Offset (RTI)
vs. Temperature
1
30
ppm/°C
VCM = 0.15 V; 25°C
−40°C to +125°C
−40°C to +150°C
−1
−10
+1
−2
−20
+2
+20
−1
−10
−15
+1
+10
+15
mV
μV/°C
μV/°C
+0.3 +10
+2
+0.3
+5
INPUT
Input Impedance
Differential
Common Mode
CMV
260
130
−6
320
160
380
190
+30
260
130
−6
320
160
380
190
+30
260
130
−6
320
160
380
190
+30
kΩ
kΩ
V
Continuous
VCM = −6 V to +30 V
f = dc
CMRR1
82
82
80
82
82
80
82
82
80
dB
dB
dB
f = 1 kHz
f = 10 kHz2
PREAMPLIFIER
Gain
Gain Error
Output Voltage Range
Output Resistance
OUTPUT BUFFER
Gain
7
7
7
V/V
%
V
−0.3
0.02
97
+0.3
4.8
103
−0.3
0.02
97
+0.3
4.8
103
−0.3
0.02
97
+0.3
4.8
103
100
2
100
2
100
2
kΩ
V/V
%
V
nA
Ω
Gain Error
0.02 ≤ VOUT ≤ 4.8 V dc
−0.3
0.02
+0.3
4.8
−0.3
0.02
+0.3
4.8
−0.3
0.02
+0.3
4.8
Output Voltage Range
Input Bias Current
Output Resistance
DYNAMIC RESPONSE
System Bandwidth
Slew Rate
40
2
40
2
40
2
VIN = 0.01 V p-p, VOUT = 0.14 V p-p 40
VIN = 0.28 V, VOUT = 4 V step
60
0.33
40
60
0.33
40
60
0.33
kHz
V/μs
NOISE
0.1 Hz to 10 Hz
Spectral Density, 1 kHz (RTI)
POWER SUPPLY
Operating Range
Quiescent Current vs.
Temperature
10
300
10
300
10
300
μV p-p
nV/√Hz
3.5
12
3.5
75
12
1.0
3.5
75
12
1.0
V
mA
VO = 0.1 V dc
0.25 1.0
0.25
83
0.25
83
PSRR
VS = 3.5 V to 12 V
75
83
dB
TEMPERATURE RANGE
For Specified Performance
−40
+125 −40
+125 −40
+150 °C
1 Source imbalance <2 Ω.
2 The AD8203 preamplifier exceeds 80 dB CMRR at 10 kHz. However, since the signal is available only by way of a 100 kΩ resistor, even the small amount of pin-to-pin
capacitance between Pin 1, Pin 8 and Pin 3, Pin 4 may couple an input common-mode signal larger than the greatly attenuated preamplifier output. The effect of pin-
to-pin coupling may be neglected in all applications by using filter capacitors at Node 3.
Rev. B | Page 3 of 20
AD8203
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
12.5 V
44 V
35 V
0.3 V
Supply Voltage
Transient Input Voltage (400 ms)
Continuous Input Voltage (Common Mode)
Reversed Supply Voltage Protection
Operating Temperature Range
Die
−40°C to +150°C
−40°C to +125°C
−40°C to +125°C
−65°C to +150°C
Indefinite
SOIC
MSOP
Storage Temperature
Output Short-Circuit Duration
Lead Temperature Range (Soldering 10 sec)
300°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product
features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to
high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid
performance degradation or loss of functionality.
Rev. B | Page 4 of 20
AD8203
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
–IN
GND
A1
1
2
3
4
8
7
6
5
+IN
+V
AD8203
S
NC
TOP VIEW
(Not to Scale)
A2
OUT
NC = NO CONNECT
Figure 4. Pin Configuration
Table 3. Pin Function Descriptions
1036μm
+V
S
Pin No.
Mnemonic
X
Y
1
2
3
4
5
6
7
8
−IN
−205.2
−413.0
−413.0
−308.6
+272.4
NA
−409.0
−244.6
+229.4
+410.0
+410.0
NA
GND
A1
A2
OUT
NC
+VS
OUT
+IN
+121.0
−409.0
+417.0
+205.2
1048μm
+IN
–IN
A2
GND
A1
Figure 5. Metallization Photograph
Rev. B | Page 5 of 20
AD8203
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = 5 V, VCM = 0 V, RL = 10 kΩ, unless otherwise noted.
90
80
70
60
50
40
30
20
0
–5
–55°C
–40°C
–10
–15
–20
+25°C
+125°C
–25
–30
10
0
+150°C
10
100
1k
10k
100k
3
4
5
6
7
8
9
10
11
12
FREQUENCY (Hz)
POWER SUPPLY (V)
Figure 6. Power Supply Rejection Ratio vs. Frequency
Figure 9. Negative Common-Mode Voltage vs. Voltage Supply
for Common-Mode Range −6 V to +30 V
40
25
35
+25°C
20
15
10
30
–55°C
25
+150°C
20
5
0
15
+125°C
–40°C
10
3
4
5
6
7
8
9
10
11
12
100
1k
10k
100k
1M
POWER SUPPLY (V)
FREQUENCY (Hz)
Figure 10. Positive Common-Mode Voltage vs. Voltage Supply
Figure 7. Bandwidth
100
5.0
95
90
85
80
75
4.0
3.0
70
65
2.0
60
1.0
0
55
50
10
100
1k
10k
100k
10
100
1k
10k
FREQUENCY (Hz)
LOAD RESISTANCE (Ω)
Figure 8. Common-Mode Rejection Ratio vs. Frequency
Figure 11. Output Swing vs. Load Resistance
for Common-Mode Range −6 V to +30 V
Rev. B | Page 6 of 20
AD8203
0
40
35
30
25
20
15
10
5
–6V TO +30V COMMON MODE
TEMPERATURE = 25°C
–10
–20
NO LOAD
–30
–40
–50
10kΩ LOAD
–60
–70
0
3
4
5
6
7
8
9
10
11
12
13
SUPPLY VOLTAGE (V)
CMRR (μV/V)
Figure 12. Swing Minus Supply vs. Supply Voltage
Figure 15. CMRR Distribution, Temperature = 25°C
7
V
= 5V
SUPPLY
TEMPERATURE RANGE =
+25°C TO –40°C
6
5
4
3
2
1
0
OUTPUT
4
3
INPUT
CH3 100mVΩ CH4 1.0VΩ M 20μs 2.5MS/s 400NS/PT
A CH3 260mV
V
DRIFT (μV/°C)
OS
Figure 16. Offset Drift Distribution, MSOP,
Temperature Range = +25°C to −40°C
Figure 13. Pulse Response
8
7
1000
V
= 5V
SUPPLY
800
600
400
200
0
TEMPERATURE RANGE =
25°C TO 85°C
–40°C
+25°C
6
5
4
3
2
–200
–400
–600
+85°C
+125°C
1
0
–800
–1000
–10
–5
0
5
10
15
20
25
30
35
COMMON-MODE VOLTAGE (V)
V
DRIFT (μV/°C)
OS
Figure 14. VOS vs. Common-Mode Voltage
Figure 17. Offset Drift Distribution, MSOP,
Temperature Range = 25°C to 85°C
Rev. B | Page 7 of 20
AD8203
9
8
7
6
5
4
3
2
1
0
V
= 5V
PACKAGE = MSOP @ –40°C
SUPPLY
8
7
6
5
4
3
2
1
0
TEMPERATURE RANGE =
25°C TO 125°C
V
DRIFT (μV/°C)
OS
V
(μV)
OS
Figure 18. VOS Distribution, MSOP, Temperature Range = 25°C to 125°C
Figure 21. VOS Distribution, MSOP, Temperature = −40°C
8
7
6
5
4
3
2
10
PACKAGE = MSOP @ 25°C
TEMPERATURE = 25°C
9
8
7
6
5
4
3
2
1
1
0
0
ERROR (%)
V
(μV)
OS
Figure 19. VOS Distribution, MSOP, Temperature = 25°C
Figure 22. MSOP Gain Accuracy, Temperature = 25°C
7
14
12
10
8
PACKAGE = MSOP @ 125°C
TEMPERATURE = 125°C
6
5
4
6
3
2
4
1
0
2
0
ERROR (%)
V
(μV)
OS
Figure 20. VOS Distribution, MSOP, Temperature = 125°C
Figure 23. MSOP Gain Accuracy, Temperature = 125°C
Rev. B | Page 8 of 20
AD8203
7
6
5
4
3
2
1
0
18
16
14
12
10
8
PACKAGE = MSOP
= 5V
TEMPERATURE RANGE =
TEMPERATURE = –40°C
V
SUPPLY
25°C TO 125°C
6
4
2
0
ERROR (%)
GAIN DRIFT (ppm/°C)
Figure 24. MSOP Gain Accuracy, Temperature = −40°C
Figure 27. Gain Drift Distribution, MSOP,
Temperature Range = 25°C to 125°C
14
12
10
8
12
10
8
PACKAGE = MSOP
SUPPLY
TEMPERATURE RANGE = +25°C TO –40°C
PACKAGE = SOIC @ 25°C
V
= 5V
6
6
4
4
2
2
0
0
V
(μV)
GAIN DRIFT (ppm/°C)
OS
Figure 28. VOS Distribution, SOIC, Temperature = 25°C
Figure 25. Gain Drift Distribution,
Temperature Range = +25°C to −40°C
12
10
8
9
8
7
6
5
4
3
2
1
0
PACKAGE = MSOP
= 5V
TEMPERATURE RANGE =
PACKAGE = SOIC @ 125°C
V
SUPPLY
25°C TO 85°C
6
4
2
0
GAIN DRIFT (ppm/°C)
V
(μV)
OS
Figure 26. Gain Drift Distribution, MSOP,
Temperature Range = 25°C to 85°C
Figure 29. VOS Distribution, SOIC, Temperature = 125°C
Rev. B | Page 9 of 20
AD8203
14
6
5
4
3
2
1
0
PACKAGE = SOIC
= 5V
PACKAGE = SOIC @ –40°C
V
SUPPLY
TEMPERATURE RANGE = 25°C TO 125°C
12
10
8
6
4
2
0
V
(μV)
V
DRIFT (mV/°C)
OS
OS
Figure 30. VOS Distribution, SOIC, Temperature = −40°C
Figure 33. Offset Drift Distribution, SOIC,
Temperature Range = +25°C to 125°C
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
PACKAGE = SOIC
TEMPERATURE = 25°C
V
= 5V
SUPPLY
TEMPERATURE RANGE = +25°C TO –40°C
V
DRIFT (μV/°C)
ERROR (%)
OS
Figure 31. Offset Drift Distribution, SOIC,
Temperature Range = +25°C to −40°C
Figure 34. Gain Accuracy, SOIC, Temperature = 25°C
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
PACKAGE = SOIC
= 5V
TEMPERATURE = 125°C
V
SUPPLY
TEMPERATURE RANGE = 25°C TO 85°C
V
DRIFT (μV/°C)
ERROR (%)
OS
Figure 35. Gain Accuracy, SOIC, Temperature = 125°C
Figure 32. Offset Drift Distribution, SOIC,
Temperature Range = 25°C to 85°C
Rev. B | Page 10 of 20
AD8203
12
10
8
10
9
8
7
6
5
4
3
2
1
0
TEMPERATURE = –40°C
PACKAGE = SOIC
= 5V
TEMPERATURE RANGE =
V
SUPPLY
25°C TO 85°C
6
4
2
0
ERROR (%)
GAIN DRIFT (ppm/°C)
Figure 36. Gain Accuracy, SOIC, Temperature = −40°C
Figure 38. Gain Drift Distribution, SOIC,
Temperature Range = 25°C to 85°C
10
9
8
7
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0
PACKAGE = SOIC
V = 5V
SUPPLY
TEMPERATURE RANGE =
PACKAGE = SOIC
V
= 5V
SUPPLY
TEMPERATURE RANGE =
+25°C to –40°C
25°C TO 125°C
GAIN DRIFT (ppm/°C)
GAIN DRIFT (ppm/°C)
Figure 37. Gain Drift Distribution, SOIC,
Temperature Range = +25°C to −40°C
Figure 39. Gain Drift Distribution, SOIC,
Temperature Range = 25°C to 125°C
Rev. B | Page 11 of 20
AD8203
THEORY OF OPERATION
A3 amplifier detects the common-mode signal applied to A1
and adjusts the voltage on the matched RCM resistors to reduce
the common-mode voltage range at the A1 inputs. By adjusting
the common voltage of these resistors, the common-mode input
range is extended while, at the same time, the normal mode
signal attenuation is reduced, leading to better performance
referred to input.
The AD8203 consists of a preamp and buffer, arranged as
shown in Figure 40. Like-named resistors have equal values.
The preamp incorporates a dynamic bridge (subtractor) circuit.
Identical networks (within the shaded areas) consisting of RA,
RB, RC, and RG, attenuate input signals applied to Pin 1 and
Pin 8. Note that when equal amplitude signals are asserted at
Input 1 and Input 8, and the output of A1 is equal to the
common potential (that is, 0), the two attenuators form a
balanced-bridge network. When the bridge is balanced, the
differential input voltage at A1, and thus its output, is 0.
The output of the dynamic bridge taken from A1 is connected
to Pin 3 by way of a 100 kΩ series resistor, provided for low-
pass filtering and gain adjustment. The resistors in the input
networks of the preamp and the buffer feedback resistors are
ratio-trimmed for high accuracy.
Any common-mode voltage applied to both inputs keeps the
bridge balanced and the A1 output at 0. Because the resistor
networks are carefully matched, the common-mode signal
rejection approaches this ideal state.
The output of the preamp drives a gain-of-2 buffer amplifier,
A2, implemented with carefully matched feedback resistors RF.
The 2-stage system architecture of the AD8203 enables the user
to incorporate a low-pass filter prior to the output buffer. By
separating the gain into two stages, a full-scale, rail-to-rail
signal from the preamp can be filtered at Pin 3, and a half-scale
signal, resulting from filtering, can be restored to full scale by
the output buffer amp. The source resistance seen by the
inverting input of A2 is approximately 100 kΩ to minimize the
effects of the input bias current of A2. However, this current is
quite small, and errors resulting from applications that
mismatch the resistance are correspondingly small.
However, if the signals applied to the inputs differ, the result is a
difference at the input to A1. A1 responds by adjusting its output
to drive RB, by way of RG, to adjust the voltage at its inverting
input until it matches the voltage at its noninverting input.
By attenuating voltages at Pin 1 and Pin 8, the amplifier inputs
are held within the power supply range, even if Pin 1 and Pin 8
input levels exceed the supply or fall below common (ground).
The input network also attenuates normal (differential) mode
voltages. RC and RG form an attenuator that scales A1 feedback,
forcing large output signals to balance relatively small differen-
tial inputs. The resistor ratios establish the preamp gain at 7.
The A2 input bias current has a typical value of 40 nA, however,
this can increase under certain conditions. For example, if the
input signal to the A2 amplifier is VCC/2, the output attempts to
go to VCC due to the gain of 2. However, the output saturates
because the maximum specified voltage for correct operation is
200 mV below VCC. Under these conditions the total input bias
current increases (see Figure 41 for more information).
Because the differential input signal is attenuated and then
amplified to yield an overall gain of 7, Amplifier A1 operates at
a higher noise gain, multiplying deficiencies such as input offset
voltage and noise with respect to Pin 1 and Pin 8.
+IN
8
–IN
1
–140
–120
–100
–80
–60
–40
–20
0
R
R
A
A
100kΩ
3
4
A1
5
(TRIMMED)
A2
R
R
R
R
F
F
CM
CM
A3
R
R
R
B
B
C
R
R
R
G
AD8203
G
C
2
COM
Figure 40. Simplified Schematic
0
0.5
1.0
1.5
2.0
2.5
To minimize these errors while extending the common-mode
DIFFERENTIAL MODE VOLTAGE (V)
range, a dedicated feedback loop is used to reduce the range of
common-mode voltage applied to A1 for a given overall range
at the inputs. By offsetting the range of voltage applied to the
compensator, the input common-mode range is also offset to
include voltages more negative than the power supply. The
Figure 41. A2 Input Bias Current vs. Input Voltage and Temperature. The
Shaded Area Is the Bias Current from −40°C to +125°C.
An increase in the A2 bias current, in addition to the output
saturation voltage of A1, directly affects the output voltage of
Rev. B | Page 12 of 20
AD8203
the AD8203 system (Pin 3 and Pin 4 shorted). An example of
how to calculate the correct output voltage swing of the
AD8203, by taking all variables into account, follows:
•
•
The total error at the input of A2, 24 mV, multiplied by the
buffer gain generates a resulting error of 48 mV at the
output of the buffer. This is the AD8203 system output low
saturation potential.
•
Amplifier A1 output saturation potential can go as low as
20 mV at its output.
The high output voltage range of the AD8203 is specified
as 4.8 V. Therefore, assuming a typical A2 input bias
current, the output voltage range for the AD8203 is 48 mV
to 4.8 V.
•
A2 typical input bias current of 40 nA multiplied by the
100 kΩ preamplifier output resistor produces
40 nA × 100 kΩ = 4 mV at the A2 input
For an example of the effect of changes in A2 input bias current
vs. applied input potentials, see Figure 41. The change in bias
current causes a change in error voltage at the input of the
buffer amplifier. This results in a change in overall error
potential at the output of the buffer amplifier.
•
Total voltage at the A2 input equals the output saturation
voltage of A1 combined with the voltage error generated
by the input bias current
20 mV + 4 mV = 24 mV
Rev. B | Page 13 of 20
AD8203
APPLICATIONS
+V
+V
S
The AD8203 difference amplifier is intended for applications
that require extracting a small differential signal in the presence
of large common-mode voltages. The input resistance is nominally
320 kΩ, and the device can tolerate common-mode voltages
higher than the supply voltage and lower than ground.
OUT
+IN
NC
OUT
S
V
V
DIFF
2
10kΩ
10kΩ
14R
EXT
GAIN =
R
+ 100kΩ
EXT
AD8203
GAIN
14 – GAIN
DIFF
2
R
= 100kΩ
V
The open collector output stage sources current to within
20 mV of ground and to within 200 mV of VS.
100kΩ
EXT
CM
–IN GND
A1
A2
CURRENT SENSING
R
EXT
High Line, High Current Sensing
Basic automotive applications making use of the large common-
mode range are shown in Figure 2 and Figure 3. The capability
of the device to operate as an amplifier in primary battery sup-
ply circuits is shown in Figure 2. Figure 3 illustrates the ability
of the device to withstand voltages below system ground.
NC = NO CONNECT
Figure 43. Adjusting for Gains < 14
The overall bandwidth is unaffected by changes in gain by using
this method, although there may be a small offset voltage due to
the imbalance in source resistances at the input to the buffer.
This can often be ignored, but if desired, it can be nulled by
inserting a resistor equal to 100 kΩ minus the parallel sum of
EXT and 100 kΩ, in series with Pin 4. For example, with
EXT = 100 kΩ (yielding a composite gain of ×7), the optional
offset nulling resistor is 50 kΩ.
Low Current Sensing
The AD8203 is also used in low current sensing applications,
such as the 4 to 20 mA current loop shown in Figure 42. In such
applications, the relatively large shunt resistor can degrade the
common-mode rejection. Adding a resistor of equal value on the
low impedance side of the input corrects this error.
R
R
Gains Greater Than 14
10Ω
1%
5V
Connecting a resistor from the output of the buffer amplifier to
its noninverting input, as shown in Figure 44, increases the
OUTPUT
+IN
+VS
NC OUT
gain. The gain is now multiplied by the factor REXT/(REXT
−
100 kΩ); for example, the gain is doubled for REXT = 200 kΩ.
Overall gains as high as 50 are achievable this way. Note that the
accuracy of the gain becomes critically dependent on the
resistor value at high gains. Also, the effective input offset
voltage at Pin 1 and Pin 8 (about six times the actual offset of
A1) limits the part’s use in high gain, dc-coupled applications.
+
10Ω
1%
AD8203
–IN GND A1
A2
+V
S
OUT
NC = NO CONNECT
+IN
+VS
NC
OUT
Figure 42. 4 to 20 mA Current Loop Receiver
V
V
DIFF
2
10kΩ
10kΩ
14R
EXT
GAIN =
R
– 100kΩ
EXT
GAIN ADJUSTMENT
AD8203
R
EXT
GAIN
GAIN – 14
DIFF
2
R
= 100kΩ
V
100kΩ
EXT
CM
The default gain of the preamplifier and buffer are ×7 and ×2,
respectively, resulting in a composite gain of ×14. With the
addition of external resistor(s) or trimmer(s), the gain can be
lowered, raised, or finely calibrated.
–IN GND
A1
A2
NC = NO CONNECT
Gains Less Than 14
Figure 44. Adjusting for Gains > 14
Since the preamplifier has an output resistance of 100 kΩ, an
external resistor connected from Pin 3 and Pin 4 to GND
decreases the gain by a factor REXT/(100 kΩ + REXT), as shown
in Figure 43.
Rev. B | Page 14 of 20
AD8203
Low-pass filters can be implemented in several ways by using
GAIN TRIM
the features provided by the AD8203. In the simplest case, a
single-pole filter (20 dB/decade) is formed when the output of
A1 is connected to the input of A2 via the internal 100 kΩ
resistor by strapping Pin 3, Pin 4, and a capacitor added from
this node to ground, as shown in Figure 46. If a resistor is added
across the capacitor to lower the gain, the corner frequency
increases; it should be calculated using the parallel sum of the
resistor and 100 kΩ.
Figure 45 shows a method for incremental gain trimming by
using a trim potentiometer and external resistor REXT
.
The following approximation is useful for small gain ranges:
ΔG ≈ (10 MΩ/REXT)%
Thus, the adjustment range is 2% for REXT = 5 MΩ; 10% for
R
EXT = 1 MΩ, and so on.
5V
5V
OUTPUT
OUT
+IN +VS NC OUT
+IN +VS NC OUT
V
V
DIFF
2
V
V
DIFF
2
1
f
=
C
5
2πC10
AD8203
AD8203
DIFF
2
C IN FARADS
DIFF
2
V
CM
V
CM
–IN GND A1
A2
–IN GND A1
A2
GAIN TRIM
20kΩ MIN
R
EXT
C
NC = NO CONNECT
NC = NO CONNECT
Figure 46. Single-Pole, Low-Pass Filter Using the Internal 100 kΩ Resistor
Figure 45. Incremental Gain Trim
If the gain is raised using a resistor, as shown in Figure 44, the
corner frequency is lowered by the same factor as the gain is
raised. Thus, using a resistor of 200 kΩ (for which the gain
would be doubled), the corner frequency is now 0.796 Hz μF
(0.039 μF for a 20 Hz corner frequency).
Internal Signal Overload Considerations
When configuring gain for values other than 14, the maximum
input voltage with respect to the supply voltage and ground
must be considered, since either the preamplifier or the output
buffer reaches its full-scale output (approximately VS − 0.2 V)
with large differential input voltages. The input of the AD8203
is limited to (VS − 0.2)/7 for overall gains ≤ 7, since the pre-
amplifier, with its fixed gain of ×7, reaches its full-scale output
before the output buffer. For gains greater than 7, the swing at
the buffer output reaches its full scale first and limits the
AD8203 input to (VS − 0.2)/G, where G is the overall gain.
5V
OUT
+IN +VS NC OUT
V
DIFF
2
C
AD8203
V
DIFF
2
V
CM
–IN GND A1
A2
LOW-PASS FILTERING
255kΩ
(Hz) = 1/C(μF)
In many transducer applications, it is necessary to filter the
signal to remove spurious high frequency components, includ-
ing noise, or to extract the mean value of a fluctuating signal
with a peak-to-average ratio (PAR) greater than unity. For
example, a full-wave rectified sinusoid has a PAR of 1.57, a
raised cosine has a PAR of 2, and a half-wave sinusoid has a
PAR of 3.14. Signals having large spikes can have PARs of
10 or more.
f
C
C
NC = NO CONNECT
Figure 47. 2-Pole, Low-Pass Filter
A 2-pole filter (with a roll-off of 40 dB/decade) can be implemented
using the connections shown in Figure 47. This is a Sallen-Key
form based on a ×2 amplifier. It is useful to remember that a 2-pole
filter with a corner frequency f2 and a 1-pole filter with a corner at f1
have the same attenuation at the frequency (f22/f1). The attenuation
at that frequency is 40 log (f2/f1), which is illustrated in Figure 48.
Using the standard resistor value shown and equal capacitors (see
Figure 47), the corner frequency is conveniently scaled at 1 Hz μF
(0.05 μF for a 20 Hz corner). A maximally flat response occurs
when the resistor is lowered to 196 kΩ and the scaling is then
1.145 Hz μF. The output offset is raised by approximately 5 mV
(equivalent to 250 μV at the input pins).
When implementing a filter, the PAR should be considered so
that the output of the AD8203 preamplifier (A1) does not clip
before A2, since this nonlinearity would be averaged and appear
as an error at the output. To avoid this error, both amplifiers
should be made to clip at the same time. This condition is
achieved when the PAR is no greater than the gain of the sec-
ond amplifier (2 for the default configuration). For example, if a
PAR of 5 is expected, the gain of A2 should be increased to 5.
Rev. B | Page 15 of 20
AD8203
FREQUENCY
by a 1-pole low-pass filter, shown in Figure 49, set with a corner
frequency of 3.6 Hz, which provides about 30 dB of attenuation
at 100 Hz. A higher rate of attenuation can be obtained using a
2-pole filter with fC = 20 Hz, as shown in Figure 50. Although
this circuit uses two separate capacitors, the total capacitance is
less than half that needed for the 1-pole filter.
40dB/DECADE
20dB/DECADE
40log (f /f )
2
1
INDUCTIVE
LOAD
5V
CLAMP
DIODE
OUTPUT
+IN +V
NC OUT
S
A 1-POLE FILTER, CORNER f , AND
1
A 2-POLE FILTER, CORNER f , HAVE
301kΩ
2
BATTERY
14V
THE SAME ATTENUATION –40log (f /f )
2
1
4-TERM
SHUNT
C
2
f /f
2 1
AD8203
AT FREQUENCY
50kΩ
2
f /f
2 1
f
f
1
2
–IN GND A1
A2
POWER
DEVICE
Figure 48. Comparative Responses of 1-Pole and 2-Pole Low-Pass Filters
93kΩ
HIGH LINE CURRENT SENSING WITH LPF AND
GAIN ADJUSTMENT
C
NC = NO CONNECT
COMMON
f (Hz) = 1/C(μF)
C
(0.05μF FOR f = 20Hz)
C
Figure 49 is another refinement of Figure 2, including gain
adjustment and low-pass filtering.
Figure 50. 2-Pole Low-Pass Filter
INDUCTIVE
DRIVING CHARGE REDISTRIBUTION ADCS
LOAD
5V
OUT
CLAMP
DIODE
4V/AMP
When driving CMOS ADCs, such as those embedded in popu-
lar microcontrollers, the charge injection (ΔQ) can cause a
significant deflection in the output voltage of the AD8203.
Though generally of short duration, this deflection may persist
until after the sample period of the ADC has expired due to the
relatively high open-loop output impedance (21 kΩ) of the
AD8203. Including an R-C network in the output can signifi-
cantly reduce the effect. The capacitor helps to absorb the
transient charge, effectively lowering the high frequency output
impedance of the AD8203. For these applications, the output
signal should be taken from the midpoint of the
+IN +VS NC OUT
133kΩ
BATTERY
14V
4-TERM
SHUNT
AD8203
20kΩ
–IN GND A1
A2
POWER
DEVICE
V
OS/IB
NULL
C
NC = NO CONNECT
COMMON
5% CALIBRATION RANGE
(Hz) = 0.767Hz/C(μF)
(0.22μF FOR f = 3.6Hz)
f
C
C
RLAG to CLAG combination, as shown in Figure 51.
Figure 49. High Line Current Sensor Interface;
Gain = ×40, Single-Pole Low-Pass Filter
Since the perturbations from the analog-to-digital converter are
small, the output impedance of the AD8203 appears to be low. The
transient response, therefore, has a time constant governed by the
product of the two LAG components, CLAG × RLAG. For the values
shown in Figure 51, this time constant is programmed at approxi-
mately 10 μs. Therefore, if samples are taken at several tens of
microseconds or more, there is negligible charge stack-up.
A power device that is either on or off controls the current in
the load. The average current is proportional to the duty cycle
of the input pulse and is sensed by a small value resistor. The
average differential voltage across the shunt is typically 100 mV,
although its peak value is higher by an amount that depends on
the inductance of the load and the control frequency. The
common-mode voltage, conversely, extends from roughly 1 V
above ground for the on condition to about 1.5 V above the
battery voltage for the off condition. The conduction of the
clamping diode regulates the common-mode potential applied
to the device. For example, a battery spike of 20 V may result in
an applied common-mode potential of 21.5 V to the input of
the devices.
5V
4
7
AD8203
+IN
–IN
RLAG
1kΩ
A2
MICROPROCESSOR
A/D
5
CLAG
0.01μF
10kΩ
10kΩ
To produce a full-scale output of 4 V, a gain ×40 is used, adjust-
able by 5% to absorb the tolerance in the shunt. There is
sufficient headroom to allow 10% overrange (to 4.4 V). The
roughly triangular voltage across the sense resistor is averaged
2
Figure 51. Recommended Circuit for Driving CMOS A/D
Rev. B | Page 16 of 20
AD8203
OUTLINE DIMENSIONS
3.20
3.00
2.80
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2440)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
1.27 (0.0500)
BSC
0.50 (0.0196)
0.25 (0.0099)
× 45°
1.75 (0.0688)
1.35 (0.0532)
PIN 1
0.25 (0.0098)
0.10 (0.0040)
0.65 BSC
0.95
0.85
0.75
8°
0.51 (0.0201)
0.31 (0.0122)
0° 1.27 (0.0500)
COPLANARITY
0.10
1.10 MAX
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
0.40 (0.0157)
0.80
0.60
0.40
8°
0°
0.15
0.00
0.38
0.22
0.23
0.08
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 53. 8-Lead Standard Small Outline Package [SOIC_N]
Figure 52. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Narrow Body
(R-8)
Dimensions shown in millimeters
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model
Temperature Package Package Description
Package Outline
Branding
JXA
JXA
AD8203YRMZ1
AD8203YRMZ-RL1
AD8203YRMZ-R71
AD8203YRZ1
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
8-Lead Mini Small Outline Package [MSOP]
RM-8
RM-8
RM-8
R-8
R-8
R-8
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
Die
JXA
AD8203YRZ-RL1
AD8203YRZ-R71
AD8203YCSURF
1 Z = Pb-free part.
Rev. B | Page 17 of 20
AD8203
NOTES
Rev. B | Page 18 of 20
AD8203
NOTES
Rev. B | Page 19 of 20
AD8203
NOTES
©
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05013-0-10ꢀ05(B)
Rev. B | Page 20 of 20
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