AD8178ABPZ1_技术文档

450 MHz, Triple 16 × 5

Video Crosspoint Switch

AD8178

FEATURES

FUNCTIONAL BLOCK DIAGRAM

D0 D1 D2 D3 D4 VPOS VNEG VDD DGND

Large, triple 16 × 5 high speed, nonblocking switch array

Pin compatible with the AD8175 and AD8176 (16 × 9 switch

arrays) and the AD8177 (16 × 5 switch array)

Differential or single-ended operation

Supports sync-on common-mode and sync-on color

operating modes

AD8178

A0

A1

A2

SERIN

CLR

SER/PAR

45-BIT SHIFT

RGB and HV outputs available for driving monitor directly

G = +4 operation (differential input to differential output)

Flexible power supplies: +5 V or 2.5 V

Logic ground for convenient control interface

Serial or parallel programming of switch array

High impedance output disable allows connection of

multiple devices with minimal loading on output bus

Adjustable output CM and black level through external pins

Excellent ac performance

REGISTER WITH

5-BIT PARALLEL

LOADING

1

0

WE

SEROUT

CLK

20

25

NO

CS

CONNECT

UPDATE

RST

PARALLEL LATCH

CMENC

25

5

DECODE

5 × 5:16 DECODERS

Bandwidth: 450 MHz

Slew rate: 1650 V/μs

Settling time: 4 ns to 1% to support 1600 × 1200 @ 85Hz

Low power of 2.3 W

Low all hostile crosstalk

80

INPUT

RECEIVER

G = +2

OUTPUT

BUFFER

G = +1

2

R

G

B

R

G

B

H

V

−82 dB @ 5 MHz

−47 dB @ 500 MHz

Wide input common-mode range of 4 V

Reset pin allows disabling of all outputs

Fully populated 26 × 26 ball PBGA package

(27 mm × 27 mm, 1 mm ball pitch)

SWITCH

MATRIX

G = +2

2

R

G

B

R

G

B

H

V

Convenient grouping of RGB signals for easy routing

2

APPLICATIONS

RGB video switching

KVM

Professional video

VBLK

VOCM_CMENCON

VOCM_CMENCOFF

Figure 1.

GENERAL DESCRIPTION

The AD8178 is a high speed, triple 16 × 5 video crosspoint switch

matrix. It supports 1600 × 1200 RGB displays @ 85 Hz refresh rate,

by offering a 450 MHz bandwidth and a slew rate of 1650 V/μs.

With −82 dB of crosstalk and −90 dB isolation (@ 5 MHz), the

AD8178 is useful in many high speed video applications.

The outputs can be used single-ended in conjunction with

decoded H and V outputs to drive a monitor directly.

The independent output buffers of the AD8178 can be placed

into a high impedance state to create larger arrays by paralleling

crosspoint outputs. Inputs can be paralleled as well. The AD8178

offers both serial and a parallel programming modes.

The AD8178 supports two modes of operation: differential-in

to differential-out mode with sync-on CM signaling passed

through the switch and differential-in to differential-out mode

with CM signaling removed through the switch. The output CM

and black level can be conveniently set via external pins.

The AD8178 is packaged in a fully-populated 26 × 26 ball

PBGA package and is available over the extended industrial

temperature range of −40°C to +85°C.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD8178

TABLE OF CONTENTS

Features .............................................................................................. 1

Pin Configurations and Function Descriptions............................8

Truth Table and Logic Diagram ............................................... 17

Equivalent Circuits......................................................................... 19

Typical Performance Characteristics ........................................... 21

Theory of Operation ...................................................................... 26

Applications Information.............................................................. 27

Operating Modes........................................................................ 27

Programming.............................................................................. 28

Differential and Single-Ended Operation............................... 29

Outline Dimensions....................................................................... 38

Ordering Guide .......................................................................... 38

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Characteristics (Serial Mode) ....................................... 5

Timing Characteristics (Parallel Mode).................................... 6

Absolute Maximum Ratings............................................................ 7

Thermal Resistance ...................................................................... 7

Power Dissipation......................................................................... 7

ESD Caution.................................................................................. 7

REVISION HISTORY

7/07—Revision 0: Initial Version

Rev. 0 | Page 2 of 40

AD8178

SPECIFICATIONS

V_S= 2.5 V at T_A= 25°C, G = +4, R_L= 100 Ω (each output), VBLK = 0 V, output CM voltage = 0 V, differential I/O mode, unless

otherwise noted.

Table 1.

Parameter

Conditions

Min

Typ

Max

Unit

DYNAMIC PERFORMANCE

−3 dB Bandwidth

200 mV p-p

2 V p-p

0.1 dB, 200 mV p-p

2 V p-p

1% , 2 V step

450

420

17

1.3

4

MHz

ns

Gain Flatness

Propagation Delay

Settling Time

ns

Slew Rate, Differential Output

2 V step

1650

1450

300

400

V/μs

2 V step, 10% to 90%

1 V step , 10% to 90%

Rail-to-rail, TTL load

Slew Rate, RGB Common Mode

Slew Rate, HV Outputs

NOISE/DISTORTION PERFORMANCE

Crosstalk, All Hostile

f = 5 MHz

f = 10 MHz

f = 100 MHz

f = 500 MHz

f = 10 MHz, R_L= 100 Ω, one channel

0.01 MHz to 50 MHz

−82

−74

−56

−47

−90

50

dB

nV/√Hz

Off Isolation, Input-Output

Input Voltage Noise

DC PERFORMANCE

Gain Error

1

%

Gain Matching

R, G, B same channel

0.5

32

%

Gain Temperature Coefficient

OUTPUT CHARACTERISTICS

Output Offset Voltage

ppm/°C

CMENC on or off

Temperature coefficient

CMENC on or off

20

58

10

mV

μV/°C

mV

Output Offset Voltage,

RGB Common Mode

Temperature coefficient

Enabled, differential

Disabled, differential

Disabled

No load, differential

Short circuit

−16

1.5

2.7

2

μV/°C

Ω

kΩ

pF

μA

Output Impedance

Output Disable Capacitance

Output Leakage Current

Output Voltage Range

Output Current

1

4

1

V p-p

mA

45

INPUT CHARACTERISTICS

Input Voltage Range,

Differential Mode

Input Voltage Range,

Common Mode

V p-p

V_IN= 1 V p-p

2.25

CMR, RGB Input

ΔV_{OUT, DM}/ΔV_{IN, CM}, ΔV_{IN, CM}= 0.5 V, CMENC off

ΔV_{OUT, DM}/ΔV_{IN, CM}, ΔV_{IN, CM}= 0.5 V, CMENC on

ΔV_{OUT, CM}/ΔV_{IN, CM}, ΔV_{IN, CM}= 0.5 V CMENC off

ΔV_{OUT, CM}/ΔV_{IN, CM}, ΔV_{IN, CM}= 0.5 V, CMENC on

Any switch configuration

–62

−45

−70

0

2

3.33

1

dB

pF

kΩ

μA

CM Gain, RGB Input

Input Capacitance

Input Resistance

Input Offset Current

Differential

Rev. 0 | Page 3 of 40

AD8178

Parameter

Conditions

Min

Typ

Max

Unit

SWITCHING CHARACTERISTICS

Enable On Time

50% UPDATE to 50% output

80

70

ns

Switching Time, 2 V Step

POWER SUPPLIES

Supply Current

V_POS, outputs enabled, no load

Outputs disabled

V_NEG, outputs enabled, no load

Outputs disabled

460

290

460

290

mA

V

D_VDD, outputs enabled, no load

4

Supply Voltage Range

PSR

4.5 to 5.5

−55

ΔV_{OUT, DM}/ΔV_POS, ΔV_POS= 0.5 V

ΔV_{OUT, DM}/ΔV_NEG, ΔV_NEG= 0.5 V

dB

OPERATING TEMPERATURE RANGE

Temperature Range

θ_JA

Operating (still air)

−40 to +85

15

°C

°C/W

Rev. 0 | Page 4 of 40

AD8178

TIMING CHARACTERISTICS (SERIAL MODE)

Table 2.

Limit

Typ

Parameter

Symbol

Min

40

60

Max

Unit

ns

μs

ns

Serial Data Setup Time

CLK Pulse Width

t₁

t₂

t₃

t₄

t₅

t₆

t₇

Serial Data Hold Time

CLK Pulse Separation

CLK to UPDATE Delay

UPDATE Pulse Width

CLK to SEROUT Valid

Propagation Delay, UPDATE to Switch On

Data Load Time, CLK = 5 MHz, Serial Mode

RST Time

50

140

10

90

120

80

9

140

200

t₂

t₄

1

CLK

0

LOAD DATA INTO

SERIAL REGISTER

ON FALLING EDGE

t₁

t₃

1

0

SERIN

OUT4 (D4)

OUT4 (D3)

OUT0 (D0)

t₅

t₆

1 = LATCHED

TRANSFER DATA FROM SERIAL

REGISTER TO PARALLEL

LATCHES DURING LOW LEVEL

UPDATE

0 = TRANSPARENT

t₇

1

SEROUT

0

Figure 2. Timing Diagram, Serial Mode

Table 3. Logic Levels, V_DD= 3.3 V

V_IH

V_IL

V_OH

SEROUT

V_OL

I_IH

I_IL

I_OH

I_OL

SER/PAR, CLK,

SEROUT

SER/PAR, CLK,

SEROUT

SERIN, UPDATE SERIN, UPDATE

2.0 V min 0.6 V max

2.8 V min

0.4 V max

20 μA max

–20 μA max

–1 mA min

1 mA min

Table 4. H and V Logic Levels, V_DD= 3.3 V

V_OH

V_OL

I_OH

I_OL

2.7 V min

0.5 V max

–3 mA max

3 mA max

RST

Table 5.

V_IH

Logic Levels, V_DD= 3.3 V

V_IL

I_IH

I_IL

2.0 V min

0.6 V max

−60 μA max

−120 μA max

CS

Table 6.

V_OH

Logic Levels, V_DD= 3.3 V

V_OL

I_IH

I_OL

2.0 V min

0.6 V max

100 μA max

40 μA max

Rev. 0 | Page 5 of 40

AD8178

TIMING CHARACTERISTICS (PARALLEL MODE)

Table 7.

Limit

Typ

Parameter

Symbol

Min

80

110

150

90

Max

Unit

ns

Parallel Data Setup Time

WE Pulse Width

t₁

t₂

t₃

t₄

t₅

t₆

Parallel Hold Time

ns

WE Pulse Separation

WE to UPDATE Delay

UPDATE Pulse Width

Propagation Delay, UPDATE to Switch On

RST Time

10

ns

90

ns

80

ns

140

200

ns

t₂

t₄

1

0

WE

t₁

t₃

1

D0 TO D4

A0 TO A2

0

t₅

t₆

1 = LATCHED

UPDATE

0 = TRANSPARENT

Figure 3. Timing Diagram, Parallel Mode

Table 8. Logic Levels, V_DD= 3.3 V

V_IH

V_IL

V_OH

V_OL

I_IH

I_IL

SER/PAR, WE,

I_OH

I_OL

SER/PAR, WE,

SEROUT

SER/PAR, WE,

SEROUT

D0, D1, D2, D3, D0, D1, D2, D3,

D4, A0, A1, A2, D4, A0, A1, A2,

D0, D1, D2, D3, D0, D1, D2, D3,

D4, A0, A1, A2, D4, A0, A1, A2,

A3, UPDATE

2.0 V min

0.6 V max

Disabled

20 μA max

−20 μA max

Disabled

Table 9. H and V Logic Levels, V_DD= 3.3 V

V_OH

V_OL

I_OH

I_OL

2.7 V min

0.5 V max

–3 mA max

3 mA max

RST

Table 10.

V_IH

Logic Levels, V_DD= 3.3 V

V_IL

I_IH

I_IL

2.0 V min

0.6 V max

−60 μA max

−120 μA max

CS

Table 11.

V_OH

Logic Levels, V_DD= 3.3 V

V_OL

I_IH

I_OL

2.0 V min

0.6 V max

100 μA max

40 μA max

Rev. 0 | Page 6 of 40

AD8178

ABSOLUTE MAXIMUM RATINGS

Table 12.

POWER DISSIPATION

The AD8178 is operated with 2.5 V or +5 V supplies and can

drive loads down to 100 ꢀ, resulting in a large range of possible

power dissipations. For this reason, extra care must be taken

when derating the operating conditions based on ambient

temperature.

Parameter

Rating

Analog Supply Voltage (V_POS– V_NEG

Digital Supply Voltage (V_DD– D_GND

Ground Potential Difference

)

6 V

+0.5 V to –2.5 V

(V_NEG– D_GND

Maximum Potential Difference

(V_DD– V_NEG

Common-Mode Analog Input Voltage (V_NEG– 0.5 V) to

(V_POS+ 0.5 V)

Differential Analog Input Voltage

Digital Input Voltage

Output Voltage

)

8 V

Packaged in a 676-lead BGA, the AD8178 junction-to-ambient

thermal impedance (θ_JA) is 15°C/W. For long-term reliability,

the maximum allowed junction temperature of the die should

not exceed 150°C. Temporarily exceeding this limit may cause

a shift in parametric performance due to a change in stresses

exerted on the die by the package. Exceeding a junction

temperature of 175°C for an extended period can result in

device failure. The curve in Figure 4 shows the range of allowed

internal die power dissipations that meet these conditions over

the −40°C to +85°C ambient temperature range. When using

Table 13, do not include external load power in the maximum

power calculation, but do include load current dropped on the

die output transistors.

)

2 V

V_DD

(V_POS– 1 V) to (V_NEG+ 1 V)

(Disabled Analog Output)

Output Short-Circuit Duration

Storage Temperature Range

Operating Temperature Range

Lead Temperature

(Soldering, 10 sec)

Momentary

−65°C to +125°C

−40°C to +85°C

300°C

Junction Temperature

150°C

10

T

= 150°C

J

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

9

8

7

6

5

4

3

THERMAL RESISTANCE

θ_JAis specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

15

25

35

45

55

65

75

85

Table 13. Thermal Resistance

AMBIENT TEMPERATURE (°C)

Package Type

θ_JA

Unit

Figure 4. Maximum Die Power Dissipation vs. Ambient Temperature

PBGA

15

°C/W

ESD CAUTION

Rev. 0 | Page 7 of 40

AD8178

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

VNEG

NC

VNEG

OPR4

ONB4

VPOS

IPR8

INB8

VNEG

IPR9

INB9

VPOS

IPR10

INB10

VNEG

IPR11

INB11

VPOS

IPR12

INB12

VNEG

A

B

A

VNEG

VPOS

ONB3

OPR3

VNEG

NC

VNEG

VPOS

OPB3

ONR3

VNEG

NC

VNEG

VPOS

ONG3

OPG3

VNEG

NC

VNEG

VPOS

ONR4

OPG4

H4

OPB4

ONG4

V4

VPOS

DGND

VPOS

VNEG

VPOS

DGND

VPOS

VNEG

INR8

IPG8

IPB8

ING8

VNEG

VPOS

CS

INR9

IPG9

IPB9

ING9

VPOS

INR10

IPG10

VPOS

A2

IPB10

ING10

VPOS

A1

VNEG

VPOS

A0

INR11

IPG11

VPOS

CLR

IPB11

ING11

VPOS

VDD

VPOS

DGND

VPOS

DGND

VPOS

VNEG

INR12

IPG12

VPOS

IPB12

ING12

VPOS

IPG4

VNEG

IPG13

ING13

VPOS

IPG14

ING14

VNEG

IPG15

ING15

VPOS

IPG7

VNEG

INR13

IPB13

VPOS

INR14

IPB14

VNEG

INR15

IPB15

VPOS

INR7

VNEG

IPR13

INB13

VPOS

IPR14

INB14

VNEG

IPR15

INB15

VPOS

IPR7

B

NC

C

NC

VPOS

VDD

VPOS

SEROUT

VPOS

CLK

VPOS

SERIN

VPOS

VNEG

VPOS

CMENC

VPOS

IPG1

VPOS

D

SER/PAR

VPOS

V3

VPOS

NC

VPOS

VNEG

VPOS

V0

VPOS

VNEG

VPOS

H0

E

VPOS

VNEG

VPOS

VDD

VPOS

VNEG

VPOS

RST

VPOS

VNEG

VPOS

UPDATE

VPOS

VNEG

VPOS

WE

VPOS

VNEG

VPOS

D4

VPOS

VNEG

VPOS

D3

VPOS

VNEG

VPOS

D2

VPOS

VNEG

VPOS

D1

VPOS

VNEG

VPOS

D0

VPOS

VDD

F

G

H3

H

VPOS

NC

J

K

NC

L

VPOS

ONB2

OPR2

VNEG

NC

VPOS

OPB2

ONR2

VNEG

NC

VPOS

ONG2

OPG2

VNEG

NC

VPOS

V2

M

N

M

N

VOCM_

CMENCON

H2

VBLK

P

VOCM_

CMENCOFF

VPOS

NC

R

VPOS

ING4

ING7

IPB7

INB7

T

NC

VNEG

IPG6

VNEG

INR6

VNEG

IPR6

U

VPOS

ONB1

OPR1

VNEG

VPOS

OPB1

ONR1

VNEG

VPOS

ONG1

OPG1

VNEG

VPOS

V1

V

ING6

IPB6

INB6

W

Y

W

Y

H1

VPOS

IPG5

VPOS

INR5

VPOS

IPR5

VPOS

NC

AA

AB

AC

AD

AE

AF

AA

AB

AC

AD

AE

AF

VPOS

ING0

VPOS

IPG0

VPOS

ING1

VPOS

VNEG

VPOS

ING2

VPOS

IPG2

VPOS

ING3

VPOS

IPG3

ING5

IPB5

INB5

NC

ONG0

OPB0

OPG0

ONR0

VNEG

NC

IPB0

INR0

IPB1

INR1

IPB2

INR2

IPB3

INR3

IPB4

INR4

VNEG

NC

VPOS

ONB0

OPR0

VNEG

INB0

IPR0

VPOS

INB1

IPR1

VNEG

INB2

IPR2

VPOS

INB3

IPR3

VNEG

INB4

IPR4

VNEG

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

Figure 5. Pin Configuration, Package Bottom View

Rev. 0 | Page 8 of 40

AD8178

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

A

B

VNEG

INB12

IPR12

VPOS

INB11

IPR11

VNEG

INB10

IPR10

VPOS

INB9

IPR9

VNEG

INB8

IPR8

VPOS

ONB4

OPR4

VNEG

NC

VNEG

VPOS

ONB3

OPR3

VNEG

NC

A

B

VNEG

IPR13

INB13

VPOS

IPR14

INB14

VNEG

IPR15

INB15

VPOS

IPR7

VNEG

INR13

IPB13

VPOS

INR14

IPB14

VNEG

INR15

IPB15

VPOS

INR7

VNEG

IPG13

ING13

VPOS

IPG14

ING14

VNEG

IPG15

ING15

VPOS

IPG7

IPB12

ING12

VPOS

IPG4

INR12

IPG12

VPOS

DGND

VPOS

DGND

VPOS

VNEG

6

IPB11

ING11

VPOS

VDD

INR11

IPG11

VPOS

CLR

VNEG

VPOS

A0

IPB10

ING10

VPOS

A1

INR10

IPG10

VPOS

A2

VPOS

SER/PAR

VPOS

VNEG

VPOS

D4

IPB9

ING9

INR9

IPG9

VNEG

VPOS

CS

IPB8

ING8

INR8

IPG8

VPOS

DGND

VPOS

VNEG

VPOS

DGND

VPOS

VNEG

18

OPB4

ONG4

V4

ONR4

OPG4

H4

VNEG

VPOS

21

NC

VNEG

VPOS

ONG3

OPG3

VNEG

NC

VNEG

VPOS

OPB3

ONR3

VNEG

NC

C

NC

C

D

VPOS

SERIN

VPOS

VNEG

VPOS

CMENC

VPOS

IPG1

VPOS

CLK

VPOS

SEROUT

VPOS

VNEG

VPOS

RST

VPOS

VDD

NC

D

E

VPOS

VNEG

VPOS

H0

VPOS

VNEG

VPOS

V0

VPOS

NC

VPOS

V3

E

F

VPOS

VDD

VPOS

VNEG

VPOS

D0

VPOS

VNEG

VPOS

D1

VPOS

VNEG

VPOS

D2

VPOS

VNEG

VPOS

D3

VPOS

VNEG

VPOS

WE

VPOS

VNEG

VPOS

UPDATE

VPOS

15

VPOS

VNEG

VPOS

VDD

F

G

H

H3

H

J

VPOS

NC

J

K

L

NC

L

M

N

VPOS

V2

VPOS

ONG2

OPG2

VNEG

NC

VPOS

OPB2

ONR2

VNEG

NC

VPOS

ONB2

OPR2

VNEG

NC

M

N

VOCM_

CMENCON

P

VBLK

H2

P

VOCM_

CMENCOFF

R

VPOS

NC

R

T

INB7

IPB7

ING7

VPOS

ING4

IPB4

T

U

VNEG

IPR6

VNEG

INR6

VNEG

IPG6

NC

U

V

VPOS

V1

VPOS

ONG1

OPG1

VNEG

24

VPOS

OPB1

ONR1

VNEG

25

VPOS

ONB1

OPR1

VNEG

26

V

W

Y

INB6

IPB6

ING6

W

Y

VPOS

IPR5

VPOS

INR5

VPOS

IPG5

H1

AA

AB

AC

AD

AE

AF

VPOS

NC

AA

AB

AC

AD

AE

AF

INB5

IPB5

ING5

VPOS

IPG3

VPOS

ING3

VPOS

9

VPOS

IPG2

VPOS

ING2

VPOS

VNEG

12

VPOS

ING1

VPOS

IPG0

VPOS

ING0

VNEG

1

VNEG

2

VNEG

3

OPG0

ONR0

OPR0

19

ONG0

OPB0

ONB0

20

NC

INR4

INR3

IPB3

INR2

IPB2

INR1

IPB1

INR0

IPB0

NC

IPR4

INB4

5

IPR3

INB3

IPR2

INB2

IPR1

INB1

IPR0

INB0

NC

4

7

8

10

11

13

14

16

17

22

23

Figure 6. Pin Configuration, Package Top View

Rev. 0 | Page 9 of 40

AD8178

Table 14. Ball Grid Description

Ball No. Mnemonic

Description

Ball No. Mnemonic

Description

A1

A2

A3

A4

A5

A6

A7

A8

VNEG

INB12

IPR12

VPOS

INB11

IPR11

VNEG

INB10

IPR10

VPOS

INB9

Negative Analog Power Supply.

Input Number 12, Negative Phase.

Input Number 12, Positive Phase.

Positive Analog Power Supply.

Input Number 11, Negative Phase.

Input Number 11, Positive Phase.

Negative Analog Power Supply.

Input Number 10, Negative Phase.

Input Number 10, Positive Phase.

Positive Analog Power Supply.

Input Number 9, Negative Phase.

Input Number 9, Positive Phase.

Negative Analog Power Supply.

Input Number 8, Negative Phase.

Input Number 8, Positive Phase.

Positive Analog Power Supply.

Output Number 4, Negative Phase.

Output Number 4, Positive Phase.

Negative Analog Power Supply.

No Connect.

B26

C1

C2

C3

C4

C5

C6

C7

C8

VNEG

ING12

IPG12

VPOS

ING11

IPG11

VNEG

ING10

IPG10

VPOS

ING9

IPG9

VNEG

ING8

IPG8

VPOS

ONG4

OPG4

VNEG

NC

Negative Analog Power Supply.

Input Number 12, Negative Phase.

Input Number 12, Positive Phase.

Positive Analog Power Supply.

Input Number 11, Negative Phase.

Input Number 11, Positive Phase.

Negative Analog Power Supply.

Input Number 10, Negative Phase.

Input Number 10, Positive Phase.

Positive Analog Power Supply.

Input Number 9, Negative Phase.

Input Number 9, Positive Phase.

Negative Analog Power Supply.

Input Number 8, Negative Phase.

Input Number 8, Positive Phase.

Positive Analog Power Supply.

Output Number 4, Negative Phase.

Output Number 4, Positive Phase.

Negative Analog Power Supply.

No Connect.

A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

B1

B2

B3

B4

B5

B6

B7

B8

B9

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

C9

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

C25

C26

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

IPR9

VNEG

INB8

IPR8

VPOS

ONB4

OPR4

VNEG

NC

No Connect.

VNEG

IPB12

INR12

VPOS

IPB11

INR11

VNEG

IPB10

INR10

VPOS

IPB9

Negative Analog Power Supply.

Input Number 12, Positive Phase.

Input Number 12, Negative Phase.

Positive Analog Power Supply.

Input Number 11, Positive Phase.

Input Number 11, Negative Phase.

Negative Analog Power Supply.

Input Number 10, Positive Phase.

Input Number 10, Negative Phase.

Positive Analog Power Supply.

Input Number 9, Positive Phase.

Input Number 9, Negative Phase.

Negative Analog Power Supply.

Input Number 8, Positive Phase.

Input Number 8, Negative Phase.

Positive Analog Power Supply.

Output Number 4, Positive Phase.

Output Number 4, Negative Phase.

Negative Analog Power Supply.

No Connect.

NC

No Connect.

VNEG

IPR13

INR13

IPG13

VPOS

V4

Negative Analog Power Supply.

Input Number 13, Positive Phase.

Input Number 13, Negative Phase.

Input Number 13, Positive Phase.

Positive Analog Power Supply.

Output Number 4, V Sync.

INR9

VNEG

IPB8

INR8

VPOS

OPB4

ONR4

VNEG

NC

VNEG

H4

VPOS

NC

VNEG

Output Number 4, H Sync.

Positive Analog Power Supply.

No Connect.

Negative Analog Power Supply.

No Connect.

Negative Analog Power Supply.

Rev. 0 | Page 10 of 40

AD8178

Ball No. Mnemonic

Description

Ball No. Mnemonic

Description

D25

D26

E1

E2

E3

E4

E5

E6

E7

VNEG

INB13

IPB13

ING13

VPOS

DGND

VDD

CLR

A0

A1

A2

Negative Analog Power Supply.

Input Number 13, Negative Phase.

Input Number 13, Positive Phase.

Input Number 13, Negative Phase.

Positive Analog Power Supply.

Digital Power Supply.

F25

F26

G1

G2

G3

G4

G5

G6

G7

VPOS

V3

ONG3

OPB3

ONB3

IPR14

INR14

IPG14

VPOS

VNEG

VPOS

H3

Positive Analog Power Supply.

Output Number 3, V Sync.

Output Number 3, Negative Phase.

Output Number 3, Positive Phase.

Output Number 3, Negative Phase.

Input Number 14, Positive Phase.

Input Number 14, Negative Phase.

Input Number 14, Positive Phase.

Positive Analog Power Supply.

Negative Analog Power Supply.

Positive Analog Power Supply.

Output Number 3, H Sync.

Digital Power Supply.

Internal Register Clearing

E8

E9

G8

G9

Control Pin 0, Output Address Bit 0.

Control Pin 1, Output Address Bit 1.

Control Pin 2, Output Address Bit 2.

Control Pin: Serial Parallel Select Mode.

Control Pin: Serial Data In.

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

E21

E22

E23

E24

E25

E26

F1

F2

F3

F4

F5

F6

F7

F8

F9

F10

F11

F12

F13

F14

F15

F16

F17

F18

F19

F20

F21

F22

F23

F24

G10

G11

G12

G13

G14

G15

G16

G17

G18

G19

G20

G21

G22

G23

G24

G25

G26

H1

H2

H3

H4

H5

H6

H7

H8

H9

H10

H11

H12

H13

H14

H15

H16

H17

H18

H19

H20

H21

H22

H23

H24

SER/PAR

SERIN

CLK

Control Pin: Serial Data Clock.

Control Pin: Chip Select.

CS

SEROUT

VDD

Control Pin: Serial Data Out.

Digital Power Supply.

DGND

VPOS

VNEG

VPOS

Positive Analog Power Supply.

Negative Analog Power Supply.

Positive Analog Power Supply.

OPG3

Output Number 3, Positive Phase.

Rev. 0 | Page 11 of 40

AD8178

Ball No. Mnemonic

Description

Ball No. Mnemonic

Description

H25

H26

J1

J2

J3

J4

J5

J6

J7

ONR3

OPR3

INB14

IPB14

ING14

VPOS

VNEG

VPOS

VNEG

VPOS

VNEG

VPOS

NC

Output Number 3, Negative Phase.

Output Number 3, Positive Phase.

Input Number 14, Negative Phase.

Input Number 14, Positive Phase.

Input Number 14, Negative Phase.

Positive Analog Power Supply.

Negative Analog Power Supply.

Positive Analog Power Supply.

Negative Analog Power Supply.

Positive Analog Power Supply.

Negative Analog Power Supply.

Positive Analog Power Supply.

No Connect.

K25

K26

L1

L2

L3

L4

L5

L6

L7

NC

No Connect.

IPR15

INR15

IPG15

VPOS

VNEG

VPOS

NC

Input Number 15, Positive Phase.

Input Number 15, Negative Phase.

Input Number 15, Positive Phase.

Positive Analog Power Supply.

Negative Analog Power Supply.

Positive Analog Power Supply.

No Connect.

J8

J9

L8

L9

J10

J11

J12

J13

J14

J15

J16

J17

J18

J19

J20

J21

J22

J23

J24

J25

J26

K1

K2

K3

K4

K5

K6

K7

K8

K9

K10

K11

K12

K13

K14

K15

K16

K17

K18

K19

K20

K21

K22

K23

K24

L10

L11

L12

L13

L14

L15

L16

L17

L18

L19

L20

L21

L22

L23

L24

L25

L26

M1

M2

M3

M4

M5

M6

M7

M8

M9

M10

M11

M12

M13

M14

M15

M16

M17

M18

M19

M20

M21

M22

M23

M24

NC

No Connect.

INB15

IPB15

ING15

VPOS

VNEG

VPOS

Input Number 15, Negative Phase.

Input Number 15, Positive Phase.

Input Number 15, Negative Phase.

Positive Analog Power Supply.

Negative Analog Power Supply.

Positive Analog Power Supply.

NC

No Connect.

Rev. 0 | Page 12 of 40

AD8178

Ball No. Mnemonic

Description

Ball No. Mnemonic

Description

M25

M26

N1

N2

N3

VPOS

Positive Analog Power Supply.

P25

P26

R1

R2

R3

ONR2

OPR2

IPR7

INR7

IPG7

VPOS

Output Number 2, Negative Phase.

Output Number 2, Positive Phase.

Input Number 7, Positive Phase.

Input Number 7, Negative Phase.

Input Number 7, Positive Phase.

Positive Analog Power Supply.

N4

R4

N5

VOCM_

CMENCON

Output CM Reference with CM

Encoding On.

R5

VOCM_

CMENCOFF

Output Reference with CM

Encoding Off.

N6

N7

N8

N9

VPOS

VNEG

VPOS

V2

ONG2

OPB2

ONB2

VPOS

VBLK

VPOS

VNEG

VPOS

H2

Positive Analog Power Supply.

Negative Analog Power Supply.

Positive Analog Power Supply.

Output Number 2, V Sync.

Output Number 2, Negative Phase.

Output Number 2, Positive Phase.

Output Number 2, Negative Phase.

Positive Analog Power Supply.

Output Blank Level.

Positive Analog Power Supply.

Negative Analog Power Supply.

Positive Analog Power Supply.

Output Number 2, H Sync.

R6

R7

R8

R9

VPOS

VNEG

VPOS

VNEG

INB7

Positive Analog Power Supply.

Negative Analog Power Supply.

Positive Analog Power Supply.

Negative Analog Power Supply.

Input Number 7, Negative Phase.

Input Number 7, Positive Phase.

Input Number 7, Negative Phase.

Positive Analog Power Supply.

Negative Analog Power Supply.

Positive Analog Power Supply.

No Connect.

N10

N11

N12

N13

N14

N15

N16

N17

N18

N19

N20

N21

N22

N23

N24

N25

N26

P1

P2

P3

P4

P5

P6

P7

P8

P9

P10

P11

P12

P13

P14

P15

P16

P17

P18

P19

P20

P21

P22

P23

P24

R10

R11

R12

R13

R14

R15

R16

R17

R18

R19

R20

R21

R22

R23

R24

R25

R26

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

T21

T22

T23

T24

IPB7

ING7

VPOS

VNEG

VPOS

NC

OPG2

Output Number 2, Positive Phase.

NC

No Connect.

Rev. 0 | Page 13 of 40

AD8178

Ball No. Mnemonic

Description

Ball No. Mnemonic

Description

T25

T26

U1

U2

U3

U4

U5

U6

U7

NC

No Connect.

V25

V26

W1

W2

W3

W4

W5

W6

W7

VPOS

INB6

Positive Analog Power Supply.

Input Number 6, Negative Phase.

Input Number 6, Positive Phase.

Input Number 6, Negative Phase.

Positive Analog Power Supply.

Negative Analog Power Supply.

Positive Analog Power Supply.

Output Number 1, V Sync.

Output Number 1, Negative Phase.

Output Number 1, Positive Phase.

Output Number 1, Negative Phase.

Positive Analog Power Supply.

Output Number 1, H Sync.

VNEG

VPOS

VNEG

VPOS

NC

Negative Analog Power Supply.

Positive Analog Power Supply.

Negative Analog Power Supply.

Positive Analog Power Supply.

No Connect.

IPB6

ING6

VPOS

VNEG

VPOS

V1

ONG1

OPB1

ONB1

VPOS

H1

U8

U9

W8

W9

U10

U11

U12

U13

U14

U15

U16

U17

U18

U19

U20

U21

U22

U23

U24

U25

U26

V1

V2

V3

V4

V5

V6

V7

V8

V9

V10

V11

V12

V13

V14

V15

V16

V17

V18

V19

V20

V21

V22

V23

V24

W10

W11

W12

W13

W14

W15

W16

W17

W18

W19

W20

W21

W22

W23

W24

W25

W26

Y1

Y2

Y3

Y4

Y5

Y6

Y7

Y8

Y9

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

Y19

Y20

Y21

Y22

Y23

Y24

NC

IPR6

INR6

IPG6

No Connect.

Input Number 6, Positive Phase.

Input Number 6, Negative Phase.

Input Number 6, Positive Phase.

Positive Analog Power Supply.

Negative Analog Power Supply.

Positive Analog Power Supply.

VPOS

VNEG

VPOS

OPG1

Output Number 1, Positive Phase.

Rev. 0 | Page 14 of 40

AD8178

Ball No. Mnemonic

Description

Ball No. Mnemonic

Description

Y25

Y26

AA1

AA2

AA3

AA4

AA5

AA6

ONR1

OPR1

VPOS

VNEG

IPR5

Output Number 1, Negative Phase.

Output Number 1, Positive Phase.

Positive Analog Power Supply.

Negative Analog Power Supply.

Input Number 5, Positive Phase.

Input Number 5, Negative Phase.

Input Number 5, Positive Phase.

Positive Analog Power Supply.

Digital Power Supply.

AB25

AB26

AC1

AC2

AC3

AC4

AC5

AC6

AC7

VNEG

INB5

IPB5

Negative Analog Power Supply.

Input Number 5, Negative Phase.

Input Number 5, Positive Phase.

Input Number 5, Negative Phase.

Positive Analog Power Supply.

Output Number 0, H Sync.

ING5

VPOS

H0

AA7

AA8

AA9

AC8

AC9

AA10

AA11

AA12

AA13

AA14

AA15

AA16

AA17

AA18

AA19

AA20

AA21

AA22

AA23

AA24

AA25

AA26

AB1

AB2

AB3

AB4

AB5

AB6

AB7

AB8

AB9

AB10

AB11

AB12

AB13

AB14

AB15

AB16

AB17

AB18

AB19

AB20

AB21

AB22

AB23

AB24

AC10

AC11

AC12

AC13

AC14

AC15

AC16

AC17

AC18

AC19

AC20

AC21

AC22

AC23

AC24

AC25

AC26

AD1

AD2

AD3

AD4

AD5

AD6

AD7

AD8

AD9

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

V0

VPOS

NC

Output Number 0, V Sync.

Positive Analog Power Supply.

No Connect.

NC

No Connect.

VNEG

IPG4

ING4

VNEG

IPG3

ING3

VPOS

IPG2

ING2

VNEG

IPG1

ING1

VPOS

IPG0

ING0

VNEG

OPG0

ONG0

VPOS

NC

Negative Analog Power Supply.

Input Number 4, Positive Phase.

Input Number 4, Negative Phase.

Negative Analog Power Supply.

Input Number 3, Positive Phase.

Input Number 3, Negative Phase.

Positive Analog Power Supply.

Input Number 2, Positive Phase.

Input Number 2, Negative Phase.

Negative Analog Power Supply.

Input Number 1, Positive Phase.

Input Number 1, Negative Phase.

Positive Analog Power Supply.

Input Number 0, Positive Phase.

Input Number 0, Negative Phase.

Negative Analog Power Supply.

Output Number 0, Positive Phase.

Output Number 0, Negative Phase.

Positive Analog Power Supply.

No Connect.

INR5

IPG5

VPOS

DGND

VDD

D0

D1

D2

D3

Digital Power Supply.

Control Pin, Input Address Bit 0.

Control Pin, Input Address Bit 1.

Control Pin, Input Address Bit 2.

Control Pin, Input Address Bit 3.

Control Pin, Input Address Bit 4.

Control Pin, Pass/Stop CM Encoding.

Control Pin, 1st Rank Write Strobe.

Control Pin, 2nd Rank Write Strobe.

Control Pin, 2nd Rank Data Reset.

Digital Power Supply.

D4

CMENC

WE

UPDATE

RST

VDD

DGND

VPOS

VNEG

Digital Power Supply.

Positive Analog Power Supply.

Negative Analog Power Supply.

NC

VNEG

No Connect.

Negative Analog Power Supply.

Rev. 0 | Page 15 of 40

AD8178

Ball No. Mnemonic

Description

Ball No. Mnemonic

Description

AD25

AD26

AE1

AE2

AE3

AE4

AE5

AE6

AE7

VNEG

INR4

IPB4

VNEG

INR3

IPB3

VPOS

INR2

IPB2

VNEG

INR1

IPB1

VPOS

INR0

IPB0

VNEG

ONR0

OPB0

VPOS

NC

Negative Analog Power Supply.

Input Number 4, Negative Phase.

Input Number 4, Positive Phase.

Negative Analog Power Supply.

Input Number 3, Negative Phase.

Input Number 3, Positive Phase.

Positive Analog Power Supply.

Input Number 2, Negative Phase.

Input Number 2, Positive Phase.

Negative Analog Power Supply.

Input Number 1, Negative Phase.

Input Number 1, Positive Phase.

Positive Analog Power Supply.

Input Number 0, Negative Phase.

Input Number 0, Positive Phase.

Negative Analog Power Supply.

Output Number 0, Negative Phase.

Output Number 0, Positive Phase.

Positive Analog Power Supply.

No Connect.

AE26

AF1

AF2

AF3

AF4

AF5

AF6

AF7

AF8

VNEG

IPR4

INB4

VNEG

IPR3

INB3

VPOS

IPR2

INB2

VNEG

IPR1

INB1

VPOS

IPR0

INB0

VNEG

OPR0

ONB0

VPOS

NC

Negative Analog Power Supply.

Input Number 4, Positive Phase.

Input Number 4, Negative Phase.

Negative Analog Power Supply.

Input Number 3, Positive Phase.

Input Number 3, Negative Phase.

Positive Analog Power Supply.

Input Number 2, Positive Phase.

Input Number 2, Negative Phase.

Negative Analog Power Supply.

Input Number 1, Positive Phase.

Input Number 1, Negative Phase.

Positive Analog Power Supply.

Input Number 0, Positive Phase.

Input Number 0, Negative Phase.

Negative Analog Power Supply.

Output Number 0, Positive Phase.

Output Number 0, Negative Phase.

Positive Analog Power Supply.

No Connect.

AE8

AE9

AF9

AF10

AF11

AF12

AF13

AF14

AF15

AF16

AF17

AF18

AF19

AF20

AF21

AF22

AF23

AF24

AF25

AF26

AE10

AE11

AE12

AE13

AE14

AE15

AE16

AE17

AE18

AE19

AE20

AE21

AE22

AE23

AE24

AE25

NC

No Connect.

NC

VNEG

No Connect.

Negative Analog Power Supply.

VNEG

Negative Analog Power Supply.

Rev. 0 | Page 16 of 40

AD8178

TRUTH TABLE AND LOGIC DIAGRAM

Table 15. Operation Truth Table

WE

X¹

UPDATE CLK

RST

SER/PAR CS

SERIN

SEROUT

CMENC

Operation/Comment

X

0

X

Asynchronous reset. All outputs

are disabled. Contents of the

45-bit shift register are

unchanged.

1

0

1

SERIN_i

SERIN_i-45

1

0

X

Serial mode. The data on the

SERIN line is loaded into the

45-bit shift register. The first bit

clocked into the shift register

appears at SEROUT 45 clock

cycles later. Data is not applied

to the switch array.

Parallel mode. The data on

parallel lines D0 through D4 is

loaded into the shift register

location addressed by A0

through A2. Data is not applied

to the switch array.

1

X

1

0

1

0

1

X

1

X

1

0

X

Switch array update. Data in

the 45-bit shift register is trans-

ferred to the parallel latches

and applied to the switch array.

X

No change in logic.

¹X = don’t care.

Rev. 0 | Page 17 of 40

AD8178

2 8 0 8 - 6 0 0 6

R

D E C E O D 5 O T 3

S S R E A D D

T U P T O U

Figure 7. Logic Diagram

Rev. 0 | Page 18 of 40

AD8178

EQUIVALENT CIRCUITS

VPOS

0.1pF

10kΩ

OPn, ONn

VBLK,

VOCM_CMENCOFF

0.1pF

1kΩ

VNEG

(VPOS – VNEG)

2

Figure 13. VBLK and VOCM_CMENCOFF Inputs

(see also ESD Protection Map, Figure 19)

Figure 8. Enabled Output (see also ESD Protection Map, Figure 19)

VPOS

20kΩ

OPn

20kΩ

0.3pF

3.33kΩ

3.4pF

VNEG

VOCM_CMENCON

0.4pF

3.1kΩ

VPOS

0.3pF

3.4pF

20kΩ

ONn

20kΩ

VNEG

Figure 9. Disabled Output (see also ESD Protection Map, Figure 19

)

Figure 14. VOCM_CMENCON Input (see also ESD Protection Map, Figure 19

)

2500Ω

10kΩ

5050Ω

VDD

IPn

1.3pF

25kΩ

0.3pF

1kΩ

RST

INn

2500Ω

5050Ω

DGND

Figure 10. Receiver Differential (see also ESD Protection Map, Figure 19)

RST

Figure 15.

Input (see also ESD Protection Map, Figure 19)

IPn

1.3pF

2500Ω

0.3pF

CLK, SER/PAR, WE,

UPDATE, SERIN

A[2:0], D[4:0],

CMENC

10kΩ

1kΩ

2500Ω

1.3pF

INn

DGND

Figure 11. Receiver Simplified Equivalent Circuit When Driving Differentially

Figure 16. Logic Input (see also ESD Protection Map, Figure 19)

IPn

1kΩ

1.6pF

2.5kΩ

CS

25kΩ

INn

DGND

Figure 12. Receiver Simplified Equivalent Circuit When Driving Single-Ended

CS

Figure 17. Input (see also ESD Protection Map, Figure 19)

Rev. 0 | Page 19 of 40

AD8178

VDD

VPOS

VDD

CLK, RST,

SER/PAR,

WE,

UPDATE,

SERIN,

SEROUT,

A[2:0],

IPn, INn,

OPn, ONn, VBLK,

VOCM_CMENCOFF

VOCM_CMENCON

SEROUT,

H, V

D[4:0],

CMENC,

CS

DGND

VNEG

DGND

Figure 18.SEROUT, H, V Logic Outputs

(see also ESD Protection Map, Figure 19)

Figure 19. ESD Protection Map

Rev. 0 | Page 20 of 40

AD8178

TYPICAL PERFORMANCE CHARACTERISTICS

V_S= 2.5 V at T_A= 25°C, G = +2, R_L= 100 Ω (each output), VBLK = 0 V, output CM voltage = 0 V, differential I/O mode, unless

otherwise noted.

0.15

0.10

0.05

0

20

18

16

14

12

10

8

–0.05

–0.10

–0.15

6

4

2

0

2

4

6

8

10

12

14

16

18

20

1

10

100

1000

TIME (ns)

FREQUENCY (MHz)

Figure 20. Small Signal Frequency Response, 200 mV p-p

Figure 23. Small Signal Pulse Response, 200 mV p-p

18

1.5

1.0

16

14

12

10

8

0.5

0

6

–0.5

–1.0

–1.5

4

2

0

–2

1

10

100

0

2

4

6

8

10

12

14

16

18

20

FREQUENCY (MHz)

TIME (ns)

Figure 21. Large Signal Frequency Response, 2 V p-p

Figure 24. Large Signal Pulse Response, 2 V p-p

22

20

18

16

14

12

10

8

15

1.2

10pF

5pF

2pF

V

OUT

10

5

0.9

V

IN

0pF

0.6

0

0.3

ERROR

–5

0

–10

–15

–20

–25

–0.3

–0.6

–0.9

–1.2

6

4

2

0

1

10

100

0

1

2

3

4

5

6

7

8

FREQUENCY (MHz)

TIME (ns)

Figure 22. Small Signal Frequency Response with Capacitive Loads

Figure 25. Settling Time

Rev. 0 | Page 21 of 40

AD8178

5

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

4

3

2

1

0

–1

–2

–3

–4

–5

0

1

2

3

4

5

6

7

8

1

10

100

1000

TIME (ns)

FREQUENCY (MHz)

Figure 26. Settling Time, 1% Zoom

Figure 29. Crosstalk, All Hostile

2

1

6000

5000

4000

3000

2000

1000

0

–20

0

–40

–1

–2

–3

–4

–5

–60

1650V/µs PEAK

–80

–100

–120

–1000

10

0

1

2

3

4

5

6

7

8

9

10

100

TIME (ns)

FREQUENCY (MHz)

Figure 27. Large Signal Rising Edge Slew Rate

Figure 30. Crosstalk, Off Isolation

0

–10

–20

–30

–40

–50

–60

–70

–10

–20

–30

–40

–50

–60

–70

–80

CMENC HIGH

CMENC LOW

1

10

100

1000

10

100

FREQUENCY (MHz)

Figure 28. Crosstalk, All Hostile, Single-Ended

Figure 31. Common-Mode Rejection

Rev. 0 | Page 22 of 40

AD8178

600

500

400

300

200

100

0

10000

|I

| AND |I

NEG

|

POS

(BROADCAST)

1000

|I

| AND |I

|

POS

NEG

(ALL OUTPUTS DISABLED)

100

–50 –40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90 100

1

10

100

1000

TEMPERATURE (°C)

FREQUENCY (MHz)

Figure 32. Quiescent Supply Currents vs. Temperature

Figure 35. Input Impedance

3000

2500

2000

1500

1000

500

10000

1000

0

100

1

10

100

1000

10

100

1000

FREQUENCY (MHz)

Figure 33. Output Impedance, Disabled

Figure 36. Input Impedance, Single-Ended

100

90

80

70

60

50

40

30

20

10

0

–10

–20

–30

–40

–50

–60

–70

–80

1

10

100

1000

10

100

1000

FREQUENCY (MHz)

Figure 34. Output Impedance, Enabled

Figure 37. Output Balance Error

Rev. 0 | Page 23 of 40

AD8178

1.0

0.5

0

20

15

10

5

1400

1200

1000

800

600

400

200

0

RED

GREEN

BLUE

–0.5

VSYNC

HSYNC

0

–1.0

–1.5

–5

0

100 200 300 400 500 600 700 800 900 1000

–70 –60 –50 –40 –30 –20 –10

0

10 20 30 40 50 60 70

TIME (ns)

V

(mV)

OS

Figure 41. V_OSDistribution

Figure 38. Common-Mode Pulse Response

5

4

0

–10

–20

–30

–40

–50

–60

–70

–80

3

2

1

0

58µV/°C

–1

–2

–3

–4

–5

–40

–20

0

20

40

60

80

100

1

10

100

1000

TEMPERATURE (°C)

FREQUENCY (MHz)

Figure 42. V_OSDrift, RTO

Figure 39. Common-Mode Isolation, CMENC Low

1.5

1.0

200

160

120

80

0.5

–16µV/°C

0

–0.5

–1.0

–1.5

40

0

–40

–20

0

20

40

60

80

100

0

10

20

30

40

50

60

70

80

90

100

TEMPERATURE (°C)

FREQUENCY (MHz)

Figure 43. V_OSDrift, Common Mode, RTO

Figure 40. Noise Spectral Density

Rev. 0 | Page 24 of 40

AD8178

5

4

1.25

1.00

0.75

0.50

0.25

0

0.020

0.015

0.010

0.005

0

V

OUT

UPDATE

3

32ppm/°C

2

–0.005

–0.010

–0.015

–0.020

1

0

–1

–0.25

–40

–20

0

20

40

60

80

100

0

20 40 60 80 100 120 140 160 180 200 220 240 260 280

TIME (ns)

TEMPERATURE (°C)

Figure 44. Enable Time

Figure 45. Normalized DC Gain vs. Temperature

Rev. 0 | Page 25 of 40

AD8178

THEORY OF OPERATION

The AD8178 is a nonblocking crosspoint with 16 RGB input

channels and 5 RGB output channels. Architecturally, the

AD8178 is a differential-in, differential-out crosspoint suited

for middle-of-Cat-5-run applications. Furthermore, its

differential-in, differential-out gain of +4 and its decoded H and

V sync outputs make it the ideal solution for driving a monitor

directly. The ability to set the output common-mode (CM) and

black level through external pins offers additional flexibility.

The outputs of the AD8178 can be disabled to minimize on-chip

power dissipation. When disabled, there is only a common-

mode feedback network of 2.7 kꢀ between the differential outputs.

This high impedance allows multiple ICs to be bussed together

without additional buffering. Care must be taken to reduce

output capacitance, which can result in overshoot and frequency-

domain peaking. A series of internal amplifiers drive internal

nodes such that wideband high impedance is presented at the

disabled output, even while the output bus experiences fast signal

swings. When the outputs are disabled and driven externally, the

voltage applied to them should not exceed the valid output swing

range for the AD8178 to keep these internal amplifiers in their

linear range of operation. Applying excessive differential voltages

to the disabled outputs can cause damage to the AD8178 and

should be avoided (see the Absolute Maximum Ratings section

for guidelines).

Processing of CM voltage levels is achieved by placing the AD8178

in either of its two operation modes. In the first operation mode

(CMENC low), the input CM of each RGB differential pair

(possibly present in the form of either sync-on CM signaling or

noise) is removed through the switch, and the output CM is set

to a global reference voltage via the VOCM_CMENCOFF analog

input. In this mode, the AD8178 behaves as a traditional

differential-in, differential-out switch. If sync-on CM signaling

is present at the differential RGB inputs, then the H and V

outputs represent decoded syncs. In the second operation mode

(CMENC high), input sync-on CM signaling is propagated

through the switch with unity gain. In this mode, the overall

output CM is set to a global reference voltage via the

The connectivity of the AD8178 is controlled by a flexible TTL-

compatible logic interface. Either parallel or serial loading into

a first rank of latches preprograms each output. A global update

signal moves the programming data into the second rank of latches,

simultaneously updating all outputs. In serial mode, a serial-out

pin allows devices to be daisy-chained together for a single-pin

programming of multiple ICs. A power-on reset pin is available

to avoid bus conflicts by disabling all outputs. This power-on

reset clears the second rank of latches but does not clear the first

rank of latches. In serial mode, preprogramming individual inputs

is not possible and the entire shift register needs to be flushed. A

global chip-select pin gates the input clock and the global update

signal to the second rank of buffers.

VOCM_CMENCON analog input. Note that in both operation

modes, the overall input CM is blocked through the switch.

Input Pin VBLK defines the black level of the positive output

phase. The combination of VBLK and VOCM_CMENCOFF

allows the user to position the positive and negative output

phases anywhere in the allowable output voltage range, thus

maximizing output headroom usage.

The switch is organized into five 16:1 RBG multiplexers, with

each being responsible for connecting an RGB input channel to

its respective RGB output channel. Decoding logic selects a single

input (or none) in each multiplexer and connects it to its respective

output. Feedback around each multiplexer realizes a closed-loop

differential-in, differential-out gain of +2 in the core.

The AD8178 can operate on a single 5 V supply, powering both

the signal path (with the VPOS/VNEG supply pins) and the control

logic interface (with the VDD/DGND supply pins). Split supply

operation is possible with 2.5 V supplies that easily interface to

ground-referenced video signals. In this case, a flexible logic

interface allows the control logic supplies (VDD/DGND) to be

run off 5 V/0 V to 3.3 V/0 V while the analog core remains on

split supplies. Additional flexibility in the analog output common-

mode level (VOCM_CMENCOFF) and output black level (VBLK)

facilitates operation with unequally split supplies. If +3 V/−2 V

supplies to +2 V/−3 V supplies are desired, the output CM can

still be set to 0 V for ground-referenced video signals.

Each differential RGB input channel is buffered by a differential

receiver that is capable of accepting input CM voltages extending

all the way to either supply rail. Excess closed-loop receiver

bandwidth reduces the effect of the receiver on the overall device

bandwidth. Feedback around each differential receiver realizes

a gain of +2 yielding an overall differential-in, differential-out

crosspoint gain of +4. A separate loop realizes a closed-loop

common-mode gain of +1.

The output stage is designed for fast slew rate and settling time,

while driving a series-terminated Cat-5 cable. Unlike competing

multiplexer designs, the small signal bandwidth closely approaches

the large signal bandwidth.

Rev. 0 | Page 26 of 40

AD8178

APPLICATIONS INFORMATION

Figure 47 shows the voltage levels and CM handling for a single

input channel connected to a single output channel in a middle-

of-Cat-5-run application with CM encoding turned on.

OPERATING MODES

Depending on the state of the CMENC logic input, the AD8178

can be set in either of two differential-in, differential-out operat-

ing modes. In addition, monitors can be driven directly by tapping

the outputs single-ended and making use of the decoded H and

V sync outputs.

DIFF. R

DIFF. B

DIFF. R

CM

R

CM

B

DIFF. B

CM

R

CM

B

AD8178

INPUT

OVERALL

CM

Middle-of-Cat-5-Run Application, CM Encoding Turned Off

OUTPUT

OVERALL

CM

In this application, the AD8178 is placed somewhere in the middle

of a Cat-5 run. By tying CMENC low, the CM of each RGB differ-

ential pair is removed through the device (or turned off), and

the overall CM at the output is defined by the reference value

VOCM_CMENCOFF. In this mode of operation, CM noise is

removed, while the intended differential RGB signals are buffered

and passed to the outputs. The AD8178 is placed in this operation

mode when used in a sync-on color scheme. Figure 46 shows

the voltage levels and CM handling for a single input channel

connected to a single output channel in a middle-of-Cat-5-run

application with CM encoding turned off.

DIFF. G

CM

G

DIFF. G

CM

G

CMENC

VOCM_CMENCON

Figure 47. AD8178 in Middle-of-Cat-5-Run Application, CM Encoding On

(Note that in this application, the H and V outputs, though asserted, are not used.)

In this operation mode, the difference Δ_diff= 2 × (VBLK −

VOCM_CMENCOFF) still adds an output differential voltage,

as described in the Middle-of-Cat-5-Run Application, CM

Encoding Turned Off section.

End-of-Cat-5-Run Application, CM Encoding Turned Off—

Driving a Monitor Directly

DIFF. R

DIFF. B

CM

R

CM

B

In this application, the AD8178 is placed at the end of a Cat-5

run to drive a monitor directly: the differential outputs are

tapped single-ended to drive the monitor inputs, CMENC is

tied to logic low to remove sync-on-CM information at the

output of the part, and the decoded H and V sync outputs are

tied to the sync inputs of the monitor.

DIFF. R

CM

DIFF. B

DIFF. G

CM

B

AD8178

INPUT

OVERALL

CM

R

G

OUTPUT

OVERALL

CM

DIFF. G

CM

G

CMENC

VOCM_CMENCOFF

The differential-in, differential-out gain of +4 provides a

differential-in, single-ended out gain of +2 at the output pins of

the AD8178. This yields the correct differential-in, single-ended

out gain of +1 at the input of the monitor.

Figure 46. AD8178 in a Middle-of-Cat-5-Run Application, CM Encoding Off

(Note that in this application, the H and V outputs, though asserted, are not used.)

Input VBLK and Input VOCM_CMENCOFF allow the user

complete flexibility in defining the output CM level and the

amount of overlap between the positive and negative phases,

thus maximizing output headroom usage. Whenever VBLK

differs from VOCM_CMENCOFF by more than 100 mV,

a differential voltage, Δ_diff, is added at the outputs according

to the expression Δ_diff= 2 × (VBLK − VOCM_CMENCOFF.)

Conversely, whenever the difference between VBLK and

VOCM_CMENCOFF is less than 100 mV, no differential

voltage is added at the outputs.

The relationship between the incoming sync-on CM signaling

and the H and V syncs is defined according to Table 16.

Table 16. H and V Sync Truth Table (V_POS/V_NEG

=

2.5 V)

V

CM_R

0.5

0

CM_G

CM_B

H

0

−0.5

0

Low

High

Low

High

0.5

−0.5

0

0.5

Middle-of-Cat-5-Run Application, CM Encoding Turned On

The following two statements are equivalent to the truth table

(Table 16) in producing H and V for all allowable CM inputs:

In this application, the AD8178 is also placed somewhere in the

middle of a Cat-5 run, although the common-mode handling is

different. By tying CMENC high, the CM of each RGB input is

passed through the part with a gain of +1, while at the same time,

the overall output CM is stripped and set equal to the voltage

applied at the VOCM_CMENCON pin. The AD8178 is placed in

this operation mode when used with a sync-on CM scheme.

Although asserted, the H and V outputs are not used in this

application.

•

H sync is high when the CM of Blue is larger than the CM

of Red.

•

V sync is high when the combined CM of Red and Blue is

larger than the CM of Green.

Rev. 0 | Page 27 of 40

AD8178

For a practical example, refer to Figure 48. Note that the output

pulses have been shifted slightly with respect to each other for

clarity.

If D4 is low (output disabled), the four associated bits (D3 to

D0) do not matter because no input is switched to that output.

A sequence of five bits at Logic 0 must be supplied in between

each D4 to D0 group of bits for padding purposes. There is a total

of four such sequences of zeros.

VOCM_CMENCOFF = 0.7V

NEGATIVE

The most significant output address data is shifted in first, with

the enable bit (D4) shifted in first, followed by the input address

(D3 to D0) entered sequentially with D3 first and D0 last. The first

sequence of five bits at Logic 0 is shifted in next. Each remaining

output is programmed sequentially in a similar fashion, until

the least significant output address data is shifted in. Note that

the last D4 to D0 group is not followed by a corresponding group

PHASE

1.4V

VBLK = 0V

0V

POSITIVE

PHASE

Figure 48. Output at the AD8178 Pins for 0 V to 0.7 V Input Differential Pulse,

VBLK = 0 V, VOCM_CMENCOFF = 0.7 V

UPDATE

of five zeros. At this point,

causes the programming of the device according to the data that

UPDATE

can be taken low, which

The input to the AD8178 is a differential pulse with a low level

of 0 V and a high level of 0.7 V. VBLK is set to 0 V, and VOCM_

CMENCOFF is set to 0.7 V. With this choice of values, the positive

and negative output phases are overlapped, with the positive phase

ranging from 0 V to 1.4 V, and the negative phase ranging from

1.4 V to 0 V, respectively. The supplies are set to +3 V/−2 V to be in

compliance with output headroom requirements.

was just shifted in. The

latches are asynchronous; and

is low, they are transparent.

UPDATE

when

If more than one AD8178 device is to be serially programmed

in a system, the SEROUT signal from one device can be connected

to the SERIN of the next device to form a serial chain. All of the

CLK UPDATE

SER

,

, and

/PAR pins should be connected in parallel

The voltage on the positive output phase for a 0 V differential

input is equal to the voltage on VBLK, for all cases when VBLK

and VOCM_CMENCOFF differ by more than 100 mV.

and operated as described previously. The serial data is input to

the SERIN pin of the first device of the chain, and it ripples

through to the last. Therefore, the data for the last device in the

chain should come at the beginning of the programming sequence.

The length of the programming sequence is 45 bits times the

PROGRAMMING

The AD8178 has two options for changing the programming of

the crosspoint matrix. In the first option, a serial word of 45 bits

can be provided that updates the entire matrix each time. The

second option allows for changing the programming of a single

output using a parallel interface. The serial option requires

fewer signals, but more time (clock cycles), for changing the

programming; the parallel programming technique requires more

signals, but it allows for changing a single output at a time,

therefore requiring fewer clock cycles.

CS

CLK

and

is held low, both

UPDATE

number of devices in the chain. gates the

and

UPDATE

CS CLK

signals, so that when

held in their inactive high state. When

UPDATE

is held high, both

are

CLK

CS

and

function normally.

Parallel Programming Description

When using the parallel programming mode, it is not necessary

to reprogram the entire device when making changes to the matrix.

In fact, parallel programming allows the modification of a single

output or more at a time. Because this modification takes only

Serial Programming Description

CS CLK

,

The serial programming mode uses the device pins

,

WE UPDATE

one

/

cycle, significant time savings can be realized

UPDATE

SER

/PAR. The first step is to enable the

SERIN,

, and

by using parallel programming.

CLK

CS

SER

/PAR is pulled low to

on by pulling

low. Next,

One important consideration in using parallel programming is

WE

enable the serial programming mode. The parallel clock

RST

that the

signal does not reset all registers in the AD8178.

RST

should be held high during the entire serial programming

operation.

When taken low, the

signal only sets each output to the

disabled state. This is helpful during power-up to ensure that

two parallel outputs are not active at the same time.

UPDATE

The

is shifted into the serial port of the device. Although the data still

UPDATE

signal should be high during the time that data

After initial power-up, the internal registers in the device generally

have random data, even though the

shifts in when

is low, the transparent, asynchronous

RST

signal is asserted. If

latches allow the shifting data to reach the matrix. This causes

the matrix to try to update to every intermediate state as

defined by the shifting data.

parallel programming is used to program one output, then that

output is properly programmed, but the rest of the device has

a random program state, depending on the internal register content

at power-up. Therefore, when using parallel programming, it is

essential that all outputs be programmed to a desired state after

power-up. This ensures that the programming matrix is always

in a known state. From then on, parallel programming can be

used to modify a single output or more at a time.

CLK

The data at SERIN is clocked in at every falling edge of

.

A total of 45 bits must be shifted in to complete the programming.

A total of five bits must be supplied for each of the five RGB

output channels: an output enable bit (D4) and four bits (D3

to D0) that determine the input channel.

Rev. 0 | Page 28 of 40

AD8178

UPDATE

RST

pin has a 20 kꢀ pull-up resistor to VDD that can be

In similar fashion, if

is taken low after initial power-up,

The

used to create a simple power-up reset circuit. A capacitor from

RST RST

the random power-up data in the shift register is programmed into

the matrix. Therefore, to prevent the crosspoint from being

programmed into an unknown state, do not apply a logic level

after power is initially applied. Programming the

device into a known state after reset or power-up is a one-time

event that is accomplished by the following two steps:

to ground holds

low for some time, while the rest of the

device stabilizes. The low condition causes all the outputs to be

disabled. The capacitor then charges through the pull-up resistor

to the high state, thus allowing full programming capability of

the device.

UPDATE

to

1. Output 4 to Output 0 are programmed to the off state

while holding the CLR input at a logic high.

2. Each output (Output 4 to Output 0) is programmed to its

desired state while holding the CLR input at a logic low.

DIFFERENTIAL AND SINGLE-ENDED OPERATION

Although the AD8178 has fully differential inputs and outputs,

it can also be operated in single-ended fashion. Single-ended

and differential configurations are discussed in the following

sections, along with implications on gain, impedances, and

terminations.

CLR is held at logic low thereafter.

To change the programming of an output via parallel program-

Differential Input

CS

SER

UPDATE

ming,

should be taken low, and /PAR and

CLK

should be taken high. The serial programming clock,

should be left high during parallel programming. The parallel

WE

,

Each differential input to the AD8178 is applied to a differential

receiver. These receivers allow the user to drive the inputs with

an uncertain common-mode voltage, such as from a remote source

over twisted pair. The receivers respond only to the differences

in input voltages and restore an internal common mode suitable

for the internal signal path. Noise or crosstalk, which affect each

the inputs of each receiver equally, are rejected by the input stage,

as specified by its common-mode rejection ratio (CMRR).

clock,

, should start in the high state. The 3-bit address of

the output to be programmed should be put on A2 to A0. Data

Bit D3 to Data Bit D0 should contain the information that identifies

the input that gets programmed to the output that is addressed.

Data Bit D4 determines the enabled state of the output. If D4 is low

(output disabled), the data on D3 to D0 does not matter.

Furthermore, the overall common-mode voltage of all three

differential pairs comprising an RGB channel is processed and

rejected by a separate circuit block. For example, a static discharge

or a resistive voltage drop in a middle-of-Cat-5-run application

with sync-on CM signaling coupling into all three pairs in an RGB

channel are rejected at the output of the AD8178, while the

sync-on CM signals are allowed through the switch.

After the desired address and data signals have been established,

they can be latched into the shift register by a high-to-low transi-

WE

UPDATE

tion of the

until the

signal. The matrix is not programmed, however,

signal is taken low. It is thus possible to latch

in new data for several or all of the outputs first via successive

WE UPDATE

negative transitions of

while

is held high, and then

UPDATE

have all the new data take effect when

goes low. This

The circuit configuration used by the differential input receivers

is similar to that of several Analog Devices, Inc. general-purpose

differential amplifiers, such as the AD8131. The topology is that

of a voltage-feedback amplifier with internal gain resistors. The

input differential impedance for each receiver is 5 kꢀ in parallel

with 10 kꢀ or 3.33 kꢀ, as shown in Figure 49.

is the technique that should be used to program the device for the

first time after power-up when using parallel programming.

Programming the device to a known state can be accomplished

in serial programming mode by clocking in the entire 45-bit

sequence immediately after reset or power-up.

Reset

R

F

When powering up the AD8178, it is usually desirable to have

RST

R

G

the outputs come up in the disabled state. The

taken low, causes all outputs to be in the disabled state. However,

RST

pin, when

IN+

IN–

OUT–

TO SWITCH MATRIX

OUT+

R

RCVR

CM

the

signal does not reset all registers in the AD8178. This is

R

G

important when operating in the parallel programming mode.

See the Parallel Programming Description section for

information about programming internal registers after power-

up. Serial programming programs the entire matrix each time,

so no special considerations apply.

R

F

Figure 49. Input Receiver Equivalent Circuit

This impedance creates a small differential termination error

if the user does not account for the 3.33 kꢀ parallel element.

However, this error is less than 1% in most cases. Additionally,

the source impedance driving the AD8178 appears in parallel

with the internal gain-setting resistors, such that there may be

a gain error for some values of source resistance.

Because the data in the shift register is random after power-up,

it should not be used to program the matrix, or the matrix can

enter unknown states. To prevent this, do not apply a logic low

UPDATE

signal to

should first be loaded with the desired data, and only then can

UPDATE

initially after power-up. The shift register

the

be taken low to program the device.

Rev. 0 | Page 29 of 40

AD8178

The AD8178 is adjusted such that its gain is correct when

driven by a back-terminated Cat-5 cable (25 ꢀ effective

impedance to ground at each input pin, or 100 ꢀ differential

source impedance across pairs of input pins). If a different

source impedance is presented, the differential gain of the

AD8178 input receiver can be calculated as

resistance (R_CM, also shown in Figure 49) is present across the

inputs in both single-ended and differential operation.

In single-ended operation, an input is driven, and the undriven

input is often tied to midsupply or ground. Because signal-

frequency current flows at the undriven input, such input

should be treated as a signal line in the board design.

5.05 kꢀ

2.5kꢀ+R_S

For example, to achieve best dynamic performance, the undriven

input should be terminated with an impedance matching that seen

by the part at the driven input.

G_DM

=

where R_Sis the effective impedance to ground at each input pin.

Differential Output

When operating with a differential input, care must be taken to

keep the common mode, or average, of the input voltages within

the linear operating range of the AD8178 receiver. For the AD8178

receiver, this common-mode range can extend rail-to-rail, provided

the differential signal swing is small enough to avoid forward

biasing the ESD diodes (it is safest to keep the common mode plus

differential signal excursions within the supply voltages of the part).

Benefits of Differential Operation

The AD8178 has a fully differential switch core with differential

outputs. The two output voltages move in opposite directions,

with a differential feedback loop maintaining a fixed output

stage differential gain of +2 through the core. This differential

output stage provides improved crosstalk cancellation due to

parasitic coupling from one output to another being equal and

out of phase. Additionally, if the output of the device is utilized

in a differential design, then noise, crosstalk, and offset voltages

generated on-chip that are coupled equally into both outputs

are cancelled by the common-mode rejection ratio of the next

device in the signal chain. By utilizing the AD8178 outputs in

a differential application, the best possible noise and offset

specifications can be realized.

The input voltage of the AD8178 is linear for 0.5 V of differen-

tial input voltage difference (this limitation is primarily due to

the ability of the output to swing close to the rails because the

differential gain through the part is +4). Beyond this level, the

signal path saturates and limits the signal swing. This is not

a desired operation because the supply current increases and

the signal path is slow to recover from clipping. The absolute

maximum allowed differential input signal is limited by long-

term reliability of the input stage. The limits in the Absolute

Maximum Ratings section should be observed to avoid degrading

device performance permanently.

Differential Gain

The specified signal path gain of the AD8178 refers to its

differential gain. For the AD8178, the gain of +4 means that the

difference in voltage between the two output terminals is equal

to four times the difference between the two input terminals.

AC Coupling of Inputs

It is possible to ac-couple the inputs of the AD8178 receiver

so that bias current does not need to be supplied externally.

A capacitor in series with the inputs to the AD8178 creates

a high-pass filter with the input impedance of the device. This

capacitor needs to be large enough that the corner frequency

includes all frequencies of interest.

Common-Mode Gain

The common-mode, or average voltage pairs of output signals

is set by the voltage on the VOCM_CMENCOFF pin when

common-mode encoding is off (CMENC is a logic low), or by

the voltage on the VOCM_CMENCON pin when common-mode

encoding is on (CMENC is a logic high). Note that in the latter

case, VCOM_CMENCON sets the overall common mode of

RGB triplets of differential outputs, and the individual common

mode of each RGB output is free to change. VCOM_CMENCON

and VCOM_CMENCOFF are typically set to midsupply (often

ground) but can be moved approximately 0.5 V to accommodate

cases where the desired output common-mode voltage may not

be midsupply (as in the case of unequal split supplies). Adjusting

the output common-mode voltage beyond 0.5 V can limit differ-

ential swing internally below the specifications on the data sheet.

The overall common mode of the output voltages follow the

voltage applied to VOCM_CMENCON or VCOM_CMENCOFF,

implying a gain of +1. Likewise, sync-on common-mode signaling

is carried through the AD8178 (CMENC must be in its high

state), implying a gain of +1 for this path as well.

Single-Ended Input

The AD8178 input receiver can be driven single-endedly

(unbalanced). Single-ended inputs apply a component of

common-mode signal to the receiver inputs, which is then

rejected by the receiver (see the Specifications section for

common-mode-to-differential-mode ratio of the part).

The single-ended input resistance, R_IN, differs from the

differential input impedance, and is equal to

R_G

R_F

R_IN

=

1 −

2 × (R_G+ R_F)

with R_Gand R_F, as shown in Figure 49.

Note that this value is smaller than the differential input

resistance, but it is larger than R_G. The difference is due to the

component of common-mode level applied to the receiver by

single-ended inputs. A second, smaller component of input

The common-mode reference pins are analog signal inputs,

common to all output stages on the device. They require only

Rev. 0 | Page 30 of 40

AD8178

small amounts of bias current, but noise appearing on these

pins is buffered to all the output stages. As such, they should

be connected to low noise, low impedance voltage references

to avoid being sources of noise, offset, and crosstalk in the

signal path.

ended output sums half the differential offset voltage and all

of the common-mode offset voltage for a net increase in

observed offset.

Single-Ended Gain

The AD8178 operates as a closed-loop differential amplifier.

The primary control loop forces the difference between the

output terminals to be a ratio of the difference between the

input terminals. One output increases in voltage, while the

other decreases an equal amount to make the total output

voltage difference correct. The average of these output voltages

is forced to the voltage on the common-mode reference terminal

(VOCM_CMENCOFF or VOCM_CMENCON) by a second

control loop. If only one output terminal is observed with respect

to the common-mode reference terminal, only half of the differ-

ence voltage is observed. This implies that when using only one

output of the device, half of the differential gain is observed.

An AD8178 taken with single-ended output appears to have

a gain of +2.

Termination

The AD8178 is designed to drive 100 ꢀ terminated to ground

on each output (or an effective 200 ꢀ differential) while

meeting data sheet specifications over the specified operating

temperature range, if care is taken to observe the maximum

power derating curves.

Termination at the load end is recommended to shorten settling

time and provide for best signal integrity. In differential signal

paths, it is often desirable to series-terminate the outputs, with a

resistor in series with each output. A side effect of termination

is an attenuation of the output signal by a factor of two. In this

case, gain is usually necessary somewhere else in the signal path

to restore the signal level.

It is important to note that all considerations that apply to the

used output phase regarding output voltage headroom apply

unchanged to the complement output phase, even if this is not

actually used.

Whenever a differential output is used single-ended, it is desirable

to terminate the used single-ended output with a series resistor,

as well as to place a resistor on the unused output to match the

load seen by the used output.

Termination

When disabled, the outputs float to midsupply. A small current

is required to drive the outputs away from their midsupply state.

This current is easily provided by an AD8178 output (in its

enabled state) bussed together with the disabled output.

Exceeding the allowed output voltage range may saturate

internal nodes in the disabled output, and consequently,

an increase in disabled output current may be observed.

When operating the AD8178 with a single-ended output, the

preferred output termination scheme is to refer the load to the

output common mode. A series termination can be used, at an

additional cost of one half the signal gain.

In single-ended output operation, the complementary phase of

the output is not used and may or may not be terminated locally.

Although the unused output can be floated to reduce power dissi-

pation, there are several reasons for terminating the unused output

with a load resistance matched to the load on the signal output.

Single-Ended Output

Usage

The AD8178 output pairs can be used single-ended, taking only

one output and not using the second. This is often desired to

reduce the routing complexity in the design or because a single-

ended load is being driven directly. This mode of operation

produces good results but has some shortcomings when compared

to taking the output differentially. When observing the single-

ended output, noise that is common to both outputs appears in

the output signal.

One component of crosstalk is magnetic coupling by mutual

inductance between output package traces and bond wires that

carry load current. In a differential design, there is coupling from

one pair of outputs to other adjacent pairs of outputs. The differ-

ential nature of the output signal simultaneously drives the

coupling field in one direction for one phase of the output and

in an opposite direction for the other phase of the output. These

magnetic fields do not couple equally into adjacent output pairs,

due to different proximities; but they do destructively cancel the

crosstalk to some extent. If the load current in each output is equal,

this cancellation is greater and less adjacent crosstalk is observed

(regardless of whether the second output is actually being used).

When observing the output single-ended, the distribution of offset

voltages appears greater. In the differential case, the difference

between the outputs, when the difference between the inputs is

zero, is a small differential offset. This offset is created from

mismatches in devices in the signal path. In the single-ended

case, this differential offset is still observed, but an additional

offset component is also relevant. This additional component

is the common-mode offset, which is the difference between the

average of the outputs and the output common-mode reference.

This offset is created by mismatches that affect the signal path

in a common-mode manner. A differential receiver rejects this

common-mode offset voltage, but in the single-ended case, this

offset is observed with respect to the signal ground. The single-

A second benefit of balancing the output loads in a differential

pair is to reduce fluctuations in current requirements from the

power supply. In single-ended loads, the load currents alternate

from the positive supply to the negative supply. This creates a

parasitic signal voltage in the supply pins due to the finite

resistance and inductance of the supplies. This supply fluctuation

appears as crosstalk in all outputs, attenuated by the power

supply rejection ratio (PSRR) of the device.

Rev. 0 | Page 31 of 40

AD8178

At low frequencies, this is a negligible component of crosstalk,

but PSRR falls off as frequency increases. With differential,

balanced loads, as one output draws current from the positive

supply, the other output draws current from the negative supply.

When the phase alternates, the first output draws current from

the negative supply and the second draws from the positive

supply. The effect is that a more constant current is drawn from

each supply, such that the crosstalk-inducing supply fluctuation

is minimized.

Power Dissipation

Calculation of Power Dissipation

10

T

= 150°C

J

9

8

7

6

5

4

3

A third benefit of driving balanced loads is that the output pulse

response changes as the load changes. The differential signal

control loop in the AD8178 forces the difference of the outputs

to be a fixed ratio to the difference of the inputs. If the two

output responses are different due to loading, this creates a

difference that the control loop sees as signal response error, and

it attempts to correct this error. This distorts the output signal

from the ideal response compared to the case when the two

outputs are balanced.

15

25

35

45

55

65

75

85

AMBIENT TEMPERATURE (°C)

Figure 50. Maximum Die Power Dissipation vs. Ambient Temperature

The curve in Figure 50 was calculated from

T_{JUNCTION, MAX}− T_AMBIENT

Decoupling

P_{D, MAX}

=

(1)

The signal path of the AD8178 is based on high open-loop gain

amplifiers with negative feedback. Dominant-pole compensation

is used on-chip to stabilize these amplifiers over the range of

expected applied swing and load conditions. To guarantee this

designed stability, proper supply decoupling is necessary with

respect to both the differential control loops and the common-

mode control loops of the signal path. Signal-generated currents

must return to their sources through low impedance paths at all

frequencies in which there is still loop gain (up to 700 MHz at

a minimum).

θ_JA

As an example, if the AD8178 is enclosed in an environment at

45°C (T_A), the total on-chip dissipation under all load and supply

conditions must not be allowed to exceed 7.0 W.

When calculating on-chip power dissipation, it is necessary to

include the power dissipated in the output devices due to current

flowing in the loads. For a sinusoidal output about ground and

symmetrical split supplies, the on-chip power dissipation due to

the load can be approximated by

The signal path compensation capacitors in the AD8178 are

connected to the VNEG supply. At high frequencies, this limits

the power supply rejection ratio (PSRR) from the VNEG supply

to a lower value than that from the VPOS supply. If given a

choice, an application board should be designed such that the

VNEG power is supplied from a low inductance plane, subject

to a least amount of noise.

P

_D,OUTPUT= (V_POS− V_OUTPUT,RMS) × I_OUTPUT,RMS

(2)

For nonsinusoidal output, the power dissipation should be

calculated by integrating the on-chip voltage drop across the

output devices multiplied by the load current over one period.

The user can subtract the quiescent current for the Class AB

output stage when calculating the loaded power dissipation. For

each output stage driving a load, subtract a quiescent power,

according to

VOCM_CMENCON and VOCM_CMENCOFF are high speed

common-mode control loops of all output drivers. In the single-

ended output sense, there is no rejection from noise on these

inputs to the outputs. For this reason, care must be taken to

produce low noise sources over the entire range of frequencies

of interest. This is important not only to single-ended operation,

but to differential operation, because there is a common-mode-

to-differential gain conversion that becomes greater at higher

frequencies.

P

_DQ,OUTPUT= (V_POS− V_NEG) × I_{OUTPUT,QUIESCENT}

(3)

where I_{OUTPUT, QUIESCENT}= 1.65 mA for each single-ended output

pin of the AD8178.

For each disabled RGB output channel, the quiescent power supply

current in V_POSand V_NEGdrops by approximately 34 mA.

VOCM_CMENCON and VOCM_CMENCOFF are internally

buffered to prevent transients flowing into or out of these inputs

from acting on the source impedance and becoming sources of

crosstalk.

Rev. 0 | Page 32 of 40

AD8178

V

POS

I

loads driven by the H and V outputs are high and because the

voltage at these outputs typically sits close to either rail, the

correction to the on-chip power estimate is small. Furthermore,

the H and V outputs are active only briefly during sync

generation and returned to digital ground thereafter.

O, QUIESCENT

QNPN

QPNP

V

OUTPUT

Short-Circuit Output Conditions

I

OUTPUT

I

O, QUIESCENT

Although there is short-circuit current protection on the AD8178

outputs, the output current can reach values of 80 mA into

a grounded output. Any sustained operation with too many

shorted outputs can exceed the maximum die temperature

and can result in device failure (see the Absolute Maximum

Ratings section).

V

NEG

Figure 51. Simplified Output Stage

Example

With an ambient temperature of 85°C, all nine RGB output

channels driving 1 V_rmsinto 100 ꢀ loads, and power supplies at

2.5 V, follow these steps:

Crosstalk

Many systems (such as KVM switches) that handle numerous

analog signal channels have strict requirements for keeping the

various signals from influencing any of the other signals in the

system. Crosstalk is the term used to describe the coupling of

the signals of other nearby channels to a given channel.

1. Calculate the power dissipation of the AD8178 using data

sheet quiescent currents, neglecting the V_DDcurrent because

it is insignificant.

P

_D,QUIESCENT= (V_POS× I_VPOS) + (V_NEG× I_VNEG

)

(4)

When there are many signals in close proximity in a system,

as is undoubtedly the case in a system that uses the AD8178,

the crosstalk issues can be quite complex. A good understanding

of the nature of crosstalk and some definition of terms is required

to specify a system that uses one or more crosspoint devices.

P

_D,QUIESCENT= (2.5 V × 460 mA) + (2.5 V × 460 mA) = 2.3 W

2. Calculate power dissipation from loads. For a differential

output and ground-referenced load, the output power is

symmetrical in each output phase.

Types of Crosstalk

P

_D,OUTPUT= (V_POS− V_OUTPUT,RMS) × I_OUTPUT,RMS

(5)

Crosstalk can be propagated by means of any of three methods.

These fall into the categories of electric field, magnetic field, and the

sharing of common impedances. This section explains these effects.

_D,OUTPUT= (2.5 V − 1 V) × (1 V/100 Ω) = 15 mW

There are 15 output pairs, or 30 output currents.

Every conductor can be both a radiator of electric fields and

a receiver of electric fields. The electric field crosstalk mechanism

occurs when the electric field created by the transmitter propagates

across a stray capacitance (for example, free space) and couples

with the receiver and induces a voltage. This voltage is an unwanted

crosstalk signal in any channel that receives it.

nP_D,OUTPUT= 30 × 15 mW = 0.45 W

3. Subtract quiescent output stage current for the number of

loads (30 in this example). The output stage is either standing

or driving a load, but the current needs to be counted only

once (valid for output voltages > 0.5 V).

P

_DQ,OUTPUT= (V_POS− V_NEG) × I_{OUTPUT,QUIESCENT}

(6)

Currents flowing in conductors create magnetic fields that circulate

around the currents. These magnetic fields then generate voltages

in any other conductors whose paths they link. The undesired

induced voltages in these other channels are crosstalk signals.

The channels that crosstalk can be said to have a mutual inductance

that couples signals from one channel to another.

_DQ,OUTPUT= (2.5 V − (−2.5 V)) × 1.65 mA = 8.25 mW

There are 15 output pairs, or 30 output currents.

nP_D,OUTPUT= 30 × 8.25 mW = 0.25 W

4. Verify that the power dissipation does not exceed the

maximum allowed value.

The power supplies, grounds, and other signal return paths

of a multichannel system are generally shared by the various

channels. When a current from one channel flows in one of these

paths, a voltage that is developed across the impedance becomes

an input crosstalk signal for other channels that share the common

impedance.

P

_D,ON-CHIP= P_D,QUIESCENT+ nP_D,OUTPUT− nP_DQ,OUTPUT

(7)

_D,ON-CHIP= 2.3 W + 0.45 W − 0.25 W = 2.5 W

From Figure 50 or Equation 1, this power dissipation is below

the maximum allowed dissipation for all ambient temperatures

up to and including 85°C.

All these sources of crosstalk are vector quantities, so the magni-

tudes cannot simply be added together to obtain the total crosstalk.

In fact, there are conditions where driving additional circuits in

parallel in a given configuration can actually reduce the crosstalk.

The fact that the AD8178 is a fully differential design means that

In a general case, the power delivered by the digital supply and

dissipated into the digital output devices has to be taken into

account following a similar derivation. However, because the

Rev. 0 | Page 33 of 40

AD8178

many sources of crosstalk either destructively cancel, or are

common mode to, the signal and can be rejected by a differential

receiver.

three at a time; and so on, until, finally, there is only one way to

drive a test signal into all 15 other input channels in parallel.

Each of these cases is legitimately different from the others and

can yield a unique value, depending on the resolution of the

measurement system, but it is hardly practical to measure all

these terms and then specify them. In addition, this measurement

describes the crosstalk matrix for just one input channel. A similar

crosstalk matrix can be proposed for every other input. In addition,

if the possible combinations and permutations for connecting

inputs to the other outputs (not used for measurement) are taken

into consideration, the numbers rather quickly grow to astro-

nomical proportions. If a larger crosspoint array of multiple

AD8178 devices is constructed, the numbers grow larger still.

Areas of Crosstalk

A practical AD8178 circuit must be mounted to an actual circuit

board to connect it to power supplies and measurement equipment.

Great care has been taken to create an evaluation board (available

upon request) that adds minimum crosstalk to the intrinsic device.

This, however, raises the issue that system crosstalk is a combi-

nation of the intrinsic crosstalk of the devices, in addition to the

circuit board to which they are mounted. It is important to try

to separate these two areas when attempting to minimize the

effect of crosstalk.

Obviously, some subset of all these cases must be selected to be

used as a guide for a practical measure of crosstalk. One common

method is to measure all hostile crosstalk; this means that the

crosstalk to the selected channel is measured while all other system

channels are driven in parallel. In general, this yields the worst

crosstalk number; but this is not always the case, due to the vector

nature of the crosstalk signal.

In addition, crosstalk can occur among the inputs to a crosspoint

and among the outputs. It can also occur from input to output.

In the following sections, techniques are discussed for diagnosing

which part of a system is contributing to crosstalk.

Measuring Crosstalk

Crosstalk is measured by applying a signal to one or more channels

and measuring the relative strength of that signal on a desired

selected channel. The measurement is usually expressed as decibels

(dB) down from the magnitude of the test signal. The crosstalk

is expressed by

Other useful crosstalk measurements are those created by one

nearest neighbor or by the two nearest neighbors on either side.

These crosstalk measurements are generally higher than those

of more distant channels, so they can serve as a worst-case

measure for any other one-channel or two-channel crosstalk

measurements.

⎛

⎜

⎞

⎟

A

_SEL(s)

XT = 20 log₁₀

(8)

⎜

⎝

⎟

⎠

A_TEST(s)

Input and Output Crosstalk

where:

s = jω is the Laplace transform variable.

_SEL(s) is the amplitude of the crosstalk induced signal in the

selected channel.

_TEST(s) is the amplitude of the test signal.

Capacitive coupling is voltage-driven (dV/dt), but it is generally

a constant ratio. Capacitive crosstalk is proportional to input or

output voltage, but this ratio is not reduced by simply reducing

signal swings. Attenuation factors must be changed by changing

impedances (lowering mutual capacitance), or destructive

canceling must be utilized by summing equal and out-of-phase

components. For high input impedance devices such as the

AD8178, capacitances generally dominate input-generated

crosstalk.

A

It can be seen that crosstalk is a function of frequency but not

a function of the magnitude of the test signal (to first order).

In addition, the crosstalk signal has a phase relative to the test

signal associated with it.

A network analyzer is most commonly used to measure crosstalk

over a frequency range of interest. It can provide both magnitude

and phase information about the crosstalk signal.

Inductive coupling is proportional to current (dI/dt) and often

scales as a constant ratio with signal voltage, but it also shows

a dependence on impedances (load current). Inductive coupling

can also be reduced by constructive canceling of equal and out-

of-phase fields. In the case of driving low impedance video loads,

output inductances contribute highly to output crosstalk.

As a crosspoint system or device grows larger, the number of

theoretical crosstalk combinations and permutations can become

extremely large. For example, in the case of the triple 16 × 5 matrix

of the AD8178, note the number of crosstalk terms that can be

considered for a single channel, for example, Input Channel

INPUT0. INPUT0 is programmed to connect to one of the

AD8178 outputs where the measurement can be made.

The flexible programming capability of the AD8178 can be used

to diagnose whether crosstalk is occurring more on the input

side or the output side. Some examples are illustrative. A given

input channel (INPUT7 roughly in the middle for this example)

can be programmed to drive OUTPUT2 (exactly in the middle).

The inputs to INPUT7 are just terminated to ground (via 50 ꢀ

or 75 ꢀ), and no signal is applied.

First, the crosstalk terms associated with driving a test signal into

each of the other 15 input channels can be measured one at a time,

while applying no signal to INPUT0. Next, the crosstalk terms

associated with driving a parallel test signal into all 15 other inputs

can be measured two at a time in all possible combinations; then

All the other inputs are driven in parallel with the same test signal

(practically provided by a distribution amplifier), with all other

outputs except OUTPUT2 disabled. Because grounded INPUT7

Rev. 0 | Page 34 of 40

AD8178

is programmed to drive OUTPUT2, no signal should be present.

Any signal that is present can be attributed to the other 15 hostile

input signals because no other outputs are driven (they are all

disabled). Thus, this method measures the all hostile input

contribution to crosstalk into INPUT7. Of course, the method

can be used for other input channels and combinations of

hostile inputs.

windings that drives a load resistor. For low frequencies, the

magnitude of the crosstalk is given by

⎛

⎜

⎝

⎞

⎟

⎠

s

⎜

XT = 20 log₁₀M_XY

×

(10)

R_L

where:

_XYis the mutual inductance of output X to output Y.

M

R_Lis the load resistance on the measured output.

For output crosstalk measurement, a single input channel is

driven (INPUT0, for example) and all outputs other than

a given output (OUTPUT2 in the middle) are programmed to

connect to INPUT0. OUTPUT2 is programmed to connect to

INPUT15 (far away from INPUT0), which is terminated to

ground. Thus, OUTPUT2 should not have a signal present because

it is listening to a quiet input. Any signal measured at OUTPUT2

can be attributed to the output crosstalk of the other eight hostile

outputs. Again, this method can be modified to measure other

channels and other crosspoint matrix combinations.

This crosstalk mechanism can be minimized by keeping the

mutual inductance low and increasing R_L. The mutual

inductance can be kept low by increasing the spacing of the

conductors and minimizing their parallel length.

PCB Layout

Extreme care must be exercised to minimize additional crosstalk

generated by the system circuit board(s). The areas that must be

carefully detailed are grounding, shielding, signal routing, and

supply bypassing.

Effect of Impedances on Crosstalk

The packaging of the AD8178 is designed to help keep crosstalk

to a minimum. On the BGA substrate, each pair is carefully routed

to predominately couple to each other, with shielding traces sepa-

rating adjacent signal pairs. The ball grid array is arranged such

that similar board routing can be achieved. Input and output differ-

ential pairs are grouped by channel rather than by color to allow

for easy, convenient board routing.

The input side crosstalk can be influenced by the output

impedance of the sources that drive the inputs. The lower the

impedance of the drive source, the lower the magnitude of the

crosstalk. The dominant crosstalk mechanism on the input side

is capacitive coupling. The high impedance inputs do not have

significant current flow to create magnetically induced crosstalk.

However, significant current can flow through the input termi-

nation resistors and the loops that drive them. Thus, the PC board

on the input side can contribute to magnetically coupled crosstalk.

The input and output signals have minimum crosstalk if they

are located between ground planes on layers above and below,

and are separated by ground in between. Vias should be located

as close to the IC as possible to carry the inputs and outputs to

the inner layer. The input and output signals surface at the input

termination resistors and the output series back-termination

resistors. To the extent possible, these signals should also be

separated as soon as they emerge from the IC package.

From a circuit standpoint, the input crosstalk mechanism looks

like a capacitor coupling to a resistive load. For low frequencies,

the magnitude of the crosstalk is given by

XT = 20 log₁₀

where:

R_Sis the source resistance.

[

(R_SC_M) × s

]

(9)

PCB Termination Layout

C_Mis the mutual capacitance between the test signal circuit and

the selected circuit.

s is the Laplace transform variable.

As frequencies of operation increase, the importance of proper

transmission line signal routing becomes more important. The

bandwidth of the AD8178 is large enough that using high imped-

ance routing does not provide a flat in-band frequency response

for practical signal trace lengths. It is necessary for the user to

choose a characteristic impedance suitable for the application and

properly terminate the input and output signals of the AD8178.

Traditionally, video applications have used 75 ꢀ single-ended

environments. RF applications are generally 50 ꢀ single-ended

(and board manufacturers have the most experience with this

application). Cat-5 cabling is usually driven as differential pairs

of 100 ꢀ differential impedance.

Equation 9 illustrates that this crosstalk mechanism has a high-pass

nature; it can also be minimized by reducing the coupling capaci-

tance of the input circuits and lowering the output impedance

of the drivers. If the input is driven from a 75 ꢀ terminated cable,

the input crosstalk can be reduced by buffering this signal with

a low output impedance buffer.

On the output side, the crosstalk can be reduced by driving

a lighter load. Although the AD8178 is specified with excellent

settling time when driving a properly terminated Cat-5, the

crosstalk is higher than the minimum obtainable due to the

high output currents. These currents induce crosstalk via the

mutual inductance of the output pins and the bond wires of

the AD8178.

For flexibility, the AD8178 does not contain on-chip termina-

tion resistors. This flexibility in application comes with some

board layout challenges. The distance between the termination

of the input transmission line and the AD8178 die is a high

impedance stub and causes reflections of the input signal. With

some simplification, it can be shown that these reflections cause

peaking of the input at regular intervals in frequency, dependent

From a circuit standpoint, this output crosstalk mechanism

looks like a transformer with a mutual inductance between the

Rev. 0 | Page 35 of 40

AD8178

on the propagation speed (V_P) of the signal in the chosen board

material and the distance (d) between the termination resistor

and the AD8178. If the distance is great enough, these peaks can

occur in-band. In fact, practical experience shows that these

peaks are not high Q and should be pushed out to three or four

times the desired bandwidth to not have an effect on the signal.

For a board designer using FR4 (V_P= 144 × 10⁶m/sec), this

means the AD8178 should be no more than 1.5 cm after the

termination resistors and should preferably be placed even closer.

The BGA substrate routing inside the AD8178 is approximately

1 cm in length and adds to the stub length, so 1.5 cm PCB routing

equates to d = 2.5 × 10^–2m in the calculations.

When driving the AD8178 single-endedly, the undriven input is

often terminated with a resistance to balance the input stage.

By terminating the undriven input with a resistor of one-half

the characteristic impedance, the input stage is perfectly

balanced (25 ꢀ, for example, to balance the two parallel 50 ꢀ

terminations on the driven input). However, due to the

feedback in the input receiver, there is high speed signal current

leaving the undriven input. To terminate this high speed signal,

proper transmission line techniques should be used. One

solution is to adjust the trace width to create a transmission line

of half the characteristic impedance and terminate the far end

with this resistance (25 ꢀ in a 50 ꢀ system). This is not often

practical because trace widths become large. In most cases, the

best practical solution is to place the half-characteristic impedance

resistor as close as possible (preferably less than 1.5 cm away)

and reduce the parasitics of the stub (by removing the ground

plane under the stub, for example). In either case, the designer

must decide if the layout complexity created by a balanced,

terminated solution is preferable to simply grounding the

undriven input at the ball with no trace.

(

2n + 1 V_P

)

f_PEAK

=

(11)

4d

where n = {0, 1, 2, 3, ...}.

In some cases, it is difficult to place the termination close to the

AD8178 due to space constraints, differential routing, and large

resistor footprints. A preferable solution in this case is to maintain

a controlled transmission line past the AD8178 inputs and termi-

nate the end of the line. This is known as fly-by termination.

The input impedance of the AD8178 is large enough, and stub

length inside the package is small enough, that this works well

in practice. Implementation of fly-by input termination often

includes bringing the signal in on one routing layer, then passing

through a filled via under the AD8178 input ball, then back out

to termination on another signal layer. In this case, care must be

taken to tie the reference ground planes together near the signal

via if the signal layers are referenced to different ground planes.

While the examples discussed so far are for input termination,

the theory is similar for output back-termination. Taking the

AD8178 as an ideal voltage source, any distance of routing between

the AD8178 and a back-termination resistor is an impedance

mismatch that potentially creates reflections. For this reason,

back-termination resistors should also be placed close to the

AD8178. In practice, because back-termination resistors are

series elements, they can be placed close to the AD8178

outputs.

Finally, the AD8178 pinout allows the user to bring the outputs

out as surface traces to the back-termination resistors. The

designer can avoid creating stubs and reflections by keeping the

AD8178 output signal path on the surface of the board. A stub

is created when a top-to-bottom via connection is made on the

output signal path that is perpendicular to the signal flow.

AD8178

OPn

ONn

IPn

INn

50Ω

Figure 52. Fly-By Input Termination. (Grounds for the two transmission lines

shown must be tied together close to the INn pin.)

If multiple AD8178s are to be driven in parallel, a fly-by input

termination scheme is very useful, but the distance from each

AD8178 input to the driven input transmission line is a stub

that should be minimized in length and parasitics by using the

discussed guidelines.

Rev. 0 | Page 36 of 40

AD8178

VPOS

VDD

FOUR AD8147

(G = +2)

AD8003

(G = +4)

FOUR 15-PIN HD

CONNECTORS

15-PIN HD

CONNECTOR

THREE 15-PIN HD

CONNECTORS

THREE RGB, HV

CHANNELS

FOUR RGB, HV

CHANNELS

RGB

MONITOR

PC

OUT0 TO OUT1

IN0 TO IN3

THREE 15-PIN HD

CONNECTORS

THREE RGB, HV

CHANNELS

FOUR DIFFERENTIAL

RGB WITH SYNC-ON

CM CHANNELS

FOUR AD8147

(G = +2)

RGB

MONITOR

THREE RGB

CHANNELS

FOUR 15-PIN HD

CONNECTORS

OUT2

15-PIN HD

CONNECTOR

FOUR RGB, HV

CHANNELS

THREE HV

PAIRS

RJ-45

PC

IN0 TO IN3

OUT0 TO OUT1

OUT2

CONNECTOR

IN4 TO IN7

THREE RGB, HV

CHANNELS

RGB, HV

CHANNEL

AD8145

(G = +2)

IN4 TO IN7

IN8 TO IN11

IN12 TO IN13

IN14 TO IN15

OUT3

DIFFERENTIAL

OFFSET

DIFFERENTIAL

RGB WITH

SYNC-ON CM

CAT-5

OUT3

15-PIN HD

CONNECTORS

RGB

MONITOR

OUT4

RJ-45

CONNECTOR

AD8178 DUT

CAT5

PC

IN8 TO IN11

FOUR RJ-45

CONNECTORS

RGB, HV

CHANNEL

TWO

AD8147 (G = +2)

EVALUATION BOARD

TWELVE SMA

DIFFERENTIAL

RGB CHANNELS

CONNECTORS

DIFFERENTIAL

RGB, HV

CHANNEL

SIGNAL GENERATOR/

NETWORK ANALYZER

IN12 TO IN13

GORE

HEADER

RIBBON CABLE

OUT4

IN14 TO IN15

NATIONAL

INSTRUMENTS

CONTROLLER BOARD

TWO GORE

HEADERS

USB

AD8178

CUSTOMER

EVALUATION BOARD

GND

VNEG

TO CONTROLLER PC USB

Figure 53. Evaluation Board Schematic

Rev. 0 | Page 37 of 40

AD8178

OUTLINE DIMENSIONS

27.20

27.00 SQ

26.80

A1 CORNER

INDEX AREA

26 24 22 20 18 16 14 12 10

25 23 21 19 17 15 13 11

8

6

4

2

9

7

5

3

1

A

B

C

D

E

F

A1 BALL

PAD CORNER

G

H

J

K

24.20

24.00 SQ

23.80

L

M

N

TOP VIEW

P

R

T

U

V

W

Y

1.00

BSC

AA

AB

AC

AD

AE

AF

2.43

2.32

2.15

DETAIL A

1.19

1.17

1.15

DETAIL A

0.60

0.55

0.50

COPLANARITY

0.20 MAX

0.70

0.60

0.50

0.70

0.60

0.50

SEATING

PLANE

BALL DIAMETER

COMPLIANT TO JEDEC STANDARDS MS-034-AAL-1

Figure 54. 676-Ball Plastic Ball Grid Array [PBGA]

(B-676)

Dimensions shown in millimeters

ORDERING GUIDE

Model

Temperature Range

Package Description

Package Option

AD8178ABPZ¹

AD8178-EVALZ¹

−40°C to +85°C

676-Ball Plastic Ball Grid Array [PBGA]

Evaluation Board

B-676

¹Z = RoHS Compliant Part.

Rev. 0 | Page 38 of 40

AD8178

NOTES

Rev. 0 | Page 39 of 40

AD8178

NOTES

registered trademarks are the property of their respective owners.

D06608-0-7/07(0)

Rev. 0 | Page 40 of 40


型号：	AD8178ABPZ1
厂家：	ADI
描述：	450 MHz, Triple 16 】 5 Video Crosspoint Switch 450兆赫，三人间16 】 5视频交叉点开关开关
文件：	总40页 (文件大小：824K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD8178ABPZ1 [ADI]

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