AD8063AR [ADI]
Low-Cost, 300 MHz Rail-to-Rail Amplifiers; 低成本， 300 MHz轨到轨放大器
| 型号： | AD8063AR |
| 厂家： | 
ADI |
| 描述： | Low-Cost, 300 MHz Rail-to-Rail Amplifiers |
| 文件： | 总16页 (文件大小：315K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low-Cost, 300 MHz
Rail-to-Rail Amplifiers
a
AD8061/AD8062/AD8063
CONNECTION DIAGRAMS
(Top Views)
FEATURES
Low Cost
SOIC-8 (R)
SOT-23-6 (RT)
Single (AD8061), Dual (AD8062)
Single with Disable (AD8063)
Rail-to-Rail Output Swing
6 mV VOS
High Speed
300 MHz, –3 dB Bandwidth (G = 1)
800 V/ꢀs Slew Rate
AD8061/
AD8063
AD8063
DISABLE
1
8
7
6
5
NC
–IN
+IN
V
+V
S
1
2
3
6
5
4
OUT
(AD8063 ONLY)
2
3
+V
S
–V
DISABLE
S
V
OUT
–V
4
NC
–IN
+IN
S
(Not to Scale)
(Not to Scale)
NC = NO CONNECT
8.5 nV/√Hz @ 5 V
35 ns Settling Time to 0.1% with 1 V Step
Operates on 2.7 V to 8 V Supplies
Input Voltage Range = –0.2 V to +3.2 V with VS = 5
Excellent Video Specs (RL = 150 ꢁ, G = 2)
Gain Flatness 0.1 dB to 30 MHz
0.01% Differential Gain Error
0.04ꢂ Differential Phase Error
35 ns Overload Recovery
SOIC-8 (R) and ꢀSOIC (RM)
SOT-23-5 (RT)
AD8061
AD8062
V
5
4
+V
S
1
2
3
V
+V
V
1
2
3
4
8
7
6
5
OUT
OUT1
S
–V
–IN1
S
OUT2
–IN2
+IN2
+IN1
–IN
+IN
(Not to Scale)
Low Power
–V
S
6.8 mA/Amplifier Typical Supply Current
AD8063 400 ꢀA when Disabled
Small Packaging
(Not to Scale)
AD8061 Available in SOIC-8 and SOT-23-5
AD8062 Available in SOIC-8 and ꢀSOIC
AD8063 Available in SOIC-8 and SOT-23-6
The AD8061, AD8062, and AD8063 offer a typical low power
of 6.8 mA/amplifier, while being capable of delivering up to
50 mA of load current. The AD8063 has a power-down disable
feature that reduces the supply current to 400 µA. These features
make the AD8063 ideal for portable and battery-powered
applications where size and power are critical.
APPLICATIONS
Imaging
Photodiode Preamp
Professional Video and Cameras
Hand Sets
DVD/CD
Base Stations
Filters
3
R
= 50ꢁ
F
A-to-D Driver
0
–3
–6
V
= 0.2V p-p
O
R
= 1kꢁ
R
= 0ꢁ
L
F
PRODUCT DESCRIPTION
V
= 1V
BIAS
The AD8061, AD8062, and AD8063 are rail-to-rail output volt-
age feedback amplifiers offering ease of use and low cost. They
have bandwidth and slew rate typically found in current feed-
back amplifiers. All have a wide input common-mode voltage
range and output voltage swing, making them easy to use on
single supplies as low as 2.7 V.
R
F
OUT
IN
R
L
50ꢁ
–9
ꢃ
V
BIAS
Despite being low cost, the AD8061, AD8062, and AD8063
provide excellent overall performance. For video applications
their differential gain and phase errors are 0.01% and 0.04°
into a 150 Ω load, along with 0.1 dB flatness out to 30 MHz.
Additionally, they offer wide bandwidth to 300 MHz along
with 800 V/µs slew rate.
–12
1
10
100
1000
FREQUENCY – MHz
Figure 1. Small Signal Response, RF = 0 Ω, 50 Ω
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2001
AD8061/AD8062/AD8063–SPECIFICATIONS(T = 25ꢂC, V = 5 V, R = 1 kꢁ, V = 1 V,
unless otherwise noted)
A
S
L
O
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth
G = 1, VO = 0.2 V p-p
G = –1, +2, VO = 0.2 V p-p
G = 1, VO = 1 V p-p
150
60
320
MHz
MHz
MHz
MHz
V/µs
V/µs
ns
115
280
30
650
500
35
–3 dB Large Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
G = 1, VO = 0.2 V p-p
G = 1, VO = 2 V Step, RL = 2 kΩ
G = 2, VO = 2 V Step, RL = 2 kΩ
G = 2, VO = 2 V Step
500
300
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion
fC = 5 MHz, VO = 2 V p-p, RL = 1 kΩ
fC = 20 MHz, VO = 2 V p-p, RL = 1 kΩ
f = 5 MHz, G = 2, AD8062
f = 100 kHz
f = 100 kHz
G = 2, RL = 150 Ω
G = 2, RL = 150 Ω
–77
–50
–90
8.5
1.2
0.01
0.04
28
dBc
dBc
dBc
nV/√Hz
pA/√Hz
%
Degree
dBc
Crosstalk, Output to Output
Input Voltage Noise
Input Current Noise
Differential Gain Error (NTSC)
Differential Phase Error (NTSC)
Third Order Intercept
SFDR
f = 10 MHz
f = 5 MHz
62
dB
DC PERFORMANCE
Input Offset Voltage
1
2
6
6
mV
mV
µV/°C
µA
TMIN to TMAX
Input Offset Voltage Drift
Input Bias Current
3.5
3.5
4
0.3
70
90
9
9
4.5
TMIN to TMAX
µA
Input Offset Current
Open-Loop Gain
µA
dB
dB
VO = 0.5 V to 4.5 V, RL = 150 Ω
VO = 0.5 V to 4.5 V, RL = 2 kΩ
68
74
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
13
1
MΩ
pF
V
–0.2 to +3.2
80
VCM = –0.2 V to +3.2 V
62
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing—Load Resistance
Is Terminated at Midsupply
Output Current
Capacitive Load Drive, VOUT = 0.8 V
RL = 150 Ω
0.3
0.25
25
0.1 to 4.5
0.1 to 4.9
50
25
300
4.75
4.85
V
V
mA
pF
pF
RL = 2 kΩ
VO = 0.5 V to 4.5 V
30% Overshoot: G = 1, RS = 0 Ω
G = 2, RS = 4.7 Ω
POWER-DOWN DISABLE
Turn-On Time
Turn-Off Time
DISABLE Voltage—Off
DISABLE Voltage—On
40
ns
ns
V
300
2.8
3.2
V
POWER SUPPLY
Operating Range
2.7
72
5
6.8
0.4
8
9.5
V
mA
mA
Quiescent Current per Amplifier
Supply Current when Disabled
(AD8063 Only)
Power Supply Rejection Ratio
∆VS = 2.7 V to 5 V
80
dB
Specifications subject to change without notice.
REV. C
–2–
AD8061/AD8062/AD8063
(TA = 25ꢂC, VS = 3 V, RL = 1 kꢁ, VO = 1 V, unless otherwise noted)
SPECIFICATIONS
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth
G = 1, VO = 0.2 V p-p
G = –1, +2, VO = 0.2 V p-p
G = 1, VO = 1 V p-p
150
60
300
115
250
30
280
230
40
MHz
MHz
MHz
MHz
V/µs
V/µs
ns
–3 dB Large Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
G = 1, VO = 0.2 V p-p
G = 1, VO = 1 V Step, RL = 2 kΩ
G = 2, VO = 1.5 V Step, RL = 2 kΩ
G = 2, VO = 1 V Step
190
180
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion
fC = 5 MHz, VO = 2 V p-p, RL = 1 kΩ
fC = 20 MHz, VO = 2 V p-p, RL = 1 kΩ
f = 5 MHz, G = 2
f = 100 kHz
f = 100 kHz
–60
–44
–90
8.5
1.2
dBc
dBc
dBc
nV/√Hz
pA/√Hz
Crosstalk, Output to Output
Input Voltage Noise
Input Current Noise
DC PERFORMANCE
Input Offset Voltage
1
2
6
6
mV
mV
µV/°C
µA
TMIN to TMAX
Input Offset Voltage Drift
Input Bias Current
3.5
3.5
4
0.3
70
90
8.5
8.5
4.5
TMIN to TMAX
µA
Input Offset Current
Open-Loop Gain
µA
dB
dB
VO = 0.5 V to 2.5 V, RL = 150 Ω
VO = 0.5 V to 2.5 V, RL = 2 kΩ
66
74
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
13
1
MΩ
pF
V
–0.2 to +1.2
80
VCM = –0.2 V to +1.2 V
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
RL = 150 Ω
0.3
0.3
0.1 to 2.87
0.1 to 2.9
25
25
300
2.85
2.90
V
V
mA
pF
pF
RL = 2 kΩ
Output Current
Capacitive Load Drive, VOUT = 0.8 V
VO = 0.5 V to 2.5 V
30% Overshoot, G = 1, RS = 0 Ω,
G = 2, RS = 4.7 Ω
POWER-DOWN DISABLE
Turn-On Time
Turn-Off Time
DISABLE Voltage—Off
DISABLE Voltage—On
40
ns
ns
V
300
0.8
1.2
V
POWER SUPPLY
Operating Range
2.7
72
3
9
V
mA
mA
Quiescent Current per Amplifier
Supply Current when Disabled
(AD8063 Only)
6.8
0.4
Power Supply Rejection Ratio
80
dB
Specifications subject to change without notice.
REV. C
–3–
(TA = 25ꢂC, VS = 2.7 V, RL = 1 kꢁ, VO = 1 V,
unless otherwise noted)
AD8061/AD8062/AD8063–SPECIFICATIONS
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth
G = 1, VO = 0.2 V p-p
G = –1, +2, VO = 0.2 V p-p
G = 1, VO = 1 V p-p
G = 1, VO = 0.2 V p-p, VO DC = 1 V
G = 1, VO = 0.7 V Step, RL = 2 kΩ
G = 2, VO = 1.5 V Step, RL = 2 kΩ
G = 2, VO = 1 V Step
150
60
300
115
230
30
150
130
40
MHz
MHz
MHz
MHz
V/µs
V/µs
ns
Bandwidth for 0.1 dB Flatness
Slew Rate
110
95
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion
f
f
C = 5 MHz, VO = 2 V p-p, RL = 1 kΩ
C = 20 MHz, VO = 2 V p-p, RL = 1 kΩ
–60
–44
–90
8.5
1.2
dBc
dBc
dBc
nV/√Hz
pA/√Hz
Crosstalk, Output to Output
Input Voltage Noise
Input Current Noise
f = 5 MHz, G = 2
f = 100 kHz
f = 100 kHz
DC PERFORMANCE
Input Offset Voltage
1
2
6
6
mV
mV
µV/°C
µA
TMIN to TMAX
Input Offset Voltage Drift
Input Bias Current
3.5
3.5
4
0.3
70
90
TMIN to TMAX
8.5
4.5
µA
Input Offset Current
Open-Loop Gain
µA
dB
dB
VO = 0.5 V to 2.2 V, RL = 150 Ω
VO = 0.5 V to 2.2 V, RL = 2 kΩ
63
74
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
13
1
MΩ
pF
V
–0.2 to +0.9
80
VCM = –0.2 V to +0.9 V
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
RL = 150 Ω
0.3
0.25
0.1 to 2.55
0.1 to 2.6
25
2.55
2.6
V
V
mA
pF
pF
RL = 2 kΩ
Output Current
Capacitive Load Drive, VOUT = 0.8 V
VO = 0.5 V to 2.2 V
30% Overshoot: G = 1, RS = 0 Ω,
G = 2, RS = 4.7 Ω
25
300
POWER-DOWN DISABLE
Turn-On Time
Turn-Off Time
DISABLE Voltage—Off
DISABLE Voltage—On
40
ns
ns
V
300
0.5
0.9
V
POWER SUPPLY
Operating Range
2.7
8
V
Quiescent Current per Amplifier
Supply Current when Disabled
(AD8063 Only)
6.8
0.4
8.5
mA
mA
Power Supply Rejection Ratio
80
dB
Specifications subject to change without notice.
REV. C
–4–
AD8061/AD8062/AD8063
MAXIMUM POWER DISSIPATION
ABSOLUTE MAXIMUM RATINGS1
The maximum power that can be safely dissipated by the AD806x
is limited by the associated rise in junction temperature. The
maximum safe junction temperature for plastic encapsulated
devices is determined by the glass transition temperature of the
plastic, approximately 150°C. Temporarily exceeding this limit
may cause a shift in parametric performance due to a change
in the stresses exerted on the die by the package. Exceeding a
junction temperature of 175°C for an extended period can result
in device failure. While the AD806x is internally short circuit
protected, this may not be sufficient to guarantee that the
maximum junction temperature (150°C) is not exceeded under
all conditions.
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V
Internal Power Dissipation2
Plastic Package (N) . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 W
Small Outline Package (R) . . . . . . . . . . . . . . . . . . . . . 0.8 W
SOT-23-5 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 W
SOT-23-6 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 W
µSOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 W
Input Voltage (Common-Mode) (–VS – 0.2 V) to (+VS – 1.8 V)
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . VS
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves
Storage Temperature Range R, RM, SOT-23-5,
SOT-23-6 . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . 300°C
To ensure proper operation, it is necessary to observe the
maximum power derating curves.
2.0
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Specification is for device in free air:
8-Lead SOIC Package: θJA = 160°C/W; θJC = 56°C/W
5-Lead SOT-23-5 Package: θJA = 240°C/W; θJC = 92°C/W
6-Lead SOT-23-6 Package: θJA = 230°C/W; θJC = 92°C/W
8-Lead µSOIC Package: θJA = 200°C/W; θJC = 44°C/W.
T
= 150ꢂC
8-LEAD SOIC
PACKAGE
J
1.5
1.0
0.5
0
ꢀSOIC
SOT-23-5, -6
–50 –40 –30
90
–20 –10
0
10 20 30 40 50 60 70 80
AMBIENT TEMPERATURE – ꢂC
Figure 2. Plot of Maximum Power Dissipation vs.
Temperature for AD8061/AD8062/AD8063
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Option
Branding
Information
Model
AD8061AR
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
5-Lead SOT-23
5-Lead SOT-23
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead µSOIC
8-Lead µSOIC
8-Lead µSOIC
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
6-Lead SOT-23
6-Lead SOT-23
SO-8
AD8061AR-REEL
AD8061AR-REEL7
AD8061ART-REEL
AD8061ART-REEL7
AD8062AR
AD8062AR-REEL
AD8062AR-REEL7
AD8062ARM
AD8062ARM-REEL
AD8062ARM-REEL7
AD8063AR
AD8063AR-REEL
AD8063AR-REEL7
AD8063ART-REEL
AD8063ART-REEL7
13-Inch Tape and Reel
7-Inch Tape and Reel
RT-5, 13-Inch Tape and Reel
RT-5, 7-Inch Tape and Reel
SO-8
13-Inch Tape and Reel
7-Inch Tape and Reel
RM-8
13-Inch Tape and Reel
7-Inch Tape and Reel
SO-8
13-Inch Tape and Reel
7-Inch Tape and Reel
RT-6, 13-Inch Tape and Reel
RT-6, 7-Inch Tape and Reel
HGA
HGA
HCA
HCA
HCA
HHA
HHA
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8061/AD8062/AD8063 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. C
–5–
AD8061/AD8062/AD8063–Typical Performance Characteristics
1.2
3
G = 1
1.0
+V
@ +85ꢂC
OUT
0
–3
–6
+V
@ +25ꢂC
OUT
0.8
0.6
0.4
0.2
0
G = 2
+V
@ –40ꢂC
OUT
–V
@ –40ꢂC
OUT
G = 5
V
R
= 0.2V p-p
= 1kꢁ
= 1V
O
–9
–V
@ +85ꢂC
OUT
L
V
BIAS
–V
@ +25ꢂC
OUT
–12
10
20
30
40
50
60
70
80
90
0
1
10
100
1000
LOAD CURRENT – mA
FREQUENCY – MHz
TPC 1. Output Saturation Voltage vs. Load Current
TPC 4. Small Signal Frequency Response
18
3
V
= 1.0V p-p
O
R
= 1kꢁ
= 1V
AD8062
L
16
G = 1
V
BIAS
0
–3
–6
14
12
G = 2
10
AD8061
8
G = 5
6
4
–9
2
0
–12
2
3
4
5
6
7
8
1
10
100
1000
SINGLE POWER SUPPLY – Voltage
FREQUENCY – MHz
TPC 2. ISUPPLY vs. VSUPPLY
TPC 5. Large Signal Frequency Response
3
3
R
= 50ꢁ
V
V
R
= 5V
= 0.2V p-p
= 1kꢁ
F
S
O
L
0
–3
–6
0
–3
–6
V
= 1V
BIAS
V
R
= 0.2V p-p
= 1kꢁ
= 1V
O
R
= 0ꢁ
L
F
G = –1
G = –2
V
BIAS
G = –5
R
R
F
F
OUT
OUT
IN
IN
R
R
L
L
50ꢁ
50ꢁ
–9
–9
ꢃ
ꢃ
V
BIAS
V
BIAS
–12
–12
1
10
100
1000
1
10
100
1000
FREQUENCY – MHz
FREQUENCY – MHz
TPC 3. Small Signal Response, RF = 0 Ω, 50 Ω
TPC 6. Small Signal Frequency Response
REV. C
–6–
AD8061/AD8062/AD8063
0
3
V
V
R
= 5V
= 1V p-p
= 1kꢁ
V
= 5V
S
S
–10
R
= 1kꢁ
O
L
G = 1
L
–20
–30
0
–3
–6
V
= 1V
BIAS
G = –1
2ND @ 1MHz
3RD @ 10MHz
–40
–50
G = –2
G = –5
–60
–70
–80
–90
–9
3RD @ 1MHz
2.5
2ND @ 10MHz
1.5 2.0
–100
–12
0.5
1.0
3.5
3.0
1
10
100
1000
INPUT SIGNAL BIAS – V
FREQUENCY – MHz
TPC 7. Large Signal Frequency Response
TPC 10. Harmonic Distortion for a 1 V p-p Signal vs.
Input Signal DC Bias
–40
0.1
0
604ꢁ
V
R
= 0.2V p-p
= 1kꢁ
= 1V
V
= 2.7V
O
S
10ꢀF
+5V
+
L
–50
V
BIAS
0.1ꢀF
G = 1
1kꢁ
50ꢁ
1Mꢁ INPUT
–60
52.3ꢁ
0.1ꢀF
–0.1
–0.2
+
V
= 5.0V
1kꢁ
S
+1.25V
dc
(R
)
–
LOAD
–70
–80
V
= 3.0V
S
2ND H
–0.3
–0.4
–90
–100
–110
3RD H
–0.5
1
10
100
1000
0.01
0.1
1
10
50
FREQUENCY – MHz
FREQUENCY – MHz, START = 10kHz, STOP = 30MHz
TPC 8. 0.1 dB Flatness
TPC 11. Harmonic Distortion for a 1 V p-p Output
Signal vs. Input Signal DC Bias
80
60
200
–30
V
R
= 5V
= 1kꢁ
S
150
100
50
L
–40
–50
G = 5
= 1V p-p
SERIES 1
V
O
2ND
3RD
10MHz
40
–60
SERIES 2
0
–70
20
–50
–100
–150
–200
–250
–300
–80
0
2ND
–90
3RD
2ND
5MHz
–100
–110
–120
1MHz
–20
–40
3RD
0.01
0.1
1.0
10
100
1000
0
1
5
2
3
4
OUTPUT SIGNAL DC BIAS – V
FREQUENCY – MHz
TPC 12. Harmonic Distortion vs. Output Signal
DC Bias
TPC 9. AD8062 Open-Loop Gain and Phase vs.
Frequency, VS = 5 V, RL = 1 kΩ
REV. C
–7–
AD8061/AD8062/AD8063
–40
0.01
0.00
V
R
G = 2
= 5V
S
= R = 1kꢁ
F
L
–50
2ND @ 10MHz
–0.01
–0.02
–0.04
–0.06
–60
–70
–80
–90
5V
+
10ꢀF
1Mꢁ
0.1ꢀF
INPUT
TO
3589A
50ꢁ
1kꢁ
50ꢁ
1kꢁ
2ND @ 2MHz
1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH
1kꢁ
2ND @ 500kHz
0.02
0.00
3RD @ 2MHz
–0.02
–0.04
–0.06
–100
–110
3RD @ 500kHz
1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH
1.0
3.5
4.0
4.5
1.5
2.0
2.5
3.0
RTO OUTPUT – V p-p
TPC 13. Harmonic Distortion vs. Output Signal
Amplitude
TPC 16. Differential Gain and Phase Error, G = 2,
NTSC Input Signal, RL = 1 kΩ, VS = 5 V
–30
V
= 5V
0.010
0.005
S
R = R = 1kꢁ
I
L
–40
–50
–60
V
= 2V p-p
O
G = +2
0.000
–0.005
S1 3RD HARMONIC/
DUAL ꢃ2.5V SUPPLY
–0.010
1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH
S1 2ND HARMONIC/
DUAL ꢃ2.5V SUPPLY
–70
–80
0.04
0.03
S1 2ND HARMONIC/
SINGLE +5V SUPPLY
0.02
0.01
0.00
–0.01
–0.02
–90
–100
–110
S1 3RD HARMONIC/
SINGLE +5V SUPPLY
1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH
0.01
0.1
1
10
FREQUENCY – MHz, START = 10kHz, STOP = 30MHz
TPC 14. Harmonic Distortion vs. Frequency
TPC 17. Differential Gain and Phase Error, G = 2,
NTSC Input Signal, RL = 150 Ω, VS = 5 V
1.0
1000
V
= 5V
S
FALLING EDGE
R
G = 1
= 1kꢁ
0.9
0.8
L
900
800
700
600
500
V
R
G = 1
= 5V
= 1kꢁ
S
L
0.7
0.6
RISING EDGE
0.5
0.4
0.3
0.2
0.1
400
300
200
100
0
0
0.20
TIME – ꢀs
0.30
0.40
0.50
0
0.10
1.5
OUTPUT STEP AMPLITUDE – V
3.0
1.0
2.0
2.5
TPC 18. Slew Rate vs. Output Step Amplitude
TPC 15. 400 mV Pulse Response
REV. C
–8–
AD8061/AD8062/AD8063
1400
1200
1000
800
V
= ꢃ2.5V
S
FALLING EDGE
G = 1
= 1kꢁ
V
= ꢃ4V
V
IN
R
S
L
2.5V
FALLING EDGE
= +5V
V
S
V
OUT
600
400
200
0
RISING EDGE
V
= ꢃ4V
S
0.0V
RISING EDGE
V
= +5V
S
500mV/DIV
20 40
2.5
0
0.5
1.0
1.5
2.0
3.0
3.5
4.0
0
60
80 100 120 140 160
180 200
TIME – ns
OUTPUT STEP – V
TPC 19. Slew Rate vs. Output Step Amplitude, G = 2,
TPC 22. Input Overload Recovery, Input Step = 0 V to 2 V
RL = 1 kΩ, VS = 5 V
1000
V
= ꢃ2.5V
S
V
R
= 5V
= 1kꢁ
S
G = 5
= 1kꢁ
R
L
L
V
OUT
2.5V
1.0V
100
10
1
V
IN
0.0V
500mV/DIV
20 40
10
100
1k
10k
100k
1M
10M
0
60
80 100 120 140 160
180 200
FREQUENCY – Hz
TIME – ns
TPC 20. Voltage Noise vs. Frequency
TPC 23. Output Overload Recovery, Input Step = 0 V to 1 V
100
10
1
0
V
= 0.2V p-p
= 100ꢁ
= ꢃ2.5V
CM
–10
–20
–30
V
R
= 5V
= 1kꢁ
R
V
S
L
L
SIDE 2
S
SIDE 1
–40
–50
–60
–70
–80
–90
–100
604ꢁ
154ꢁ
604ꢁ
154ꢁ
50ꢁ
V
IN
200mV p-p
57.6ꢁ
0
10
10M
100
1k
10k
100k
1M
0.01
0.1
1
10
100
500
FREQUENCY – Hz
FREQUENCY – MHz
TPC 21. Current Noise vs. Frequency
TPC 24. CMRR vs. Frequency
REV. C
–9–
AD8061/AD8062/AD8063
0
7
6
5
4
3
2
1
ꢄV = 0.2V p-p
S
V
= 5V
S
R
V
= 1kꢁ
= 5V
–10
–20
–30
–40
–50
–60
–70
L
S
–PSRR
+PSRR
–80
–90
–100
0.01
0
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.1
1
10
100
500
FREQUENCY – MHz
DISABLE VOLTAGE
TPC 28. DISABLE Voltage vs. Supply Current
TPC 25. PSRR vs. Frequency Delta
–20
–30
6
5
V
= 5V
S
1kꢁ
50ꢁ
1kꢁ
G = 2
= 10MHz
f
+2.5V
V
IN
DISABLE
@ 1.3V
= 100ꢁ
–40
BIAS
R
L
OUT
1kꢁ
4
IN
–50
–2.5V
–60
3
–70
INPUT = SIDE 2
INPUT = SIDE 1
2
–80
–90
V
V
R
= 5V
= 400mV rms
= 1kꢁ
1
S
IN
–100
–110
–120
L
0
V
OUT
G = 2
–1
0.1
1
10
100
500
0
0.4
0.8
1.2
1.6
2.0
0.01
FREQUENCY – MHz
TIME – ꢀs
TPC 26. AD8062 Crosstalk, VOUT = 2.0 V p-p, RL = 1 kΩ,
G = 2, VS = 5 V
TPC 29. DISABLE Function, Voltage = 0 V to 5 V
0
1000
V
V
R
= 5V
= 0.2V p-p
= 1kꢁ
S
V
V
R
= 5V
= 0.2V p-p
= 1kꢁ
S
O
–10
–20
–30
–40
–50
–60
–70
–80
–90
O
L
L
100
10
V
= 1V
BIAS
V
= 1V
BIAS
1
0.1
0.01
0.1
1
10
100
1000
1
10
100
1000
FREQUENCY – MHz
FREQUENCY – MHz
TPC 30. Output Impedance vs. Frequency, VOUT = 0.2 V
TPC 27. Disabled Output Isolation Frequency Response
p-p, RL = 1 kΩ, VS = 5 V
REV. C
–10–
AD8061/AD8062/AD8063
V
R
= 5V
= 1kꢁ
S
V
G = 2
= 5V
S
L
R
= 1kꢁ
= 1V p-p
L
V
IN
+0.1%
3.5V
2.5V
–0.1%
1kꢁ
1kꢁ
50ꢁ
1.5V
R
= 1kꢁ
L
500mV/DIV
t = 0
0
10
20
30
40
50
60
70
80
90
100
20ns/DIV
TIME – ns
TPC 34. 1 V Step Response
TPC 31. Output Settling Time to 0.1%
50
45
40
35
30
V
G = 2
R
= 5V
S
FALLING EDGE
= 1kꢁ
= 100mV
L
2.6V
2.5V
V
IN
RISING EDGE
25
20
15
10
5
2.4V
V
R
G = 1
= 5V
= 1kꢁ
S
L
20mV/DIV
0
0.5
1
1.5
2
2.5
0
10
20
30
40
50
60
70
80
90
100
TIME – ns
OUTPUT VOLTAGE STEP
TPC 35. 100 mV Step Response
TPC 32. Settling Time vs. VOUT
V
= 5V
V
= 5V
S
S
G = –1
G = 2
R
= 1kꢁ
R
= R = 1kꢁ
F
L
F
L
R
= 1kꢁ
V
= 4V p-p
IN
4.86
2.43
0.0V
0.0V
1V
2ꢀs
2ꢀs/DIV
1V/DIV
TPC 36. Output Rail-to-Rail Swing
TPC 33. Output Swing
REV. C
–11–
AD8061/AD8062/AD8063
The input stage will be the headroom limit for signals when the
amplifier is used in a gain of 1 for signals approaching the
positive rail. Figure 3 shows a typical offset voltage versus
input common-mode voltage for the AD806x amplifier on a
5 V supply. Accurate dc performance is maintained from about
200 mV below the minus supply to within 1.8 V of the positive
supply. For high-speed signals, however, there are other consid-
erations. Figure 4 shows –3 dB bandwidth versus dc input
V
G = 1
R
= 5V
S
= 1kꢁ
L
2.6V
2.5V
2.4V
–0.4
–0.8
–1.2
–1.6
–2.0
–2.4
–2.8
–3.2
–3.6
–4.0
50mV/DIV
0
5
10
15
20
25
30
35
40
45
50
TIME – ns
TPC 37. 200 mV Step Response
V
= 5V
S
G = 2
R
V
= R = 1kꢁ
L
F
= 2V p-p
IN
4.5V
2.5V
0.5V
–0.5
0
0.5
1.0
1.5
V
2.0
– V
2.5
3.0
3.5
4.0
CM
Figure 3. VOS vs. Common-Mode Voltage, VS = 5 V
2
0
V
V
V
V
V
= 3.0
= 3.1
= 3.2
= 3.3
= 3.4
CM
CM
CM
CM
CM
1V/DIV
0
5
10
15
20
25
30
35
40
45
50
–2
–4
–6
–8
TIME – ns
TPC 38. 2 V Step Response
CIRCUIT DESCRIPTION
The AD8061/AD8062/AD8063 family are very high-speed volt-
age feedback op amps. The high slew rate input stage is a true
single-supply topology, capable of sensing signals at or below
the minus supply rail. The rail-to-rail output stage can pull
within 30 mV of either supply rail when driving light loads and
within 0.3 V when driving 150 Ω. High-speed performance is
maintained at supply voltages as low as 2.7 V.
0.1
1
10
100
1000
10000
FREQUENCY – MHz
Figure 4. Unity Gain Follower Bandwidth vs. Input
Common Mode, VS = 5 V
Headroom Considerations
These amplifiers are designed for use in low-voltage systems. To
obtain optimum performance, it is useful to understand the
behavior of the amplifier as input and output signals approach
the amplifier’s headroom limits.
voltage for a unity gain follower. As the common-mode voltage
approaches the positive supply, the amplifier holds together
well, but the bandwidth begins to drop at 1.9 V within +VS.
This can manifest itself in increased distortion or settling time.
TPC 10 plots the distortion of a 1 V p-p signal with the AD806x
amplifier used as a follower on a 5 V supply versus signal common-
mode voltage. Distortion performance is maintained until the
input signal center voltage gets beyond 2.5 V, as the peak of the
input sine wave begins to run into the upper common-mode
voltage limit. Higher frequency signals require more headroom
than the lower frequencies to maintain distortion performance.
Figure 5 illustrates how the rising edge settling time for the
amplifier configured as a unity gain follower stretches out as the
top of a 1 V step input approaches and exceeds the specified input
common-mode voltage limit.
The AD806x’s input common-mode voltage range extends from
the negative supply voltage (actually 200 mV below this), or
“ground” for single supply operation, to within 1.8 V of the
positive supply voltage. Thus, at a gain of 2, the AD806x can
provide full “rail-to-rail” output swing for supply voltage as low
as 3.6 V, assuming the input signal swing from –VS (or ground)
to +VS/2. At a gain of 3, the AD806x can provide a rail-to-rail
output range down to 2.7 V total supply voltage.
Exceeding the headroom limit is not a concern for any inverting
gain on any supply voltage, as long as the reference voltage at
the amplifier’s positive input lies within the amplifier’s input
common-mode range.
REV. C
–12–
AD8061/AD8062/AD8063
For signals approaching the minus supply and inverting gain
and high positive gain configurations, the headroom limit will be
the output stage. The AD806x amplifiers use a common emitter
style output stage. This output stage maximizes the available
output range, limited by the saturation voltage of the output
transistors. The saturation voltage increases with the drive
current the output transistor is required to supply, due to the
output transistors’ collector resistance. The saturation voltage
can be estimated using the equation VSAT = 25 mV + IO × 8 Ω,
where IO is the output current, and 8 Ω is a typical value for the
output transistors’ collector resistance.
3.7
3.5
3.3
3.1
2.9
2.7
2.5
2.3
2.1
VOLTAGE STEP
FROM 2.4V TO 3.4V
VOLTAGE STEP
FROM 2.4V TO 3.6V
VOLTAGE STEP
FROM 2.4V TO 3.8V,
4V AND 5V
3.6
3.4
3.2
0
100
200
300
400
500
600
TIME – ns
Figure 6. Pulse Response for G = 1 Follower, Input Step
Overloading the Input Stage
3.0
2V TO 3V STEP
2.8
2.6
2.4
2.2
2.0
2.1V TO 3.1V STEP
Output
2.2V TO 3.2V STEP
2.3V TO 3.3V STEP
Output overload recovery is typically within 40 ns after the
amplifier’s input is brought to a nonoverloading value. Figure
7 shows output recovery transients for the amplifier recovering
from a saturated output from the top and bottom supplies to a
point at midsupply.
2.4V TO 3.4V STEP
5.0
0
4
8
12
16
20
24
28
32
4.6
TIME – ns
OUTPUT VOLTAGE
5V TO 2.5V
4.2
3.8
3.4
3.0
2.6
2.2
1.8
1.4
1.0
0.60
Figure 5. Output Rising Edge for 1 V Step at Input Head-
room Limits, G = 1, VS = 5 V, 0 V
OUTPUT VOLTAGE
0V TO 2.5V
As the saturation point of the output stage is approached, the
output signal will show increasing amounts of compression and
clipping. As in the input headroom case, the higher frequency
signals require a bit more headroom than the lower frequency
signals. TPCs 11, 12, and 13 illustrate the point, plotting typical
distortion versus output amplitude and bias for gains of 2 and 5.
INPUT VOLTAGE
EDGES
R
5V
R
V
IN
2.5V
V
O
Overload Behavior and Recovery
Input
0.20
–0.20
The specified input common-mode voltage of the AD806x is
–200 mV below the negative supply to within 1.8 V of the posi-
tive supply. Exceeding the top limit results in lower bandwidth
and increased settling time as seen in Figures 4 and 5. Push-
ing the input voltage of a unity gain follower beyond 1.6 V within
the positive supply leads to the behavior shown in Figure 6—an
increasing amount of output error as well as much increased
settling time. Recovery time from input voltages 1.6 V or closer
to the positive supply is about 35 ns, which is limited by the
settling artifacts caused by transistors in the input stage com-
ing out of saturation.
0
10
20
30
40
TIME – ns
50
60
70
Figure 7. Overload Recovery, G = –1, VS = 5 V
CAPACITIVE LOAD DRIVE
The AD806x family is optimized for bandwidth and speed, not
for driving capacitive loads. Output capacitance will create a
pole in the amplifier’s feedback path, leading to excessive
peaking and potential oscillation. If dealing with load capaci-
tance is a requirement of the application, the two strategies to
consider are (1) using a small resistor in series with the
amplifier’s output and the load capacitance and (2) reducing
the bandwidth of the amplifier’s feedback loop by increasing the
overall noise gain.
The AD806x family does not exhibit phase reversal, even for input
voltages beyond the voltage supply rails. Going more than 0.6 V
beyond the power supplies will turn on protection diodes at the
input stage, which will greatly increase the device’s current draw.
REV. C
–13–
AD8061/AD8062/AD8063
Figure 8 shows a unity gain follower using the series resistor
strategy. The resistor isolates the output from the capacitance
and, more importantly, creates a zero in the feedback path that
compensates for the pole created by the output capacitance.
BOARD LAYOUT CONSIDERATIONS
Maintaining the high-speed performance of the AD806x family
requires the use of high-speed board layout techniques and low
parasitic components.
The PCB should have a ground plane covering unused portions
of the component side of the board to provide a low impedance
path. The ground plane should be removed near the package to
reduce parasitic capacitance.
R
SERIES
V
AD8061
O
C
LOAD
V
IN
Proper bypassing is critical. A ceramic 0.1 µF chip capacitor
should be used to bypass both supplies, and be located within
3 mm of each power pin. An additional 4.7 µF to 10 µF tanta-
lum electrolytic capacitor should be connected in parallel to
provide charge for fast, large signal changes at the output.
Figure 8. Series Resistor Isolating Capacitive Load
Voltage feedback amplifiers like those in AD806x family will be
able to drive more capacitive load without excessive peaking
when used in higher-gain configurations. This is because the
increased noise gain reduces the bandwidth of the overall feed-
back loop. Figure 9 plots the capacitance that produces 30%
overshoot versus noise gain for a typical amplifier.
Minimizing parasitic capacitance at the amplifier’s inverting
input pin is very important. The feedback resistor should be
located close to the inverting input pin. The value of the feed-
back resistor may come into play—for instance, 1 kΩ interacting
with 1 pF of parasitic capacitance creates a pole at 159 MHz.
10000
Stripline design techniques should be used for signal traces
longer than 25 mm. These should be designed with either 50 Ω
or 75 Ω characteristic impedance and be properly terminated at
each end.
R
= 4.7
S
1000
100
10
APPLICATIONS
Single Supply Sync Stripper
R
= 0
S
When a video signal contains synchronization pulses, it is
sometimes desirable to remove them prior to performing
certain operations. In the case of A-to-D conversion, the sync
pulses will consume some of the dynamic range, so removing
them will increase the converter’s available dynamic range for
the video information.
1
2
3
4
5
CLOSED-LOOP GAIN
Figure 11 shows a basic circuit for creating a sync stripper using
the AD8061 powered by a single supply. When the nega-
tive supply is at ground potential, the lowest potential to
which the output can go is ground. This feature is exploited
to create a waveform whose lowest amplitude is the black level
of the video and does not include the sync level.
Figure 9. Capacitive Load vs. Closed-Loop Gain
DISABLE OPERATION
The internal circuit for the AD8063 disable function is shown in
Figure 10. When the DISABLE node is pulled below 2 V from
the positive supply, the supply current will decrease from typi-
cally 6.5 mA to under 400 µA, and the AD8063 output will
enter a high impedance state. If the DISABLE node is not con-
nected, and thus is allowed to float, the AD8063 will stay biased
at full power.
3V
0.1ꢀF
10ꢀF
75ꢁ
7
3
2
VIDEO IN
VIDEO OUT
6
VCC
75ꢁ
AD8061
4
75ꢁ
R
F
1kꢁ
2V
R
1kꢁ
G
PIN NUMBERS ARE
FOR 8-PIN PACKAGE
TO AMPLIFIER
BIAS
DISABLE
Figure 11. Single 3 V Sync Stripper Using AD8061
In this case, the input video signal has its black level at ground,
so it comes out at ground at the input. Since the sync level is below
the black level, it will not show up at the output. However, all
of the active video portion of the waveform will be amplified
by a gain of two and then be normalized to unity gain by the
back-terminated transmission line. Figure 12 is an oscilloscope
plot of the input and output waveforms.
VEE
Figure 10. Disable Circuit of the AD8063
TPC 28 shows AD8063 supply current versus DISABLE volt-
age. TPC 29 plots the output seen when the AD8063 input is
driven with a 10 MHz sine wave, and the DISABLE is toggled
from 0 V to 5 V, illustrating the part’s turn-on and turn-off time.
TPC 27 shows the input/output isolation response with the
AD8063 shut off.
REV. C
–14–
AD8061/AD8062/AD8063
RGB Amplifier
1
2
Most RGB graphics signals are created by video-DAC outputs
that drive a current through a resistor to ground. At the video
black level, the current goes to zero, and thus the voltage of the
video is also zero. Before the availability of high-speed rail-to-
rail op amps, it was essential that an amplifier have a negative
supply to amplify such a signal. Such an amplifier is necessary
if one wants to drive a second monitor with from the same
DAC outputs.
INPUT
OUTPUT
10ꢀs
500mV
However, high-speed, rail-to-rail output amplifiers like the
AD8061 and AD8062 can accept ground level input signals and
output ground level signals and thus be used as RGB signal
amplifiers. A combination of the AD8061 (single) and AD8062
(dual) can amplify the three video channels of an RGB system.
Figure 13 shows a circuit that performs this function.
Figure 12. Input and Output Waveforms for a Single
Supply Video Sync Stripper Using an AD8061
Some video signals with sync are derived from single supply
devices, such as video DACs. These signals can contain sync,
but the whole waveform is positive, and the black level is not at
ground but at some positive voltage. The circuit can be modified to
provide the sync stripping function for such a waveform. Instead
of connecting RG to ground, it should be connected to a dc
voltage that is two times the black level of the input signal. The
gain from the +input to the output is two, which means that
the black level will be amplified by two to the output. However,
the gain through RG is –unity to the output. It will take a dc
level of twice the input black level to shift the black level to
ground at the output. When this occurs, the sync will be
stripped, and the active video will be passed as in the ground
referenced case.
Multiplexer
The AD8063 has a disable pin that can be used to power down
the amplifier to save power, or can be used to create a mux circuit.
If two (or more) AD8063 outputs are connected together and
only one is enabled, then only the signal of the enabled amplifier
will appear at the output. This configuration can be used to select
from various input-signal sources. Additionally, the same input
signal can be applied to different gain stages or differently
tuned filters to make a gain-step amplifier or a selectable-
frequency amplifier.
Figure 14 shows a schematic of two AD8063s used to create a
mux that selects between two inputs. One of these is a 1 V p-p,
3 MHz sine wave and the other is a 2 V p-p, 1 MHz sine wave.
RED
DAC
75ꢁ
75ꢁ
75ꢁ
75ꢁ
75ꢁ
75ꢁ
+4V
MONITOR
#1
GREEN
DAC
0.1ꢀF
10ꢀF
10ꢀF
BLUE
DAC
1
TIME
BASE
OUT
49.9ꢁ
AD8063
1V
P-P
1kꢁ
3MHz
0.1ꢀF
1kꢁ
3V
–4V
0.1ꢀF
10ꢀF
V
7
49.9ꢁ
OUT
1kꢁ
2
3
1kꢁ
75ꢁ
RED
75ꢁ
+4V
6
49.9ꢁ
AD8061
4
0.1ꢀF
10ꢀF
10ꢀF
1kꢁ
1
49.9ꢁ
AD8063
3V
2V
1MHz
MONITOR
#2
P-P
TIME
BASE
IN
0.1ꢀF
10ꢀF
0.1ꢀF
1kꢁ
8
–4V
1kꢁ
1kꢁ
2
75ꢁ
75ꢁ
GREEN
1
AD8062
1kꢁ
3
5
75ꢁ
HCO4
SELECT
BLUE
7
AD8062
Figure 14. Two-to-One Multiplexer Using Two AD8063s
75ꢁ
6
4
1kꢁ
Figure 13. RGB Cable Driver Using AD8061 and AD8062
REV. C
–15–
AD8061/AD8062/AD8063
The SELECT signal and the output waveforms for this circuit
are shown in Figure 15. For synchronization clarity, two differ-
ent frequency synthesizers whose time bases are locked to each
other generate the signals.
2ꢀs
OUTPUT
SELECT
1V
2V
Figure 15. AD8063 Mux Output
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
5-Lead SOT-23-5
(RT-5)
8-Lead SOIC
(SO-8)
0.1220 (3.100)
0.1063 (2.700)
0.1968 (5.00)
0.1890 (4.80)
8
1
5
4
5
1
4
0.2440 (6.20)
0.2284 (5.80)
0.1574 (4.00)
0.1497 (3.80)
0.1181 (3.000)
0.0984 (2.500)
0.0709 (1.800)
0.0590 (1.500)
2
3
PIN 1
PIN 1
0.0196 (0.50)
0.0099 (0.25)
0.0500 (1.27)
BSC
0.0374 (0.950) REF
ꢅ 45ꢂ
0.0688 (1.75)
0.0532 (1.35)
0.0748 (1.900)
REF
0.0098 (0.25)
0.0040 (0.10)
0.0079 (0.200)
0.0035 (0.090)
8ꢂ
0ꢂ
0.0500 (1.27)
0.0160 (0.41)
0.0192 (0.49)
0.0138 (0.35)
0.0512 (1.300)
0.0354 (0.900)
0.0571 (1.450)
0.0354 (0.900)
0.0098 (0.25)
0.0075 (0.19)
SEATING
PLANE
10ꢂ
0ꢂ
SEATING
PLANE
0.0197 (0.500)
0.0118 (0.300)
0.0059 (0.150)
0.0000 (0.000)
0.0236 (0.600)
0.0039 (0.100)
6-Lead SOT-23-6
(RT-6)
8-Lead ꢀSOIC
(RM-8)
0.122 (3.10)
0.106 (2.70)
0.122 (3.10)
0.114 (2.90)
8
5
4
6
5
2
4
3
0.193
(4.90)
BSC
0.071 (1.80)
0.059 (1.50)
0.118 (3.00)
0.098 (2.50)
0.122 (3.10)
0.114 (2.90)
1
1
PIN 1
0.037 (0.95) BSC
PIN 1
0.0256 (0.65) BSC
0.037 (0.95)
0.030 (0.75)
0.075 (1.90)
BSC
0.043
(1.10)
MAX
0.006 (0.15)
0.002 (0.05)
6ꢂ
0ꢂ
0.051 (1.30)
0.035 (0.90)
0.057 (1.45)
0.035 (0.90)
0.016 (0.40)
0.010 (0.25)
SEATING
PLANE
0.028 (0.70)
0.016 (0.40)
0.009 (0.23)
0.005 (0.13)
10ꢂ
0ꢂ
0.020 (0.50)
0.010 (0.25)
0.022 (0.55)
0.014 (0.35)
0.006 (0.15)
0.000 (0.00)
SEATING
PLANE
0.009 (0.23)
0.003 (0.08)
AD8061/AD8062/AD8063–Revision History
Location
Page
Data Sheet changed from REV. B to REV. C.
Replaced TPC 9 with new graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
REV. C
–16–
相关型号：
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