AD7834AR-REEL [ADI]
IC QUAD, SERIAL INPUT LOADING, 10 us SETTLING TIME, 14-BIT DAC, PDSO28, MS-013AE, SOIC-28, Digital to Analog Converter;
| 型号： | AD7834AR-REEL |
| 厂家： | 
ADI |
| 描述： | IC QUAD, SERIAL INPUT LOADING, 10 us SETTLING TIME, 14-BIT DAC, PDSO28, MS-013AE, SOIC-28, Digital to Analog Converter |
| 文件： | 总16页 (文件大小：406K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LC2MOS
Quad 14-Bit DAC
a
AD7834/AD7835
FEATURES
GENERAL DESCRIPTION
Four 14-Bit DACs in One Package
AD7834—Serial Loading
AD7835—Parallel 8-/14-Bit Loading
Voltage Outputs
The AD7834 and AD7835 contain four 14-bit DACs on one
monolithic chip. The AD7834 and AD7835 have output volt-
ages in the range of ±8.192 V with a maximum span of 14 V.
The AD7834 is a serial input device. Data is loaded in 16-bit
format from the external serial bus, MSB first after two leading
0s, into one of the input latches via DIN, SCLK and FSYNC.
The AD7834 has five dedicated package address pins, PA0–
PA4, that can be wired to AGND or VCC to permit up to 32
AD7834s to be individually addressed in a multipackage
application.
Power-On Reset Function
Max/Min Output Voltage Range of +/–8.192 V
Maximum Output Voltage Span of 14 V
Common Voltage Reference Inputs
User Assigned Device Addressing
Clear Function to User-Defined Voltage
Surface Mount Packages
The AD7835 can accept either 14-bit parallel loading or
double-byte loading, where right-justified data is loaded in one
8-bit and one 6-bit byte. Data is loaded from the external bus
into one of the input latches under the control of the WR, CS,
BYSHF and DAC channel address pins, A0–A2.
AD7834—28-Pin SO, DIP and Cerdip
AD7835—44-Pin PQFP and PLCC
APPLICATIONS
Process Control
Automatic Test Equipment
General Purpose Instrumentation
With either device, the LDAC signal can be used to update
either all four DAC outputs simultaneously or individually,
on reception of new data. In addition, for either device, the
asynchronous CLR input can be used to set all signal outputs,
VOUT1–VOUT4, to the user-defined voltage level on the Device
Sense Ground pin, DSG. On power-on, before the power sup-
plies have stabilized, internal circuitry holds the DAC output
voltage levels to within ±2 V of the DSG potential. As the sup-
plies stabilize, the DAC output levels move to the exact DSG
potential (assuming CLR is exercised).
The AD7834 is available in 28-pin 0.3" SO and 0.6" DIP pack-
ages, and the AD7835 is available in a 44-pin PQFP package
and a 44-pin PLCC package.
AD7835 FUNCTIONAL BLOCK DIAGRAM
AD7834 FUNCTIONAL BLOCK DIAGRAM
V
(–)A
V
V
V
V
(+)A
REF
V
V (–)
V
REF
V
V
(+)
DSG A
REF
CC
DD
SS
CC
DD
SS
REF
INPUT
REGISTER
1
INPUT
REGISTER
1
AD7835
AD7834
DAC 1
LATCH
DAC 1
LATCH
DAC 1
DAC 2
DAC 1
DAC 2
BYSHF
PAEN
X1
X1
X1
X1
V
1
2
V
1
2
OUT
OUT
14
DB13
DB0
PA0
PA1
PA2
PA3
PA4
INPUT
BUFFER
INPUT
REGISTER
2
INPUT
REGISTER
2
DAC 2
LATCH
DAC 2
LATCH
CONTROL
LOGIC
V
V
OUT
OUT
WR
CS
&
ADDRESS
DECODE
INPUT
REGISTER
3
INPUT
REGISTER
3
DAC 3
LATCH
DAC 3
LATCH
DAC 3
DAC 4
DAC 3
DAC 4
X1
X1
V
3
4
X1
X1
V
3
4
OUT
OUT
FSYNC
A0
A1
A2
INPUT
REGISTER
4
INPUT
REGISTER
4
ADDRESS
DECODE
DAC 4
LATCH
DAC 4
LATCH
SERIAL-TO-
PARALLEL
CONVERTER
DIN
V
V
OUT
OUT
CLR
SCLK
CLR
AGND
DGND
DSG
LDAC
DSG B
(+)B
REF
AGND
V
V (–)B
REF
DGND
LDAC
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
(VCC = +5 V ± 5%; VDD = +15 V ± 5%; VSS = –15 V ± 5%; AGND =
1
DGND = 0 V; T = TMIN to TMAX, unless otherwise noted)
AD7834/AD7835–SPECIFICATIONS
A
P
arameter
A
B
S
Units
Test Conditions/Comments
ACCURACY
Resolution
14
14
14
Bits
Relative Accuracy
Differential Nonlinearity
Full-Scale Error
TMIN to TMAX
±2
±0.9
±1
±0.9
±2
±0.9
LSB max
LSB max
Guaranteed Monotonic Over Temperature
VREF(+) = +7 V, VREF(–) = –7 V
±5
±4
±0.5
4
20
50
±5
±4
±0.5
4
20
50
±8
±5
±0.5
4
20
50
mV max
mV max
mV typ
ppm FSR/°C typ
ppm FSR/°C max
µV max
Zero-Scale Error
Gain Error
VREF(+) = +7 V, VREF(–) = –7 V
VREF(+) = +7 V, VREF(–) = –7 V
Gain Temperature Coefficient2
DC Crosstalk2
See Terminology. RL = 10 kΩ
REFERENCE INPUTS
DC Input Resistance
Input Current
30
±1
30
±1
30
±1
MΩ typ
µA max
Per Input
VREF(+) Range
VREF(–) Range
[VREF(+)–VREF(–)]
0/+8.192
–8.192/0
5/14
+7/+8.192 0/+8.192 V min/max
–8.192/0
7/14
–8.192/0 V min/max
5/14
V min/max
For Specified Performance. Can Go as Low as
0 V, but Performance Not Guaranteed
DEVICE SENSE GROUND INPUTS
Input Current
±2
±2
±2
µA max
Per Input. VDSG = –2 V to +2 V
DIGITAL INPUTS
VINH, Input High Voltage
VINL, Input Low Voltage
IINH, Input Current
2.4
0.8
±10
10
2.4
0.8
±10
10
2.4
0.8
±10
10
V min
V max
µA max
pF max
CIN, Input Capacitance
POWER REQUIREMENTS
VCC
VDD
VSS
5.0
15.0
–15.0
5.0
15.0
–15.0
5.0
15.0
–15.0
V nom
V nom
V nom
±5% for Specified Performance
±5% for Specified Performance
±5% for Specified Performance
Power Supply Sensitivity
∆Full Scale/∆VDD
∆Full Scale/∆VSS
ICC
110
100
0.2
3
110
100
0.2
3
110
100
0.5
3
dB typ
dB typ
mA max
mA max
mA max
mA max
mA max
mA max
VINH = VCC, VINL = DGND
AD7834. VINH = 2.4 V min, VINL = 0.8 V max
AD7835. VINH = 2.4 V min, VINL = 0.8 V max
AD7834. Outputs Unloaded
AD7835. Outputs Unloaded
Outputs Unloaded
6
6
6
IDD
ISS
10
15
10
10
15
10
15
15
15
(These characteristics are included for Design Guidance and are not
subject to production testing. )
AC PERFORMANCE CHARACTERISTICS
P
arameter
A
B
S
Units
Test Conditions/Comments
DYNAMIC PERFORMANCE
Output Voltage Settling Time
10
10
10
µs typ
Full-Scale Change to ±1/2 LSB. DAC Latch Contents
Alternately Loaded with All 0s and All 1s
Measured with VREF(+) = VREF(–) = 0 V. DAC Latch
Alternately Loaded with All 0s and All 1s
See Terminology
See Terminology; Applies to the AD7835 Only
See Terminology
Feedthrough to DAC Output Under Test Due to
Change in Digital Input Code to Another Converter
Effect of Input Bus Activity on DAC Output Under Test
Digital-to-Analog Glitch Impulse
120
120
120
nV-s typ
DC Output Impedance
Channel-to-Channel Isolation
DAC to DAC Crosstalk
Digital Crosstalk
0.5
100
25
3
0.5
100
25
3
0.5
100
25
3
Ω typ
dB typ
nV-s typ
nV-s typ
Digital Feedthrough – AD7834
Digital Feedthrough – AD7834
Output Noise Spectral Density
@ 1 kHz
0.2
0.1
0.2
0.1
0.2
0.1
nV-s typ
nV-s typ
40
40
40
nV/√Hz typ All 1s Loaded to DAC. VREF(+) = VREF(–) = 0 V
NOTES
1Temperature range is as follows: A Version: –40°C to +85°C; B Version: –40°C to +85°C; S Version: –55°C to +125°C.
2Guaranteed by design.
Specifications subject to change without notice
–2–
REV. A
AD7834/AD7835
TIMING SPECIFICATIONS1
(VCC = +5 V ± 5%; VDD = +15 V ± 5%; VSS = –15 V ± 5%; AGND = DGND = 0 V)
Parameter
Limit at TMIN, TMAX
Units
Description
AD7834 Specific
2
t12
100
50
60
66
30
30
40
30
10
0
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
SCLK Cycle Time
t2
SCLK Low Time @ +25°C
SCLK Low Time –40°C to +85°C
SCLK Low Time –55°C to +125°C
SCLK High Time
FSYNC, PAEN Setup Time
FSYNC, PAEN Hold Time
Data Setup Time
2
t3
t4
t5
t6
t7
t8
t9
Data Hold Time
LDAC to FSYNC Setup Time
LDAC to FSYNC Hold Time
Delay Between Write Operations
40
20
t21
AD7835 Specific
t11
t12
t13
t14
t15
t16
t17
t18
t19
15
15
0
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
A0, A1, A2, BYSHF to CS Setup Time
A0, A1, A2, BYSHF to CS Hold Time
CS to WR Setup Time
CS to WR Hold Time
WR Pulse Width
Data Setup Time
Data Hold Time
LDAC to CS Setup Time
CS to LDAC Setup Time
LDAC to CS Hold Time
0
40
40
10
0
0
0
t20
General
t10
40
ns min
LDAC, CLR Pulse Width
NOTES
1All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2Rise and fall times should be no longer than 50 ns.
Specifications subject to change without notice.
A0. A1 A2
BYSHF
t11
t12
1ST
CLK
2ND
CLK
24TH
CLK
t1
t13
CS
WR
SCLK
t14
t15
t3
t5
t4
t2
FSYNC
t20
t17
t16
t6
t7
D0
DATA
D1
D23
DIN
D22
t10
t10
LDAC
(SIMULTANEOUS
UPDATE)
LDAC
(SIMULTANEOUS
UPDATE)
t8
t9
LDAC
(PRE-CHANNEL
UPDATE)
t19
t18
LDAC
(PRE-CHANNEL
UPDATE)
Figure 2. AD7835 Timing Diagram
Figure 1. AD7834 Timing Diagram
REV. A
–3–
AD7834/AD7835
ABSOLUTE MAXIMUM RATINGS1
(TA = +25°C unless otherwise noted)
VCC to DGND . . . . . . . . . . . . . . . –0.3 V, +7 V or VDD + 0.3 V
(Whichever Is Lower)
SOIC Package
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . +75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
PQFP Package
V
V
DD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V
SS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –17 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +0.3 V
Digital Inputs to DGND . . . . . . . . . . . . . . –0.3 V, VCC + 0.3 V
V
V
V
REF(+) to VREF(–) . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +18 V
REF(+) to AGND . . . . . . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V
REF(–) to AGND . . . . . . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 95°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
PLCC Package
DSG to AGND . . . . . . . . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V
OUT (1–4) to AGND . . . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V
V
Operating Temperature Range
θJA Thermal Impedance. . . . . . . . . . . . . . . . . . . . . . +55°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
Power Dissipation (Any Package) . . . . . . . . . . . . . . . . 480 mW
Industrial (A Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (S Version). . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Plastic Package
NOTES
1Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2Transient currents of up to 100 mA will not cause SCR latch up.
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . +75°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260°C
Cerdip Package
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . +52°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +300°C
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7834/AD7835 feature proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Linearity
Temperature
Range
Error
(LSBs)
DNL
(LSBs)
Package
Model
Option1
AD7834AR
AD7834BR
AD7834AN
AD7834BN
AD7834SQ
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
±2
±1
±2
±1
±2
±0.9
±0.9
±0.9
±0.9
±0.9
R-28
R-28
N-28
N-28
Q-28
AD7835AS2
AD7835BS2
AD7835AP2
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
±2
±1
±2
±0.9
±0.9
±0.9
S-44
S-44
P-44A
NOTES
1R = Small Outline IC (SOIC); N = Plastic DIP; Q = Cerdip; S = Plastic Quad Flatpack (PQFP);
P = Plastic Leaded Chip Carrier (PLCC).
2Contact Sales Office for availability.
–4–
REV. A
AD7834/AD7835
AD7834 PIN DESCRIPTION
Pin Mnemonic
Description
VCC
Logic Power Supply; +5 V ± 5%.
VSS
Negative Analog Power Supply; –15 V ± 5%.
Positive Analog Power Supply; +15 V ± 5%.
Digital Ground.
VDD
DGND
AGND
VREF(+)
VREF(–)
VOUT1 . . . VOUT
DSG
Analog Ground.
Positive Reference Input. The positive reference voltage is referred to AGND.
Negative Reference Input. The negative reference voltage is referred to AGND.
DAC Outputs.
4
Device Sense Ground Input. Used in conjunction with the CLR input for power-on protection of the DACs.
When CLR is low, the DAC outputs are forced to the potential on the DSG pin.
DIN
Serial Data Input.
SCLK
FSYNC
Clock input for writing data to the device.
Frame Sync Input. Active low logic input used, in conjunction with DIN and SCLK, to write data to the device
with serial data expected after the falling edge of this signal. The contents of the 24-bit serial-to-parallel input
register are transferred on the rising edge of this signal.
PA0 . . . PA4
Package Address Inputs. These inputs are hardwired high (VCC) or low (DGND) to assign dedicated package
addresses in a multipackage environment.
PAEN
Package Address Enable Input. When low, this input allows normal operation of the device. When it is high, the
device ignores the package address (but not the channel address) in the serial data stream and loads the serial
data into the input registers. This feature is useful in a multipackage application where it can be used to load the
same data into the same channel in each package.
LDAC
CLR
Load DAC Input (level sensitive). This input signal in conjunction with the FSYNC input signal, determines
how the analog outputs are updated. If LDAC is maintained high while new data is being loaded into the
device’s input registers, no change occurs on the analog outputs. Subsequently, when LDAC is brought low, the
contents of all four input registers are transferred into their respective DAC latches, updating the analog outputs.
Alternatively, if LDAC is kept low while new data is shifted into the device, then the addressed DAC latch (and
corresponding analog output) is updated immediately on the rising edge of FSYNC.
Asynchronous Clear Input (level sensitive, active low). When this input is brought low, all analog outputs are
switched to the externally set potential on the DSG pin. When CLR is brought high, the signal outputs remain at
the DSG potential until LDAC is brought low. When LDAC is brought low, the analog outputs are switched
back to reflect their individual DAC output levels. As long as CLR remains low, the LDAC signals are ignored
and the signal outputs remain switched to the potential on the DSG pin.
PIN CONFIGURATION
DIP AND SOIC
AGND
NC
V
1
2
28
27
SS
DSG
(–)
V
V
3
26 NC
REF
(+)
NC
25
4
REF
NC
2
NC
24
5
AD7834
TOP VIEW
(Not to Scale)
V
6
23
22
21
20
19
18
17
16
15
V
V
V
OUT
DD
V
4
7
1
3
OUT
OUT
OUT
8
DGND
V
9
CLR
CC
SCLK
10
11
12
13
14
LDAC
FSYNC
PAEN
DIN
PA0
PA1
PA2
PA4
PA3
NC = NO CONNECT
REV. A
–5–
AD7834/AD7835
AD7835 PIN DESCRIPTION
Pin Mnemonic
Description
VCC
Logic Power Supply; +5 V ± 5%.
VSS
Negative Analog Power Supply; –15 V ± 5%.
Positive Analog Power Supply; +15 V ± 5%.
Digital Ground.
VDD
DGND
AGND
Analog Ground.
VREF(+)A, VREF(–)A
VREF(+)B, VREF(–)B
Reference Inputs for DACs 1 and 2. These reference voltages are referred to AGND.
Reference Inputs for DACs 3 and 4. These reference voltages are referred to AGND.
DAC Outputs.
VOUT1 . . . VOUT
CS
4
Level-Triggered Chip Select Input (active low). The device is selected when this input is low.
DB0 . . . DB13
Parallel Data Inputs. The AD7835 can accept a straight 14-bit parallel word on DB0 to DB13, where
DB13 is the MSB and the BYSHF input is hardwired to a logic high. Alternatively for byte loading, the
bottom 8 data inputs, DB0–DB7, are used for data loading while the top 6 data inputs, DB8 to DB13,
should be hardwired to a logic low. The BYSHF control input selects whether 8 LSBs or 6 MSBs of data
are being loaded into the device.
BYSHF
Byte Shift Input. When low, it shifts the data on DB0–DB7 into the DB8–DB13 half of the input register.
A0, A1, A2
Address inputs. A0 and A1 are decoded to select one of the four input latches for a data transfer. A2 is
used to select all four DACs simultaneously.
LDAC
Load DAC Input (level sensitive). This input signal in conjunction with the WR and CS input signals, de-
termines how the analog outputs are updated. If LDAC is maintained high while new data is being loaded
into the device’s input registers, no change occurs on the analog outputs. Subsequently, when LDAC is
brought low, the contents of all four input registers are transferred into their respective DAC latches, up-
dating the analog outputs simultaneously.
Alternatively, if LDAC is brought low while new data is being entered, then the addressed DAC latch
(and corresponding analog output) is updated immediately on the rising edge of WR.
CLR
Asynchronous Clear Input (level sensitive, active low). When this input is brought low, all analog outputs
are switched to the externally set potentials on the DSG pins (VOUT1 and VOUT2 follow DSGA while
V
OUT3 and VOUT4 follow DSGB). When CLR is brought high, the signal outputs remain at the DSG po-
tentials until LDAC is brought low. When LDAC is brought low, the analog outputs are switched back to
reflect their individual DAC output levels. As long as CLR remains low, the LDAC signals are ignored
and the signal outputs remain switched to the potential on the DSG pins.
WR
Level-Triggered Write Input (active low). When active it is used in conjunction with CS to write data over
the input data bus.
DSGA
DSGB
Device Sense Ground A Input. Used in conjunction with the CLR input for power-on protection of the
DACs. When CLR is low, DAC outputs VOUT1 and VOUT2 are forced to the potential on the DSGA pin.
Device Sense Ground B Input. Used in conjunction with the CLR input for power-on protection of the
DACs. When CLR is low, DAC outputs VOUT3 and VOUT4 are forced to the potential on the DSGB pin.
–6–
REV. A
AD7834/AD7835
PIN CONFIGURATIONS
PQFP
PLCC
44 43 42 41 40 39 38 37 36 35 34
6
5
4
3
2
1
44 43 42 41 40
PIN 1
NC
NC
7
8
1
2
3
4
5
6
7
8
9
33 NC
39 NC
IDENTIFIER
PIN 1
IDENTIFIER
DSGA
DSGA
32 DSGB
38 DSGB
V
V
1
2
31
V
V
1
2
9
37
36
V
3
4
V
V
3
4
OUT
OUT
OUT
OUT
10
11
12
13
14
15
16
17
30 V
OUT
OUT
OUT
OUT
NC
A2
A1
NC
A2
29 DB13
28 DB12
27 DB11
35 DB13
34 DB12
33 DB11
AD7835
TOP VIEW
(Not to Scale)
AD7835
TOP VIEW
(Not to Scale)
A1
DB10
DB9
DB8
DB7
DB10
DB9
DB8
DB7
26
25
24
23
32
31
30
29
A0
A0
CLR
CLR
LDAC 10
LDAC
BYSHF 11
BYSHF
12 13 14 15 16 17 18 19 20 21 22
19
26
20 21 22 23 24 25 27 28
18
NC = NO CONNECT
NC = NO CONNECT
TERMINOLOGY
Relative Accuracy
signal from one DACs reference input which appears at the out-
put of the other DAC. It is expressed in dBs.
Relative Accuracy or endpoint linearity is a measure of the max-
imum deviation from a straight line passing through the endpoints
of the DAC transfer function. It is measured after adjusting for
zero error and full-scale error and is normally expressed in Least
Significant Bits or as a percentage of full-scale reading.
The AD7834 has no specification for Channel-to-channel isola-
tion because it has one reference for all DACs. Channel-to-
channel isolation is specified for the AD7835.
DAC-to-DAC Crosstalk
DAC-to-DAC Crosstalk is defined as the glitch impulse that ap-
pears at the output of one converter due to both the digital
change and subsequent analog O/P change at another converter.
It is specified in nV-s.
Differential Nonlinearity
Differential Nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.
Digital Crosstalk
The glitch impulse transferred to the output of one converter
due to a change in digital input code to the other converter is
defined as the Digital Crosstalk and is specified in nV-s.
DC Crosstalk
Although the common input reference voltage signals are inter-
nally buffered, small IR drops in the individual DAC reference
inputs across the die can mean that an update to one channel
can produce a dc output change in one or other of the channel
outputs.
Digital Feedthrough
When the device is not selected, high frequency logic activity on
the device’s digital inputs can be capacitively coupled both
across and through the device to show up as noise on the VOUT
pins. This noise is digital feedthrough.
The four DAC outputs are buffered by op amps that share com-
mon VDD and VSS power supplies. If the dc load current changes
in one channel (due to an update), this can result in a further dc
change in one or other channel outputs. This effect is most ob-
vious at high load currents and reduces as the load currents are
reduced. With high impedance loads the effect is virtually
unmeasurable.
DC Output Impedance
This is the effective output source resistance. It is dominated by
package lead resistance.
Full-Scale Error
This is the error in DAC output voltage when all 1s are loaded
into the DAC latch. Ideally the output voltage, with all 1s
loaded into the DAC latch, should be VREF(+) – 1 LSB. Full-
Scale Error does not include Zero-Scale Error.
Output Voltage Settling Time
This is the amount of time it takes for the output to settle to a
specified level for a full-scale input change.
Digital-to-Analog Glitch Impulse
Zero-Scale Error
This is the amount of charge injected into the analog output when
the inputs change state. It is specified as the area of the glitch in
nV-secs. It is measured with the reference inputs connected to 0 V
and the digital inputs toggled between all 1s and all 0s.
Zero-Scale Error is the error in the DAC output voltage when
all 0s are loaded into the DAC latch. Ideally the output voltage,
with all 0s in the DAC latch should be equal to VREF(–). Zero-
Scale Error is mainly due to offsets in the output amplifier.
Channel-to-Channel Isolation
Gain Error
Channel-to-channel isolation refers to the proportion of input
Gain Error is defined as (Full-Scale Error) – (Zero-Scale Error).
REV. A
–7–
AD7834/AD7835–Typical Performance Characteristics
0.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.4
0.8
0.3
0.6
0.2
0.4
0.1
0.2
0.0
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.2
–0.4
–0.6
–0.8
–1.0
16
16
0
2
4
6
8
10 12 14
0
1
2
3
4
5
6
7
8
0
2
4
6
8
10 12
14
V
(+) – Volts
CODE/1000
CODE/1000
REF
Figure 5. Typical INL vs. VREF(+)
(VREF(–) = –6 V)
Figure 3. Typical INL Plot
Figure 4. Typical DNL Plot
1.0
0.8
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.5
0.45
0.4
DAC 1
0.6
DAC 1
0.4
0.35
0.3
DAC 3
DAC 3
0.2
DAC 4
DAC 4
0.0
0.25
0.2
DAC 2
–0.2
–0.4
–0.6
–0.8
–1.0
DAC 2
TEMP = +25°C
ALL DACs FROM 1 DEVICE
0.15
0.1
ALL DACs FROM ONE DEVICE
0.05
0
16
0
2
4
6
8
10 12
14
–40
+25
+85
0
2.5
V
5
8
CODE/1000
TEMPERATURE – °C
(+) – Volts
REF
Figure 8. Typical DAC-to-DAC
Matching
Figure 6. Typical INL vs. VREF(+)
(VREF(+) – VREF(–) = 5 V)
Figure 7. Typical INL vs.
Temperature
8
6
–2.985
–3.005
0.7
8
6
7.25
7.225
7.2
VERT = 10mV/DIV
HORIZ = 1µs/DIV
VERT = 2V/DIV
HORIZ = 1.2µs/DIV
VERT = 100mV/DIV
0.6
HORIZ = 1µs/DIV
0.5
4
–3.025
–3.045
4
0.4
0.3
0.2
V
V
(+) = +7V
REF
(–) = –3V
V
V
(+) = +7V
(–) = –3V
REF
REF
2
2
7.175
7.15
7.125
7.1
REF
0
–3.065
0
0.1
0
–2
–4
–3.085
–3.105
–2
–4
VERT = 25mV/DIV
HORIZ = 2.5µs/DIV
VERT = 2V/DIV
HORIZ = 1µs/DIV
–0.1
–0.2
Figure 11. Settling Time (–)
Figure 9. Typical Digital/Analog
Glitch Impulse
Figure 10. Settling Time (+)
–8–
REV. A
AD7834/AD7835
Table I. D23 Control
GENERAL DESCRIPTION
DAC Architecture—General
Each channel consists of a segmented 14-bit R-2R voltage-mode
DAC. The full- scale output voltage range is equal to the entire
reference span of VREF(+) – VREF(–). The DAC coding is
straight binary; all 0s produces an output of VREF(–); all 1s pro-
duces an output of VREF(+) – 1 LSB.
D23
Control Function
0
1
Ignore following 23 bits of information.
Use following 23 bits of address and
data as normal.
The analog output voltage of each DAC channel reflects the
contents of its own DAC latch. Data is transferred from the ex-
ternal bus to the input register of each DAC latch on a per
channel basis. The AD7835 has a feature whereby using the A2
pin, data can be transferred from the input data bus to all four
input registers simultaneously.
D22 and D21: Decoded to select one of the four DAC channels
within a device. The truth table for D22 and D21 is as shown
below in Table II.
Table II. D22, D21 Control
D22
D21
Control Function
Bringing the CLR line low switches all the signal outputs,
V
OUT1 to VOUT4, to the voltage level on the DSG pin. The sig-
0
0
1
1
0
1
0
1
Select Channel 1
Select Channel 2
Select Channel 3
Select Channel 4
nal outputs are held at this level after the removal of the CLR
signal and will not switch back to the DAC outputs until the
LDAC signal is exercised.
Data Loading—AD7834, Serial Input Device
A write operation transfers 24 bits of data to the AD7834. The
first 8 bits are control data and the remaining 16 bits are DAC
data (see Figure 12). The control data identifies the DAC chan-
nel to be updated with new data and which of 32 possible pack-
ages the DAC resides in. In any communication with the device
the first 8 bits must always be control data.
D20–D16: Determines the package address. The five address
bits allow up to 32 separate packages to be individually de-
coded. Successful decoding is accomplished when these five bits
match up with the five hardwired pins on the physical package.
D15–D0: DAC Data to be loaded into identified DAC Input
Register. This data must have two leading 0s followed by 14 bits
of data, MSB first. The MSB is in location D13 of the 24-bit
data stream.
Note that the DAC output voltages, VOUT1 to VOUT4, can be
updated to reflect new data in the DAC input registers in one of
two ways. The first method normally keeps LDAC high and
only pulses LDAC low momentarily to update all DAC latches
simultaneously with the contents of their respective input regis-
ters. The second method ties LDAC low, and channel updating
occurs on a per channel basis after new data has been clocked
into the AD7834. With LDAC low, the rising edge of FSYNC
transfers the new data directly into the DAC latch, updating the
analog output voltage.
Data Loading—AD7835, Parallel Loading Device
Data can be loaded into the AD7835 in either straight 14-bit
wide words or in two 8-bit bytes.
In systems which can transfer 14-bit wide data, the BYSHF
input should be hardwired to VCC. This sets up the AD7835
as a straight 14-bit parallel-loading DAC.
In 8-bit bus systems where it is required to transfer data in two
bytes, it is necessary to have the BYSHF input under logic con-
trol. In such a system the top 6 pins of the device data bus,
DB8–DB13, must be hardwired to DGND. New low byte data
is loaded into the lower 8 places of the selected input register by
carrying out a write operation while holding BYSHF high. A
second write operation is subsequently executed with BYSHF
low and the 6 MSBs on the DB0–DB5 inputs (DB5 = MSB).
Data being shifted into the AD7834 enters a 24-bit long shift
register. If more than 24 bits are clocked in before FSYNC goes
high, the last 24 bits transmitted are used as the control data
and DAC data.
Individual bit functions are discussed below.
D23: Determines whether the following 23-bits of address and
data should be used or should be ignored. This is effectively a
software Chip Select bit. D23 is the first bit to be transmitted in
the 24-bit long word.
NOTE: D23 IS THE FIRST BIT TRANSMITTED IN THE SERIAL WORD.
D23 D22 D21 D20
D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D19
LSB, DB0
CONTROL BIT TO USE/IGNORE
FOLLOWING 23 BITS OF INFORMATION
SECOND LSB, DB1
THIRD LSB, DB2
DB3
CHANNEL ADDRESS MSB, D1
CHANNEL ADDRESS LSB, D2
PACKAGE ADDRESS MSB, PA4
PACKAGE ADDRESS, PA3
PACKAGE ADDRESS, PA2
PACKAGE ADDRESS, PA1
PACKAGE ADDRESS LSB, PA0
DB4
DB5
DB6
DB7
DB8
DB9
DB10
THIRD MSB, DB11
SECOND MSB, DB12
MSB, DB13
SECOND LEADING ZERO
FIRST LEADING ZERO
Figure 12. Bit Assignments for 24-Bit Data Stream of AD7834
–9–
REV. A
AD7834/AD7835
When 14-bit transfers are being used, the DAC output voltages,
Table IV. Code Table for Unipolar Operation
V
OUT1–VOUT4, can be updated to reflect new data in the DAC
Binary Number in DAC Latch
Analog Output
(VOUT
input registers in one of two ways. The first method normally
keeps LDAC high and only pulses LDAC low momentarily to
update all DAC latches simultaneously with the contents of
their respective input registers. The second method ties LDAC
low and channel updating occurs on a per channel basis after
new data is loaded to an input register.
MSB
LSB
)
11
10
01
00
00
1111
0000
1111
0000
0000
1111 1111
0000 0000
1111 1111
0000 0001
0000 0000
VREF (16383/16384) V
V
V
V
REF (8192/16384) V
REF (8191/16384) V
REF (1/16384) V
In order to avoid the DAC output going to an intermediate
value during a 2-byte transfer, LDAC should not be tied low
permanently, but should be held high until the 2 bytes are writ-
ten to the input register. When the selected input register has
been loaded with the 2 bytes, LDAC should then be pulsed low
to update the DAC latch and, hence, perform the digital-to-
analog conversion.
0 V
NOTE
VREF = VREF(+); VREF(–) = 0 V for unipolar operation.
For VREF(+) = +5 V, 1 LSB = +5 V/214 = +5 V/16384 = 305 µV.
Bipolar Configuration
Figure 14 shows the AD7834/AD7835 set up for ±5 V opera-
tion. The AD588 provides precision ±5 V tracking outputs
which are fed to the VREF(+) and VREF(–) inputs of the AD7834/
AD7835. The code table for bipolar operation of the AD7834/
AD7835 is shown in Table V.
In many applications, it may be acceptable to allow the DAC
output to go to an intermediate value during a 2-byte transfer.
In such applications, LDAC can be tied low, thus using one less
control line.
+15V
+5V
The actual DAC input register that is being written to is deter-
mined by the logic levels present on the devices address lines, as
shown in Table III.
R1
39kΩ
6
4
7
9
Table III. AD7835—Address Line Truth Table
2
V
V
CC
DD
C1
1µF
3
V
OUT
(–5 TO +5V)
V
V
V
(+)
OUT
REF
A2
A1
A0
DAC Selected
1
AD588
AD7834/
14
15
16
5
10
11
AD7835
*
R2
100kΩ
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
DAC 1
DAC 2
DAC 3
DAC 4
AGND
(–)
REF
DGND
V
SS
12
8
13
R3
100kΩ
SIGNAL
GND
All DACs Selected
–15V
*
ADDITIONAL PINS OMITTED FOR CLARITY
Unipolar Configuration
Figure 13 shows the AD7834/AD7835 in the unipolar binary
circuit configuration. The VREF(+) input of the DAC is driven
by the AD586, a +5 V reference. VREF(–) is tied to ground.
Table IV gives the code table for unipolar operation of the
AD7834/AD7835.
Figure 14. Bipolar ±5 V Operation
Table V. Code Table for Bipolar Operation
Binary Number in DAC Latch Analog Output
MSB
LSB
(VOUT
)
+15V
+5V
11
10
10
01
00
00
1111 1111
0000 0000
0000 0000
1111 1111
0000 0000
0000 0000
1111
0001
0000
1111
0001
0000
VREF(–) + VREF (16383/16384) V
VREF(–) + VREF (8193/16384) V
VREF(–) + VREF (8192/16384) V
VREF(–) + VREF (8191/16384) V
VREF(–) + VREF (1/16384) V
2
V
V
CC
DD
6
5
V
OUT
(0 TO +5V)
V
V
(+)
V
REF
OUT
8
AD586
4
R1
10kΩ
AD7834/
AD7835
C1
1nF
*
VREF(–) V
AGND
(–)
REF
DGND
NOTE
V
SS
VREF = (VREF(+) – VREF(–)).
SIGNAL
GND
SIGNAL
GND
For VREF(+) = +5 V, and VREF(–) = –5 V, 1 LSB = 10 V/214 = 10 V/16384 =
–15V
ADDITIONAL PINS OMITTED FOR CLARITY
610 µV.
*
In Figure 14, full-scale and bipolar zero adjustments are pro-
vided by varying the gain and balance on the AD588. R2 varies
the gain on the AD588 while R3 adjusts the offset of both the
+5 V and –5 V outputs together with respect to ground.
Figure 13. Unipolar +5 V Operation
Offset and gain may be adjusted in Figure 13 as follows: To ad-
just offset, disconnect the VREF(–) input from 0 V, load the DAC
with all 0s and adjust the VREF(–) voltage until VOUT = 0 V. For
gain adjustment, the AD7834/AD7835 should be loaded with
all 1s and R1 adjusted until VOUT = 5 V(16383/16384) =
4.999695.
For bipolar-zero adjustment, the DAC is loaded with
1000 . . . 0000 and R3 is adjusted until VOUT = 0 V. Full scale
is adjusted by loading the DAC with all 1s and adjusting R2 un-
til VOUT = 5(8191/8192) V = 4.99939 V.
When bipolar-zero and full-scale adjustment are not needed, R2
and R3 can be omitted. Pin 12 on the AD588 should be con-
nected to Pin 11 and Pin 5 should be left floating.
Many circuits will not require these offset and gain adjustments. In
these circuits R1 can be omitted. Pin 5 of the AD586 may be left
open circuit and Pin 2 (VREF(–)) of the AD7834/AD7835 tied to
0 V.
–10–
REV. A
AD7834/AD7835
CONTROLLED POWER-ON OF THE OUTPUT STAGE
A block diagram of the output stage of the AD7834/AD7835 is
shown in Figure 15. It is capable of driving a load of 10 kΩ in
parallel with 200 pF. G1 to G6 are transmission gates that are
used to control the power on voltage present at VOUT. G1 and
G2 are also used in conjunction with the CLR input to set VOUT
to the user defined voltage present at the DSG pin.
VOUT has been disconnected from the DSG pin by the opening
of G5 but will track the voltage present at DSG via the unity
gain buffer.
Power-On with LDAC Low, CLR High
In many applications of the AD7834/AD7835 LDAC will be
kept continuously low, thus updating the DAC after each valid
data transfer. If LDAC is low when power is applied, then G1 is
closed and G2 is open, thus connecting the output of the DAC
to the input of the output amplifier. G3 and G5 will be closed
and G4 and G6 open, connecting the amplifier as a unity gain
buffer, as before. VOUT is connected to DSG via G5 and R (a
thin film resistance between DSG and VOUT) until VDD and VSS
reach approximately ±10 V. Then, the internal power-on cir-
cuitry opens G3 and G5 and closes G4 and G6. This is the situa-
tion shown in Figure 18. VOUT is now at the same voltage as the
DAC output.
G
1
G
6
DAC
V
OUT
G
3
G
4
G
2
G
5
R
DSG
G
1
Figure15. BlockDiagramofAD7834/AD7835OutputStage
G
6
DAC
V
OUT
Power-On with CLR Low, LDAC High
G
3
The output stage of the AD7834/AD7835 has been designed to
allow output stability during power-on. If CLR is kept low dur-
ing power-on, then just after power is applied to the part, the
situation is as depicted in Figure 16. G1, G4 and G6 are open
while G2, G3 and G5 are closed.
G
4
G
2
G
5
R
DSG
G
1
G
6
DAC
V
Figure 18. Output Stage with LDAC Low
Loading the DAC and Using the CLR Input
OUT
G
3
G
4
When LDAC goes low, it closes G1 and opens G2 as in Fig-
ure 18. The voltage at VOUT now follows the voltage present at
the output of the DAC. The output stage remains connected in
this manner until a CLR signal is applied. Then the situation
reverts to that shown in Figure 17. Once again VOUT remains at
the same voltage as DSG until LDAC goes low. This recon-
nects the DAC output to the unity gain buffer.
G
2
G
5
R
DSG
Figure 16. Output Stage with VDD < 10 V
VOUT is kept within a few hundred millivolts of DSG via G5 and
R. R is a thin-film resistor between DSG and VOUT. The out-
put amplifier is connected as a unity gain buffer via G3 and the
DSG voltage is applied to the buffer input via G2. The amplifi-
ers output is thus at the same voltage as the DSG pin. The out-
put stage remains configured as in Figure 16 until the voltage at
DSG Voltage Range
During power-on, the VOUT pins of the AD7834/AD7835 are
connected to the relevant DSG pins via G6 and the thin film re-
sistor, R. The DSG potential must obey the max ratings at all
times. Thus, the voltage at DSG must always be within the
range VSS – 0.3 V, VDD + 0.3 V. However, in order that the volt-
ages at the VOUT pins of the AD7834/AD7835 stay within
±2 V of the relevant DSG potential during power-on, the
voltage applied to DSG should also be kept within the range
AGND – 2 V, AGND + 2 V.
V
DD and VSS reaches approximately ±10 V. By now the output
amplifier has enough headroom to handle signals at its input
and has also had time to settle. The internal power-on circuitry
opens G3 and G5 and closes G4 and G6. This situation is shown
in Figure 17. Now the output amplifier is connected in unity
gain mode via G4 and G6. The DSG voltage is still applied to
Once the AD7834/AD7835 has powered on and the on-chip
amplifiers have settled, the situation is as shown as in Figure 17.
Any voltage that is now applied to the DSG pin is buffered by
the same amplifier that buffers the DAC output voltage in nor-
mal operation. Thus, for specified operation, the maximum
voltage that can be applied to the DSG pin increases to the
maximum allowable VREF(+) voltage, and the minimum voltage
that can be applied to DSG is the minimum VREF(–) voltage. After
the AD7834/AD7835 has fully powered on, the outputs can
track any DSG voltage within this minimum/maximum range.
the noninverting input via G2. This voltage appears at VOUT
.
G
1
G
6
DAC
V
OUT
G
3
G
4
G
2
G
5
R
POWER-ON OF THE AD7834/AD7835
DSG
Power should normally be applied to the AD7834/AD7835 in
the following sequence: first VDD and VSS, then VCC, then
Figure 17. Output Stage with VDD > 10 V and CLR Low
VREF(+) and VREF(–).
REV. A
–11–
AD7834/AD7835
The VREF pins should never be allowed to float when power is
applied to the part. (VREF(+) should never be allowed to go
below VREF(–)–0.3 V. VREF(–) should never be allowed to go
below VSS–0.3 V. VDD should never be allowed to go below
the AD7834 while the MOSI output drives the serial data line,
DIN, of the AD7834. The FSYNC signal is derived from port
line PC7 in this example.
For correct operation of this interface, the 68HC11 should be
configured such that its CPOL bit is a 0 and its CPHA bit is a 1.
When data is to be transferred to the part, PC7 is taken low.
When the 68HC11 is configured like this, data on MOSI is valid
on the falling edge of SCK. The 68HC11 transmits its serial
data in 8-bit bytes, MSB first. The AD7834 expects the MSB
of the 24-bit write first also. Eight falling clock edges occur in
the transmit cycle. To load data to the AD7834, PC7 is left low
after the first eight bits are transferred. A second byte of data is
then transmitted serially to the AD7834. Then a third byte is
transmitted, and when this transfer is complete, the PC7 line is
taken high.
V
CC–0.3 V.
In some systems it may be necessary to introduce one or more
Schottky diodes between pins to prevent the above situations
arising at power-on. These diodes are shown in Figure 19. How-
ever in most systems, with careful consideration given to power
supply sequencing, the above rules will be adhered to and pro-
tection diodes won’t be necessary.
V
(+)
REF
SD103C
1N5711
1N5712
AD7834
*
V
(–)
REF
AD7834
*
68HC11
*
PC5
CLR
*ADDITIONAL PINS OMITTED FOR CLARITY
PC6
PC7
LDAC
FSYNC
SCLK
DIN
Figure 19. Power-ON Protection
MICROPROCESSOR INTERFACING
AD7834 to 80C51 Interface
SCK
MOSI
A serial interface between the AD7834 and the 80C51 micro-
controller is shown in Figure 20. TXD of the 80C51 drives
SCLK of the AD7834 while RXD drives the serial data line of
the part.
*
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 21. AD7834 to 68HC11 Interface
The 80C51 provides the LSB of its SBUF register as the first bit
in the serial data stream. The AD7834 expects the MSB of the
24-bit write first. Therefore, the user will have to ensure that
the data in the SBUF register is arranged correctly so that this is
taken into account. When data is to be transmitted to the part,
P3.3 is taken low. Data on RXD is valid on the falling edge of
TXD. The 80C51 transmits its data in 8-bit bytes with only 8
falling clock edges occurring in the transmit cycle. To load data
to the AD7834, P3.3 is left low after the first eight bits are
transferred. A second byte is then transferred, with P3.3 still
kept low. After the third byte has been transferred, the P3.3
line is taken high.
In Figure 21, LDAC and CLR are controlled by the PC6 and
PC5 port outputs. As with the 80C51, each DAC of the
AD7834 can be updated after each three-byte transfer, or else
all DACs can be simultaneously updated after twelve bytes have
been transferred.
AD7834 to ADSP-2101 Interface
An interface between the AD7834 and the ADSP-2101 is shown
in Figure 22. In the interface shown, SPORT0 is used to trans-
fer data to the part. SPORT1 is configured for alternate func-
tions. FO, the flag output on SPORT1, is connected to LDAC
and is used to load the DAC latches. In this way data can be
transferred from the ADSP-2101 to all the input registers in the
DAC and the DAC latches can be updated simultaneously. In
the application shown, the CLR pin on the AD7834 is con-
trolled by circuitry that monitors the power in the system.
AD7834
*
80C51
*
P3.5
CLR
P3.4
P3.3
TXD
RXD
LDAC
FSYNC
SCLK
DIN
POWER
MONITOR
AD7834*
ADSP-2101*
CLR
FO
LDAC
FSYNC
SCLK
DIN
TFS
SCK
DT
*
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 20. AD7834 to 80C51 Interface
LDAC and CLR on the AD7834 are also controlled by 80C51
port outputs. The user can bring LDAC low after every three
bytes have been transmitted to update the DAC which has been
programmed. Alternatively, it is possible to wait until all the in-
put registers have been loaded (twelve byte transmits) and then
update the DAC outputs.
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 22. AD7834 to ADSP-2101 Interface
The AD7834 requires 24 bits of serial data framed by a single
FSYNC pulse. It is necessary that this FSYNC pulse stays low
until all the data has been transferred. This can be provided by
the ADSP-2101 in one of two ways. Both require setting the se-
AD7834 to 68HC11 Interface
Figure 21 shows a serial interface between the AD7834 and the
68HC11 microcontroller. SCK of the 68HC11 drives SCLK of
–12–
REV. A
AD7834/AD7835
rial word length of the SPORT to 12 bits, with the following
conditions: Internal SCLK; Alternate framing mode; Active low
framing signal. Data can be transferred using the Autobuffering
feature of the ADSP-2101, sending two 12-bit words directly af-
ter each other. This ensures a continuous TFS pulse. Alterna-
tively, the first data word can be loaded to the serial port, the
subsequent interrupt that is generated can be trapped and then
the second data word can be sent immediately after the first.
Again this produces a continuous TFS pulse that frames the 24
data bits.
Interfacing the AD7835—16-Bit Interface
The AD7835 can be interfaced to a variety of microcontrollers
or DSP processors, both 8-bit and 16-bit. Figure 25 shows the
AD7835 interfaced to a generic 16-bit microcontroller/DSP
processor. BYSHF is tied to VCC in this interface. The lower ad-
dress lines from the processor are connected to A0, A1 and A2
on the AD7835 as shown. The upper address lines are decoded
to provide a chip select signal for the AD7835. They are also
decoded (in conjunction with the lower address lines if need be)
to provide a LDAC signal. Alternatively, LDAC could be
driven by an external timing circuit or just tied low. The data
lines of the processor are connected to the data lines of the
AD7835. The selection of the DACs is as given in Table III.
AD7834 to DSP56000/DSP56001 Interface
Figure 23 shows a serial interface between the AD7834 and the
DSP56000/DSP56001. The serial port is configured for a word
length of 24 bits, gated clock and with FSL0 and FSL1 control
bits each set to “0.” Normal Mode Synchronous operation is
selected which allows the use of SC0 and SC1 as outputs con-
trolling CLR and LDAC. The framing signal on SC2 has to be
inverted before being applied to FSYNC. SCK is internally
generated on the DSP56000/DSP56001 and is applied to SCLK
on the AD7834. Data from the DSP56000/DSP56001 is valid
on the falling edge of SCK.
V
CC
µCONTROLLER/
AD7835
*
DSP
PROCESSOR
BYSHF
*
D13
D13
DATA
BUS
D0
D0
UPPER BITS OF
ADDRESS BUS
CS
ADDRESS
DECODE
LDAC
DSP56000/
AD7834
*
A2
A1
A0
WR
A2
A1
DSP56001
*
CLR
SC0
SC1
SC2
SCK
STD
A0
R/W
LDAC
FSYNC
SCLK
DIN
*
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 25. AD7835 16-Bit Interface
8-Bit Interface
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 26 shows an 8-bit interface between the AD7835 and a
generic 8-bit microcontroller/DSP processor. Pins D13 to D8
of the AD7835 are tied to DGND. Pins D7 to D0 of the pro-
cessor are connected to pins D7 to D0 of the AD7835. BYSHF
is driven by the A0 line of the processor. This maps the DAC
upper bits and lower bits into adjacent bytes in the processors
address space. Table VI shows the truth table for addressing
the DACs in the AD7835. If, for example, the base address for
the DACs in the processor address space is decoded by the up-
per address bits to location HC000, then the first DAC’s upper
and lower bits are at locations HC000 and HC001 respectively.
Figure 23. AD7834 to DSP5600/DSP56001 Interface
AD7834 to TMS32020/TMS320C25
A serial interface between the AD7834 and the TMS32020/
TMS320C25 DSP processor is shown in Figure 24. The CLKX
and FSX signals for the TMS32020/TMS32025 should be gen-
erated using an external clock/timer circuit. The CLKX and
FSX pin should be configured as inputs. The TMS32020/
TMS320C25 should be set up for an 8-bit serial data length.
Data can then be written to the AD7834 by writing three bytes
to the serial port of the TMS32020/TMS320C25. In the con-
figuration shown in Figure 24 the CLR input on the AD7834 is
controlled by the XF output on the TMS32020/TMS320C25.
The clock/timer circuit controls the LDAC input on the
AD7834. Alternatively, LDAC could also be tied to ground to
allow automatic update of the DAC latches after each transfer.
D13
µCONTROLLER/
DSP
PROCESSOR
D8
*
DGND
AD7835
*
D7
D7
DATA
BUS
D0
D0
CLOCK/
TIMER
UPPER BITS OF
ADDRESS BUS
CS
TMS32020/
TMS320C25
AD7834
*
ADDRESS
DECODE
LDAC
*
LDAC
XF
FSX
A3
A2
A2
CLR
A1
FSYNC
SCLK
DIN
A0
A1
BYSHF
WR
A0
CLKX
DX
R/W
*
ADDITIONAL PINS OMITTED FOR CLARITY
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 26. AD7835 8-Bit Interface
Figure 24. AD7834 to TMS32020/TMS320C25 Interface
REV. A
–13–
AD7834/AD7835
unique address by hardwiring each of the Package Address pins
to VCC or DGND. Normal operation of the device occurs when
PAEN is low. When serial data is being written to the AD7834s,
only the device with the same package address as the package
address contained in the serial data will accept data into the
input registers. If, on the other hand, PAEN is high, the package
address is ignored and the data is loaded into the same channel
on each package.
When writing to the DACs, the lower 8 bits must be written
first, followed by the upper 6 bits. The upper 6 bits should be
output on data lines D0 to D5. Once again, the upper address
lines of the processor are decoded to provide a CS signal. They
are also decoded in conjunction with lines A3 to A0 to provide a
LDAC signal. Alternatively, LDAC can be driven by an exter-
nal timing circuit or, if it’s acceptable to allow the DAC output
to go to an intermediate value between 8-bit writes, LDAC can
be tied low.
The main limitation with multiple packages is the output update
rate. For example, if an output update rate of 10 kHz is re-
quired, then there are 100 µs to load all DACs. Assuming a se-
rial clock frequency of 10 MHz, it takes 2.5 µs to load data to
one DAC. Thus forty DACs or ten packages can be updated in
this time. As the update rate requirement decreases, the num-
ber of possible packages increases.
Table VI. DAC Selection, 8-Bit Interface
Processor Address Lines
DAC Selected
A3
A2
A1
A0
1
1
0
0
0
0
0
0
0
0
X
X
0
0
0
0
1
1
1
1
X
X
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
Upper 6 Bits of All DACs
Lower 8 Bits of All DACs
Upper 6 Bits, DAC 1
Lower 8 Bits, DAC 1
Upper 6 Bits, DAC 2
Lower 8 Bits, DAC 2
Upper 6 Bits, DAC 3
Lower 8 Bits, DAC 3
Upper 6 Bits, DAC 4
Lower 8-Bits, DAC 4
Opto-Isolated Interface
In many process control applications it is necessary to provide
an isolation barrier between the controller and the unit being
controlled. Opto-isolators can provide voltage isolation in ex-
cess of 3 kV. The serial loading structure of the AD7834 makes
it ideal for opto-isolated interfaces as the number of interface
lines is kept to a minimum. Figure 28 shows a 5-channel iso-
lated interface to the AD7834. Multiple devices are connected
to the outputs of the opto-coupler and controlled as explained
above. To reduce the number of opto-isolators, the PAEN line
doesn’t need to be controlled if it is not used. If the PAEN line
is not controlled by the microcontroller then it should be tied
low at each device. If simultaneous updating of the DACs is not
required, then LDAC pin on each part can be tied permanently
low and a further opto-isolator is not needed.
APPLICATIONS
Serial Interface to Multiple AD7834s
Figure 27 shows how the Package Address pins of the AD7834
are used to address multiple AD7834s. The figure shows only
10 devices, but up to 32 AD7834s can each be assigned a
V
CC
µCONTROLLER
AD7834
DEVICE 0
*
µCONTROLLER
CONTROL OUT
CONTROL OUT
TO PAENs
TO LDACs
TO FSYNCs
CONTROL OUT
CONTROL OUT
PA0
PAEN
LDAC
PA1
PA2
PA3
PA4
SYNC OUT
FSYNC
SCLK
SYNC OUT
SERIAL CLOCK OUT
SERIAL DATA OUT
DIN
SERIAL CLOCK OUT
SERIAL DATA OUT
TO SCLKs
TO DINs
AD7834
DEVICE 1
*
V
CC
PA0
PAEN
LDAC
OPTO-COUPLER
PA1
PA2
PA3
PA4
FSYNC
SCLK
Figure 28. Opto-Isolated Interface
Automated Test Equipment
DIN
The AD7834/AD7835 is particularly suited for use in an auto-
mated test environment. Figure 29 shows the AD7835 provid-
ing the necessary voltages for the pin driver and the window
comparator in a typical ATE pin electronics configuration. Two
AD588s are used to provide reference voltages for the AD7835.
In the configuration shown, the AD588s are configured so that
the voltage at Pin 1 is 5 V greater than the voltage at Pin 9 and
the voltage at Pin 15 is 5 V less than the voltage at Pin 9.
*
ADDITIONAL PINS
AD7834
DEVICE 9
*
OMITTED FOR CLARITY
V
CC
PA0
PAEN
LDAC
PA1
PA2
PA3
PA4
FSYNC
SCLK
DIN
One of the AD588s is used as a reference for DACs 1 and 2.
These DACs are used to provide high and low levels for the pin
driver. The pin driver may have an associated offset. This can
be nulled by applying an offset voltage to Pin 9 of the AD588.
First, the code 1000 . . . 0000 is loaded into the DAC1 latch
and the pin driver output is set to the DAC1 output. The
Figure 27. Serial Interface to Multiple AD7834s
–14–
REV. A
AD7834/AD7835
VOFFSET voltage is adjusted until 0 V appears between the pin
driver output and DUT GND. This causes both VREF(+)A and
AD7834/AD7835 is mounted should be designed such that the
analog and digital sections are separated and confined to certain
areas of the board. This facilitates the use of ground planes that
can be separated easily. A minimum etch technique is generally
best for ground planes as it gives the best shielding. Digital and
analog ground planes should only be joined at one place. If the
AD7834/AD7835 is the only device requiring an AGND to
DGND connection, then the ground planes should be con-
nected at the AGND and DGND pins of the AD7834/AD7835.
If the AD7834/AD7835 is in a system where multiple devices
require an AGND to DGND connection, the connection should
still be made at one point only, a star ground point which
should be established as close as possible to the AD7834/
AD7835.
V
REF(–)A to be offset with respect to AGND by an amount
equal to VOFFSET. However the output of the pin driver will vary
from –5 V to +5 V with respect to DUT GND as the DAC in-
put code varies from 000 . . . 000 to 111 . . . 111. The VOFFSET
voltage is also applied to the DSG A pin. When a clear is per-
formed on the AD7835, the output of the pin driver will be 0 V
with respect to DUT GND.
V
+15V –15V
OFFSET
2
16
4
6
3
1
+15V
V
(+)A
(–)A
REF
8
V
OUT
1
15
14
13
7
PIN
DRIVER
AD588
V
REF
Digital lines running under the device should be avoided as
these will couple noise onto the die. The analog ground plane
should be allowed to run under the AD7834/AD7835 to avoid
noise coupling. The power supply lines of the AD7834/
AD7835 should use as large a trace as possible to provide low
impedance paths and reduce the effects of glitches on the power
supply line. Fast switching signals like clocks should be shielded
with digital ground to avoid radiating noise to other parts of the
board and should never be run near the analog inputs. Avoid
crossover of digital and analog signals. Traces on opposite sides
of the board should run at right angles to each other. This re-
duces the effects of feedthrough through the board. A
microstrip technique is by far the best but not always possible
with a double sided board. In this technique, the component
side of the board is dedicated to ground plane while signal traces
are placed on the solder side.
V
2
OUT
9
1µF
DSG A
0.1µF
–15V
AD7835
*
10 11 12
+15V –15V
DSG B
DUT
GND
V
DUT
2
16
V
3
OUT
4
6
3
1
DUT
GND
V
(+)B
(–)B
REF
8
V
4
OUT
15
14
13
V
REF
AD588
10
11
12
AGND
WINDOW
COMPARATOR
7
8
1µF
DUT
GND
TO TESTER
*
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 29. ATE Application
The AD7834/AD7835 should have ample supply bypassing lo-
cated as close to the package as possible, ideally right up against
the device. Figure 30 shows the recommended capacitor values
of 10 µF in parallel with 0.1 µF on each of the supplies. The
10 µF capacitors are the tantalum bead type. The 0.1 µF ca-
pacitor should have low Effective Series Resistance (ESR) and
Effective Series Inductance (ESI), such as the common ceramic
types, which provide a low impedance path to ground at high
frequencies to handle transient currents due to internal logic
switching.
The other AD588 is used to provide a reference voltage for
DACs 3 and 4. These provide the reference voltages for the
window comparator shown in the diagram. Note that Pin 9 of
this AD588 is connected to DUT GND. This causes VREF(+)B
and VREF(–)B to be referenced to DUT GND. As DAC 3 and
DAC 4 input codes vary from 000 . . . 000 to 111 . . . 111,
V
OUT3 and VOUT4 vary from –5 V to +5 V with respect to DUT
GND. DUT GND is also connected to DSG B. When the
AD7835 is cleared, VOUT3 and VOUT4 are cleared to 0 V with
respect to DUT GND.
Care must be taken to ensure that the maximum and minimum
voltage specs for the AD7835 reference voltages are not broken
in the above configuration.
V
V
DD
CC
0.1µF
10µF
0.1µF
0.1µF
10µF
AD7834/
AD7835
*
AGND
DGND
Power Supply Bypassing and Grounding
V
SS
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
10µF
*
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 30. Power Supply Decoupling
REV. A
–15–
AD7834/AD7835
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Leaded Cerdip (Q-28)
28-Leaded Plastic DIP (N-28)
1.565 (39.70)
1.380 (35.10)
0.005 (0.13) MIN
28
0.100 (2.54) MAX
15
28
15
14
0.580 (14.73)
0.485 (12.32)
0.610 (15.49)
0.500 (12.70)
1
1
14
0.060 (1.52)
0.015 (0.38)
0.195 (4.95)
0.125 (3.18)
PIN 1
0.625 (15.87)
0.600 (15.24)
0.620 (15.75)
0.590 (14.99)
PIN 1
0.015
(0.38)
MIN
1.490 (37.85) MAX
0.250
(6.35)
MAX
0.225
(5.72)
MAX
∏
0.150
(3.81)
MIN
0.150
(3.81)
MIN
0.018 (0.46)
0.008 (0.20)
0.015 (0.381)
0.008 (0.204)
0.200 (5.05)
0.125 (3.18)
0.200 (5.08)
0.125 (3.18)
0.022 (0.558)
0.014 (0.356)
0.100
(2.54)
BSC
0.070
(1.77)
MAX
SEATING
PLANE
0.026 (0.66) 0.110 (2.79)
0.014 (0.36) 0.090 (2.29)
0.070 (1.78)
0.030 (0.76)
15°
0°
SEATING
PLANE
28-Leaded SOIC (R-28)
44-Pin PQFP (S-44)
0.7125 (18.10)
0.548 (13.925)
0.546 (13.875)
0.6969 (17.70)
0.096 (2.44)
MAX
0.398 (10.11)
0.390 (9.91)
28
15
0.037 (0.94)
0.025 (0.64)
8°
0.8°
33
23
22
34
SEATING
PLANE
1
14
TOP VIEW
(PINS DOWN)
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
PIN 1
x 45°
0.0098 (0.25)
44
12
11
0.0500 (1.27)
0.0157 (0.40)
8°
0°
1
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
0.040 (1.02)
0.032 (0.81)
0.0118 (0.30)
0.0040 (0.10)
SEATING
PLANE
0.0125 (0.32)
0.040 (1.02)
0.032 (0.81)
0.0091 (0.23)
0.016 (0.41)
0.012 (0.30)
0.033 (0.84)
0.029 (0.74)
0.083 (2.11)
0.077 (1.96)
44-Pin PLCC (P-44A)
0.180 (4.57)
0.165 (4.19)
0.056 (1.42)
0.042 (1.07)
0.048 (1.21)
0.042 (1.07)
0.025 (0.63)
0.015 (0.38)
0.048 (1.21)
0.042 (1.07)
6
40
39
7
PIN 1
0.050
(1.27)
BSC
IDENTIFIER
0.63 (16.00)
0.59 (14.99)
0.021 (0.53)
0.013 (0.33)
TOP VIEW
(PINS DOWN)
0.032 (0.81)
0.026 (0.66)
17
29
28
18
0.040 (1.01)
0.025 (0.64)
0.020
(0.50)
R
0.656 (16.66)
0.650 (16.51)
SQ
SQ
0.110 (2.79)
0.085 (2.16)
0.695 (17.65)
0.685 (17.40)
–16–
REV. A
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