AD7689ACPZ [ADI]
16-Bit, 4-Channel/8-Channel, 250 kSPS PulSAR ADC; 16位4通道/ 8通道， 250 kSPS时的PulSAR ADC
| 型号： | AD7689ACPZ |
| 厂家： | 
ADI |
| 描述： | 16-Bit, 4-Channel/8-Channel, 250 kSPS PulSAR ADC |
| 文件： | 总28页 (文件大小：828K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16-Bit, 4-Channel/8-Channel,
250 kSPS PulSAR ADC
AD7682/AD7689
FEATURES
FUNCTIONAL BLOCK DIAGRAM
2.7V TO 5V
0.5V TO 4.096V
0.1µF
0.5V TO VDD
22µF
16-bit resolution with no missing codes
4-channel (AD7682)/8-channel (AD7689) multiplexer with
choice of inputs
REFIN
REF
VDD
Unipolar single ended
Differential (GND sense)
Pseudobipolar
Throughput: 250 kSPS
INL: 0.5 LSB typical, 1.5 LSB maximum ( 23 ppm or FSR)
Dynamic range: 93.8 dB
SINAD: 92.5 dB @ 20 kHz
THD: −100 dB @ 20 kHz
Analog input range: 0 V to VREF with VREF up to VDD
Multiple reference types
1.8V
TO
VDD
BAND GAP
VIO
REF
AD7682/
AD7689
TEMP
SENSOR
CNV
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
SCK
SDO
DIN
SPI SERIAL
INTERFACE
16-BIT SAR
ADC
MUX
ONE-POLE
LPF
SEQUENCER
COM
GND
Internal selectable 2.5 V or 4.096 V
External buffered (up to 4.096 V)
External (up to VDD)
Figure 1.
Table 1. Multichannel 14-/16-Bit PulSAR® ADC
Internal temperature sensor
Channel sequencer, selectable 1-pole filter, busy indicator
No pipeline delay, SAR architecture
Single-supply 2.7 V to 5.5 V operation with
1.8 V to 5 V logic interface
Type
Channels 250 kSPS
500 kSPS ADC Driver
14-Bit
16-Bit
16-Bit
8
4
8
AD7949
AD7682
AD7689
ADA4841-x
ADA4841-x
ADA4841-x
AD7699
Serial interface compatible with SPI, MICROWIRE,
QSPI, and DSP
Power dissipation
GENERAL DESCRIPTION
The AD7682/AD7689 are 4-channel/8-channel, 16-bit, charge
redistribution successive approximation register (SAR) analog-
to-digital converters (ADCs) that operate from a single power
supply, VDD.
3.5 mW @ 2.5 V/200 kSPS
12 mW @ 5 V/250 kSPS
Standby current: 50 nA
20-lead 4 mm × 4 mm LFCSP package
The AD7682/AD7689 contain all components for use in a
multichannel, low power data acquisition system, including a
true 16-bit SAR ADC with no missing codes; a 4-channel
(AD7682) or 8-channel (AD7689), low crosstalk multiplexer
useful for configuring the inputs as single ended (with or
without ground sense), differential, or bipolar; an internal low
drift reference (selectable 2.5 V or 4.096 V) and buffer; a
temperature sensor; a selectable one-pole filter; and a sequencer
that is useful when channels are continuously scanned in order.
APPLICATIONS
Battery-powered equipment
Medical instruments: ECG/EKG
Mobile communications: GPS
Personal digital assistants
Power line monitoring
Data acquisition
Seismic data acquisition systems
Instrumentation
Process control
The AD7682/AD7689 use a simple SPI interface for writing to
the configuration register and receiving conversion results. The
SPI interface uses a separate supply, VIO, which is set to the
host logic level. Power dissipation scales with throughput.
Each AD7682/AD7689 is housed in a tiny 20-lead LFCSP with
operation specified from −40°C to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2008 Analog Devices, Inc. All rights reserved.
AD7682/AD7689
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Connection Diagrams.................................................. 17
Analog Inputs ............................................................................. 18
Driver Amplifier Choice ........................................................... 19
Voltage Reference Output/Input .............................................. 20
Power Supply............................................................................... 21
Supplying the ADC from the Reference.................................. 21
Digital Interface.............................................................................. 22
Configuration Register, CFG.................................................... 22
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications....................................................................... 6
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Typical Performance Characteristics ........................................... 11
Terminology .................................................................................... 14
Theory of Operation ...................................................................... 15
Overview...................................................................................... 15
Converter Operation.................................................................. 15
Transfer Functions...................................................................... 16
Read/Write Spanning Conversion Without a
Busy Indicator............................................................................. 24
Read/Write Spanning Conversion with a Busy Indicator..... 25
Application Hints ........................................................................... 26
Layout .......................................................................................... 26
Evaluating AD7682/AD7689 Performance ............................ 26
Outline Dimensions....................................................................... 27
Ordering Guide .......................................................................... 27
REVISION HISTORY
5/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
AD7682/AD7689
SPECIFICATIONS
VDD = 2.5 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
AD7682B/AD7689B
Parameter
Conditions/Comments
Unit
Min
Typ
Max
RESOLUTION
ANALOG INPUT
Voltage Range
16
Bits
Unipolar mode
Bipolar mode
Positive input, unipolar and bipolar modes
Negative or COM input, unipolar mode
Negative or COM input, bipolar mode
fIN = 250 kHz
0
+VREF
V
V
−VREF/2
−0.1
−0.1
+VREF/2
VREF + 0.1
+0.1
Absolute Input Voltage
VREF/2 − 0.1 VREF/2 VREF/2 + 0.1
Analog Input CMRR
Leakage Current at 25°C
Input Impedance1
THROUGHPUT
68
1
dB
nA
Acquisition phase
Conversion Rate
Full Bandwidth2
VDD = 4.5 V to 5.5 V
VDD = 2.7 V to 4.5 V
VDD = 2.3 V to 2.7 V
VDD = 4.5 V to 5.5 V
VDD = 2.7 V to 4.5 V
VDD = 2.3 V to 2.7 V
Full-scale step, full bandwidth
Full-scale step, ¼ bandwidth
0
0
0
0
0
0
250
200
190
60
50
47
kSPS
kSPS
kSPS
kSPS
kSPS
kSPS
μs
¼ Bandwidth2
Transient Response
1.8
14.5
μs
ACCURACY
No Missing Codes
Integral Linearity Error
Differential Linearity Error
Transition Noise
16
−1.5
−1
Bits
0.5
+1.5
LSB3
0.25 +1.5
0.5
2
0.5
1
2
LSB
LSB
LSB
LSB
ppm/°C
LSB
REF = VDD = 5 V
Gain Error4
−30
−2
+30
+2
Gain Error Match
Gain Error Temperature Drift
Offset Error4
Offset Error Match
Offset Error Temperature Drift
Power Supply Sensitivity
−2
0.5
1
1.5
+2
LSB
ppm/°C
LSB
VDD = 5 V ± 5%
Rev. 0 | Page 3 of 28
AD7682/AD7689
AD7682B/AD7689B
Parameter
Conditions/Comments
Unit
Min
Typ
Max
AC ACCURACY5
Dynamic Range
Signal-to-Noise
93.8
93.5
92.3
88.8
92.5
33.5
dB6
dB
dB
dB
dB
dB
fIN = 20 kHz, VREF = 5 V
92.5
91
87.5
91
fIN = 20 kHz, VREF = 4.096 V internal REF
fIN = 20 kHz, VREF = 2.5 V internal REF
fIN = 20 kHz, VREF = 5 V
SINAD
fIN = 20 kHz, VREF = 5 V
−60 dB input
fIN = 20 kHz, VREF = 4.096 V internal REF
fIN = 20 kHz, VREF = 2.5 V internal REF
fIN = 20 kHz
90
87
91
dB
dB
dB
dB
dB
88.4
−100
110
Total Harmonic Distortion
Spurious-Free Dynamic Range fIN = 20 kHz
Channel-to-Channel Crosstalk fIN = 100 kHz on adjacent channel(s)
SAMPLING DYNAMICS
−125
−3 dB Input Bandwidth
Aperture Delay
Selectable
VDD = 5 V
0.425
1.7
2.5
MHz
ns
INTERNAL REFERENCE
REF Output Voltage
2.5 V, @ 25°C
4.096 V, @ 25°C
2.5 V, @ 25°C
4.096 V, @ 25°C
2.490
4.086
2.500 2.510
4.096 4.106
V
V
V
V
REFIN Output Voltage7
1.2
2.3
300
10
15
50
5
REF Output Current
Temperature Drift
Line Regulation
ꢀA
ppm/°C
ppm/V
ppm
ms
VDD = 5 V 5%
1000 hours
CREF = 10 ꢀF
Long-Term Drift
Turn-On Settling Time
EXTERNAL REFERENCE
Voltage Range
REF input
REFIN input (buffered)
250 kSPS, REF = 5 V
0.5
0.5
VDD + 0.3
VDD − 0.2
V
V
ꢀA
Current Drain
50
TEMPERATURE SENSOR
Output Voltage8
Temperature Sensitivity
@ 25°C
283
1
mV
mV/°C
DIGITAL INPUTS
Logic Levels
VIL
VIH
IIL
IIH
−0.3
0.7 × VIO
−1
+0.3 × VIO
VIO + 0.3
+1
V
V
ꢀA
ꢀA
−1
+1
DIGITAL OUTPUTS
Data Format9
Pipeline Delay10
VOL
ISINK = +500 ꢀA
ISOURCE = −500 ꢀA
0.4
V
V
VOH
VIO − 0.3
Rev. 0 | Page 4 of 28
AD7682/AD7689
AD7682B/AD7689B
Parameter
POWER SUPPLIES
VDD
Conditions/Comments
Unit
Min
Typ
Max
Specified performance
Specified performance
Operating range
2.3
2.3
1.8
5.5
VDD + 0.3
VDD + 0.3
V
V
V
VIO
Standby Current11, 12
Power Dissipation
VDD and VIO = 5 V, @ 25°C
50
1.7
nA
ꢀW
mW
mW
mW
mW
nJ
VDD = 2.5 V, 100 SPS throughput
VDD = 2.5 V, 100 kSPS throughput
VDD = 2.5 V, 200 kSPS throughput
VDD = 5 V , 250 kSPS throughput
VDD = 5 V, 250 kSPS throughput with internal reference
1.75
3.5
12.5
15.5
50
2.1
4.1
15.9
19.2
Energy per Conversion
TEMPERATURE RANGE13
Specified Performance
TMIN to TMAX
−40
+85
°C
1 See the Analog Inputs section.
2 The bandwidth is set with the configuration register
3 LSB means least significant bit. With the 5 V input range, one LSB is 76.3 ꢀV.
4 See the Terminology section. These specifications include full temperature range variation but not the error contribution from the external reference.
5 With VDD = 5 V, unless otherwise noted.
6 All specifications expressed in decibels are referred to a full-scale input FSR and tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
7 This is the output from the internal band gap.
8 The output voltage is internal and present on a dedicated multiplexer input.
9 Unipolar mode: serial 16-bit straight binary.
Bipolar mode: serial 16-bit twos complement.
10 Conversion results available immediately after completed conversion.
11 With all digital inputs forced to VIO or GND as required.
12 During acquisition phase.
13 Contact an Analog Devices, Inc., sales representative for the extended temperature range.
Rev. 0 | Page 5 of 28
AD7682/AD7689
TIMING SPECIFICATIONS
VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, all specifications TMIN to TMAX, unless otherwise noted.
Table 3. 1
Parameter
Symbol
tCONV
tACQ
Min
Typ
Max
Unit
ꢀs
ꢀs
ꢀs
ns
ꢀs
ns
ns
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
CNV Pulse Width
Data Write/Read During Conversion
SCK Period
SCK Low Time
2.2
1.8
4
10
tCYC
tCNVH
tDATA
tSCK
1.4
15
7
tSCKL
SCK High Time
tSCKH
tHSDO
tDSDO
7
4
ns
ns
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
16
17
18
19
ns
ns
ns
ns
VIO Above 2.3 V
CNV Low to SDO D15 MSB Valid
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV High or Last SCK Falling Edge to SDO High Impedance
CNV Low to SCK Rising Edge
DIN Valid Setup Time from SCK Falling Edge
DIN Valid Hold Time from SCK Falling Edge
tEN
15
17
18
22
25
ns
ns
ns
ns
ns
ns
ns
ns
tDIS
tCLSCK
tSDIN
tHDIN
10
4
4
1 See Figure 2 and Figure 3 for load conditions.
Rev. 0 | Page 6 of 28
AD7682/AD7689
VDD = 2.5 V to 4.5 V, VIO = 2.3 V to VDD, all specifications TMIN to TMAX, unless otherwise noted.
Table 4. 1
Parameter
Symbol
Min
Typ
Max
Unit
Conversion Time: CNV Rising Edge to Data Available
VDD = 2.7 V to 4.5 V
VDD = 2.3 V to 2.7 V
Acquisition Time
Time Between Conversions
VDD = 2.7 V to 4.5 V
VDD = 2.3 V to 2.7 V
CNV Pulse Width
Data Write/Read During Conversion
SCK Period
SCK Low Time
tCONV
tCONV
tACQ
3.2
3.4
ꢀs
ꢀs
ꢀs
ꢀs
ꢀs
ꢀs
ns
ꢀs
ns
ns
ns
ns
1.8
tCYC
tCYC
5
5.2
10
tCNVH
tDATA
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
1.4
25
12
12
5
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
24
30
37
ns
ns
ns
CNV Low to SDO D15 MSB Valid
VIO Above 3 V
VIO Above 2.7 V
tEN
21
27
35
50
ns
ns
ns
ns
ns
ns
ns
VIO Above 2.3 V
CNV High or Last SCK Falling Edge to SDO High Impedance
CNV Low to SCK Rising Edge
SDI Valid Setup Time from SCK Falling Edge
SDI Valid Hold Time from SCK Falling Edge
tDIS
tCLSCK
tSDIN
tHDIN
10
5
5
1 See Figure 2 and Figure 3 for load conditions.
I
500µA
OL
1.4V
TO SDO
C
L
50pF
500µA
I
OH
Figure 2. Load Circuit for Digital Interface Timing
70% VIO
30% VIO
tDELAY
tDELAY
1
1
2V OR VIO – 0.5V
2V OR VIO – 0.5V
2
2
0.8V OR 0.5V
0.8V OR 0.5V
1
2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.
0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
2
Figure 3. Voltage Levels for Timing
Rev. 0 | Page 7 of 28
AD7682/AD7689
ABSOLUTE MAXIMUM RATINGS
Table 5.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Analog Inputs
INx,1 COM1
Rating
GND − 0.3 V to VDD + 0.3 V
or VDD 130 mA
REF, REFIN
GND − 0.3 V to VDD + 0.3 V
Supply Voltages
VDD, VIO to GND
VDD to VIO
DIN, CNV, SCK to GND2
−0.3 V to +7 V
7 V
−0.3 V to VIO + 0.3 V
−0.3 V to VIO + 0.3 V
−65°C to +150°C
150°C
ESD CAUTION
SDO to GND
Storage Temperature Range
Junction Temperature
θJA Thermal Impedance (LFCSP)
θJC Thermal Impedance (LFCSP)
47.6°C/W
4.4°C/W
1 See the Analog Inputs section.
2 CNV must be low at power up. See the Power Supply section.
Rev. 0 | Page 8 of 28
AD7682/AD7689
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
VDD
REF
REFIN
GND
1
2
3
4
5
15 VIO
14 SDO
13 SCK
12 DIN
11 CNV
PIN 1
INDICATOR
VDD
REF
REFIN
GND
1
2
3
4
5
15 VIO
14 SDO
13 SCK
12 DIN
11 CNV
AD7682
AD7689
TOP VIEW
(Not to Scale)
GND
TOP VIEW
(Not to Scale)
GND
NC = NO CONNECT
Figure 5. AD7689 20-Lead LFCSP (QFN) Pin Configuration
Figure 4. AD7682 20-Lead LFCSP (QFN) Pin Configuration
Table 6. Pin Function Descriptions
AD7682
Mnemonic
AD7689
Mnemonic
Pin
No.
Type1
Description
1, 20
VDD
VDD
P
Power Supply. Nominally 2.5 V to 5.5 V when using an external reference and decoupled
with 10 μF and 100 nF capacitors.
When using the internal reference for 2.5 V output, the minimum should be 2.7 V.
When using the internal reference for 4.096 V output, the minimum should be 4.5 V.
2
REF
REF
AI/O
Reference Input/Output. See the Voltage Reference Output/Input section.
When the internal reference is enabled, this pin produces a selectable system
reference = 2.5 V or 4.096 V.
When the internal reference is disabled and the buffer is enabled, REF produces a
buffered version of the voltage present on the REFIN pin (VDD – 0.3 V maximum) useful
when using low cost, low power references.
For improved drift performance, connect a precision reference to REF (0.5 V to VDD).
For any reference method, this pin needs decoupling with an external 10 μF capacitor
connected as close to REF as possible. See the Reference Decoupling section.
3
REFIN
REFIN
AI/O
Internal Reference Output/Reference Buffer Input. See the Voltage Reference
Output/Input section.
When using the internal reference, the internal unbuffered reference voltage is present
and needs decoupling with a 0.1μF capacitor.
When using the internal reference buffer, apply a source between 0.5 V and 4.096 V that
is buffered to the REF pin as described above.
4, 5
6
GND
NC
GND
IN4
P
AI
Power Supply Ground.
AD7682: No connection.
AD7689: Analog Input Channel 4.
AD7682: Analog Input Channel 2.
AD7689: Analog Input Channel 5.
AD7682: No connection.
AD7689: Analog Input Channel 6.
AD7682: Analog Input Channel 3.
AD7689: Analog Input Channel 7.
Common Channel Input. All channels [3:0] or [7:0] can be referenced to a common mode
point of 0 V or VREF/2 V.
Convert Input. On the rising edge, CNV initiates the conversion. During conversion, if
CNV is held high, the busy indictor is enabled.
7
IN2
IN5
AI
AI
AI
AI
DI
DI
DI
8
NC
IN6
9
IN3
IN7
10
11
12
13
COM
CNV
DIN
SCK
COM
CNV
DIN
SCK
Data Input. This input is used for writing to the 14-bit configuration register. The
configuration register can be written to during and after conversion.
Serial Data Clock Input. This input is used to clock out the data on ADO and clock in data
on DIN in an MSB first fashion.
Rev. 0 | Page 9 of 28
AD7682/AD7689
AD7682
Mnemonic
AD7689
Mnemonic
Pin
No.
Type1
Description
14
SDO
SDO
DO
Serial Data Output. The conversion result is output on this pin synchronized to SCK. In
unipolar modes, conversion results are straight binary; in bipolar modes, conversion
results are twos complement.
15
VIO
VIO
P
Input/Output Interface Digital Power. Nominally at the same supply as the host interface
(1.8 V, 2.5 V, 3 V, or 5 V).
16
17
IN0
NC
IN0
IN1
AI
AI
Analog Input Channel 0.
AD7682: No connection.
AD7689: Analog Input Channel 1.
AD7682: Analog Input Channel 1.
AD7689: Analog Input Channel 2.
AD7682: No connection.
18
19
IN1
NC
IN2
IN3
AI
AI
AD7689: Analog Input Channel 3.
1AI = analog input, AI/O = analog input/output, DI = digital input, DO = digital output, and P = power.
Rev. 0 | Page 10 of 28
AD7682/AD7689
TYPICAL PERFORMANCE CHARACTERISTICS
VDD = 2.5 V to 5.5 V, VREF = 2.5 V to 5 V, VIO = 2.3 V to VDD
1.5
1.5
1.0
0.5
0
1.0
0.5
0
–0.5
–1.0
–1.5
–0.5
–1.0
0
16,384
32,768
0
16,384
32,768
49,152
65,536
49,152
65,536
CODES
CODES
Figure 6. Integral Nonlinearity vs. Code, VREF = VDD = 5 V
Figure 9. Differential Nonlinearity vs. Code, VREF = VDD = 5 V
200k
160k
σ = 0.50
REF
σ = 0.78
REF DD
180k
160k
140k
120k
100k
80k
60k
40k
20k
0
V
= VDD = 5V
V = V = 2.5V
135,207
140k
120k
100k
80k
60k
40k
20k
0
135,326
124,689
63,257
51,778
6649
4090
0
0
487
619
0
0
0
1
78
60
1
7FFA 7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001 8002
CODE IN HEX
7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003
CODE IN HEX
Figure 7. Histogram of a DC Input at Code Center
Figure 10. Histogram of a DC Input at Code Center
0
–20
0
–20
V
= VDD = 5V
V
= VDD = 2.5V
fSR=EF250kSPS
fsR=E2F00kSPS
fIN = 19.9kHz
SNR = 92.9dB
SINAD = 92.4dB
THD = –102dB
fIN = 19.9kHz
SNR = 88.0dB
SINAD = 87.0dB
THD = –89dB
SFDR = 89dB
–40
–40
–60
–60
SFDR = 103dB
SECOND HARMONIC = –111dB
THIRD HARMONIC = –104dB
SECOND HARMONIC = –105dB
THIRD HARMONIC = –90dB
–80
–80
–100
–120
–140
–160
–180
–100
–120
–140
–160
–180
0
25
50
75
100
125
0
25
50
75
100
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 8. 20 kHz FFT, VREF = VDD = 5 V
Figure 11. 20 kHz FFT, VREF = VDD = 2.5 V
Rev. 0 | Page 11 of 28
AD7682/AD7689
100
95
90
85
80
75
100
95
90
85
80
75
70
65
60
VDD = V
VDD = V
VDD = V
VDD = V
= 5V, –0.5dB
= 5V, –10dB
= 2.5V, –0.5dB
= 2.5V, –10dB
VDD = V
VDD = V
VDD = V
VDD = V
= 5V, –0.5dB
= 5V, –10dB
= 2.5V, –0.5dB
= 2.5V, –10dB
REF
REF
REF
REF
REF
REF
REF
REF
70
65
60
0
50
100
150
200
0
50
100
150
200
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 12. SNR vs. Frequency
Figure 15. SINAD vs. Frequency
96
94
92
90
88
86
84
82
80
17.0
16.5
16.0
15.5
15.0
14.5
14.0
13.5
13.0
130
125
120
115
110
105
100
95
–60
SNR @ 2kHz
–65
SINAD @ 2kHz
SNR @ 20kHz
SINAD @ 20kHz
ENOB @ 2kHz
ENOB @ 20kHz
–70
SFDR = 2kHz
–75
–80
–85
SFDR = 20kHz
THD = 20kHz
–90
–95
90
–100
–105
–110
–115
–120
85
THD = 2kHz
80
75
70
5.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
Figure 13. SNR, SINAD, and ENOB vs. Reference Voltage
Figure 16. SFDR and THD vs. Reference Voltage
96
–90
fIN = 20kHz
fIN = 20kHz
VDD = V
= 5V
94
92
90
88
86
84
REF
–95
–100
–105
–110
VDD = V
= 5V
REF
VDD = V
= 2.5V
REF
VDD = V
REF
= 2.5V
125
–55
–35
–15
5
25
45
65
85
105
125
–55
–35
–15
5
25
45
65
85
105
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 14. SNR vs. Temperature
Figure 17. THD vs. Temperature
Rev. 0 | Page 12 of 28
AD7682/AD7689
–60
–70
3000
2750
2500
2250
2000
1750
1500
1250
1000
100
2.5V INTERNAL REF
fS = 200kSPS
90
4.096V INTERNAL REF
INTERNAL BUFFER, TEMP ON
INTERNAL BUFFER, TEMP OFF
EXTERNAL REF, TEMP ON
EXTERNAL REF, TEMP OFF
VIO
80
70
60
50
40
30
20
–80
–90
–100
–110
–120
VDD = V
VDD = V
VDD = V
VDD = V
= 5V, –0.5dB
= 2.5V, –0.5dB
= 2.5V, –10dB
= 5V, –10dB
REF
REF
REF
REF
0
50
100
FREQUENCY (kHz)
150
200
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD SUPPLY (V)
Figure 18. THD vs. Frequency
Figure 21. Operating Currents vs. Supply
95
94
93
92
91
90
89
88
87
86
85
3000
2750
2500
2250
2000
1750
1500
1250
1000
180
160
140
120
100
80
fIN = 20kHz
fS = 200kSPS
VDD = V
= 5V
REF
VDD = 5V, INTERNAL 4.096V REF
VDD = 5V, EXTERNAL REF
VDD = V
REF
= 2.5V
60
VDD = 2.5, EXTERNAL REF
VIO
40
20
125
–10
–8
–6
–4
–2
0
–55
–35
–15
5
25
45
65
85
105
INPUT LEVEL (dB)
TEMPERATURE (°C)
Figure 19. SNR vs. Input Level
Figure 22. Operating Currents vs. Temperature
25
20
15
10
5
3
2
VDD = 2.5V, 85°C
1
VDD = 2.5V, 25°C
0
–1
–2
–3
VDD = 5V, 85°C
VDD = 5V, 25°C
UNIPOLAR ZERO
UNIPOLAR GAIN
BIPOLAR ZERO
BIPOLAR GAIN
VDD = 3.3V, 85°C
VDD = 3.3V, 25°C
0
125
–55
–35
–15
5
25
45
65
85
105
0
20
40
60
80
100
120
TEMPERATURE (°C)
SDO CAPACITIVE LOAD (pF)
Figure 23. tDSDO Delay vs. SDO Capacitance Load and Supply
Figure 20. Offset and Gain Errors vs. Temperature
Rev. 0 | Page 13 of 28
AD7682/AD7689
TERMINOLOGY
Signal-to-Noise Ratio (SNR)
Least Significant Bit (LSB)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
The LSB is the smallest increment that can be represented by a
converter. For an analog-to-digital converter with N bits of
resolution, the LSB expressed in volts is
VREF
2N
LSB (V) =
Signal-to-(Noise + Distortion) Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.
Integral Nonlinearity Error (INL)
INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs ½ LSB before the first
code transition. Positive full scale is defined as a level 1½ LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line (see Figure 25).
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in decibels.
Differential Nonlinearity Error (DNL)
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels, between the rms amplitude
of the input signal and the peak spurious signal.
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD by the formula
Offset Error
The first transition should occur at a level ½ LSB above analog
ground. The unipolar offset error is the deviation of the actual
transition from that point.
ENOB = (SINADdB − 1.76)/6.02
and is expressed in bits.
Gain Error
Channel-to-Channel Crosstalk
The last transition (from 111 … 10 to 111 … 11) should occur
for an analog voltage 1½ LSB below the nominal full scale. The
gain error is the deviation in LSB (or percentage of full-scale
range) of the actual level of the last transition from the ideal
level after the offset error is adjusted out. Closely related is the
full-scale error (also in LSB or percentage of full-scale range),
which includes the effects of the offset error.
Channel-to-channel crosstalk is a measure of the level of
crosstalk between any two adjacent channels. It is measured by
applying a dc to the channel under test and applying a full-scale,
100 kHz sine wave signal to the adjacent channel(s). The
crosstalk is the amount of signal that leaks into the test channel
and is expressed in decibels.
Reference Voltage Temperature Coefficient
Aperture Delay
Reference voltage temperature coefficient is derived from the
typical shift of output voltage at 25°C on a sample of parts at the
maximum and minimum reference output voltage (VREF) meas-
ured at TMIN, T (25°C), and TMAX. It is expressed in ppm/°C as
Aperture delay is the measure of the acquisition performance. It
is the time between the rising edge of the CNV input and the
point at which the input signal is held for a conversion.
Transient Response
Transient response is the time required for the ADC to accurately
acquire its input after a full-scale step function is applied.
V
REF (Max) –VREF (Min)
TCVREF (ppm/°C) =
×106
V
REF (25°C) × (TMAX –TMIN )
where:
Dynamic Range
V
V
V
REF (Max) = maximum VREF at TMIN, T (25°C), or TMAX.
REF (Min) = minimum VREF at TMIN, T (25°C), or TMAX
REF (25°C) = VREF at 25°C.
MAX = +85°C.
Dynamic range is the ratio of the rms value of the full scale to
the total rms noise measured with the inputs shorted together.
The value for dynamic range is expressed in decibels.
.
T
TMIN = –40°C.
Rev. 0 | Page 14 of 28
AD7682/AD7689
THEORY OF OPERATION
INx+
SWITCHES CONTROL
MSB
LSB
SW+
32,768C
16,384C
4C
4C
2C
2C
C
C
C
C
BUSY
REF
CONTROL
LOGIC
COMP
GND
OUTPUT CODE
32,768C
16,384C
MSB
LSB
SW–
CNV
INx– OR
COM
Figure 24. ADC Simplified Schematic
OVERVIEW
CONVERTER OPERATION
The AD7682/AD7689 are 4-channel/8-channel, 16-bit, charge
redistribution successive approximation register (SAR) analog-to-
digital converters (ADCs). These devices are capable of
converting 250,000 samples per second (250 kSPS) and power
down between conversions. For example, when operating with
an external reference at 1 kSPS, they consumes 17 μW typically,
ideal for battery-powered applications.
The AD7682/AD7689 are successive approximation ADCs
based on a charge redistribution DAC. Figure 24 shows the
simplified schematic of the ADC. The capacitive DAC consists
of two identical arrays of 16 binary-weighted capacitors, which
are connected to the two comparator inputs.
During the acquisition phase, terminals of the array tied to the
comparator input are connected to GND via SW+ and SW−. All
independent switches are connected to the analog inputs.
The AD7682/AD7689 contain all of the components for use in a
multichannel, low power data acquisition system, including
Thus, the capacitor arrays are used as sampling capacitors and
acquire the analog signal on the INx+ and INx− (or COM)
inputs. When the acquisition phase is complete and the CNV
input goes high, a conversion phase is initiated. When the
conversion phase begins, SW+ and SW− are opened first. The
two capacitor arrays are then disconnected from the inputs and
connected to the GND input. Therefore, the differential voltage
between the INx+ and INx− (or COM) inputs captured at the
end of the acquisition phase is applied to the comparator inputs,
causing the comparator to become unbalanced. By switching
each element of the capacitor array between GND and CAP, the
comparator input varies by binary-weighted voltage steps
(VREF/2, VREF/4, ... VREF/32,768). The control logic toggles these
switches, starting with the MSB, to bring the comparator back
into a balanced condition. After the completion of this process,
the part returns to the acquisition phase, and the control logic
generates the ADC output code and a busy signal indicator.
•
•
•
•
•
•
16-bit SAR ADC with no missing codes
4-channel/8-channel, low crosstalk multiplexer
Internal low drift reference and buffer
Temperature sensor
Selectable one-pole filter
Channel sequencer
These components are configured through an SPI-compatible,
14-bit register. Conversion results, also SPI compatible, can be
read after or during conversions with the option for reading
back the current configuration.
The AD7682/AD7689 provide the user with an on-chip track-
and-hold and do not exhibit pipeline delay or latency.
The AD7682/AD7689 are specified from 2.3 V to 5.5 V and can
be interfaced to any 1.8 V to 5 V digital logic family. They are
housed in a 20-lead, 4 mm × 4 mm LFCSP that combines space
savings and allows flexible configurations. They are pin-for-pin
compatible with the 16-bit AD7699 and 14-bit AD7949.
Because the AD7682/AD7689 have an on-board conversion
clock, the serial clock, SCK, is not required for the conversion
process.
Rev. 0 | Page 15 of 28
AD7682/AD7689
TRANSFER FUNCTIONS
TWOS
COMPLEMENT
STRAIGHT
BINARY
With the inputs configured for unipolar range (single ended,
COM with ground sense, or paired differentially with INx− as
ground sense), the data output is straight binary.
011...111 111...111
011...110 111...110
011...101 111...101
With the inputs configured for bipolar range (COM = VREF/2 or
paired differentially with INx− = VREF/2), the data outputs are
twos complement.
The ideal transfer characteristic for the AD7682/AD7689 is
shown in Figure 25 and for both unipolar and bipolar ranges
with the internal 4.096 V reference.
100...010 000...010
100...001 000...001
100...000 000...000
–FSR
–FSR + 1LSB
+FSR – 1LSB
+FSR – 1.5LSB
–FSR + 0.5LSB
ANALOG INPUT
Figure 25. ADC Ideal Transfer Function
Table 7. Output Codes and Ideal Input Voltages
Unipolar Analog Input1
VREF = 4.096 V
Digital Output Code
(Straight Binary Hex)
Bipolar Analog Input2
VREF = 4.096 V
Digital Output Code
(Twos Complement Hex)
Description
FSR − 1 LSB
Midscale + 1 LSB
Midscale
4.095938 V
2.048063 V
2.048 V
0xFFFF
0x8001
0x8000
2.047938 V
62.5 μV
0 V
0x7FFF
0x0001
0x00004
Midscale − 1 LSB
−FSR + 1 LSB
−FSR
2.047938 V
62.5 μV
0 V
0x7FFF
0x0001
0x0000
−62.5 μV
−2.047938 V
−2.048 V
0xFFFF3
0x8001
0x8000
1 With COM or INx− = 0 V or all INx referenced to GND.
2 With COM or INx− = VREF /2.
3 This is also the code for an overranged analog input ((INx+) − (INx−), or COM, above VREF − VGND).
4 This is also the code for an underranged analog input ((INx+) − (INx−), or COM, below VGND).
Rev. 0 | Page 16 of 28
AD7682/AD7689
TYPICAL CONNECTION DIAGRAMS
5V
1.8V TO VDD
100nF
100nF
100nF
2
10µF
V+
REFIN VDD
REF
VIO
0V TO V
REF
3
ADA4841-x
IN0
INx
V–
V+
AD7682/AD7689
DIN
SCK
SDO
CNV
MOSI
SCK
MISO
SS
0V TO V
REF
3
ADA4841-x
V–
0V OR
COM
V
/2
REF
GND
NOTES:
1. INTERNAL REFERENCE SHOWN. SEE VOLTAGE REFERENCE OUTPUT/INPUT SECTION FOR
REFERENCE SELECTION.
2. C
IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).
REF
3. SEE DRIVER AMPLIFIER CHOICE SECTION FOR ADDITIONAL RECOMMENDED AMPLIFIERS.
4. SEE THE DIGITAL INTERFACE SECTION FOR CONFIGURING AND READING CONVERSION DATA.
Figure 26. Typical Application Diagram with Multiple Supplies
5V
1.8V TO VDD
100nF
100nF
100nF
2
10µF
V+
REFIN VDD
REF
VIO
3
ADA4841-x
IN0
INx
AD7682/AD7689
V+
DIN
SCK
SDO
CNV
MOSI
SCK
MISO
SS
3
ADA4841-x
V
p-p
REF
COM
GND
V
/2
REF
NOTES:
1. INTERNAL REFERENCE SHOWN. SEE VOLTAGE REFERENCE OUTPUT/INPUT SECTION FOR
REFERENCE SELECTION.
2. C
REF
IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).
3. SEE DRIVER AMPLIFIER CHOICE SECTION FOR ADDITIONAL RECOMMENDED AMPLIFIERS.
4. SEE THE DIGITAL INTERFACE SECTION FOR CONFIGURING AND READING CONVERSION DATA.
Figure 27. Typical Application Diagram Using Bipolar Input
Rev. 0 | Page 17 of 28
AD7682/AD7689
70
65
60
55
50
45
40
35
30
Unipolar or Bipolar
Figure 26 shows an example of the recommended connection
diagram for the AD7682/AD7689 when multiple supplies are
available.
Bipolar Single Supply
Figure 27 shows an example of a system with a bipolar input
using single supplies with the internal reference (optional
different VIO supply). This circuit is also useful when the
amplifier/signal conditioning circuit is remotely located with
some common mode present. Note that for any input config-
uration, the inputs INx are unipolar and always referenced to
GND (no negative voltages even in bipolar range).
1
10
100
1k
10k
FREQUENCY (kHz)
For this circuit, a rail-to-rail input/output amplifier can be used;
however, the offset voltage vs. input common-mode range
should be noted and taken into consideration (1 LSB = 62.5 ꢀV
with VREF = 4.096 V). Note that the conversion results are in
twos complement format when using the bipolar input
configuration. Refer to the AN-581 Application Note for
additional details about using single-supply amplifiers.
Figure 29. Analog Input CMRR vs. Frequency
During the acquisition phase, the impedance of the analog
inputs can be modeled as a parallel combination of the
capacitor, CPIN, and the network formed by the series
connection of RIN and CIN. CPIN is primarily the pin capacitance.
IN is typically 3.5 kΩ and is a lumped component made up of
serial resistors and the on resistance of the switches. CIN is
typically 27 pF and is mainly the ADC sampling capacitor.
R
ANALOG INPUTS
Input Structure
Selectable Low Pass Filter
Figure 28 shows an equivalent circuit of the input structure of
the AD7682/AD7689. The two diodes, D1 and D2, provide ESD
protection for the analog inputs, IN[7:0] and COM. Care must
be taken to ensure that the analog input signal does not exceed
the supply rails by more than 0.3 V because this causes the
diodes to become forward biased and to start conducting
current.
During the conversion phase, where the switches are opened,
the input impedance is limited to CPIN. While the AD7682/
AD7689 are acquiring, RIN and CIN make a one-pole, low-pass
filter that reduces undesirable aliasing effects and limits the
noise from the driving circuitry. The low-pass filter can be
programmed for the full bandwidth or ¼ of the bandwidth with
CFG[6] as shown in Table 9. Note that the converters
throughout must also be reduced by ¼ when using the filter. If
the maximum throughput is used with the BW set to ¼, the
converter acquisition time, tACQ, will be violated, resulting in
increased THD.
These diodes can handle a forward-biased current of 130 mA
maximum. For instance, these conditions may eventually occur
when the input buffer supplies are different from VDD. In such
a case, for example, an input buffer with a short circuit, the
current limitation can be used to protect the part.
VDD
Input Configurations
Figure 30 shows the different methods for configuring the analog
inputs with the configuration register (CFG[12:10]). Refer to
the Configuration Register, CFG, section for more details.
D1
D2
INx+
OR INx–
OR COM
C
IN
R
IN
C
PIN
GND
Figure 28. Equivalent Analog Input Circuit
This analog input structure allows the sampling of the true
differential signal between INx+ and COM or INx+ and INx−.
(COM or INx− = GND 0.1 V or VREF 0.1 V). By using these
differential inputs, signals common to both inputs are rejected,
as shown in Figure 29.
Rev. 0 | Page 18 of 28
AD7682/AD7689
channel pairs are always paired IN (even) = INx+ and IN (odd)
= INx− regardless of CFG[7].
CH0+
CH1+
CH2+
CH0+
CH1+
CH2+
IN0
IN1
IN2
IN3
IN0
IN1
IN2
IN3
To enable the sequencer, CFG[2:1] are written to for initializing
the sequencer. After CFG[13:0] are updated, DIN must be held
low while reading data out (at least for Bit 13), or the CFG will
begin updating again.
CH3+
CH4+
CH5+
CH6+
CH7+
CH3+
CH4+
CH5+
CH6+
CH7+
COM–
IN4
IN5
IN4
IN5
IN6
IN6
While operating in a sequence, the CFG can be changed by
writing 012 to CFG[2:1]. However, if changing CFG11 (paired
or single channel) or CFG[9:7] (last channel in sequence), the
sequence reinitializes and converts IN0 (or IN1) after CFG is
updated.
IN7
IN7
COM
GND
COM
GND
B—8 CHANNELS,
A—8 CHANNELS,
SINGLE ENDED
COMMON REFERNCE
Examples
Only the bits for input and sequencer are highlighted.
CH0+ (–)
CH0– (+)
CH1+ (–)
CH1– (+)
CH0+ (–)
IN0
IN1
IN2
IN3
IN0
IN1
IN2
IN3
CH0– (+)
CH1+ (–)
CH1– (+)
As a first example, scan all IN[7:0] referenced to COM = GND
with temperature sensor.
13
CFG
-
12 11 10
9
8
INx
1
7
6
5
4
REF
-
3
2
1
0
CH2+ (–)
CH2– (+)
CH2+
CH3+
CH4+
CH5+
COM–
IN4
IN5
IN4
IN5
IN6
IN7
INCC
BW
-
SEQ
1
RB
-
1
1
0
1
1
-
-
0
CH3+ (–)
CH3– (+)
IN6
As a second example, scan three paired channels without
temperature sensor and referenced to VREF/2.
IN7
COM
GND
COM
GND
13
CFG
-
12 11 10
9
8
INx
0
7
6
5
4
REF
-
3
2
1
0
INCC
BW
-
SEQ
1
RB
-
C—4 CHANNELS,
DIFFERENTIAL
D—COMBINATION
0
0
X
1
X
-
-
1
Figure 30. Multiplexed Analog Input Configuraitons
Source Resistance
The analog inputs can be configured as
When the source impedance of the driving circuit is low, the
AD7682/AD7689 can be driven directly. Large source
impedances significantly affect the ac performance, especially
•
Figure 30A, single ended referenced to system ground;
CFG[12:10] = 1112.
total harmonic distortion (THD). The dc performances are less
sensitive to the input impedance. The maximum source imped-
ance depends on the amount of THD that can be tolerated. The
THD degrades as a function of the source impedance and the
maximum input frequency.
•
Figure 30B, bipolar differential with a common reference
point; COM = VREF/2; CFG[12:10] = 0102.
Unipolar differential with COM connected to a ground
sense; CFG[12:10] = 1102.
Figure 30C, bipolar differential pairs with INx− referenced
to VREF/2; CFG[12:10] = 00X2.
•
DRIVER AMPLIFIER CHOICE
Unipolar differential pairs with INx− referenced to a
ground sense; CFG[12:10] = 10X2.
Although the AD7682/AD7689 are easy to drive, the driver
amplifier must meet the following requirements:
In this configuration, the INx+ is identified by the channel
in CFG[9:7]. Example: for IN0 = IN1+ and IN1 = IN1−,
CFG[9:7] = 0002; for IN1 = IN1+ and IN0 = IN1−,
CFG[9:7] = 0012.
Figure 30D, inputs configured in any of the above
combinations (showing that the AD7682/AD7689 can be
configured dynamically).
•
The noise generated by the driver amplifier must be kept as
low as possible to preserve the SNR and transition noise
performance of the AD7682/AD7689. Note that the AD7682/
AD7689 have a noise much lower than most of the other
16-bit ADCs and, therefore, can be driven by a noisier
amplifier to meet a given system noise specification. The
noise from the amplifier is filtered by the AD7682/AD7689
analog input circuit low-pass filter made by RIN and CIN or
by an external filter, if one is used. Because the typical noise
of the AD7682/AD7689 is 35 μV rms (with VREF = 5 V), the
SNR degradation due to the amplifier is
•
Sequencer
The AD7682/AD7689 include a channel sequencer useful for
scanning channels in a IN0 to INx fashion. Channels are
scanned as singles or pairs, with or without the temperature
sensor, after the last channel is sequenced.
The sequencer starts with IN0 and finishes with INx set in
CFG[9:7]. For paired channels, the channels are paired
depending on the last channel set in CFG[9:7]. Note that the
Rev. 0 | Page 19 of 28
AD7682/AD7689
AD7682/AD7689 and is thus useful for performing a system
calibration. Note that, when using the temperature sensor, the
output is straight binary referenced from the AD7682/AD7689
GND pin.
⎛
⎜
⎞
⎟
35
⎜
⎟
⎟
⎟
⎠
SNRLOSS = 20log
⎜
π
352 + f−3dB (NeN )2
⎜
⎝
2
The internal reference is temperature-compensated to within
15 mV. The reference is trimmed to provide a typical drift of
3 ppm/°C.
where:
f
–3dB is the input bandwidth in megahertz of the AD7682/AD7689
(1.7 MHz in full BW or 425 kHz in ¼ BW) or is the cutoff
frequency of an input filter, if one is used.
N is the noise gain of the amplifier (for example, 1 in buffer
External Reference and Internal Buffer
For improved drift performance, an external reference can be
used with the internal buffer. The external reference is con-
nected to REFIN, and the output is produced on the REF pin.
An external reference can be used with the internal buffer with
or without the temperature sensor enabled. Refer to Table 9 for
the register details. With the buffer enabled, the gain is unity and is
limited to an input/output of 4.096 V.
configuration).
eN is the equivalent input noise voltage of the op amp, in nV/√Hz.
•
For ac applications, the driver should have a THD
performance commensurate with the AD7682/AD7689.
Figure 18 shows THD vs. frequency for the
AD7682/AD7689.
The internal reference buffer is useful in multiconverter appli-
cations because a buffer is typically required in these applications.
In addition, a low power reference can be used because the
internal buffer provides the necessary performance to drive the
SAR architecture of the AD7682/AD7689.
•
For multichannel, multiplexed applications on each input
or input pair, the driver amplifier and the AD7682/
AD7689 analog input circuit must settle a full-scale step
onto the capacitor array at a 16-bit level (0.0015%). In the
amplifier data sheet, settling at 0.1% to 0.01% is more
commonly specified. This may differ significantly from the
settling time at a 16-bit level and should be verified prior to
driver selection.
External Reference
In any of the six voltage reference schemes, an external
reference can be connected directly on the REF pin because the
output impedance of REF is >5 kꢁ. To reduce power
consumption, the reference and buffer can be powered down
independently or together for the lowest power consumption.
However, for applications requiring the use of the temperature
sensor, the reference must be active. Refer to Table 9 for register
details. For improved drift performance, an external reference
such as the ADR43x or ADR44x is recommended.
Table 8. Recommended Driver Amplifiers
Amplifier
ADA4841-x
AD8655
AD8021
AD8022
OP184
Typical Application
Very low noise, small, and low power
5 V single supply, low noise
Very low noise and high frequency
Low noise and high frequency
Low power, low noise, and low frequency
Reference Decoupling
AD8605, AD8615 5 V single supply, low power
Whether using an internal or external reference, the AD7682/
AD7689 voltage reference output/input, REF, has a dynamic
input impedance and should therefore be driven by a low
impedance source with efficient decoupling between the REF
and GND pins. This decoupling depends on the choice of the
voltage reference but usually consists of a low ESR capacitor
connected to REF and GND with minimum parasitic inductance.
A 10 μF (X5R, 1206 size) ceramic chip capacitor is appropriate
when using the internal reference, the ADR43x/ADR44x
external reference, or a low impedance buffer such as the
AD8031 or the AD8605.
VOLTAGE REFERENCE OUTPUT/INPUT
The AD7682/AD7689 allow the choice of a very low temper-
ature drift internal voltage reference, an external reference, or an
external buffered reference.
The internal reference of the AD7682/AD7689 provide excel-
lent performance and can be used in almost all applications.
There are six possible choices of voltage reference schemes
briefly described in Table 9 with more details in each of the
following sections.
Internal Reference/Temperature Sensor
The placement of the reference decoupling capacitor is also
important to the performance of the AD7682/AD7689, as
explained in the Layout section. The decoupling capacitor should
be mounted on the same side as the ADC at the REF pin with a
thick PCB trace. The GND should also connect to the reference
decoupling capacitor with the shortest distance and to the
analog ground plane with several vias.
The internal reference can be set for either 2.5 V or a 4.096 V
output as detailed in Table 9. With the internal reference
enabled, the band gap voltage is also present on the REFIN pin,
which requires an external 0.1 ꢀF capacitor. Because the current
output of REFIN is limited, it can be used as a source if followed
by a suitable buffer, such as the AD8605.
Enabling the reference also enables the internal temperature
sensor, which measures the internal temperature of the
Rev. 0 | Page 20 of 28
AD7682/AD7689
If desired, smaller reference decoupling capacitor values down
to 2.2 μF can be used with a minimal impact on performance,
especially on DNL.
10000
1000
100
Regardless, there is no need for an additional lower value
ceramic decoupling capacitor (for example, 100 nF) between the
REF and GND pins.
VDD = 5V, INTERNAL REF
VDD = 5V, EXTERNAL REF
For applications that use multiple AD7682/AD7689s or other
PulSAR devices, it is more effective to use the internal reference
buffer to buffer the external reference voltage, thus reducing
SAR conversion crosstalk.
10
VDD = 2.5V, EXTERNAL REF
1
VIO
0.1
The voltage reference temperature coefficient (TC) directly impacts
full scale; therefore, in applications where full-scale accuracy
matters, care must be taken with the TC. For instance, a
0.010
0.001
15 ppm/°C TC of the reference changes full scale by 1 LSB/°C.
10
100
1k
10k
100k
1M
SAMPLING RATE (sps)
POWER SUPPLY
Figure 32. Operating Currents vs. Sampling Rate
The AD7682/AD7689 use two power supply pins: an analog
and digital core supply (VDD) and a digital input/output
interface supply (VIO). VIO allows direct interface with any
logic between 1.8 V and VDD. To reduce the supplies needed,
the VIO and VDD pins can be tied together. The
AD7682/AD7689 are independent of power supply sequencing
between VIO and VDD. The only restriction is that CNV must
be low when powering up the AD7682/AD7689. Additionally, it
is very insensitive to power supply variations over a wide
frequency range, as shown in Figure 31.
SUPPLYING THE ADC FROM THE REFERENCE
For simplified applications, the AD7682/AD7689, with their
low operating current, can be supplied directly using the
reference circuit as shown in Figure 33. The reference line can
be driven by
•
•
The system power supply directly
A reference voltage with enough current output capability,
such as the ADR43x/ADR44x
•
A reference buffer, such as the AD8605, which can also
filter the system power supply, as shown in Figure 33
75
70
65
60
55
50
45
40
35
30
5V
5V
10Ω
5V 10kΩ
1µF
1µF
0.1µF
0.1µF
10µF
AD8605
1
REF
VDD
VIO
AD7689
1
OPTIONAL REFERENCE BUFFER AND FILTER.
1
10
100
1k
10k
FREQUENCY (kHz)
Figure 33. Example of an Application Circuit
Figure 31. PSRR vs. Frequency
The AD7682/AD7689 power down automatically at the end of
each conversion phase; therefore, the operating currents and
power scale linearly with the sampling rate. This makes the part
ideal for low sampling rates (even of a few hertz) and low
battery-powered applications.
Rev. 0 | Page 21 of 28
AD7682/AD7689
The SCK frequency required is calculated by
DIGITAL INTERFACE
Number _ SCK _ Edges
f
≥
The AD7682/AD7689 use a simple 4-wire interface and are
compatible with SPI, MICROWIRE™, QSPI™, digital hosts, and
DSPs, for example, Blackfin® ADSP-BF53x, SHARC®, ADSP-
219x, and ADSP-218x.
SCK
t
DATA
The time between tDATA and tCONV is a safe time when digital
activity should not occur, or sensitive bit decisions may be
corrupt.
The interface uses the CNV, DIN, SCK, and SDO signals and
allows CNV, which initiates the conversion, to be independent
of the readback timing. This is useful in low jitter sampling or
simultaneous sampling applications.
Reading/Writing During Acquisition, Any Speed Hosts
When reading/writing during acquisition (n), conversion
results are for the previous (n − 1) conversion, and writing is for
the (n + 1) acquisition.
A 14-bit register, CFG[13:0], is used to configure the ADC for
the channel to be converted, the reference selection, and other
components, which are detailed in the Configuration Register,
CFG, section.
For the maximum throughput, the only time restriction is that
the reading/writing take place during the tACQ (min) time. For
slow throughputs, the time restriction is dictated by throughput
required by the user, and the host is free to run at any speed.
Thus for slow hosts, data access must take place during the
acquisition phase.
When CNV is low, reading/writing can occur during
conversion, acquisition, and spanning conversion (acquisition
plus conversion), as detailed in the following sections. The CFG
word is updated on the first 14 SCK rising edges, and conversion
results are read back on the first 15 (or 16 if busy mode is
selected) SCK falling edges. If the CFG readback is enabled, an
additional 14 SCK falling edges are required to read back the
CFG word associated with the conversion results with the CFG
MSB following the LSB of the conversion result.
Reading/Writing Spanning Conversion, Any Speed Host
When reading/writing spanning conversion, the data access
starts at the current acquisition (n) and spans into the
conversion (n). Conversion results are for the previous (n − 1)
conversion, and writing the CFG is for the next (n + 1)
acquisition and conversion.
A discontinuous SCK is recommended because the part is
selected with CNV low, and SCK activity begins to write a new
configuration word and clock out data.
Similar to reading/writing during conversion, reading/writing
should only occur up to tDATA. For the maximum throughput,
the only time restriction is that reading/writing take place
during the tACQ (min) + tDATA time.
Note that in the following sections, the timing diagrams
indicate digital activity (SCK, CNV, DIN, SDO) during the
conversion. However, due to the possibility of performance
degradation, digital activity should occur only prior to the safe
data reading/writing time, tDATA, because the AD7682/AD7689
provide error correction circuitry that can correct for an
incorrect bit during this time. From tDATA to tCONV, there is no
error correction and conversion results may be corrupted. The
user should configure the AD7682/AD7689 and initiate the
busy indicator (if desired) prior to tDATA. It is also possible to
corrupt the sample by having SCK or DIN transitions near the
sampling instant. Therefore, it is recommended to keep the
digital pins quiet for approximately 30 ns before and 10 ns after
the rising edge of CNV, using a discontinuous SCK whenever
possible to avoid any potential performance degradation.
For slow throughputs, the time restriction is dictated by the
user’s required throughput, and the host is free to run at any
speed. Similar to the reading/writing during acquisition, for
slow hosts, the data access must take place during the
acquisition phase with additional time into the conversion.
Note that data access spanning conversion requires the CNV to
be driven high to initiate a new conversion, and data access is
not allowed when CNV is high. Thus, the host must perform
two bursts of data access when using this method.
CONFIGURATION REGISTER, CFG
The AD7682/AD7689 use a 14-bit configuration register
(CFG[13:0]) as detailed in Table 9 for configuring the inputs,
channel to be converted, one-pole filter bandwidth, reference,
and channel sequencer. The CFG is latched (MSB first) on DIN
with 14 SCK rising edges. The CFG update is edge dependent,
allowing for asynchronous or synchronous hosts.
Reading/Writing During Conversion, Fast Hosts
When reading/writing during conversion (n), conversion
results are for the previous (n − 1) conversion, and writing the
CFG is for the next (n + 1) acquisition and conversion.
After the CNV is brought high to initiate conversion, it must be
brought low again to allow reading/writing during conversion.
Reading/writing should only occur up to tDATA and, because this
time is limited, the host must use a fast SCK.
Rev. 0 | Page 22 of 28
AD7682/AD7689
The register can be written to during conversion, during
acquisition, or spanning acquisition/conversion and is updated at
the end of conversion, tCONV (max). There is always a one deep
delay when writing CFG. Note that, at power up, the CFG is
undefined and two dummy conversions are required to update
the register. To preload the CFG with a factory setting, hold
DIN high for two conversions. Thus CFG[13:0] = 0x3FFF. This
sets the AD7682/AD7689 for
•
•
•
IN[7:0] unipolar referenced to GND, sequenced in order
Full bandwidth for one-pole filter
Internal reference/temperature sensor disabled, buffer
enabled
•
No readback of CFG
Table 9 summarizes the configuration register bit details. See
the Theory of Operation section for more details.
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CFG
INCC
INCC
INCC
INx
INx
INx
BW
REF
REF
REF
SEQ
SEQ
RB
Table 9. Configuration Register Description
Bit(s)
[13]
Name Description
CFG Configuration update.
0 = Keep current configuration settings.
1 = Overwrite contents of register.
[12:10] INCC
Input channel configuration. Selection of pseudobipolar, pseudodifferential, pairs, single-ended or temperature sensor. Refer to
the Input Configurations section.
Bit 12
Bit 11
Bit 10
Function
0
0
0
1
1
1
0
1
1
0
1
1
X
0
1
X
0
1
Bipolar differential pairs; INx− referenced to VREF/2 0.1 V.
Bipolar; INx referenced to COM = VREF/2 0.1 V.
Temperature sensor.
Unipolar differential pairs; INx− referenced to GND 0.1 mV.
Unipolar, IN0 to IN7 referenced to COM = GND 0.1 V (GND sense).
Unipolar, IN0 to IN7 referenced to GND.
[9:7]
INx
Input channel selection in binary fashion.
AD7682
AD7689
Bit 9
Bit 8
Bit 7
Channel Bit 9
Bit 8
0
0
…
1
Bit 7
0
1
…
1
Channel
IN0
IN1
0
0
1
1
0
1
0
1
X
X
X
X
IN0
IN1
IN2
IN3
0
0
…
1
IN7
[6]
BW
REF
Select bandwidth for low-pass filter. Refer to the Selectable Low Pass Filter section.
0 = ¼ of BW, uses an additional series resistor to further bandwidth limit the noise. Maximum throughout must be reduced to ¼
also.
1 = Full BW.
[5:3]
Reference/buffer selection. Selection of internal, external, external buffered, and enabling of the on-chip temperature sensor.
Refer to the Voltage Reference Output/Input section.
Bit 5
Bit 4
Bit 3
Function
0
0
0
0
1
1
0
0
1
1
1
1
0
1
0
1
0
1
Internal reference, REF = 2.5 V output.
Internal reference, REF = 4.096 V output.
External reference, temperature enabled.
External reference, internal buffer, temperature enabled.
External reference, temperature disabled.
External reference, internal buffer, temperature disabled.
[2:1]
SEQ
Channel sequencer. Allows for scanning channels in an IN0 to INx fashion. Refer to the Sequencer section.
Bit 2
Bit 1
Function
0
0
1
1
0
1
0
1
Disable sequencer.
Update configuration during sequence.
Scan IN0 to INx (set in CFG[9:7]), then temperature.
Scan IN0 to INx (set in CFG[9:7]).
0
RB
Read back the CFG register.
0 = Read back current configuration at end of data.
1 = Do not read back contents of configuration.
Rev. 0 | Page 23 of 28
AD7682/AD7689
to begin the CFG update. While CNV is low, both a CFG
update and a data readback take place. The first 14 SCK rising
edges are used to update the CFG, and the first 15 SCK falling
edges clock out the conversion results starting with MSB − 1.
The restriction for both configuring and reading is that they
both occur before the tDATA time of the next conversion elapses.
All 14 bits of CFG[13:0] must be written, or they are ignored. In
addition, if the 16-bit conversion result is not read back before
READ/WRITE SPANNING CONVERSION WITHOUT
A BUSY INDICATOR
This mode is used when the AD7682/AD7689 are connected to
any host using an SPI, serial port, or FPGA. The connection
diagram is shown in Figure 34, and the corresponding timing is
given in Figure 35. For SPI, the host should use CPHA = CPOL
= 0. Reading/writing spanning conversion is shown, which
covers all three modes detailed in the Digital Interface section.
tDATA elapses, it is lost.
A rising edge on CNV initiates a conversion, forces SDO to
high impedance, and ignores data present on DIN. After a
conversion is initiated, it continues until completion
irrespective of the state of CNV. CNV must be returned high
before the safe data transfer time, tDATA, and then held high
beyond the conversion time, tCONV, to avoid generation of the
busy signal indicator.
The SDO data is valid on both SCK edges. Although the rising
edge can be used to capture the data, a digital host using the
SCK falling edge allows a faster reading rate, provided it has an
acceptable hold time. After the 16th (or 30th) SCK falling edge, or
when CNV goes high (whichever occurs first), SDO returns to
high impedance. If CFG readback is enabled, the CFG associ-
ated with the conversion result (n − 1) is read back MSB first
following the LSB of the conversion result. A total of 30 SCK
falling edges is required to return SDO to high impedance if
this is enabled.
After the conversion is complete, the AD7682/AD7689 enter
the acquisition phase and power down. When the host brings
CNV low after tCONV (max), the MSB is enabled on SDO. The
host also must enable the MSB of CFG at this time (if necessary)
DIGITAL HOST
AD7682/
AD7689
CNV
SS
MISO
SDO
MOSI
SCK
DIN
SCK
FOR SPI USE CPHA = 0, CPOL = 0.
Figure 34. Connection Diagram for the AD7682/AD7689 Without a Busy Indicator
tCYC
>
tCONV
tCONV
tDATA
tCONV
tDATA
tCNVH
RETURN CNV HIGH
FOR NO BUSY
RETURN CNV HIGH
FOR NO BUSY
CNV
tACQ
(QUIET
TIME)
(QUIET
TIME)
ACQUISITION
(n + 1)
ACQUISITION
(n - 1)
CONVERSION (n)
ACQUISITION (n)
CONVERSION (n – 1)
UPDATE (n + 1)
CFG/SDO
UPDATE (n)
SEE NOTE
CFG/SDO
tCLSCK
16/
30
16/
30
SCK
DIN
1
14
15
X
2
14
15
X
tSDIN
tHDIN
CFG
MSB – 1
CFG
LSB
CFG
LSB
CFG
MSB
X
X
tHSDO
tDSDO
tEN
END CFG (n + 1)
tEN
tEN
END CFG (n)
LSB + 1
BEGIN CFG (n + 1)
SEE NOTE
tDIS
SDO
LSB
MSB MSB – 1
BEGIN DATA (n – 1)
LSB + 1 LSB
END DATA (n – 1)
tDIS
tDIS
tDIS
END DATA (n – 2)
NOTES:
1. THE LSB IS FOR CONVERSION RESULTS OR THE CONFIGURATION REGISTER CFG (n – 1) IF
15 SCK FALLING EDGES = LSB OF CONVERSION RESULTS.
29 SCK FALLING EDGES = LSB OF CONFIGURATION REGISTER.
ON THE 16TH OR 30TH SCK FALLING EDGE, SDO IS DRIVEN TO HIGH IMPENDANCE.
Figure 35. Serial Interface Timing for the AD7682/AD7689 Without a Busy Indicator
Rev. 0 | Page 24 of 28
AD7682/AD7689
update. While CNV is low, both a CFG update and a data
READ/WRITE SPANNING CONVERSION WITH A
BUSY INDICATOR
readback take place. The first 14 SCK rising edges are used to
update the CFG, and the first 16 SCK falling edges clock out the
conversion results starting with the MSB. The restriction for
both configuring and reading is that they both occur before the
This mode is used when the AD7682/AD7689 are connected to
any host using an SPI, serial port, or FPGA with an interrupt
input. The connection diagram is shown in Figure 36, and the
corresponding timing is given in Figure 37. For SPI, the host
should use CPHA = CPOL = 1. Reading/writing spanning
conversion is shown, which covers all three modes detailed in
the Digital Interface section.
tDATA time elapses for the next conversion. All 14 bits of
CFG[13:0] must be written or they are ignored. Also, if the 16-bit
conversion result is not read back before tDATA elapses, it is lost.
The SDO data is valid on both SCK edges. Although the rising
edge can be used to capture the data, a digital host using the
SCK falling edge allows a faster reading rate, provided it has an
acceptable hold time. After the optional 17th SCK falling edge,
SDO returns to high impedance. Note that, if the optional SCK
falling edge is not used, the busy feature cannot be detected if
the LSB for the conversion is low.
A rising edge on CNV initiates a conversion, forces SDO to
high impedance, and ignores data present on DIN. After a
conversion is initiated, it continues until completion
irrespective of the state of CNV. CNV must be returned low
before the safe data transfer time, tDATA, and then held low
beyond the conversion time, tCONV, to generate the busy signal
indicator. When the conversion is complete, SDO transitions
from high impedance to low with a pull-up to VIO, which can
be used to interrupt the host to begin data transfer.
If CFG readback is enabled, the CFG associated with the
conversion result (n − 1) is read back MSB first following the
LSB of the conversion result. A total of 31 SCK falling edges is
required to return SDO to high impedance if this is enabled.
After the conversion is complete, the AD7682/AD7689 enter
the acquisition phase and power down. The host must enable
the MSB of CFG at this time (if necessary) to begin the CFG
VIO
DIGITAL HOST
AD7682/
AD7689
SDO
MISO
IRQ
SS
CNV
MOSI
SCK
DIN
SCK
FOR SPI USE CPHA = 1, CPOL = 1.
Figure 36. Connection Diagram for the AD7682/AD7689 with a Busy Indicator
tCYC
tCONV
tACQ
tDATA
tDATA
tCNVH
CNV
CONVERSION
(n – 1)
(QUIET
TIME)
(QUIET
TIME)
ACQUISITION
(n + 1)
CONVERSION (n – 1)
ACQUISITION (n)
CONVERSION (n)
UPDATE (n + 1)
CFG/SDO
UPDATE (n)
CFG/SDO
SEE NOTE
17/
17/
16
X
15
X
SCK
DIN
1
2
16
15
X
31
31
tHDIN
tSDIN
CFG
MSB MSB –1
CFG
X
X
X
tHSDO
tDSDO
tDIS
BEIGN CFG (n + 1)
tEN
tDIS
END CFG (n)
END CFG (n + 1)
MSB
MSB
LSB
+ 1
LSB
+ 1
SDO
LSB
LSB
– 1
SEE NOTE
END DATA (n – 1)
END DATA (n – 2)
BEGIN DATA (n – 1)
tEN
tDIS
tEN
NOTES:
1. THE LSB IS FOR CONVERSION RESULTS OR THE CONFIGURATION REGISTER CFG (n – 1) IF
16 SCK FALLING EDGES = LSB OF CONVERSION RESULTS.
30 SCK FALLING EDGES = LSB OF CONFIGURATION REGISTER.
ON THE 17TH OR 31st SCK FALLING EDGE, SDO IS DRIVEN TO HIGH IMPENDANCE.
OTHERWISE, THE LSB REMAINS ACTIVE UNTIL THE BUSY INDICATOR IS DRIVEN LOW.
Figure 37. Serial Interface Timing for the AD7682/AD7689 with a Busy Indicator
Rev. 0 | Page 25 of 28
AD7682/AD7689
APPLICATION HINTS
reference decoupling ceramic capacitor close to, ideally right up
against, the REF and GND pins and connecting them with wide,
low impedance traces.
LAYOUT
The printed circuit board that houses the AD7682/AD7689
should be designed so that the analog and digital sections are
separated and confined to certain areas of the board. The pinout of
the AD7682/AD7689, with all its analog signals on the left side
and all its digital signals on the right side, eases this task.
Finally, the power supplies VDD and VIO of the AD7682/
AD7689 should be decoupled with ceramic capacitors, typically
100 nF, placed close to the AD7682/AD7689 and connected
using short, wide traces to provide low impedance paths and
reduce the effect of glitches on the power supply lines.
Avoid running digital lines under the device because these
couple noise onto the die unless a ground plane under the
AD7682/AD7689 is used as a shield. Fast switching signals,
such as CNV or clocks, should not run near analog signal paths.
Crossover of digital and analog signals should be avoided.
EVALUATING AD7682/AD7689 PERFORMANCE
Other recommended layouts for the AD7682/AD7689 are
outlined in the documentation of the evaluation board for the
AD7682/AD7689 (EVAL-AD7682CBZ/EVAL-AD7689CBZ).
The evaluation board package includes a fully assembled and
tested evaluation board, documentation, and software for
controlling the board from a PC via the evaluation controller
board, EVAL-CONTROL BRD3.
At least one ground plane should be used. It can be common or
split between the digital and analog sections. In the latter case,
the planes should be joined underneath the AD7682/AD7689.
The AD7682/AD7689 voltage reference input REF has a
dynamic input impedance and should be decoupled with
minimal parasitic inductances. This is done by placing the
Rev. 0 | Page 26 of 28
AD7682/AD7689
OUTLINE DIMENSIONS
0.60 MAX
4.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
15
16
20
1
5
0.50
BSC
2.65
2.50 SQ
2.35
PIN 1
INDICATOR
3.75
BSC SQ
EXPOSED
PAD
(BOTTOM VIEW)
10
11
6
0.50
0.40
0.30
0.25 MIN
TOP VIEW
0.80 MAX
0.65 TYP
12° MAX
1.00
0.85
0.80
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
0.30
0.23
0.18
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1
Figure 38. 20-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
4 mm × 4 mm Body, Very Thin Quad
(CP-20-4)
Dimensions shown in millimeters
ORDERING GUIDE
Integral
Nonlinearity
No Missing
Code
Temperature
Range
Package
Option
Ordering
Quantity
Model
AD7682BCPZ1
AD7682BCPZRL71
AD7689ACPZ1
AD7689ACPZRL71
AD7689BCPZ1
AD7689BCPZRL71
EVAL-AD7682CBZ1
EVAL-AD7689CBZ1
EVAL-CONTROL BRD32
Package Description
20-Lead QFN (LFCSP_VQ)
20-Lead QFN (LFCSP_VQ)
20-Lead QFN (LFCSP_VQ)
20-Lead QFN (LFCSP_VQ)
20-Lead QFN (LFCSP_VQ)
20-Lead QFN (LFCSP_VQ)
Evaluation Board
2 LSB max
2 LSB max
6 LSB max
6 LSB max
2 LSB max
2 LSB max
16 bits
16 bits
15 bits
15 bits
16 bits
16 bits
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
CP-20-4
CP-20-4
CP-20-4
CP-20-4
CP-20-4
CP-20-4
Tray, 490
Reel, 1,500
Tray, 490
Reel, 1,500
Tray, 490
Reel, 1,500
Evaluation Board
Controller Board
1 Z = RoHS Compliant Part.
2 This controller board allows a PC to control and communicate with all Analog Devices evaluation boards whose model numbers end in CB.
Rev. 0 | Page 27 of 28
AD7682/AD7689
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07353-0-5/08(0)
Rev. 0 | Page 28 of 28
相关型号：
AD7689BCPZ
8-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, QCC20, 4 X 4 MM, ROHS COMPLIANT, MO-220VGGD-1, LFCSP-20
ROCHESTER
AD768AR-REEL
IC PARALLEL, WORD INPUT LOADING, 0.025 us SETTLING TIME, 16-BIT DAC, PDSO28, 0.300 INCH, SOIC-28, Digital to Analog Converter
ADI
©2020 ICPDF网 联系我们和版权申明