AD7686CRM [ADI]
16-Bit, 500 kSPS PulSAR ADC in MSOP/QFN; 16位500 kSPS时的PulSAR ADC ，采用MSOP / QFN
| 型号： | AD7686CRM |
| 厂家： | 
ADI |
| 描述： | 16-Bit, 500 kSPS PulSAR ADC in MSOP/QFN |
| 文件： | 总28页 (文件大小：611K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16-Bit, 500 kSPS PulSAR
ADC in MSOP/QFN
AD7686
FUNCTIONAL BLOCK DIAGRAM
FEATURES
0.5V TO 5V
5V
16-bit resolution with no missing codes
Throughput: 500 kSPS
INL: 0.6 LSB typical, 2 LSB maximum ( 0.003% of FSR)
SINAD: 92.5 dB @ 20 kHz
THD: −110 dB @ 20 kHz
Pseudo differential analog input range
0 V to VREF with VREF up to VDD
VIO
SDI
1.8V TO VDD
REF VDD
0 TO VREF
IN+
IN–
SCK
SDO
CNV
AD7686
3- OR 4-WIRE INTERFACE
(SPI, DAISY CHAIN, CS)
GND
No pipeline delay
Single-supply 5 V operation with
1.8 V/2.5 V/3 V/5 V logic interface
Serial interface SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible
Daisy-chain multiple ADCs and busy indicator
Power dissipation
3.75 μW @ 5 V/100 SPS
3.75 mW @ 5 V/100 kSPS
Standby current: 1 nA
Figure 2.
Table 1. MSOP, QFN (LFCSP)/SOT-23
14-/16-/18-Bit PulSAR ADC
400 kSPS
to
500 kSPS kSPS
100
kSPS
250
1000
ADC
Driver
Type
kSPS
18-Bit True
Differential
16-Bit True
Differential
AD7691 AD7690
AD7982
AD7982 ADA4941
ADA4841
10-lead MSOP (MSOP-8 size) and
3 mm × 3 mm, 10-lead QFN (LFCSP) (SOT-23 size)
Pin-for-pin-compatible with 10-lead MSOP/QFN PulSAR® ADCs
AD7684 AD7687 AD7688
AD7693
ADA4941
ADA4841
16-Bit Pseudo AD7680 AD7685 AD7686
Differential AD7683 AD7694
AD7980 ADA4841
APPLICATIONS
Battery-powered equipment
Data acquisitions
14-Bit Pseudo AD7940 AD7942 AD7946
Differential
ADA4841
Instrumentation
Medical instruments
Process controls
GENERAL DESCRIPTION
The AD7686 is a 16-bit, charge redistribution, successive
approximation, analog-to-digital converter (ADC) that operates
from a single 5 V power supply, VDD. It contains a low power,
high speed, 16-bit sampling ADC with no missing codes, an
internal conversion clock, and a versatile serial interface port.
The part also contains a low noise, wide bandwidth, short
aperture delay track-and-hold circuit. On the CNV rising edge,
the AD7686 samples an analog input IN+ between 0 V to REF
with respect to a ground sense IN−. The reference voltage, REF,
is applied externally and can be set up to the supply voltage.
2.0
POSITIVE INL = +0.52LSB
NEGATIVE INL = –0.38LSB
1.5
1.0
0.5
0
–0.5
–1.0
Power dissipation scales linearly with throughput.
The SPI-compatible serial interface also features the ability,
using the SDI input, to daisy-chain several ADCs on a single,
3-wire bus or provides an optional busy indicator. This device is
compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate
supply VIO.
–1.5
–2.0
0
16384
32768
CODE
49152
65535
Figure 1. Integral Nonlinearity vs. Code
The AD7686 is housed in a 10-lead MSOP or a 10-lead QFN
(LFCSP) with operation specified from −40°C to +85°C.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2005–2007 Analog Devices, Inc. All rights reserved.
AD7686
TABLE OF CONTENTS
Features .............................................................................................. 1
Driver Amplifier Choice ........................................................... 15
Voltage Reference Input ............................................................ 15
Power Supply............................................................................... 15
Supplying the ADC from the Reference.................................. 16
Digital Interface.......................................................................... 16
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications....................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Terminology ...................................................................................... 8
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 12
Circuit Information.................................................................... 12
Converter Operation.................................................................. 12
Typical Connection Diagram ................................................... 13
Analog Input ............................................................................... 14
CS
CS
CS
CS
MODE 3-Wire, No Busy Indicator .................................... 17
Mode 3-Wire with Busy Indicator ..................................... 18
Mode 4-Wire, No Busy Indicator....................................... 19
Mode 4-Wire with Busy Indicator ..................................... 20
Chain Mode, No Busy Indicator .............................................. 21
Chain Mode with Busy Indicator............................................. 22
Application Hints ........................................................................... 23
Layout .......................................................................................... 23
Evaluating Performance ............................................................ 23
True 16-Bit Isolated Application Example.............................. 24
Outline Dimensions....................................................................... 25
Ordering Guide .......................................................................... 26
REVISION HISTORY
3/07—Rev. A to Rev. B
4/06—Rev. 0 to Rev. A
Changes to Features and Table 1 .................................................... 1
Changes to Table 3............................................................................ 4
Moved Figure 3 and Figure 4 to Page............................................. 5
Changes to Figure 13 and Figure 15............................................. 10
Changes to Figure 26...................................................................... 13
Changes to Table 8.......................................................................... 15
Changes to Figure 31...................................................................... 16
Changes to Figure 42...................................................................... 21
Changes to Figure 44...................................................................... 22
Updated Outline Dimensions....................................................... 25
Changes to Ordering Guide .......................................................... 26
Updated Format..................................................................Universal
Updated Outline Dimensions....................................................... 25
Changes to Ordering Guide.......................................................... 26
4/05—Revision 0: Initial Version
Rev. B | Page 2 of 28
AD7686
SPECIFICATIONS
VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, TA = –40°C to +85°C, unless otherwise noted.
Table 2.
B Grade
C Grade
Parameter
Conditions
Min Typ
Max
Min Typ
Max
Unit
RESOLUTION
16
16
Bits
ANALOG INPUT
Voltage Range
Absolute Input Voltage
IN+ − IN−
IN+
IN−
fIN = 200 kHz
Acquisition phase
0
VREF
0
VREF
VDD + 0.1
+0.1
V
V
V
dB
nA
−0.1
−0.1
65
VDD + 0.1 −0.1
+0.1 −0.1
Analog Input CMRR
Leakage Current @ 25°C
Input Impedance
65
1
1
See the Analog Input
section
See the Analog Input
section
ACCURACY
No Missing Codes
16
−1
−3
16
−1
−2
Bits
LSB1
LSB1
LSB1
LSB1
ppm/°C
mV
ppm/°C
LSB1
Differential Linearity Error
Integral Linearity Error
Transition Noise
Gain Error2, TMIN to TMAX
Gain Error Temperature Drift
Offset Error2, TMIN to TMAX
Offset Temperature Drift
Power Supply Sensitivity
0.7
1
0.5
0.5
0.6
0.45
2
0.3
0.1
0.3
+1.5
+2
+3
8
REF = VDD = 5 V
2
6
0.3
0.1
0.3
0.05
1.6
1.6
0.05
VDD = 5 V ± 5%
THROUGHPUT
Conversion Rate
Transient Response
AC ACCURACY
0
500
400
0
500
400
kSPS
ns
Full-scale step
Signal-to-Noise Ratio
fIN = 20 kHz, VREF = 5 V
fIN = 20 kHz, VREF = 2.5 V
89
92
91
92.7
88
dB3
dB2
dB2
dB2
dB2
dB2
dB2
87.5
−106
−106
92
32
−110
Spurious-Free Dynamic Range fIN = 20 kHz
Total Harmonic Distortion
Signal-to-(Noise + Distortion)
−110
−110
92.5
33.5
−115
fIN = 20 kHz
fIN = 20 kHz, VREF = 5 V
fIN = 20 kHz, VREF = 5 V, −60 dB input
89
91
Intermodulation Distortion4
1 LSB means least significant bit. With the 5 V input range, 1 LSB is 76.3 μV.
2 See the Terminology section. These specifications do include full temperature range variation, but do not include the error contribution from the external reference.
3 All specifications in dB are referred to a full-scale input FSR. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
4 fIN1 = 21.4 kHz, fIN2 = 18.9 kHz, each tone at −7 dB below full scale.
Rev. B | Page 3 of 28
AD7686
VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, TA = –40°C to +85°C, unless otherwise noted.
Table 3.
Parameter
REFERENCE
Voltage Range
Load Current
SAMPLING DYNAMICS
−3 dB Input Bandwidth
Aperture Delay
DIGITAL INPUTS
Logic Levels
VIL
Conditions
Min
Typ
Max
Unit
0.5
VDD + 0.3
V
μA
500 kSPS, REF = 5 V
VDD = 5 V
100
9
2.5
MHz
ns
–0.3
0.7 × VIO
−1
+0.3 × VIO
VIO + 0.3
+1
V
V
μA
μA
VIH
IIL
IIH
−1
+1
DIGITAL OUTPUTS
Data Format
Pipeline Delay
Serial 16 bits straight binary
Conversion results available immediately
after completed conversion
VOL
VOH
ISINK = +500 μA
ISOURCE = −500 μA
0.4
V
V
VIO − 0.3
POWER SUPPLIES
VDD
VIO
VIO Range
Standby Current1, 2
Power Dissipation
Specified performance
Specified performance
4.5
2.3
1.8
5.5
V
V
V
nA
μW
mW
mW
VDD + 0.3
VDD + 0.3
50
VDD and VIO = 5 V, 25°C
1
VDD = 5 V, 100 SPS throughput
VDD = 5 V, 100 kSPS throughput
VDD = 5 V, 500 kSPS throughput
3.75
3.75
15
4.3
21.5
TEMPERATURE RANGE3
Specified Performance
TMIN to TMAX
−40
+85
°C
1 With all digital inputs forced to VIO or GND as required.
2 During acquisition phase.
3 Contact sales for extended temperature range.
Rev. B | Page 4 of 28
AD7686
TIMING SPECIFICATIONS
−40°C to +85°C, VDD = 4.5 V to 5.5 V, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated.
See Figure 3 and Figure 4 for load conditions.
Table 4.
Parameter
Symbol
tCONV
tACQ
Min
0.5
400
2
Typ
Max
Unit
μs
ns
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
1.6
tCYC
μs
CNV Pulse Width ( CS Mode)
SCK Period (CS Mode)
tCNVH
tSCK
10
ns
15
ns
SCK Period (Chain Mode)
tSCK
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO Above 4.5 V
17
18
19
20
7
ns
ns
ns
ns
ns
ns
ns
tSCKL
tSCKH
tHSDO
tDSDO
7
5
14
15
16
17
ns
ns
ns
ns
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
VIO Above 4.5 V
tEN
15
18
22
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
SDI High to SDO High (Chain Mode with Busy Indicator)
VIO Above 4.5 V
tDIS
tSSDICNV
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
tDSDOSDI
15
0
5
5
3
4
15
26
ns
ns
VIO Above 2.3 V
70% VIO
500µA
I
OL
30% VIO
tDELAY
tDELAY
1
1
2V OR VIO – 0.5V
2V OR VIO – 0.5V
1.4V
TO SDO
2
2
0.8V OR 0.5V
0.8V OR 0.5V
C
L
50pF
1
2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.
0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
2
500µA
I
OH
Figure 4. Voltage Levels for Timing
Figure 3. Load Circuit for Digital Interface Timing
Rev. B | Page 5 of 28
AD7686
ABSOLUTE MAXIMUM RATINGS
Table 5.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Analog Inputs
IN+1, IN−1
Rating
GND − 0.3 V to VDD + 0.3 V
or 130 mA
GND − 0.3 V to VDD + 0.3 V
REF
Supply Voltages
VDD, VIO to GND
VDD to VIO
−0.3 V to +7 V
7 V
ESD CAUTION
Digital Inputs to GND
Digital Outputs to GND
Storage Temperature Range
Junction Temperature
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature
−0.3 V to VIO + 0.3 V
−0.3 V to VIO + 0.3 V
−65°C to +150°C
150°C
200°C/W (MSOP-10)
44°C/W (MSOP-10)
JEDEC J-STD-20
1 See the Analog Input section.
Rev. B | Page 6 of 28
AD7686
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
REF
VDD
IN+
1
2
3
4
5
10 VIO
REF
VDD
IN+
1
2
3
4
5
10 VIO
9
8
7
6
SDI
AD7686
TOP VIEW
9
8
7
6
SDI
SCK
SDO
CNV
AD7686
TOP VIEW
(Not to Scale)
SCK
SDO
CNV
IN–
(Not to Scale)
IN–
GND
GND
Figure 5. 10-Lead MSOP Pin Configuration
Figure 6. 10-Lead QFN (LFCSP) Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic Type1 Description
1
REF
AI
Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. This pin should
be decoupled closely to the pin with a 10 μF capacitor.
2
3
4
5
6
VDD
IN+
IN−
GND
CNV
P
Power Supply.
AI
AI
P
Analog Input. It is referred to IN−. The voltage range, that is, the difference between IN+ and IN−, is 0 V to VREF
Analog Input Ground Sense. It is connected to the analog ground plane or to a remote sense ground.
Power Supply Ground.
Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and
selects the interface mode, chain, or CS. In CS mode, it enables the SDO pin when low. In chain mode,
the data should be read when CNV is high.
.
DI
7
8
9
SDO
SCK
SDI
DO
DI
DI
Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock.
Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as
follows:
Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data
input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital
data level on SDI is output on SDO with a delay of 16 SCK cycles.
CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can
enable the serial output signals when low. If SDI or CNV is low when the conversion is completed,
the busy indicator feature is enabled.
10
VIO
P
Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V,
3 V, or 5 V).
1AI = analog input, DI = digital input, DO = digital output, and P = power.
Rev. B | Page 7 of 28
AD7686
TERMINOLOGY
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD by
Integral Nonlinearity Error (INL)
INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs ½ LSB before the first
code transition. Positive full scale is defined as a level 1½ LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line (see Figure 25).
ENOB = (SINADdB − 1.76)/6.02
and is expressed in bits.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in dB.
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in dB.
Offset Error
The first transition should occur at a level ½ LSB above analog
ground (38.1 μV for the 0 V to 5 V range). The offset error is
the deviation of the actual transition from that point.
Signal-to-(Noise + Distortion), SINAD
Gain Error
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in dB.
The last transition (from 111 . . . 10 to 111 . . . 11) should occur
for an analog voltage 1½ LSB below the nominal full scale
(4.999886 V for the 0 V to 5 V range). The gain error is the
deviation of the actual level of the last transition from the ideal
level after the offset is adjusted out.
Aperture Delay
It is the measure of the acquisition performance and is the time
between the rising edge of the CNV input and when the input
signal is held for a conversion.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels (dB), between the rms
amplitude of the input signal and the peak spurious signal.
Transient Response
Transient response is the time required for the ADC to accurately
acquire its input after a full-scale step function is applied.
Rev. B | Page 8 of 28
AD7686
TYPICAL PERFORMANCE CHARACTERISTICS
2.0
2.0
POSITIVE INL = +0.52LSB
POSITIVE DNL = +0.35LSB
NEGATIVE DNL = –0.36LSB
NEGATIVE INL = –0.38LSB
1.5
1.5
1.0
0.5
0
1.0
0.5
0
–0.5
–1.0
–0.5
–1.0
–1.5
–2.0
–1.5
–2.0
0
16384
32768
CODE
49152
65535
0
16384
32768
CODE
49152
65535
Figure 7. Integral Nonlinearity vs. Code
Figure 10. Differential Nonlinearity vs. Code
250000
160000
140000
120000
100000
80000
VDD = REF = 5V
VDD = REF = 5V
133575
202719
124164
200000
150000
100000
50000
0
60000
40000
30770
27583
20000
0
0
0
26
22
0
0
0
0
1703
8026
1678
0
0
8026 8027 8028 8029 802A 802B 802C 802D 802E
CODE IN HEX
8024
8025
8027
8028
8029 802A
802B
CODE IN HEX
Figure 8. Histogram of a DC Input at the Code Center
Figure 11. Histogram of a DC Input at the Code Transition
0
–20
95
94
93
92
91
90
–105
8192 POINT FFT
VDD = REF = 5V
f
f
= 500kSPS
= 19.99kHz
S
IN
–108
–40
SNR = 92.8dB
THD = –108.7dB
SECOND HARMONIC = –110.1dB
THIRD HARMONIC = –119.2dB
THD
SNR
–60
–111
–114
–117
–120
–80
–100
–120
–140
–160
–180
0
20 40 60 80 100 120 140 160 180 200 220 240
FREQUENCY (kHz)
–10
–8
–6
–4
–2
0
INPUT LEVEL (dB)
Figure 9. FFT Plot
Figure 12. SNR and THD vs. Input Level
Rev. B | Page 9 of 28
AD7686
100
17.0
16.0
–90
–95
95
90
85
–100
–105
–110
–115
–120
–125
–130
THD
SNR
SINAD
SFDR
15.0
14.0
13.0
ENOB
70
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
125
200
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
Figure 13. SNR, SINAD, and ENOB vs. Reference Voltage
Figure 16. THD, SFDR vs. Reference Voltage
100
–90
–100
–110
–120
–130
VREF = 5V
VREF = 5V
95
90
85
80
–55
–35
–15
5
25
45
65
85
105
125
–55
–35
–15
5
25
45
65
85
105
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 14. SNR vs. Temperature
Figure 17. THD vs. Temperature
100
95
90
85
80
75
70
–60
–70
VREF = 5V, –10dB
VREF = 5V, –1dB
–80
VREF = 5V, –1dB
–90
–100
–110
–120
VREF = 5V, –10dB
150
0
50
100
FREQUENCY (kHz)
150
200
0
50
100
FREQUENCY (kHz)
Figure 15. SINAD vs. Frequency
Figure 18. THD vs. Frequency
Rev. B | Page 10 of 28
AD7686
1000
750
500
250
0
4
3
fS = 100kSPS
VDD
2
OFFSET ERROR
1
–0
–1
–2
–3
–4
GAIN ERROR
VIO
4.50
4.75
5.00
SUPPLY (V)
5.25
5.50
125
125
–55
–35
–15
5
25
45
65
85
105
125
TEMPERATURE (°C)
Figure 19. Operating Currents vs. Supply
Figure 22. Offset and Gain Error vs. Temperature
1000
750
500
250
0
25
20
15
10
5
VDD = 5V, 85°C
VDD = 5V, 25°C
VDD + VIO
0
–55
–35
–15
5
25
45
65
85
105
0
20
40
60
80
100
120
TEMPERATURE (°C)
SDO CAPACITIVE LOAD (pF)
Figure 20. Power-Down Currents vs. Temperature
Figure 23. tDSDO Delay vs. Capacitance Load and Supply
1000
750
500
250
0
fS = 100kSPS
VDD = 5V
VIO
–55
–35
–15
5
25
45
65
85
105
TEMPERATURE (°C)
Figure 21. Operating Currents vs. Temperature
Rev. B | Page 11 of 28
AD7686
THEORY OF OPERATION
IN+
SWITCHES CONTROL
CONTROL
MSB
LSB
LSB
SW+
SW–
32,768C 16,384C
4C
4C
2C
2C
C
C
C
C
BUSY
REF
COMP
LOGIC
GND
OUTPUT CODE
32,768C 16,384C
MSB
CNV
IN–
Figure 24. ADC Simplified Schematic
CIRCUIT INFORMATION
CONVERTER OPERATION
The AD7686 is a fast, low power, single-supply, precise 16-bit
ADC using a successive approximation architecture.
The AD7686 is a successive approximation ADC based on a
charge redistribution DAC. Figure 24 shows a simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 16 binary weighted capacitors, which are
connected to two comparator inputs.
The AD7686 is capable of converting 500,000 samples per
second (500 kSPS) and powers down between conversions.
For example, when operating at 100 SPS, the device consumes
3.75 μW typically, which is ideal for battery-powered
applications.
During the acquisition phase, terminals of the array tied to the
comparator input are connected to GND via SW+ and SW−.
All independent switches are connected to the analog inputs.
Therefore, the capacitor arrays are used as sampling capacitors
and acquire the analog signal on the IN+ and IN− inputs. When
the acquisition phase is complete and the CNV input goes high,
a conversion phase initiates. When the conversion phase begins,
SW+ and SW− are opened first.
The AD7686 provides the user with on-chip, track-and-hold
and does not exhibit any pipeline delay or latency, making it
ideal for multiple, multiplexed channel applications.
The AD7686 is specified from 4.5 V to 5.5 V and can be
interfaced to any of the 1.8 V to 5 V digital logic family. It is
housed in a 10-lead MSOP or a tiny 10-lead QFN (LFCSP) that
combines space savings and allows flexible configurations.
The two capacitor arrays are then disconnected from the inputs
and connected to the GND input. Therefore, the differential
voltage between the inputs IN+ and IN−, captured at the end of
the acquisition phase, is applied to the comparator inputs,
causing the comparator to become unbalanced.
This device is pin-for-pin-compatible with the AD7685,
AD7687, and AD7688.
By switching each element of the capacitor array between GND
and REF, the comparator input varies by binary weighted
voltage steps (VREF/2, VREF/4 . . . VREF/65536). The control logic
toggles these switches, starting with the MSB, to bring the
comparator back into a balanced condition. After the
completion of this process, the part returns to the acquisition
phase and the control logic generates the ADC output code and
a busy signal indicator. Because the AD7686 has an on-board
conversion clock, the serial clock, SCK, is not required for the
conversion process.
Rev. B | Page 12 of 28
AD7686
Transfer Functions
Table 7. Output Codes and Ideal Input Voltages
Analog Input Digital Output Code
The ideal transfer characteristic for the AD7686 is shown in
Figure 25 and Table 7.
Description
VREF = 5 V
Hexadecimal
FFFF1
FSR – 1 LSB
4.999924 V
Midscale + 1 LSB 2.500076 V
Midscale 2.5 V
Midscale – 1 LSB 2.499924 V
8001
8000
7FFF
0001
00002
111...111
111...110
111...101
–FSR + 1 LSB
–FSR
76.3 μV
0 V
TYPICAL CONNECTION DIAGRAM
Figure 26 shows an example of the recommended connection
diagram for the AD7686 when multiple supplies are available.
000...010
000...001
000...000
1 This is also the code for an overranged analog input (VIN+ − VIN− above VREF − VGND).
2 This is also the code for an underranged analog input (VIN+ − VIN− below VGND).
–FSR
–FSR + 1 LSB
+FSR – 1 LSB
+FSR – 1.5 LSB
–FSR + 0.5 LSB
ANALOG INPUT
Figure 25. ADC Ideal Transfer Function
1
≥7V
≥7V
REF
5V
2
10µF
100nF
1.8V TO VDD
100nF
REF
VDD
VIO
SDI
33Ω
IN+
IN–
0 TO VREF
SCK
5
3- OR 4-WIRE INTERFACE
3
2.7nF
4
AD7686
SDO
CNV
≤–2V
GND
1
2
3
4
5
SEE THE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION.
IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).
SEE DRIVER AMPLIFIER CHOICE SECTION.
OPTIONAL FILTER. SEE ANALOG INPUT SECTION.
SEE DIGITAL INTERFACE SECTION FOR MOST CONVENIENT INTERFACE MODE.
C
REF
Figure 26. Typical Application Diagram with Multiple Supplies
Rev. B | Page 13 of 28
AD7686
During the acquisition phase, the impedance of the analog
inputs (IN+ or IN−) can be modeled as a parallel combination
of capacitor, CPIN, and the network formed by the series
connection of RIN and CIN. CPIN is primarily the pin capacitance.
RIN is typically 600 Ω and is a lumped component made up of
some serial resistors and the on resistance of the switches. CIN is
typically 30 pF and is mainly the ADC sampling capacitor.
During the conversion phase, where the switches are opened,
the input impedance is limited to CPIN. RIN and CIN make a
1-pole, low-pass filter that reduces undesirable aliasing effects
and limits the noise.
ANALOG INPUT
Figure 27 shows an equivalent circuit of the input structure
of the AD7686. The two diodes, D1 and D2, provide ESD
protection for the analog inputs IN+ and IN−. Care must be
taken to ensure that the analog input signal never exceeds the
supply rails by more than 0.3 V because this causes these
diodes to begin to forward-bias and start conducting current.
These diodes can handle a forward-biased current of 130 mA
maximum. For instance, these conditions could eventually
occur when the input buffer’s (U1) supplies are different from
VDD. In such a case, an input buffer with a short-circuit
current limitation can be used to protect the part.
VDD
When the source impedance of the driving circuit is low, the
AD7686 can be driven directly. Large source impedances
significantly affect the ac performance, especially THD. The dc
performances are less sensitive to the input impedance. The
maximum source impedance depends on the amount of THD
that can be tolerated. The THD degrades as a function of the
source impedance and the maximum input frequency, as shown
in Figure 29.
D1
D2
C
IN
R
IN
IN+
OR IN–
C
PIN
GND
Figure 27. Equivalent Analog Input Circuit
–80
The analog input structure allows the sampling of the
differential signal between IN+ and IN−. By using this
differential input, small signals common to both inputs are
rejected, as shown in Figure 28, which represents the typical
CMRR over frequency. For instance, by using IN− to sense a
remote signal ground, ground potential differences between
the sensor and the local ADC ground are eliminated.
80
–85
–90
–95
R
= 250Ω
S
–100
–105
–110
R
= 100Ω
S
R
R
70
= 50Ω
= 33Ω
S
S
VDD = 5V
0
25
50
75
100
FREQUENCY (kHz)
60
50
40
Figure 29. THD vs. Analog Input Frequency and Source Resistance
1
10
100
1000
10000
FREQUENCY (kHz)
Figure 28. Analog Input CMRR vs. Frequency
Rev. B | Page 14 of 28
AD7686
DRIVER AMPLIFIER CHOICE
VOLTAGE REFERENCE INPUT
Although the AD7686 is easy to drive, the driver amplifier
should meet the following requirements:
The AD7686 voltage reference input, REF, has a dynamic input
impedance and should, therefore, be driven by a low impedance
source with efficient decoupling between the REF and GND
pins, as explained in the Layout section.
•
The noise generated by the driver amplifier needs to be
kept as low as possible to preserve the SNR and transition
noise performance of the AD7686. Note that the AD7686
has a noise much lower than most of the other 16-bit
ADCs and, therefore, can be driven by a noisier amplifier
to meet a given system noise specification. The noise
coming from the amplifier is filtered by the AD7686 analog
input circuit 1-pole, low-pass filter made by RIN and CIN or
by the external filter, if one is used. Because the typical
noise of the AD7686 is 37 μV rms, the SNR degradation
due to the amplifier is
When REF is driven by a very low impedance source, such as a
reference buffer using the AD8031 or the AD8605, a 10 μF
(X5R, 0805 size) ceramic chip capacitor is appropriate for
optimum performance.
If an unbuffered reference voltage is used, the decoupling value
depends on the reference used. For instance, a 22 μF (X5R,
1206 size) ceramic chip capacitor is appropriate for optimum
performance using a low temperature drift ADR43x reference.
If desired, smaller reference decoupling capacitor values down
to 2.2 μF can be used with a minimal impact on performance,
especially DNL.
⎛
⎜
⎞
⎟
37
⎜
⎜
⎜
⎝
⎟
⎟
⎟
⎠
SNRLOSS = 20log
π
2
372 + f−3dB (NeN )2
Regardless, there is no need for an additional lower value
ceramic decoupling capacitor, such as 100 nF, between the REF
and GND pins.
where:
POWER SUPPLY
f–3dB is the input bandwidth in MHz of the AD7686
(9 MHz) or the cutoff frequency of the input filter, if
one is used.
The AD7686 is specified at 4.5 V to 5.5 V. The device uses two
power supply pins: a core supply VDD and a digital input/
output interface supply VIO. VIO allows direct interface with
any logic between 1.8 V and VDD. To reduce the supplies
needed, the VIO and VDD can be tied together.
N is the noise gain of the amplifier (for example, 1 in buffer
configuration).
eN is the equivalent input noise voltage of the op amp,
in nV/√Hz.
The AD7686 is independent of power supply sequencing
between VIO and VDD. Additionally, it is very insensitive to
power supply variations over a wide frequency range, as shown
in Figure 30, which represents PSRR over frequency.
110
•
•
For ac applications, the driver should have a THD
performance commensurate with the AD7686. Figure 18
shows the THD vs. frequency that the driver should exceed.
For multichannel multiplexed applications, the driver
amplifier and the AD7686 analog input circuit must settle a
full-scale step onto the capacitor array at a 16-bit level
(0.0015%). In the data sheet for the amplifier, settling at
0.1% to 0.01% is more commonly specified. This could
differ significantly from the settling time at a 16-bit level
and should be verified prior to driver selection.
100
90
80
VDD = 5V
70
60
50
40
30
Table 8. Recommended Driver Amplifiers
Amplifier
ADA4841-x
AD8605, AD8615
AD8655
Typical Application
Very low noise and low power
5 V single-supply, low power
5 V single-supply, low power
1
10
100
1000
10000
FREQUENCY (kHz)
OP184
AD8021
AD8022
AD8519
Low power, low noise, and low frequency
Very low noise and high frequency
Very low noise and high frequency
Small, low power and low frequency
High frequency and low power
Figure 30. PSRR vs. Frequency
AD8031
Rev. B | Page 15 of 28
AD7686
The AD7686 powers down automatically at the end of each
conversion phase and, therefore, the power scales linearly with
the sampling rate, as shown in Figure 31. This makes the part
ideal for low sampling rates (even a few Hz) and low battery-
powered applications.
DIGITAL INTERFACE
Though the AD7686 has a reduced number of pins, it offers
flexibility in its serial interface modes.
CS
The AD7686, when in
mode, is compatible with SPI, QSPI,
digital hosts, and DSPs, such as Blackfin® ADSP-BF53x or
ADSP-219x. This interface can use either 3-wire or 4-wire. A
3-wire interface using the CNV, SCK, and SDO signals
minimizes wiring connections useful, for instance, in isolated
applications. A 4-wire interface using the SDI, CNV, SCK, and
SDO signals allows CNV, which initiates the conversions, to be
independent of the readback timing (SDI). This is useful in low
jitter sampling or simultaneous sampling applications.
10000
1000
VDD = 5V
100
10
VIO
1
0.1
The AD7686, when in chain mode, provides a daisy-chain
feature using the SDI input for cascading multiple ADCs on a
single data line similar to a shift register.
0.01
0.001
The mode in which the part operates depends on the SDI level
when the CNV rising edge occurs. The
10
100
1000
10000
100000
1000000
CS
mode is selected if
SAMPLING RATE (SPS)
SDI is high, and the chain mode is selected if SDI is low. The
SDI hold time is such that when SDI and CNV are connected
together, the chain mode is always selected.
Figure 31. Operating Currents vs. Sampling Rate
SUPPLYING THE ADC FROM THE REFERENCE
In either mode, the AD7686 offers the flexibility to optionally
force a start bit in front of the data bits. This start bit can be
used as a busy signal indicator to interrupt the digital host and
trigger the data reading. Otherwise, without a busy indicator,
the user must timeout the maximum conversion time prior to
readback.
For simplified applications, the AD7686, with its low operating
current, can be supplied directly using the reference circuit
shown in Figure 32. The reference line can be driven by either:
•
•
The system power supply directly.
A reference voltage with enough current output capability,
such as the ADR43x.
The busy indicator feature is enabled as follows:
•
A reference buffer, such as the AD8031, which can also
filter the system power supply, as shown in Figure 32.
CS
• In
mode, if CNV or SDI is low when the ADC conversion
ends (see Figure 36 and Figure 40).
5V
• In chain mode, if SCK is high during the CNV rising edge
5V
(see Figure 44).
10Ω
5V 10kΩ
10µF
1µF
AD8031
1µF
1
REF
VDD
VIO
AD7686
1
OPTIONAL REFERENCE BUFFER AND FILTER.
Figure 32. Example of Application Circuit
Rev. B | Page 16 of 28
AD7686
The data is valid on both SCK edges. Although the rising edge
can be used to capture the data, a digital host using the SCK
falling edge allows a faster reading rate provided it has an
acceptable hold time. After the 16th SCK falling edge, or when
CNV goes high, whichever occurs first, SDO returns to high
impedance.
CS MODE 3-WIRE, NO BUSY INDICATOR
This mode is most often used when a single AD7686 is
connected to an SPI-compatible digital host. The connection
diagram is shown in Figure 33, and the corresponding timing is
provided in Figure 34.
With SDI tied to VIO, a rising edge on CNV initiates a
CS
CONVERT
conversion, selects the
mode, and forces SDO to high
impedance. Once a conversion is initiated, it continues to
completion irrespective of the state of CNV. For instance, it
could be useful to bring CNV low to select other SPI devices,
such as analog multiplexers. However, CNV must be returned
high before the minimum conversion time and held high until
the maximum conversion time to avoid generating the busy
signal indicator. When the conversion is complete, the AD7686
enters the acquisition phase and powers down. When CNV
goes low, the MSB is output onto SDO. The remaining data bits
are then clocked by subsequent SCK falling edges.
DIGITAL HOST
CNV
VIO
DATA IN
SDI
SDO
AD7686
SCK
CLK
CS
Figure 33. Mode 3-Wire, No Busy Indicator
Connection Diagram (SDI High)
SDI = 1
tCYC
tCNVH
CNV
tCONV
tACQ
ACQUISITION
CONVERSION
ACQUISITION
tSCK
tSCKL
SCK
1
2
3
14
15
16
D0
tHSDO
tSCKH
tDSDO
tEN
tDIS
SDO
D15
D14
D13
D1
CS
Figure 34. Mode 3-Wire, No Busy Indicator Serial Interface Timing (SDI High)
Rev. B | Page 17 of 28
AD7686
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge allows a faster reading
rate, provided it has an acceptable hold time. After the optional
17th SCK falling edge or when CNV goes high, whichever
occurs first, SDO returns to high impedance.
CS MODE 3-WIRE WITH BUSY INDICATOR
This mode is generally used when a single AD7686 is connected
to an SPI-compatible digital host having an interrupt input. The
connection diagram is shown in Figure 35, and the correspond-
ing timing is provided in Figure 36.
If multiple AD7686s are selected at the same time, the SDO
output pin handles this connection without damage or induced
latch-up. Meanwhile, it is recommended to keep this connection as
short as possible to limit extra power dissipation.
With SDI tied to VIO, a rising edge on CNV initiates a
CS
conversion, selects the
mode, and forces SDO to high
impedance. SDO is maintained in high impedance until the
completion of the conversion, irrespective of the state of CNV.
Prior to the minimum conversion time, CNV can be used to
select other SPI devices, such as analog multiplexers. However,
CNV must be returned low before the minimum conversion
time and held low until the maximum conversion time to
guarantee the generation of the busy signal indicator. When the
conversion is complete, SDO goes from high impedance to low.
With a pull-up on the SDO line, this transition can be used as
an interrupt signal to initiate the data reading controlled by the
digital host. The AD7686 then enters the acquisition phase and
powers down. The data bits are then clocked out, MSB first, by
subsequent SCK falling edges. The data is valid on both SCK edges.
CONVERT
VIO
DIGITAL HOST
CNV
VIO
47kΩ
DATA IN
IRQ
SDI
SDO
AD7686
SCK
CLK
CS
Figure 35. Mode 3-Wire with Busy Indicator
Connection Diagram (SDI High)
SDI = 1
tCYC
tCNVH
CNV
tACQ
tCONV
ACQUISITION
CONVERSION
ACQUISITION
tSCK
tSCKL
SCK
1
2
3
15
16
17
tHSDO
tDSDO
tSCKH
tDIS
SDO
D15
D14
D1
D0
CS
Figure 36. Mode 3-Wire with Busy Indicator Serial Interface Timing (SDI High)
Rev. B | Page 18 of 28
AD7686
avoid the generation of the busy signal indicator. When the
CS MODE 4-WIRE, NO BUSY INDICATOR
conversion is complete, the AD7686 enters the acquisition
phase and powers down. Each ADC result can be read by
bringing its SDI input low, which consequently outputs the MSB
onto SDO. The remaining data bits are then clocked by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge allows a faster reading
rate, provided it has an acceptable hold time. After the 16th
SCK falling edge or when SDI goes high, whichever occurs first,
SDO returns to high impedance and another AD7686 can
be read.
This mode is generally used when multiple AD7686s are
connected to an SPI-compatible digital host. A connection
diagram example using two AD7686 devices is shown in
Figure 37, and the corresponding timing is given in Figure 38.
With SDI high, a rising edge on CNV initiates a conversion,
CS
selects the
mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI could
be used to select other SPI devices, such as analog multiplexers.
but SDI must be returned high before the minimum conversion
time and held high until the maximum conversion time to
CS2
CS1
CONVERT
DIGITAL HOST
CNV
CNV
SDI
SDO
SDI
SDO
AD7686
AD7686
SCK
SCK
DATA IN
CLK
CS
Figure 37. Mode 4-Wire, No Busy Indicator Connection Diagram
tCYC
CNV
tACQ
tCONV
ACQUISITION
tSSDICNV
CONVERSION
ACQUISITION
SDI(CS1)
tHSDICNV
SDI(CS2)
SCK
tSCK
tSCKL
1
2
3
14
15
16
17
18
30
31
32
tHSDO
tSCKH
tDSDO
tDIS
tEN
SDO
D15
D14
D13
D1
D0
D15
D14
D1
D0
CS
Figure 38. Mode 4-Wire, No Busy Indicator Serial Interface Timing
Rev. B | Page 19 of 28
AD7686
With a pull-up on the SDO line, this transition can be used as
an interrupt signal to initiate the data readback controlled by
the digital host. The AD7686 then enters the acquisition phase
and powers down. The data bits are then clocked out, MSB first,
by subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge allows a faster reading
rate, provided it has an acceptable hold time. After the optional
17th SCK falling edge or SDI going high, whichever occurs first,
the SDO returns to high impedance.
CS MODE 4-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7686 is connected
to an SPI-compatible digital host, which has an interrupt input,
and when it is desired to keep CNV, which is used to sample the
analog input, independent of the signal used to select the data
reading. This requirement is particularly important in applications
where low jitter on CNV is desired. The connection diagram is
shown in Figure 39, and the corresponding timing is provided
in Figure 40.
With SDI high, a rising edge on CNV initiates a conversion,
CS1
CONVERT
CS
selects the
mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned low before the minimum conversion
time and held low until the maximum conversion time to
guarantee the generation of the busy signal indicator. When
conversion is complete, SDO goes from high impedance to low.
VIO
DIGITAL HOST
CNV
47kΩ
DATA IN
IRQ
SDI
SDO
AD7686
SCK
CLK
CS
Figure 39. Mode 4-Wire with Busy Indicator Connection Diagram
tCYC
CNV
tACQ
tCONV
ACQUISITION
CONVERSION
ACQUISITION
tSSDICNV
SDI
tSCK
tHSDICNV
tSCKL
SCK
SDO
1
2
3
15
16
17
tHSDO
tDSDO
tSCKH
tDIS
tEN
D15
D14
D1
D0
CS
Figure 40. Mode 4-Wire with Busy Indicator Serial Interface Timing
Rev. B | Page 20 of 28
AD7686
When the conversion is complete, the MSB is output onto SDO,
and the AD7686 enters the acquisition phase and powers down.
The remaining data bits stored in the internal shift register are
then clocked by subsequent SCK falling edges. For each ADC,
SDI feeds the input of the internal shift register and is clocked
by the SCK falling edge. Each ADC in the chain outputs its data
MSB first, and 16 × N clocks are required to read back the N
ADCs. The data is valid on both SCK edges. Although the rising
edge can be used to capture the data, a digital host using the
SCK falling edge allows a faster reading rate and, consequently,
more AD7686s in the chain, provided the digital host has an
acceptable hold time. The maximum conversion rate can be
reduced due to the total readback time. For instance, with a 3 ns
digital host setup time and 3 V interface, up to four AD7686s
running at a conversion rate of 360 kSPS can be daisy-chained
on a 3-wire port.
CHAIN MODE, NO BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7686s on a
3-wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
A connection diagram example using two AD7686s is shown in
Figure 41, and the corresponding timing is given in Figure 42.
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects the chain
mode, and disables the busy indicator. In this mode, CNV is
held high during the conversion phase and the subsequent data
readback.
CONVERT
CNV
CNV
DIGITAL HOST
SDI
SDO
SDI
SDO
AD7686
AD7686
DATA IN
A
B
SCK
SCK
CLK
Figure 41. Chain Mode, No Busy Indicator Connection Diagram
SDI = 0
A
tCYC
CNV
tACQ
t
CONV
ACQUISITION
CONVERSION
tSSCKCNV
ACQUISITION
tSCK
tSCKL
SCK
1
A
B
2
3
A
B
14
15
16
17
18
30
31
32
tHSCKCNV
tSSDISCK
tSCKH
tHSDISCK
tEN
D
D
15
D
14
D
D
13
13
D
1
1
D
0
SDO = SDI
A
A
A
A
B
tHSDO
tDSDO
15
D
14
D
B
D
0
D
15
D
14
A
D
1
D 0
A
SDO
B
B
A
A
B
Figure 42. Chain Mode, No Busy Indicator Serial Interface Timing
Rev. B | Page 21 of 28
AD7686
This transition on SDO can be used as a busy indicator to
trigger the data readback controlled by the digital host. The
AD7686 then enters the acquisition phase and powers down.
The data bits stored in the internal shift register are then
clocked out, MSB first, by subsequent SCK falling edges. For
each ADC, SDI feeds the input of the internal shift register and
is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 16 × N + 1 clocks are required to
readback the N ADCs.
CHAIN MODE WITH BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7686s
on a 3-wire serial interface while providing a busy indicator.
This feature is useful for reducing component count and
wiring connections, for example, in isolated multiconverter
applications or for systems with a limited interfacing capacity.
Data readback is analogous to clocking a shift register. A
connection diagram example using three AD7686s is shown in
Figure 43, and the corresponding timing is given in Figure 44.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge allows a faster reading
rate and, consequently, more AD7686s in the chain, provided
the digital host has an acceptable hold time. For instance,
with a 3 ns digital host setup time and 3 V interface, up to four
AD7686s running at a conversion rate of 360 kSPS can be daisy
chained to a single 3-wire port.
When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the busy indicator feature. In this
mode, CNV is held high during the conversion phase and the
subsequent data readback. When all ADCs in the chain have
completed their conversions, the nearend ADC (ADC C in
Figure 43) SDO is driven high.
CONVERT
DIGITAL HOST
DATA IN
CNV
CNV
CNV
SDI
SDO
SDI
SDO
SDI
SDO
AD7686
AD7686
AD7686
A
B
C
SCK
SCK
SCK
IRQ
CLK
Figure 43. Chain Mode with Busy Indicator Connection Diagram
tCYC
CNV = SDI
A
tCONV
tACQ
ACQUISITION
CONVERSION
ACQUISITION
tSCK
tSSCKCNV
tSCKH
SCK
1
2
3
A
4
15
16
17
18
19
31
32
33
34
35
47
48
49
tHSCKCNV
tSSDISCK
tSCKL
tDSDOSDI
tHSDISCK
tEN
SDO = SDI
D
15
D
14
D
13
D
1
D 0
A
A
B
A
A
A
tHSDO
tDSDO
tDSDOSDI
tDSDOSDI
tDSDOSDI
SDO = SDI
B
D
15
D
D
14
D
13
B
D
D
1
D
0
D
15
D
14
D 1
A
D 0
A
C
B
B
B
B
A
A
tDSDOSDI
SDO
D
15
14
D
13
1
D
0
D
15
D
14
D
1
D
0
D
15
D
14
D
1
D 0
A
C
C
C
C
C
C
B
B
B
B
A
A
A
Figure 44. Chain Mode with Busy Indicator Serial Interface Timing
Rev. B | Page 22 of 28
AD7686
APPLICATION HINTS
LAYOUT
The printed circuit board (PCB) that houses the AD7686
should be designed so that the analog and digital sections are
separated and confined to certain areas of the board. The
pinout of the AD7686, with all its analog signals on the left side
and all its digital signals on the right side, eases this task.
Avoid running digital lines under the device because doing so
couples noise onto the die, unless a ground plane under the
AD7686 is used as a shield. Fast switching signals, such as CNV
or clocks, should never run near analog signal paths. Crossover
of digital and analog signals should be avoided.
At least one ground plane should be used. It could be common
or split between the digital and analog sections. In the latter
case, the planes should be joined underneath the devices.
Figure 45. Example of Layout of the AD7686 (Top Layer)
The AD7686 voltage reference input REF has a dynamic input
impedance and should be decoupled with minimal parasitic
inductances. This is done by placing the reference decoupling
ceramic capacitor close to, and ideally right up against, the REF
and GND pins and connecting it with wide, low impedance
traces.
Finally, the AD7686 power supplies VDD and VIO should be
decoupled with ceramic capacitors (typically 100 nF) placed
close to the AD7686 and connected using short and wide traces.
This provides low impedance paths and reduces the effect of
glitches on the power supply lines. Examples of layouts that
follow these rules are shown in Figure 45 and Figure 46.
EVALUATING PERFORMANCE
Other recommended layouts for the AD7686 are outlined in
the documentation of the evaluation board (EVAL-AD7686CB).
The evaluation board package includes a fully assembled and
tested evaluation board, documentation, and software for
controlling the board from a PC via the universal evaluation
control board (EVAL-CONTROL BRD3).
Figure 46. Example of Layout of the AD7686 (Bottom Layer)
Rev. B | Page 23 of 28
AD7686
This skew is the channel-to-channel matching propagation
delay of the digital isolator (tPSKCD). This allows running the
serial interface at the maximum speed of the digital isolator
(45 Mbps for the ADuM1402C), which would have been
otherwise limited by the cascade of the propagation delays of
the digital isolator. For instance, four AD7686 devices running
at 330 kSPS can be chained together.
TRUE 16-BIT ISOLATED APPLICATION EXAMPLE
In applications where high accuracy and isolation are required,
such as power monitoring, motor control, and some medical
equipment, the circuit shown in Figure 47, using the AD7686
and the ADuM1402C digital isolator, provides a compact and
high performance solution.
Multiple AD7686 devices are daisy-chained to reduce the
number of signals to isolate. Note that the SCKOUT, which is a
readback of the AD7686 clock, has a very short skew with the
DATA signal.
The complete analog chain runs on a single 5 V supply using
the ADR391 low dropout reference voltage and the rail-to-rail
CMOS AD8618 amplifier while offering true bipolar input range.
5V
100nF
V
, V
1
V
, V
E2
2.7V TO 5V
100nF
DD1
E1
DD2
GND
GND
2
5V REF
5V
100nF
V
V
V
V
V
10µF
IA
OA
DATA
1kΩ
4kΩ
±10V INPUT
V
5V
IB
OB
IC
REF VDD VIO
SDO
SCKOUT
SCKIN
SCK
CNV
IN+
AD7686
V
V
OC
2V REF
IN– GND
SDI
1/4 AD8618
OD
ID
CONVERT
5V REF
10µF
5V
100nF
ADuM1402C
1kΩ
4kΩ
±10V INPUT
5V
REF VDD VIO
SDO
SCK
CNV
IN+
AD7686
2V REF
SDI
IN– GND
1/4 AD8618
5V REF
10µF
5V
100nF
1kΩ
4kΩ
±10V INPUT
5V
REF VDD VIO
SDO
SCK
CNV
1kΩ
1kΩ
IN+
AD7686
2V REF
5V
IN– GND
SDI
1/4 AD8618
5V REF
5V REF
10µF
5V
100nF
ADR391
1kΩ
5V
IN OUT
GND
2V REF
4kΩ
4kΩ
1kΩ
±10V INPUT
5V
REF VDD VIO
SDO
SCK
CNV
10μF 100nF
IN+
AD7686
2V REF
IN– GND
SDI
1/4 AD8618
Figure 47. A True 16-Bit Isolated Simultaneous Sampling Acquisition System
Rev. B | Page 24 of 28
AD7686
OUTLINE DIMENSIONS
3.10
3.00
2.90
6
10
5.15
4.90
4.65
3.10
3.00
2.90
1
5
PIN 1
0.50 BSC
0.95
0.85
0.75
1.10 MAX
0.80
0.60
0.40
8°
0°
0.15
0.05
0.33
0.17
SEATING
PLANE
0.23
0.08
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 48. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
INDEX
AREA
3.00
BSC SQ
PIN
1
INDICATOR
1
10
1.50
BSC SQ
0.50
BSC
2.48
2.38
2.23
EXPOSED
PAD
TOP VIEW
(BOT TOM VIEW)
6
5
0.50
0.40
0.30
1.74
1.64
1.49
0.80 MAX
0.55 TYP
PADDLE CONNECTED TO GND.
THIS CONNECTION IS NOT
REQUIRED TO MEET THE
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SIDE VIEW
ELECTRICAL PERFORMANCES
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
Figure 49. 10-Lead Lead Frame Chip Scale Package [QFN (LFCSP_WD)]
3 mm × 3 mm Body, Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters
Rev. B | Page 25 of 28
AD7686
ORDERING GUIDE
Integral
Ordering
Model
Nonlinearity Temperature Range Quantity
Package Description
Package Option Branding
AD7686BCPZRL1
AD7686BCPZRL71
AD7686BRM
AD7686BRMRL7
AD7686BRMZ1
AD7686BRMZRL71
AD7686CCPZRL1
AD7686CCPZRL71
AD7686CRM
AD7686CRMRL7
AD7686CRMZ1
AD7686CRMZRL71
EVAL-AD7686CB2
EVAL-AD7686CBZ1, 2
EVAL-CONTROL BRD23
EVAL-CONTROL BRD33
3 LSB max
3 LSB max
3 LSB max
3 LSB max
3 LSB max
3 LSB max
2 LSB max
2 LSB max
2 LSB max
2 LSB max
2 LSB max
2 LSB max
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Reel, 5000 10-Lead QFN (LFCSP_WD) CP-10-9
Reel, 1500 10-Lead QFN (LFCSP_WD) CP-10-9
C02#
C02#
C02
Tube, 50
Reel, 1000 10-Lead MSOP
Tube, 50 10-Lead MSOP
Reel, 1000 10-Lead MSOP
10-Lead MSOP
RM-10
RM-10
RM-10
RM-10
C02
C3N
C3N
C2G#
C2G#
C2G
C2G
C3P
Reel, 5000 10-Lead QFN (LFCSP_WD) CP-10-9
Reel, 1500 10-Lead QFN (LFCSP_WD) CP-10-9
Tube, 50
Reel, 1000 10-Lead MSOP
Tube, 50 10-Lead MSOP
Reel, 1000 10-Lead MSOP
Evaluation Board
10-Lead MSOP
RM-10
RM-10
RM-10
RM-10
C3P
Evaluation Board
Controller Board
Controller Board
1 Z = RoHS Compliant Part, # denotes RoHS Compliant product may be top or bottom marked.
2 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRDx for evaluation/demonstration purposes.
3 These boards allow a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
Rev. B | Page 26 of 28
AD7686
NOTES
Rev. B | Page 27 of 28
AD7686
NOTES
©2005–2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02969-0-3/07(B)
Rev. B | Page 28 of 28
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