AD7537KR [ADI]
IC DUAL, PARALLEL, 8 BITS INPUT LOADING, 0.8 us SETTLING TIME, 12-BIT DAC, PDSO24, SOIC-24, Digital to Analog Converter;
| 型号： | AD7537KR |
| 厂家： | 
ADI |
| 描述： | IC DUAL, PARALLEL, 8 BITS INPUT LOADING, 0.8 us SETTLING TIME, 12-BIT DAC, PDSO24, SOIC-24, Digital to Analog Converter 输入元件 光电二极管 转换器 |
| 文件： | 总11页 (文件大小：234K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2
LC MOS
(8+4) Loading Dual 12-Bit DAC
a
AD7537
FUNCTIO NAL BLO CK D IAGRAM
FEATURES
Tw o 12-Bit DACs in One Package
DAC Ladder Resistance Matching: 0.5%
Space Saving Skinny DIP and Surface Mount Packages
4-Quadrant Multiplication
Low Gain Error (1 LSB m ax Over Tem perature)
Byte Loading Structure
Fast Interface Tim ing
APPLICATIONS
Autom atic Test Equipm ent
Program m able Filters
Audio Applications
Synchro Applications
Process Control
GENERAL D ESCRIP TIO N
T he AD7537 contains two 12-bit current output DACs on one
monolithic chip. A separate reference input is provided for each
DAC. T he dual DAC saves valuable board space, and the
monolithic construction ensures excellent thermal tracking.
Both DACs are guaranteed 12-bit monotonic over the full tem-
perature range.
T he AD7537 has a 2-byte (8 LSBs, 4 MSBs) loading structure.
It is designed for right-justified data format. T he control signals
for register loading are A0, A1, CS, WR and UPD. Data is
loaded to the input registers when CS and WR are low. T o
transfer this data to the DAC registers, UPD must be taken low
with WR.
P RO D UCT H IGH LIGH TS
1. DAC to DAC Matching:
Since both DACs are fabricated on the same chip, precise
matching and tracking is inherent. Many applications which
are not practical using two discrete DACs are now possible.
T ypical matching: 0.5%.
Added features on the AD7537 include an asynchronous CLR
line which is very useful in calibration routines. When this is
taken low, all registers are cleared. T he double buffering of the
data inputs allows simultaneous update of both DACs. Also,
each DAC has a separate AGND line. T his increases the device
versatility; for instance one DAC may be operated with
AGND biased while the other is connected in the standard
configuration.
2. Small Package Size:
T he AD7537 is packaged in small 24-pin 0.3" DIPs and in
28-terminal surface mount packages.
3. Wide Power Supply T olerance:
T he device operates on a +12 V to +15 V VDD, with 10%
tolerance on this nominal figure. All specifications are
guaranteed over this range.
T he AD7537 is manufactured using the Linear Compatible
CMOS (LC2MOS) process. It is speed compatible with most
microprocessors and accepts T T L, 74HC and 5 V CMOS logic
level inputs.
REV.
A
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
781/329-4700
781/461-3113
Tel:
Fax:
AD7537* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
View a parametric search of comparable parts.
DESIGN RESOURCES
• AD7537 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
DOCUMENTATION
Application Notes
• AN-206: CMOS Multiplying DAC Based Panning Circuit
Provides Almost Constant Output Power
DISCUSSIONS
View all AD7537 EngineerZone Discussions.
• AN-209: 8th Order Programmable Low-Pass Analog Filter
Using Dual 12-Bit CMOS Multiplying DACs
• AN-225: 12-Bit Voltage-Output DACs for Single-Supply 5V
and 12V Systems
SAMPLE AND BUY
Visit the product page to see pricing options.
Data Sheet
• AD7537: LC2MOS (8+4) Loading, Dual 12-Bit DAC Data
Sheet
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
• AD7537: Military Data Sheet
REFERENCE MATERIALS
Solutions Bulletins & Brochures
DOCUMENT FEEDBACK
Submit feedback for this data sheet.
• Digital to Analog Converters ICs Solutions Bulletin
This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not
trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.
(V = +12 V to +15 V, ؎10%, VREFA = VREFB = 10 V; IOUTA = AGND = 0 V,
DD
AD7537–SPECIFICATIONS
IOUTB = AGNDB = 0 V. All specifications TMIN to TMAX unless otherwise noted.)
J, A
K, B
L, C
S
T
U
P aram eter
Versions Versions Versions Version
Version
Version
Units
Test Conditions/Com m ents
ACCURACY
Resolution
Relative Accuracy
Differential Nonlinearity
12
1
1
12
1/2
1
12
1/2
1
12
1
1
12
1/2
1
12
1/2
1
Bits
LSB max
LSB max
All grades guaranteed mono-
tonic over temperature.
Gain Error
6
3
1
6
3
2
LSB max
Measured using RFBA, RFBB
Both DAC registers loaded
with all 1s.
.
Gain T emperature Coefficient2;
ΔGain/ΔT emperature
Output Leakage Current
IOUT A
5
5
5
5
5
5
ppm/°C max T ypical value is 1 ppm/°C
+25°C
TMIN to T MAX
10
150
10
150
10
150
10
250
10
250
10
250
nA max
nA max
DAC A Register loaded
with all 0s
IOUT B
+25°C
T MIN to T MAX
10
150
10
150
10
150
10
250
10
250
10
250
nA max
nA max
DAC B Register loaded
with all 0s
REFERENCE INPUT
Input Resistance
9
20
9
20
9
20
9
20
9
20
9
20
kΩ min
kΩ max
T ypical Input Resistance = 14 kΩ
V
REFA, VREFB
Input Resistance Match
3
3
1
3
3
1
% max
T ypically 0.5%
DIGIT AL INPUT S
IH (lnput High Voltage)
V
2.4
0.8
2.4
0.8
2.4
0.8
2.4
0.8
2.4
0.8
2.4
0.8
V min
V max
VIIL (Input Low Voltage)
IIN (Input Current)
+25°C
1
10
10
1
10
10
1
10
10
1
10
10
1
10
10
1
10
10
μA max
μA max
pF max
VIN = VDD
T MIN to T MAX
CIN (lnput Capacitance)2
POWER SUPPLY3
VDD
IDD
10.8/16.5 10.8/16.5 10.8/16.5 10.8/16.5 10.8/16.5 10.8/16.5 V min/V max
mA max
2
2
2
2
2
2
AC PERFORMANCE CHARACTERISTICS
These characteristics are included for Design Guidance only and are not subject to test.
(V = +12 V to +15 V; VREFA = VREFB = +10 V; IOUTA = AGNDA = 0 V, IOUTB = AGNDB = 0 V. Output Amplifiers are AD644 except where noted.)
DD
P aram eter
TA = +25؇C
TA = TMIN, TMAX Units
Test Conditions/Com m ents
Output Current Settling T ime
1.5
μs max
T o 0.01% of full-scale range. IOUT load = 100 Ω, CEXT = 13 pF.
DAC output measured from falling edge of WR.
T ypical Value of Settling T ime is 0.8 μs.
Digital-to-Analog Glitch lmpulse
7
nV-s typ
Measured with VREFA = VREFB = 0 V. IOUT A, IOUT B load = 100 Ω,
CEXT = 13 pF. DAC registers alternately loaded with all 0s and all 1s.
AC Feedthrough4
VREFA to IOUT A
VREFB to IOUT B
–70
–70
–65
–65
dB max
dB max
VREFA, VREFB = 20 V p-p 10 kHz sine wave.
DAC registers loaded with all 0s.
Power Supply Rejection
ΔGain/ΔVDD
0.01
0.02
% per % max ΔVDD = VDD max – VDD min
Output Capacitance
COUT A
COUT B
COUT A
COUT B
70
70
140
140
70
70
140
140
pF max
pF max
pF max
pF max
DAC A, DAC B loaded with all 0s
DAC A, DAC B loaded with all 1s
Channel-to-Channel Isolation
VREFA to IOUT B
–84
–84
dB typ
dB typ
VREFA = 20 V p-p 10 kHz sine wave, VREFB = 0 V.
Both DACs loaded with all 1s.
VREFB = 20 V p-p 10 kHz sine wave, VREFA = 0 V.
Both DACs loaded with all 1s.
VREFB to IOUT A
Digital Crosstalk
7
nV-s typ
nV/√Hz typ
dB typ
Measured for a Code T ransition of all 0s to all 1s.
IOUT A, IOUT B load = 100 Ω, CEXT = 13 pF.
Output Noise Voltage Density
(10 Hz–100 kHz)
25
–82
Measured between RFBA and IOUT A or RFBB and IOUT B.
Frequency of measurement is 10 Hz–100 kHz.
T otal Harmonic Distortion
NOT ES
VIN = 6 V rms, 1 kHz. Both DACs loaded with all 1s.
1T emperature range as follows: J, K, L Versions: –40°C to +85°C;
A, B, C Versions: –40°C to +85°C;
2Sample tested at +25°C to ensure compliance.
3Functional at VDD = 5 V, with degraded specifications.
4Pin 12 (DGND) on ceramic DIPs is connected to lid.
S, T , U Versions: –55°C to +125°C
Specifications subject to change without notice.
–2–
REV.
A
AD7537
TIMING CHARACTERISTICS (V = +10.8 V to +16.5 V, V
REFA = VREFB = +10 V; IOUTA = AGNDA = 0 V, IOUTB = AGNDB = 0 V.)
DD
Lim it at
Lim it at
Lim it at
TA = +25؇C
TA = –40؇C
to +85؇C
TA = +55؇C
to +125؇C
P aram eter
Units
Test Conditions/Com m ents
t1
t2
t3
t4
t5
t6
t7
t8
15
15
60
25
0
0
80
80
15
15
80
25
0
0
80
80
30
25
80
25
0
0
100
100
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Address Valid to Write Setup T ime
Address Valid to Write Hold T ime
Data Setup T ime
Data Hold T ime
Chip Select or Update to Write Setup T ime
Chip Select or Update to Write Hold T ime
Write Pulse Width
Clear Pulse Width
Specifications subject to change without notice.
ABSO LUTE MAXIMUM RATINGS*
(T A = +25°C unless otherwise stated)
Operating T emperature Range
Commercial Plastic (J, K, L Versions) . . . . –40°C to +85°C
Industrial Hermetic (A, B, C Versions) . . . –40°C to +85°C
Extended Hermetic (S, T , U Versions) . . –55°C to +125°C
Storage T emperature . . . . . . . . . . . . . . . . –65°C to +150°C
Lead T emperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V
V
V
REFA, VREFB to AGNDA, AGNDB . . . . . . . . . . . . . . . . 25 V
RFBA, VRFBB to AGNDA, AGNDB . . . . . . . . . . . . . . . . 25 V
Digital Input Voltage to DGND . . . . . . . –0.3 V, VDD +0.3 V
OUT A, IOUT B to DGND . . . . . . . . . . . . . . –0.3 V, VDD +0.3 V
I
AGNDA, AGNDB to DGND . . . . . . . . . –0.3 V, VDD +0.3 V
Power Dissipation (Any Package)
T o +75°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW
Derates Above +75°C . . . . . . . . . . . . . . . . . . . . . 6 mW/°C
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7537 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
Figure 1. Tim ing Diagram
REV.
A
–3–
AD7537
P IN FUNCTIO N D ESCRIP TIO N (PDIP)
current flowing in each ladder leg is constant, irrespective of
switch state. T he feedback resistor RFBA is used with an op amp
(see Figures 4 and 5) to convert the current flowing in IOUT A to
a voltage output.
P IN
MNEMO NIC
D ESCRIP TIO N
1
2
3
4
5
AGNDA
IOUT A
RFBA
VREFA
CS
Analog Ground for DAC A.
Current output terminal of DAC A.
Feedback resistor for DAC A.
Reference input to DAC A.
Chip Select Input Active low.
Eight data inputs, DB0–DB7.
Digital Ground.
6–14 DB0–DB7
12
15
16
17
DGND
A0
Address Line 0.
A1
Address Line 1.
CLR
Clear Input. Active low. Clears all
registers.
Figure 2. Sim plified Circuit Diagram for DAC A
18
19
WR
UPD
Write Input. Active low.
Updates DAC Registers from inputs
registers.
EQ UIVALENT CIRCUIT ANALYSIS
Figure 3 shows the equivalent circuit for one of the D/A con-
verters (DAC A) in the AD7537. A similar equivalent circuit
can be drawn for DAC B.
20
VDD
Power supply input. Nominally +12 V
to +15 V, with 10% tolerance.
Reference input to DAC B.
Feedback resistor for DAC B.
Current output terminal of DAC B.
Analog Ground for DAC B.
21
22
23
24
VREFB
RFBB
IOUT B
COUT is the output capacitance due to the N-channel switches
and varies from about 50 pF to 150 pF with digital input code.
T he current source ILKG is composed of surface and junction
leakages and approximately doubles every 10°C. R0 is the
equivalent output resistance of the device which varies with
input code.
AGNDB
P IN CO NFIGURATIO NS
PDIP and SOIC
D IGITAL CIRCUIT INFO RMATIO N
T he digital inputs are designed to be both T T L and 5 V CMOS
compatible. All logic inputs are static protected MOS gates with
typical input currents of less than 1 nA.
Table I. AD 7537 Truth Table
CLR UPD CS WR A1 A0 FUNCTIO N
1
1
0
1
1
1
X
1
1
X
1
X
0
X
X
X
0
X
X
X
0
No Data T ransfer
No Data T ransfer
All Registers Cleared
X
X
0
DAC A LS Input Register
Loaded with DB7–DB0 (LSB)
DAC A MS Input Register
Loaded with DB3 (MSB)–DB0
DAC B LS Input Register
Loaded with DB7–DB0 (LSB)
DAC B MS Input Register
Loaded with DB3 (MSB)–DB0
DAC A, DAC B Registers
Updated Simultaneously from
Input Registers
1
1
1
1
1
1
1
0
0
0
0
1
0
0
0
0
0
1
P LCC
1
0
1
1
X
X
1
0
0
0
X
X
DAC A, DAC B Registers are
T ransparent
NOT ES: X = Don’t care
CIRCUIT INFO RMATIO N – D /A SECTIO N
T he AD7537 contains two identical 12-bit multiplying D/A
converters. Each DAC consists of a highly stable R-2R ladder
and 12 N-channel current steering switches. Figure 2 shows a
simplified D/A circuit for DAC A. In the R-2R ladder, binary
weighted currents are steered between IOUT A and AGNDA. T he
Figure 3. Equivalent Analog Circuit for DAC A
REV. A
–4–
Applications–AD7537
UNIP O LAR BINARY O P ERATIO N
BIP O LAR O P ERATIO N
(2-Q UAD RANT MULTIP LICATIO N)
(4-Q UAD RANT MULTIP LICATIO N)
Figure 4 shows the circuit diagram for unipolar binary opera-
tion. With an ac input, the circuit performs 2-quadrant multipli-
cation. T he code table for Figure 4 is given in T able II.
T he recommended circuit diagram for bipolar operation is
shown in Figure 5. Offset binary coding is used.
With the appropriate DAC register loaded to 1000 0000 0000,
adjust R1 (R3) so that VOUT A (VOUT B) = 0 V. Alternatively, R1,
R2 (R3, R4) may be omitted and the ratios of R6, R7 (R9, 10)
varied for VOUT A (VOUT B) = 0 V. Full-scale trimming can be ac-
complished by adjusting the amplitude of VIN or by varying the
value of R5 (R8).
Operational amplifiers A1 and A2 can be in a single package
(AD644, AD712) or separate packages (AD544, AD711,
AD OP27). Capacitors C1 and C2 provide phase compensation
to help prevent overshoot and ringing when high-speed op amps
are used.
For zero offset adjustment, the appropriate DAC register is
loaded with all 0s and amplifier offset adjusted so that VOUT A or
VOUT B is 0 V. Full-scale trimming is accomplished by loading
the DAC register with all 1s and adjusting R1 (R3) so that
If R1, R2 (R3, R4) are not used, then resistors R5, R6, R7 (R8,
R9, R10) should be ratio matched to 0.01% to ensure gain error
performance to the data sheet specification. When operating
over a wide temperature range, it is important that the resistors
be of the same type so that their temperature coefficients match.
VOUT A (VOUT B) = –VIN (4095/4096). For high temperature op-
eration, resistors and potentiometers should have a low T em-
perature Coefficient. In many applications, because of the
excellent Gain T .C. and Gain Error specifications of the
AD7537, Gain Error trimming is not necessary. In fixed refer-
ence applications, full scale can also be adjusted by omitting R1,
R2, R3, R4 and trimming the reference voltage magnitude.
T he code table for Figure 5 is given in T able III.
Figure 5. Bipolar Operation (Offset Binary Coding)
Table III. Bipolar Code Table for O ffset Binary
Circuit of Figure 5
Binary Num ber in
D AC Register
Analog O utput,
VO UTA or VO UTB
Figure 4. AD7537 Unipolar Binary Operation
MSB
LSB
Table II. Unipolar Binary Code Table for
Circuit of Figure 4
⎛ 2047 ⎞
2048
+VIN
⎜
⎝
⎟
⎠
1111 1111 1111
Binary Num ber in
D AC Register
Analog O utput,
VO UTA or VO UTB
⎛
1
⎞
+VIN
0 V
⎜
⎝
⎟
⎠
1000 0000 0001
1000 0000 0000
MSB
LSB
2048
⎛ 4095 ⎞
−VIN
−VIN
⎜
⎟
1111 1111 1111
⎛
1
⎞
4096
⎝
⎠
−VIN
⎜
⎝
⎟
⎠
0111 1111 1111
0000 0000 0000
2048
⎛ 2048 ⎞
1
= − VIN
⎜
⎝
⎟
⎠
1000 0000 0000
2
⎛ 2048 ⎞
4096
−VIN
= −VIN
⎟
⎜
2048
⎝
⎠
⎛
1
⎞
−VIN
0 V
⎜
⎝
⎟
⎠
0000 0000 0001
0000 0000 0000
A
4096
REV.
–5–
AD7537
SEP ARATE AGND P INS
the AD7537 controls the programmable integrators. T he fre-
quency of oscillation is given by:
T he DACs in the AD7537 have separate AGND lines taken to
pins AGNDA and AGNDB on the package. T his increases the
applications versatility of the part. Figure 6 is an example of
this. DAC A is connected in standard fashion as a program-
mable attenuator. AGNDA is at ground potential. DAC B is op-
erating with AGND B biased to +5 V by the AD584. T his gives
an output range of +5 V to +10 V.
1
R6
1
f =
×
2 π R5 C1×C2 × REQ1 × REQ2
where REQ1 and REQ2 are the equivalent resistances of the
DACs. T he same digital code is loaded into both DACs.
If C1 = C2 and R5 = R6, the expression reduces to
1
2 π
1
C
1
f =
×
REQ1 × REQ2
2n × RLAD
Since REQ
=
, (RLAD = DAC ladder resistance).
N
1
2 π
1
C
(N /2n )2
RLAD1 × RLAD2
f =
×
1
2π
D
C
1
⎛ N ⎞
⎝
=
×
D =
⎜
⎟
2n
⎠
RLAD1 × RLAD2
1
D
=
×
2 π C × RLAD
m
where m is the DAC ladder resistance mismatch ratio, typically
1.005.
With the values shown in Figure 7, the output frequency varies
from 0 Hz to 1.38 kHz. T he amplitude of the output signal at
the A3 output is 10 V peak-to-peak and is constant over the
entire frequency span.
Figure 6. AD7537 DACs Used in Different Modes
P RO GRAMMABLE O SCILLATO R
Figure 7 shows a conventional state variable oscillator in which
Figure 7. Program m able State Variable Oscillator
–6–
REV. A
AD7537
AP P LICATIO N H INTS
other for the MC68008. Figure 11 shows how an AD7537 sys-
tem can be easily expanded by tying all the UPD lines together
and using a single decoder output to control these. T his ex-
panded system is shown using a Z80 microprocessor but it is
just as easily configured using any other 8-bit microprocessor
system. Note how the system shown in Figure 11 produces 4
analog outputs with a minimum amount of hardware.
O utput O ffset: CMOS D/A converters in circuits such as Fig-
ures 4 and 5 exhibit a code dependent output resistance which
in turn can cause a code dependent error voltage at the output
of the amplifier. T he maximum amplitude of this error, which
adds to the D/A converter nonlinearity, depends on VOS, where
VOS is the amplifier input offset voltage. T o maintain specified
operation, it is recommended that VOS be no greater than
(25 ϫ 10–6) (VREF) over the temperature range of operation.
Suitable op amps are the AD711C and its dual version, the
AD712C. T hese op amps have a wide bandwidth and high slew
rate and are recommended for wide bandwidth ac applications.
AD711/AD712 settling time to 0.01% is typically 3 μs.
Tem per atur e Coefficients: T he gain temperature coefficient
of the AD7537 has a maximum value of 5 ppm/°C and typical
value of 1 ppm/°C. T his corresponds to worst case gain shifts of
2 LSBs and 0.4 LSBs respectively over a 100°C temperature
range. When trim resistors R1 (R3) and R2 (R4) are used to ad-
just full scale range as in Figure 4, the temperature coefficient of
R1 (R3) and R2 (R4) should also be taken into account. For
further information see “Gain Error and Gain T emperature Co-
efficient of CMOS Multiplying DACs”, Application Note, Pub-
lication Number E630c-5-3/86 available from Analog Devices.
Figure 9. AD7537–MC6809 Interface
H igh Fr equency Consider ations: AD7537 output capaci-
tance works in conjunction with the amplifier feedback resis-
tance to add a pole to the open loop response. T his can cause
ringing or oscillation. Stability can be restored by adding a
phase compensation capacitor in parallel with the feedback re-
sistor. T his is shown as C1 and C2 in Figures 4 and 5.
Feedthr ough: T he dynamic performance of the AD7537 de-
pends upon the gain and phase stability of the output amplifier,
together with the optimum choice of PC board layout and de-
coupling components. A suggested printed circuit layout for
Figure 4 is shown in Figure 8 which minimizes feedthrough
from VREFA, VREFB to the output in multiplying applications.
Figure 10. AD7537–MC68008 Interface
Figure 8. Suggested Layout for AD7537
MICRO P RO CESSO R INTERFACING
T he byte loading structure of the AD7537 makes it very easy to
interface the device to any 8-bit microprocessor system. Figures
9 and 10 show two interfaces: one for the MC6809 and the
Figure 11. Expanded AD7537 System
REV.
A
–7–
AD7537
OUTLINE DIMENSIONS
1.280 (32.51)
1.250 (31.75)
1.230 (31.24)
24
1
13
12
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
PLANE
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 12. 24-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-24-1)
Dimensions shown in inches and (millimeters)
0.180 (4.57)
0.165 (4.19)
0.048 (1.22)
0.042 (1.07)
0.056 (1.42)
0.042 (1.07)
0.020 (0.51)
MIN
4
26
25
0.048 (1.22)
0.042 (1.07)
5
0.021 (0.53)
0.013 (0.33)
PIN 1
IDENTIFIER
BOTTOM
VIEW
(PINS UP)
0.050
(1.27)
BSC
0.430 (10.92)
0.390 (9.91)
TOP VIEW
(PINS DOWN)
0.032 (0.81)
0.026 (0.66)
11
19
18
12
0.045 (1.14)
0.025 (0.64)
R
0.456 (11.582)
0.450 (11.430)
SQ
0.120 (3.04)
0.090 (2.29)
0.495 (12.57)
SQ
0.485 (12.32)
COMPLIANT TO JEDEC STANDARDS MO-047-AB
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 16. 28-Lead Plastic Leaded Chip Carrier [PLCC]
(P-28)
Dimensions shown in inches and (millimeters)
–8–
REV. A
AD7537
15.60 (0.6142)
15.20 (0.5984)
24
1
13
12
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
10.00 (0.3937)
0.75 (0.0295)
0.25 (0.0
098)
45°
2.65 (0.1043)
2.35 (0.0925)
0.30 (0.0118)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
1.27 (0.0500)
BSC
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AD
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 17. 24-Lead Standard Small Outline Package [SOIC-W]
Wide Body
(RW-24)
Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Model1, 2, 3
AD7537JN
AD7537JNZ
AD7537KN
AD7537KNZ
AD7537ꢀNZ
AD7537JP
AD7537JP-REEꢀ
AD7537JPZ
AD7537JPZ-REEꢀ
AD7537KP
AD7537KPZ
AD7537KPZ-REEꢀ
AD7537ꢀP-REEꢀ
AD7537ꢀPZ
AD7537ꢀPZ-REEꢀ
AD7537JR
AD7537JR-REEꢀ
AD7537JRZ
AD7537JRZ-REEꢀ
AD7537KRZ
AD7537KR-REEꢀ
AD7537SR
AD7537SR-REEꢀ
AD7537SRZ
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Relative Accuracy
±± ꢀLS
±± ꢀLS
±±12 ꢀLS
±±12 ꢀLS
±±12 ꢀLS
±± ꢀLS
±± ꢀLS
±± ꢀLS
±± ꢀLS
±±12 ꢀLS
±±12 ꢀLS
±±12 ꢀLS
±±12 ꢀLS
±±12 ꢀLS
±±12 ꢀLS
±± ꢀLS
±± ꢀLS
±± ꢀLS
±± ꢀLS
Gain Error
±ꢁ ꢀLS
±ꢁ ꢀLS
±3 ꢀLS
±3 ꢀLS
±± ꢀLS
±ꢁ ꢀLS
±ꢁ ꢀLS
±ꢁ ꢀLS
±ꢁ ꢀLS
±3 ꢀLS
±3 ꢀLS
±3 ꢀLS
±± ꢀLS
±± ꢀLS
±± ꢀLS
±ꢁ ꢀLS
±ꢁ ꢀLS
±ꢁ ꢀLS
±ꢁ ꢀLS
±3 ꢀLS
±3 ꢀLS
±3 ꢀLS
±3 ꢀLS
±3 ꢀLS
Package Description
Package Option
24-ꢀead PDIP
24-ꢀead PDIP
24-ꢀead PDIP
24-ꢀead PDIP
N-24-±
N-24-±
N-24-±
N-24-±
N-24-±
P-28
P-28
P-28
P-28
P-28
24-ꢀead PDIP
28-ꢀead PꢀCC
28-ꢀead PꢀCC
28-ꢀead PꢀCC
28-ꢀead PꢀCC
28-ꢀead PꢀCC
28-ꢀead PꢀCC
28-ꢀead PꢀCC
28-ꢀead PꢀCC
28-ꢀead PꢀCC
28-ꢀead PꢀCC
24-ꢀead LOIC_W
24-ꢀead LOIC_W
24-ꢀead LOIC_W
24-ꢀead LOIC_W
24-ꢀead LOIC_W
24-ꢀead LOIC_W
24-ꢀead LOIC_W
24-ꢀead LOIC_W
24-ꢀead LOIC_W
P-28
P-28
P-28
P-28
P-28
RW-24
RW-24
RW-24
RW-24
RW-24
RW-24
RW-24
RW-24
RW-24
±±12 ꢀLS
±±12 ꢀLS
±±12 ꢀLS
±±12 ꢀLS
±±12 ꢀLS
± Z = RoHL Compliant Part.
2 Analog Devices reserves the right to ship side-brazed CERDIP packages (D-24-±) in lieu of CERDIP packages (Q-24-±).
3 To order MIꢀ-LTD-883, Class S processed parts, add1883S to part number. Contact your local sales office for military data sheet.
REV. A
–9–
AD7537
REVISION HISTORY
6/12—Rev. 0 to Rev. A
Added SOIC Package......................................................... Universal
Removed LCCC Pin Configuration................................................4
Updated Outline Dimensions..........................................................8
Changes to Ordering Guide.............................................................9
10/87—Revision 0: Initial Version
©1987–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D01138-0-6/12(A)
–±0–
REV. A
相关型号：
AD7537KR-REEL
DUAL, PARALLEL, 8 BITS INPUT LOADING, 0.8 us SETTLING TIME, 12-BIT DAC, PDSO24, SOIC-24
ROCHESTER
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