AD629BR-REEL [ADI]
High Common-Mode Voltage Difference Amplifier; 高共模电压差动放大器
| 型号： | AD629BR-REEL |
| 厂家： | 
ADI |
| 描述： | High Common-Mode Voltage Difference Amplifier |
| 文件： | 总12页 (文件大小：303K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Common-Mode Voltage
Difference Amplifier
a
AD629
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Improved Replacement for:
INA117P and INA117KU
8-Lead Plastic Mini-DIP (N) and SOIC (R) Packages
؎270 V Common-Mode Voltage Range
Input Protection to:
؎500 V Common Mode
21.1k⍀
380k⍀
380k⍀
380k⍀
20k⍀
8
7
6
5
NC
+V
1
2
3
4
REF(–)
–IN
S
؎500 V Differential
+IN
OUTPUT
REF(+)
Wide Power Supply Range (؎2.5 V to ؎18 V)
؎10 V Output Swing on ؎12 V Supply
1 mA Max Power Supply Current
–V
S
AD629
NC = NO CONNECT
HIGH ACCURACY DC PERFORMANCE
3 ppm Max Gain Nonlinearity
20 V/؇C Max Offset Drift (AD629A)
10 V/؇C Max Offset Drift (AD629B)
10 ppm/؇C Max Gain Drift
GENERAL DESCRIPTION
The AD629 is a difference amplifier with a very high input
common-mode voltage range. It is a precision device that
allows the user to accurately measure differential signals in the
presence of high common-mode voltages up to 270 V.
EXCELLENT AC SPECIFICATIONS
77 dB Min CMRR @ 500 Hz (AD629A)
86 dB Min CMRR @ 500 Hz (AD629B)
500 kHz Bandwidth
The AD629 can replace costly isolation amplifiers in applications
that do not require galvanic isolation. The device will operate
over a 270 V common-mode voltage range and has inputs
that are protected from common-mode or differential mode
transients up to 500 V.
APPLICATIONS
High Voltage Current Sensing
Battery Cell Voltage Monitor
Power Supply Current Monitor
Motor Control
The AD629 has low offset, low offset drift, low gain error drift,
as well as low common-mode rejection drift, and excellent CMRR
over a wide frequency range.
Isolation
The AD629 is available in low-cost, plastic 8-lead DIP and
SOIC packages. For all packages and grades, performance is
guaranteed over the entire industrial temperature range from
–40°C to +85°C.
100
95
90
85
80
75
70
65
60
55
50
2mV/DIV
60V/DIV
–240
–120
COMMON-MODE VOLTAGE – Volts
0
120
240
20
100
1k
10k 20k
FREQUENCY – Hz
Figure 1. Common-Mode Rejection Ratio vs. Frequency
Figure 2. Common-Mode Operating Range. Error Voltage
vs. Input Common-Mode Voltage
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
(TA = 25؇C, VS = ؎15 V unless otherwise noted)
AD629–SPECIFICATIONS
AD629A
AD629B
Typ
Parameter
Condition
Min
Typ
Max
Min
Max
Unit
GAIN
Nominal Gain
Gain Error
VOUT 10 V, RL = 2 kΩ
=
1
1
V/V
0.01
0.05
10
0.01
0.03
10
3
%
Gain Nonlinearity
4
1
3
4
1
3
ppm
ppm
ppm/°C
RL = 10 kΩ
TA = TMIN to TMAX
Gain vs. Temperature
10
10
OFFSET VOLTAGE
Offset Voltage
0.2
1
0.1
0.5
1
mV
mV
VS = 5 V
vs. Temperature
vs. Supply (PSRR)
TA = TMIN to TMAX
VS = 5 V to 15 V
6
100
20
3
110
10
µV/°C
dB
84
90
INPUT
Common-Mode Rejection Ratio
VCM
=
250 V dc
77
73
77
88
88
86
82
86
96
90
dB
dB
dB
dB
V
TA = TMIN to TMAX
VCM = 500 V p-p DC to 500 Hz
VCM = 500 V p-p DC to 1 kHz
Common-Mode
Operating Voltage Range
270
13
270
13
Differential
V
Input Operating Impedance
Common-Mode
Differential
200
800
200
800
kΩ
kΩ
OUTPUT
Operating Voltage Range
RL = 10 kΩ
13
12.5
10
13
12.5
10
V
V
V
mA
pF
RL = 2 kΩ
VS = 12 V, RL = 2 kΩ
Output Short Circuit Current
Capacitive Load
25
25
Stable Operation
1000
1000
DYNAMIC RESPONSE
Small Signal –3 dB Bandwidth
Slew Rate
Full Power Bandwidth
Settling Time
500
2.1
28
15
12
5
500
2.1
28
15
12
5
kHz
V/µs
kHz
µs
1.7
1.7
VOUT = 20 V p-p
0.01%, VOUT = 10 V Step
0.1%, VOUT = 10 V Step
0.01%, VCM = 10 V Step, VDIFF = 0 V
µs
µs
OUTPUT NOISE VOLTAGE
0.01 Hz to 10 Hz
15
550
15
550
µV p-p
nV/√Hz
Spectral Density, ≥100 Hz1
POWER SUPPLY
Operating Voltage Range
Quiescent Current
2.5
18
1
2.5
18
1
V
mA
mA
VOUT = 0 V
TMIN to TMAX
0.9
1.2
0.9
1.2
TEMPERATURE RANGE
For Specified Performance
TA = TMIN to TMAX
–40
+85
–40
+85
°C
NOTES
1See Figure 19.
Specifications subject to change without notice.
REV. A
–2–
AD629
ABSOLUTE MAXIMUM RATINGS1
THEORY OF OPERATION
Supply Voltage VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
The AD629 is a unity gain differential-to-single-ended amplifier
(Diff Amp) that can reject extremely high common-mode
signals (in excess of 270 V with 15 V supplies). It consists of an
operational amplifier (Op Amp) and a resistor network.
Internal Power Dissipation2
DIP (N) . . . . . . . . . . . . . . . . . . . . . . . . See Derating Curves
SOIC (R) . . . . . . . . . . . . . . . . . . . . . . . See Derating Curves
Input Voltage Range, Continuous . . . . . . . . . . . . . . . . 300 V
Common-Mode and Differential, 10 sec . . . . . . . . . . . 500 V
Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Pin 1, Pin 5 . . . . . . . . . . . . . . . . . . –VS – 0.3 V to +VS + 0.3 V
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C
Operating Temperature Range . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300°C
In order to achieve high common-mode voltage range, an internal
resistor divider (Pin 3, Pin 5) attenuates the noninverting signal
by a factor of 20. Other internal resistors (Pin 1, Pin 2, and the
feedback resistor) restores the gain to provide a differential gain
of unity. The complete transfer function equals:
V
OUT = V (+IN) – V (–IN)
Laser wafer trimming provides resistor matching so that common-
mode signals are rejected while differential input signals are
amplified.
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may effect device reliability.
2Specification is for device in free air: 8-Lead Plastic DIP, θJA = 100°C/W; 8-Lead
SOIC Package, θJA = 155°C/W.
The op amp itself, in order to reduce output drift, uses super
beta transistors in its input stage The input offset current and
its associated temperature coefficient contribute no appreciable
output voltage offset or drift. This has the added benefit of
reducing voltage noise because the corner where 1/f noise becomes
dominant is below 5 Hz. In order to reduce the dependence of
gain accuracy on the op amp, the open-loop voltage gain of the
op amp exceeds 20 million, and the PSRR exceeds 140 dB.
2.0
T
= 150؇C
J
8-LEAD MINI-DIP PACKAGE
1.5
1.0
21.1k⍀
380k⍀
380k⍀
380k⍀
8
7
6
5
NC
+V
1
2
3
4
REF(–)
–IN
S
+IN
OUTPUT
REF(+)
20k⍀
8-LEAD SOIC PACKAGE
–V
S
AD629
0.5
0
NC = NO CONNECT
Figure 4. Functional Block Diagram
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
AMBIENT TEMPERATURE – ؇C
Figure 3. Derating Curve of Maximum Power Dissipation
vs. Temperature for SOIC and PDIP Packages
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Option
Model
AD629AR
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
8-Lead Plastic SOIC
8-Lead Plastic SOIC
8-Lead Plastic SOIC
8-Lead Plastic SOIC
8-Lead Plastic SOIC
8-Lead Plastic SOIC
8-Lead Plastic DIP
8-Lead Plastic DIP
SO-8
SO-8
SO-8
SO-8
SO-8
SO-8
N-8
AD629AR-REEL1
AD629AR-REEL72
AD629BR
AD629BR-REEL1
AD629BR-REEL72
AD629AN
AD629BN
N-8
NOTES
113" Tape and Reel of 2500 each
27" Tape and Reel of 1000 each
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD629 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
–3–
AD629–Typical Performance Characteristics (@25؇C, V = ؎15 V unless otherwise noted)
S
400
100
360
90
80
70
60
50
40
30
20
10
0
T
= +25؇C
A
320
280
240
200
160
120
80
T
= +85؇C
A
T
= –40؇C
A
40
0
0
2
4
6
8
10
12
14
16
18
20
100
1k
10k
100k
1M
10M
POWER SUPPLY VOLTAGE – ؎Volts
FREQUENCY – Hz
Figure 8. Common-Mode Operating Range vs. Power
Supply Voltage
Figure 5. Common-Mode Rejection Ratio vs. Frequency
2mV/DIV
R
= 2k⍀
R
= 10k⍀
L
L
V
= ؎18V
S
V
= ؎18V
S
V
= ؎15V
S
V
= ؎15V
S
V
= ؎12V
S
V
= ؎12V
S
S
4V/DIV
16
V
= ؎10V
4V/DIV
S
V
= ؎10V
–8
–20 –16 –12
–8
–4
0
4
8
12
20
–20 –16 –12
–4
0
4
8
12
16
20
V
– Volts
V
– Volts
OUT
OUT
Figure 9. Typical Gain Error Normalized @ VOUT = 0 V and
Output Voltage Operating Range vs. Supply Voltage,
RL = 2 kΩ (Curves Offset for Clarity)
Figure 6. Typical Gain Error Normalized @ VOUT = 0 V and
Output Voltage Operating Range vs. Supply Voltage,
RL = 10 kΩ (Curves Offset for Clarity)
R
= 1k⍀
L
V
V
= ؎5V, R = 10k⍀
S
L
V
= ؎18V
S
V
= ؎15V
= ؎5V, R = 2k⍀
S
S
L
V
= ؎12V
V
= ؎5V, R = 1k⍀
S
S
L
4V/DIV
16
V
= ؎2.5V, R = 1k⍀
1V/DIV
4
V
= ؎10V
S
L
S
–5
–4
–3
–2
–1
V
0
1
2
3
5
–20 –16 –12
–8
–4
0
4
8
12
20
– Volts
V
– Volts
OUT
OUT
Figure 10. Typical Gain Error Normalized @ VOUT = 0 V
and Output Voltage Operating Range vs. Supply Voltage
(Curves Offset for Clarity)
Figure 7. Typical Gain Error Normalized @ VOUT = 0 V
and Output Voltage Operating Range vs. Supply Voltage,
RL = 1 kΩ (Curves Offset for Clarity)
REV. A
–4–
AD629
–10
–5
0
5
10
–10 –8
–6
–4
–2
OUT
0
2
4
6
8
10
V
– Volts
OUT
V
– Volts
Figure 11. Gain Nonlinearity; VS = 15 V, RL =10 kΩ
Figure 14. Gain Nonlinearity; VS = 15 V, RL = 2 kΩ
14.0
–40؇C
13.0
12.0
–40؇C
+85؇C
V
= ؎15V
11.0
+25؇C
S
10.0
9.0
–11.5
–12.0
–12.5
–13.0
–13.5
–40؇C
+25؇C
+85؇C
–10 –8
–6
–4
–2
OUT
0
2
4
6
8
10
0
2
4
6
8
10
12
14
16
18
20
V
– Volts
OUTPUT CURRENT – mA
Figure 12. Gain Nonlinearity; VS = 12 V, RL =10 kΩ
Figure 15. Output Voltage Operating Range vs. Output
Current; VS = 15 V
11.5
+85؇C
10.5
9.5
–40؇C
–40؇C
+25؇C
8.5
V
= ؎12V
S
7.5
+85؇C
6.5
–9.0
–9.5
–10.0
–10.5
–11.0
–40؇C
+25؇C
+85؇C
10
–3.0 –2.4 –1.8 –1.2 –0.6
0
0.6 1.2
1.8
2.4
3.0
0
2
4
6
8
12
14
16
18
20
V
– Volts
OUT
OUTPUT CURRENT – mA
Figure 16. Output Voltage Operating Range vs. Output
Current; VS = 12 V
Figure 13. Gain Nonlinearity; VS = 5 V, RL =1 kΩ
REV. A
–5–
AD629
+85؇C
4.5
3.5
2.5
1.5
0.5
–40؇C
+25؇C
R
C
= 2k⍀
= 0pF
L
L
–40؇C
+85؇C
V
= ؎5V
S
+85؇C
–2.0
–2.5
–3.0
–3.5
–4.0
–40؇C
+25؇C
4s/DIV
25mV/DIV
+25؇C
+85؇C
0
2
4
6
8
10
12
14
16
18
20
OUTPUT CURRENT – mA
Figure 20. Small Signal Pulse Response; G = 1, RL = 2 kΩ
Figure 17. Output Voltage Operating Range vs. Output
Current; VS = 5 V
120
+V
S
110
100
90
R
C
= 2k⍀
= 1000pF
L
L
–V
S
80
70
60
50
40
30
4s/DIV
25mV/DIV
0.1
1
10
100
1k
10k
FREQUENCY – Hz
Figure 18. Power Supply Rejection Ratio vs. Frequency
Figure 21. Small Signal Pulse Response; G = 1, RL = 2 kΩ,
CL = 1000 pF
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
G = +1
R
C
= 2k⍀
= 1000pF
L
L
5s/DIV
5V/DIV
0.01
0.1
1
10
100
1k
10k
100k
FREQUENCY – Hz
Figure 22. Large Signal Pulse Response; G = 1,
RL = 2 kΩ, CL = 1000 pF
Figure 19. Voltage Noise Spectral Density vs. Frequency
REV. A
–6–
AD629
5V/DIV
0V
5V/DIV
+10V
V
V
OUT
OUT
0V
–10V
1mV = 0.01%
OUTPUT
ERROR
OUTPUT
ERROR
1mV = 0.01%
10s/DIV
1mV/DIV
10s/DIV
1mV/DIV
Figure 26. Settling Time to 0.01% for 0 V to –10 V Output
Step; G = –1, RL = 2 kΩ
Figure 23. Settling Time to 0.01%, For 0 V to 10 V Output
Step; G = –1, RL = 2 kΩ
300
350
N = 2180
N = 2180
n
Ϸ
200 PCS. FROM
n Ϸ 200 PCS. FROM
300
250
200
150
100
50
250
200
150
100
50
10 ASSEMBLY LOTS
10 ASSEMBLY LOTS
0
0
–900
900
–600
–300
0
300
600
–150
150
–100
–50
0
50
100
OFFSET VOLTAGE – V
COMMON-MODE REJECTION RATIO – ppm
Figure 27. Typical Distribution of Offset Voltage;
Package Option N-8
Figure 24. Typical Distribution of Common-Mode
Rejection; Package Option N-8
400
400
N = 2180
350
N = 2180
350
Ϸ 200 PCS. FROM
n Ϸ 200 PCS. FROM
n
10 ASSEMBLY LOTS
300
10 ASSEMBLY LOTS
300
250
200
150
100
50
250
200
150
100
50
0
–600
0
600
–400
–200
0
200
400
–600
600
–400
–200
0
200
400
+1 GAIN ERROR – ppm
–1 GAIN ERROR – ppm
Figure 28. Typical Distribution of +1 Gain Error;
Package Option N-8
Figure 25. Typical Distribution of –1 Gain Error;
Package Option N-8
REV. A
–7–
AD629
APPLICATIONS
Basic Connections
+V
S
AD629
21.1k⍀
REF(–)
–IN
1
2
3
4
8
7
6
5
NC
+V
Figure 29 shows the basic connections for operating the AD629
with a dual supply. A supply voltage of between 3 V and
18 V is applied between Pins 7 and 4. Both supplies should be
decoupled close to the pins using 0.1 µF capacitors. 10 µF elec-
trolytic capacitors, also located close to the supply pins, may
also be required if low frequency noise is present on the power
supply. While multiple amplifiers can be decoupled by a single
set of 10 µF capacitors, each in amp should have its own set of
0.1 µF capacitors so that the decoupling point can be located
physically close to the power pins.
380k⍀ 380k⍀
0.1F
S
V
X
I
R
SHUNT
SHUNT
380k⍀
+IN
V
Y
20k⍀
–V
REF(+)
S
OUTPUT = V
–V
REF
OUT
NC = NO CONNECT
V
REF
Figure 30. Operation with a Single Supply
+V
3V TO 18V
S
AD629
21.1k⍀
REF(–)
–IN
Applying a reference voltage to REF(+) and REF(–) and operating
on a single supply will reduce the input common-mode range of
the AD629. The new input common-mode range depends upon
the voltage at the inverting and noninverting inputs of the internal
operational amplifier, labeled VX and VY in Figure 30. These
nodes can swing to within 1 V of either rail. So for a (single)
supply voltage of 10 V, VX and VY can range between 1 V and
9 V. If VREF is set to 5 V, the permissible common-mode range
is +85 V to –75 V. The common-mode voltage ranges can be
calculated using the following equation.
1
2
3
4
8
7
6
5
NC
380k⍀ 380k⍀
(SEE
TEXT)
+V
0.1F
S
I
R
SHUNT
SHUNT
380k⍀
20k⍀
+IN
V
= I
؋
R OUT
SHUNT SHUNT
–V
REF(+)
S
(SEE
TEXT)
0.1F
NC = NO CONNECT
–V
S
–3V TO –18V
Figure 29. Basic Connections
V
= 20VX/Y
− 19VREF
CM
(
)
(
)
The differential input signal, which will typically result from a
load current flowing through a small shunt resistor, is applied to
Pins 2 and 3 with the polarity shown in order to obtain a posi-
tive gain. The common-mode range on the differential input
signal can range from –270 V to +270 V and the maximum dif-
ferential range is 13 V. When configured as shown, the device
operates as a simple gain-of-one differential-to-single-ended
amplifier, the output voltage being the shunt resistance times the
shunt current. The output is measured with respect to Pins 1 and 5.
System-Level Decoupling and Grounding
The use of ground planes is recommended to minimize the
impedance of ground returns (and hence the size of dc errors).
Figure 31 shows how to work with grounding in a mixed-signal
environment, that is, with digital and analog signals present. In
order to isolate low-level analog signals from a noisy digital
environment, many data-acquisition components have separate
analog and digital ground returns. All ground pins from mixed-
signal components such as analog-to-digital converters should
be returned through the “high quality” analog ground plane.
This includes the digital ground lines of mixed-signal converters
that should also be connected to the analog ground plane. This
may seem to break the rule of keeping analog and digital grounds
separate, but in general, there is also a requirement to keep the
voltage difference between digital and analog grounds on a con-
verter as small as possible (typically <0.3 V). The increased
noise, caused by the converter’s digital return currents flowing
through the analog ground plane, will typically be negligible.
Maximum isolation between analog and digital is achieved by
connecting the ground planes back at the supplies. Note that
Figure 31, as drawn, suggests a “star” ground system for the
analog circuitry, with all ground lines being connected, in this
case, to the ADC’s analog ground. However, when ground planes
are used, it is sufficient to connect ground pins to the nearest
point on the low impedance ground plane.
Pins 1 and 5 (REF(–) and REF(+)) should be grounded for a
gain of unity and should be connected to the same low imped-
ance ground plane. Failure to do this will result in degraded
common-mode rejection. Pin 8 is a no connect pin and should
be left open.
Single Supply Operation
Figure 30 shows the connections for operating the AD629 with
a single supply. Because the output can swing to within only
about 2 V of either rail, it is necessary to apply an offset to the
output. This can be conveniently done by connecting REF(+) and
REF(–) to a low impedance reference voltage (some analog-
to-digital converters provide this voltage as an output), which is
capable of sinking current. Thus, for a single supply of 10 V,
VREF might be set to 5 V for a bipolar input signal. This would
allow the output to swing 3 V around the central 5 V reference
voltage. Alternatively, for unipolar input signals, VREF could be
set to about 2 V, allowing the output to swing from +2 V (for a 0 V
input) to within 2 V of the positive rail.
REV. A
–8–
AD629
shows some sample error voltages generated by a common-mode
voltage of 200 V dc with shunt resistors from 20 Ω to 2000 Ω.
Assuming that the shunt resistor has been selected to utilize the
full 10 V output swing of the AD629, the error voltage becomes
quite significant as RSHUNT increases.
DIGITAL
ANALOG POWER
SUPPLY
POWER SUPPLY
+5V
GND
–5V
+5V
GND
0.1F
0.1F
0.1F 0.1F
Table I. Error Resulting from Large Values of RSHUNT
(Uncompensated Circuit)
V
AGND
DGND
DD
GND
V
DD
12
+V
–V
S
S
+IN
AD7892-2
PROCESSOR
AD629
V
OUT
V
IN1
RS (⍀)
Error VOUT (V)
Error Indicated (mA)
–IN
V
REF(+)
REF(–)
IN2
20
1000
2000
0.01
0.498
1
0.5
0.498
0.5
Figure 31. Optimal Grounding Practice for a Bipolar Supply
Environment with Separate Analog and Digital Supplies
If it is desired to measure low current or current near zero in a
high common-mode environment, an external resistor equal to
the shunt resistor value may be added to the low impedance side
of the shunt resistor as shown in Figure 33.
POWER SUPPLY
+5V
GND
0.1F
0.1F
+V
S
AD629
21.1k⍀
0.1F
REF(–)
–IN
1
2
3
4
8
7
6
5
NC
+V
V
AGND DGND
ADC
R
DD
380k⍀ 380k⍀
COMP
+V
–V
S
S
V
GND
DD
+IN
0.1F
S
AD629
V
OUT
V
I
R
SHUNT
IN
SHUNT
PROCESSOR
380k⍀
20k⍀
+IN
–IN
V
REF(+)
REF(–)
V
OUT
REF
–V
REF(+)
S
Figure 32. Optimal Ground Practice in a Single Supply
Environment
0.1F
–V
S
NC = NO CONNECT
Figure 33. Compensating for Large Sense Resistors
If there is only a single power supply available, it must be shared
by both digital and analog circuitry. Figure 32 shows how to
minimize interference between the digital and analog circuitry.
In this example, the ADC’s reference is used to drive the
AD629’s REF(+) and REF(–) pins. This means that the reference
Output Filtering
A simple 2-pole low-pass Butterworth filter can be implemented
using the OP177 at the output of the AD629 to limit noise at
the output, as shown in Figure 34. Table II gives recommended
component values for various corner frequencies, along with the
peak-to-peak output noise for each case.
must be capable of sourcing and sinking a current equal to VCM
/
200 kΩ. As in the previous case, separate analog and digital
ground planes should be used (reasonably thick traces can be
used as an alternative to a digital ground plane). These ground
planes should be connected at the power supply’s ground pin.
Separate traces (or power planes) should be run from the power
supply to the supply pins of the digital and analog circuits. Ideally,
each device should have its own power supply trace, but these
can be shared by a number of devices as long as a single trace is
not used to route current to both digital and analog circuitry.
+V
S
AD629
21.1k⍀
REF(–)
1
2
3
4
8
7
6
5
+V
S
NC
C1
0.1F
0.1F
380k⍀ 380k⍀
–IN
+V
S
V
OP177
0.1F
R1
R2
C2
OUT
380k⍀
20k⍀
+IN
–V
REF(+)
S
–V
S
–V
S
Using a Large Sense Resistor
0.1F
Insertion of a large shunt resistance across the input Pins 2 and 3
will imbalance the input resistor network, introducing a common-
mode error. The magnitude of the error will depend on the
common-mode voltage and the magnitude of RSHUNT. Table I
NC = NO CONNECT
Figure 34. Filtering of Output Noise Using a 2-Pole
Butterworth Filter
Table II. Recommended Values for 2-Pole Butterworth Filter
Corner Frequency
R1
R2
C1
C2
Output Noise (p-p)
No Filter
50 kHz
5 kHz
500 Hz
50 Hz
3.2 mV
1 mV
0.32 mV
100 µV
32 µV
2.94 kΩ 1%
2.94 kΩ 1%
2.94 kΩ 1%
2.7 kΩ 10%
1.58 kΩ 1%
1.58 kΩ 1%
1.58 kΩ 1%
1.5 kΩ 10%
2.2 nF 10%
22 nF 10%
220 nF 10%
2.2 µF 20%
1 nF 10%
10 nF 10%
0.1 µF 10%
1 µF 20%
REV. A
–9–
AD629
Output Current and Buffering
+V
S
The AD629 is designed to drive loads of 2 kΩ to within 2 V of
the rails, but can deliver higher output currents at lower output
voltages (see Figure 15). If higher output current is required,
the AD629’s output should be buffered with a precision op
amp such as the OP113 as shown in Figure 35. This op amp
can swing to within 1 V of either rail while driving a load as
small as 600 Ω.
AD629
21.1k⍀
REF(–)
–IN
1
2
3
4
8
7
6
5
NC
0.1F
THERMOCOUPLE
380k⍀ 380k⍀
380k⍀
20k⍀
+IN
V
OUT
V
REF
REF(+)
+V
S
NC = NO CONNECT
AD629
21.1k⍀
REF(–)
1
2
3
4
8
7
6
5
NC
0.1F
380k⍀ 380k⍀
Figure 36. A Gain of 19 Thermocouple Amplifier
–IN
0.1F
Error Budget Analysis Example 1
380k⍀
20k⍀
+IN
In the dc application below, the 10 A output current from a
device with a high common-mode voltage (such as a power sup-
ply or current-mode amplifier) is sensed across a 1 Ω shunt
resistor (Figure 37). The common-mode voltage is 200 V, and
the resistor terminals are connected through a long pair of lead
wires located in a high-noise environment, for example, 50 Hz/
60 Hz 440 V ac power lines. The calculations in Table III
assume an induced noise level of 1 V at 60 Hz on the leads, in
addition to a full-scale dc differential voltage of 10 V. The error
budget table quantifies the contribution of each error source.
Note that the dominant error source in this example is due to
the dc common-mode voltage.
V
OP113
0.1F
OUT
REF(+)
–V
S
0.1F
–V
S
NC = NO CONNECT
Figure 35. Output Buffering Application
A Gain of 19 Differential Amplifier
While low level signals can be connected directly to the –IN and
+IN inputs of the AD629, differential input signals can also be
connected as shown in Figure 36 to give a precise gain of 19.
However, large common-mode voltages are no longer permissible.
Cold junction compensation can be implemented using a tempera-
ture sensor such as the AD590.
Table III. AD629 vs. INA117 Error Budget Analysis Example 1 (VCM = 200 V dc)
Error, ppm of FS
Error Source
AD629
INA117
AD629
INA117
ACCURACY, TA = 25°C
Initial Gain Error
Offset Voltage
(0.0005 × 10) ÷ 10 V × 106
(0.001 V ÷ 10 V) × 106
(0.0005 × 10) ÷ 10 V × 106
(0.002 V ÷ 10 V) × 106
500
100
4,480
500
200
10,000
DC CMR (Over Temperature)
(224 × 10-6 × 200 V) ÷ 10 V × 106 (500 × 10-6 × 200 V) ÷ 10 V × 106
Total Accuracy Error: 5,080
10,700
TEMPERATURE DRIFT (85°C)
Gain
10 ppm/°C × 60°C
10 ppm/°C × 60°C
(40 µV/°C × 60°C) × 106/10 V
600
120
600
240
Offset Voltage
(20 µV/°C × 60°C) × 106/10 V
Total Drift Error:
720
840
RESOLUTION
Noise, Typ, 0.01–10 Hz, µV p-p
CMR, 60 Hz
15 µV ÷ 10 V × 106
25 µV ÷ 10 V × 106
2
14
10
3
50
10
(141 × 10–6 × 1 V) ÷ 10 V × 106 (500 × 10–6 × 1 V) ÷ 10 V × 106
Nonlinearity
(10–5 × 10 V) ÷ 10 V × 106
(10–5 × 10 V) ÷ 10 V × 106
Total Resolution Error:
26
63
Total Error: 5,826
11,603
REV. A
–10–
AD629
before. Note that the same kind of power line interference can
happen as detailed in Example 1. However, the ac common-
mode component of 200 V p-p coming from the shunt is much
larger than the interference of 1 V p-p, so that this interference
component can be neglected.
OUTPUT
CURRENT
21.1k⍀
REF(–)
–IN
10 AMPS
200V DC
TO GROUND
1
2
3
4
8
7
6
5
NC
CM
380k⍀ 380k⍀
+V
0.1F
S
1⍀
SHUNT
380k⍀
20k⍀
+IN
V
OUTPUT
CURRENT
OUT
REF(+)
REF(–)
–IN
21.1k⍀
60Hz
POWER LINE
10 AMPS
؎100V AC CM
TO GROUND
–V
1
2
3
4
8
7
6
5
NC
S
AD629
0.1F
380k⍀ 380k⍀
NC = NO CONNECT
+V
S
1⍀
SHUNT
0.1F
380k⍀
20k⍀
Figure 37. Error Budget Analysis Example 1. VIN = 10 V
Full-Scale, VCM = 200 V DC. RSHUNT = 1 Ω, 1 V p-p 60 Hz
Power-Line Interference
+IN
V
OUT
REF(+)
60Hz
POWER LINE
–V
S
AD629
0.1F
Error Budget Analysis Example 2
NC = NO CONNECT
This application is similar to the previous example except that
the sensed load current is from an amplifier with an ac common-
mode component of 100 V (frequency = 500 Hz) present on
the shunt (Figure 38). All other conditions are the same as
Figure 38. Error Budget Analysis Example 2. VIN = 10 V
Full-Scale, VCM 100 V at 500 Hz, RSHUNT = 1 Ω
=
Table IV. AD629 vs. INA117 AC Error Budget Example 2 (VCM = ؎100 V @ 500 Hz)
Error, ppm of FS
Error Source
AD629
INA117
AD629
INA117
ACCURACY, TA = 25°C
Initial Gain Error
Offset Voltage
(0.0005 × 10) ÷ 10 V × 106
(0.001 V ÷ 10 V) × 106
(0.0005 × 10) ÷ 10 V × 106
(0.002 V ÷ 10 V) × 106
500
100
500
200
Total Accuracy Error:
600
700
TEMPERATURE DRIFT (85°C)
Gain
10 ppm/°C × 60°C
10 ppm/°C × 60°C
600
120
600
240
Offset Voltage
(20 µV/°C × 60°C) × 106/10 V
(40 µV/°C × 60°C) × 106/10 V
Total Drift Error:
720
840
RESOLUTION
Noise, Typ, 0.01–10 Hz, µV p-p 15 µV ÷ 10 V × 106
25 µV ÷ 10 V × 106
2
14
10
3
50
10
CMR @ 60 Hz
Nonlinearity
AC CMR @ 500 Hz
(141 × 10–6 × 1 V) ÷ 10 V × 106
(10–5 × 10 V) ÷ 10 V × 106
(500 × 10–6 × 1 V) ÷ 10 V × 106
(10–5 × 10 V) ÷ 10 V × 106
(141 × 10–6 × 200 V) ÷ 10 V × 106 (500 × 10–6 × 200 V) ÷ 10 V × 106
2,820
10,000
Total Resolution Error: 2,846
Total Error: 4,166
10,063
11,603
REV. A
–11–
AD629
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead SOIC
(SO-8)
8-Lead Plastic DIP
(N-8)
0.1968 (5.00)
0.1890 (4.80)
0.430 (10.92)
0.348 (8.84)
8
1
5
4
8
5
0.2440 (6.20)
0.2284 (5.80)
0.1574 (4.00)
0.1497 (3.80)
0.280 (7.11)
0.240 (6.10)
1
4
0.325 (8.25)
0.300 (7.62)
PIN 1
PIN 1
0.100 (2.54)
BSC
0.0196 (0.50)
0.0099 (0.25)
0.0500 (1.27)
BSC
؋
45؇ 0.060 (1.52)
0.015 (0.38)
0.0688 (1.75)
0.0532 (1.35)
0.210
(5.33)
MAX
0.195 (4.95)
0.0098 (0.25)
0.115 (2.93)
0.0040 (0.10)
8؇
0؇
0.130
(3.30)
MIN
0.0500 (1.27)
0.0160 (0.41)
0.0192 (0.49)
0.0138 (0.35)
0.0098 (0.25)
0.0075 (0.19)
0.160 (4.06)
0.115 (2.93)
SEATING
PLANE
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
0.022 (0.558) 0.070 (1.77)
0.014 (0.356) 0.045 (1.15)
REV. A
–12–
相关型号：
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