AD5669RBRUZ-2-RL7 [ADI]
Octal, 16-bit, I<sup>2</sup>C Voltage Output denseDAC with 5 ppm/°C On-Chip Reference;
| 型号： | AD5669RBRUZ-2-RL7 |
| 厂家： | 
ADI |
| 描述： | Octal, 16-bit, I<sup>2</sup>C Voltage Output denseDAC with 5 ppm/°C On-Chip Reference 光电二极管 转换器 |
| 文件： | 总32页 (文件大小：1287K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Octal, 12-/16-Bit, I2C, denseDACs
with 5 ppm/°C On-Chip Reference
Data Sheet
AD5629R/AD5669R
FEATURES
FUNCTIONAL BLOCK DIAGRAM
V
V
/V
DD
REFIN REFOUT
Low power octal DACs
AD5629R: 12 bits
AD5669R: 16 bits
AD5629R/AD5669R
1.25V/2.5V REF
BUFFER
LDAC
INPUT
REGISTER
DAC
STRING
DAC A
V
V
V
V
V
V
V
V
A
B
C
D
E
F
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
REGISTER
2.6 mm × 2.6 mm 16-ball WLCSP
4 mm × 4 mm 16-lead LFCSP and 16-lead TSSOP
On-chip 1.25 V/2.5 V, 5 ppm/°C reference
Power down to 400 nA at 5 V, 200 nA at 3 V
2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to zero scale or midscale
3 power-down functions
SCL
SDA
A0
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
INPUT
REGISTER
DAC
REGISTER
STRING
DAC C
INPUT
REGISTER
DAC
REGISTER
STRING
DAC D
INPUT
REGISTER
DAC
REGISTER
STRING
DAC E
LDAC
CLR
functions
Hardware
and
I2C-compatible serial interface supports standard (100 kHz)
and fast (400 kHz) modes
INPUT
REGISTER
DAC
REGISTER
STRING
DAC F
APPLICATIONS
INPUT
REGISTER
DAC
REGISTER
STRING
DAC G
G
H
Process control
INPUT
REGISTER
DAC
REGISTER
STRING
DAC H
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
POWER-ON RESET
POWER-DOWN LOGIC
GND
LDAC CLR
Figure 1.
GENERAL DESCRIPTION
The AD5629R/AD5669R devices are low power, octal, 12-/16-
bit, buffered voltage-output DACs. All devices are guaranteed
monotonic by design.
The parts incorporate a power-on reset circuit to ensure that
the DAC output powers up to 0 V (AD5629R-1/AD5629R-2,
AD5669R-1/AD5669R-2) or midscale (AD5629R-3/AD5669R-3)
and remains powered up at this level until a valid write takes place.
The part contains a power-down feature that reduces the current
consumption of the device to 400 nA at 5 V and provides software-
selectable output loads while in power-down mode for any or
all DAC channels.
The AD5629R/AD5669R have an on-chip reference with an
internal gain of 2. The AD5629R-1/AD5669R-1 have a 1.25 V,
5 ppm/°C reference, giving a full-scale output range of 2.5 V.
The AD5629R-2/AD5629R-3 and the AD5669R-2/AD5669R-3
have a 2.5 V 5 ppm/°C reference, giving a full-scale output range
of 5 V depending on the option selected. Devices with 1.25 V
reference selected operate from a single 2.7 V to 5.5 V supply.
Devices with 2.5 V reference selected operate from 4.5 V to 5.5 V.
The on-chip reference is off at power-up, allowing the use of an
external reference. The internal reference is enabled via a
software write.
PRODUCT HIGHLIGHTS
1. Octal, 12-/16-bit DACs.
2. On-chip 1.25 V/2.5 V, 5 ppm/°C reference.
3. Available in 16-lead LFCSP and TSSOP, and 16-ball
WLCSP.
4. Power-on reset to 0 V or midscale.
5. Power-down capability. When powered down, the DAC
typically consumes 200 nA at 3 V and 400 nA at 5 V.
Rev. E
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2010–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD5629R/AD5669R
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Resistor String............................................................................. 21
Internal Reference ...................................................................... 21
Output Amplifier........................................................................ 22
Serial Interface............................................................................ 22
Write Operation.......................................................................... 22
Read Operation........................................................................... 22
Input Shift Register .................................................................... 23
Multiple Byte Operation............................................................ 23
Internal Reference Register....................................................... 24
Power-On Reset.......................................................................... 24
Power-Down Modes .................................................................. 25
Clear Code Register ................................................................... 25
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Characteristics........................................................................ 6
I2C Timing Characteristics.......................................................... 7
Absolute Maximum Ratings............................................................ 9
ESD Caution.................................................................................. 9
Pin Configurations and Function Descriptions ......................... 10
Typical Performance Characteristics ........................................... 12
Terminology .................................................................................... 19
Theory of Operation ...................................................................... 21
Digital-to-Analog Converter (DAC) Section ......................... 21
LDAC
Function .......................................................................... 27
Power Supply Bypassing and Grounding................................ 27
Outline Dimensions....................................................................... 28
Ordering Guide .......................................................................... 30
REVISION HISTORY
9/2016—Rev. D to Rev. E
12/2010—Rev. 0 to Rev. A
Change to Read Operation Section.............................................. 22
Changes to Features, General Description, and Product
Highlights Sections............................................................................1
Changes to AD5629R Relative Accuracy Parameter, Reference
Output (1.25 V) Reference Input Range Parameter, and Reference
Output (2.5 V) Reference Input Range Parameter (Table 1).......3
Changes to Relative Accuracy Parameter, Reference Tempco
Parameter (Table 2)...........................................................................5
Changes to Output Voltage Settling Time Parameter (Table 3)..6
Changes to Table 5.............................................................................9
4/2014—Rev. C to Rev. D
Change to VOUTB, VOUTC, VOUTD, VOUTE, VOUTG, VOUTH Ball
Numbers; Table 6............................................................................ 11
2/2014—Rev. B to Rev. C
Change to Table 6 ........................................................................... 11
Changes to Figure 38, Figure 39, and Figure 40 ......................... 17
Changes to Ordering Guide .......................................................... 30
CLR
Changes to
Pin Description (Table 6)................................. 10
Added Figure 32 and Figure 33 .................................................... 15
Added Figure 46 ............................................................................. 17
Changes to Internal Reference Section........................................ 20
Changes to Power-On Reset Section ........................................... 23
Changes to Clear Code Register Section..................................... 24
Updated Outline Dimensions....................................................... 27
Changes to Ordering Guide.......................................................... 28
2/2013—Rev. A to Rev. B
Added 16-Ball WLCSP.......................................................Universal
Changes to Features Section............................................................ 1
Added Figure 5, Renumbered Sequentially ................................ 10
Moved Table 6 ................................................................................. 11
Changes to Figure 25 and Figure 26............................................. 15
Added Figure 58.............................................................................. 29
Changes to Ordering Guide .......................................................... 30
10/2010—Revision 0: Initial Version
Rev. E | Page 2 of 32
Data Sheet
AD5629R/AD5669R
SPECIFICATIONS
VDD = 4.5 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted.
Table 1.
A Grade1
Typ Max
B Grade1
Typ Max
Parameter
Min
Min
Unit
Test Conditions/Comments
STATIC PERFORMANCE2
AD5629R
Resolution
Relative Accuracy
Differential Nonlinearity
12
12
Bits
LSB
±0.25 LSB
±0.5 ±±
±0.25
±0.5 ±1
See Figure 7
Guaranteed monotonic by design
(see Figure 9)
AD5669R
Resolution
16
16
Bits
Relative Accuracy
Differential Nonlinearity
±ꢀ
±32
±1
±ꢀ
±16
±1
LSB
LSB
See Figure 6
Guaranteed monotonic by design
(see Figure ꢀ)
Zero-Code Error
Zero-Code Error Drift
Full-Scale Error
Gain Error
Gain Temperature Coefficient
Offset Error
6
±2
−0.2 −1
±1
±2.5
19
6
±2
−0.2 −1
±1
±2.5
19
mV
All 0s loaded to DAC register (see Figure 19)
All 1s loaded to DAC register (see Figure 20)
Of FSR/°C
µV/°C
% FSR
% FSR
ppm
mV
±6
±19
±6
±19
DC Power Supply Rejection
Ratio
–ꢀ0
–ꢀ0
dB
VDD ± 10%
DC Crosstalk
(External Reference)
10
10
µV
Due to full-scale output change,
RL = 2 kΩ to GND or VDD
5
10
25
5
10
25
µV/mA
µV
µV
Due to load current change
Due to powering down (per channel)
Due to full-scale output change,
RL = 2 kΩ to GND or VDD
DC Crosstalk
(Internal Reference)
10
10
µV/mA
Due to load current change
OUTPUT CHARACTERISTICS3
Output Voltage Range
0
VDD
0
VDD
V
Capacitive Load Stability
2
2
nF
nF
Ω
mA
µs
RL = ∞
RL = 2 kΩ
10
0.5
30
±
10
0.5
30
±
DC Output Impedance
Short-Circuit Current
Power-Up Time
VDD = 5 V
Coming out of power-down mode, VDD = 5 V
REFERENCE INPUTS
Reference Current
±0
50
VDD
±0
50
VDD
µA
V
kΩ
VREFIN = VDD = 5.5 V (per DAC channel)
Reference Input Range
Reference Input Impedance
REFERENCE OUTPUT (1.25 V)
Output Voltage
0
0
1±.6
1±.6
1.2±7
1.253 1.2±7
2.505 2.±95
1.253 µA
±15 ppm/°C LFCSP, TSSOP
TA = 25°C
WLCSP
Reference Input Range
±15
7.5
±5
±15
7.5
Output Impedance
REFERENCE OUTPUT (2.5 V)
Output Voltage
kΩ
2.±95
2.505 µA
ppm/°C
kΩ
TA = 25°C
Reference Input Range
Output Impedance
±15
7.5
±5
7.5
±10
Rev. E | Page 3 of 32
AD5629R/AD5669R
Data Sheet
A Grade1
Typ Max
B Grade1
Typ Max
Parameter
LOGIC INPUTS3
Min
Min
Unit
Test Conditions/Comments
Input Current
±3
0.ꢀ
±3
0.ꢀ
µA
V
V
All digital inputs
VDD = 5 V
VDD = 5 V
Input Low Voltage, VINL
Input High Voltage, VINH
Pin Capacitance
POWER REQUIREMENTS
VDD
2
2
3
3
pF
±.5
5.5
±.5
5.5
V
All digital inputs at 0 or VDD,
DAC active, excludes load current
IDD (Normal Mode)±
VDD = ±.5 V to 5.5 V
VIH = VDD and VIL = GND
Internal reference off
Internal reference on
1.3
2
1.ꢀ
2.5
1.3
2
1.ꢀ
2.5
mA
mA
IDD (All Power-Down Modes)5
VDD = ±.5 V to 5.5 V
0.±
1
0.±
1
µA
VIH = VDD and VIL = GND
1 Temperature range is −±0°C to +105°C, typical at 25°C.
2 Linearity calculated using a reduced code range of the AD5629R (Code 32 to Code ±06±) and the AD5669R (Code 512 to 65,02±). Output unloaded.
3 Guaranteed by design and characterization; not production tested.
± Interface inactive. All DACs active. DAC outputs unloaded.
5 All eight DACs powered down.
Rev. E | Page ± of 32
Data Sheet
AD5629R/AD5669R
VDD = 2.7 V to 3.6 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
A Grade1
Typ Max
B Grade1
Typ Max
Parameter
STATIC PERFORMANCE2
Min
Min
Unit
Conditions/Comments
AD5629R
Resolution
12
12
Bits
LSB
±0.25 LSB
Relative Accuracy
Differential Nonlinearity
AD5669R
±0.5 ±±
±0.25
±0.5 ±1
See Figure 7
Guaranteed monotonic by design (see Figure 9)
Resolution
16
16
Bits
Relative Accuracy
Differential Nonlinearity
Zero-Code Error
Zero-Code Error Drift
Full-Scale Error
Gain Error
Gain Temperature Coefficient
Offset Error
DC Power Supply Rejection
Ratio
±ꢀ
±32
±1
19
±ꢀ
±16
±1
19
LSB
LSB
mV
µV/°C
% FSR
% FSR
ppm
mV
See Figure 6
Guaranteed monotonic by design (see Figure ꢀ)
All 0s loaded to DAC register (see Figure 19)
6
±2
−0.2 −1
±1
±2.5
6
±2
−0.2 −1
±1
±2.5
All 1s loaded to DAC register (see Figure 20)
Of FSR/°C
VDD ± 10%
±6
–ꢀ0
±19
±6
–ꢀ0
±19
dB
DC Crosstalk
(External Reference)
10
10
µV
Due to full-scale output change,
RL = 2 kΩ to GND or VDD
5
10
25
5
10
25
µV/mA
µV
µV
Due to load current change
Due to powering down (per channel)
Due to full-scale output change,
RL = 2 kΩ to GND or VDD
DC Crosstalk
(Internal Reference)
10
10
µV/mA
Due to load current change
OUTPUT CHARACTERISTICS3
Output Voltage Range
0
VDD
0
VDD
V
Capacitive Load Stability
2
2
nF
nF
Ω
mA
µs
RL = ∞
RL = 2 kΩ
10
0.5
30
±
10
0.5
30
±
DC Output Impedance
Short-Circuit Current
Power-Up Time
VDD = 3 V
Coming out of power-down mode, VDD = 3 V
REFERENCE INPUTS
Reference Current
Reference Input Range
Reference Input Impedance
REFERENCE OUTPUT
Output Voltage
±0
50
VDD
±0
50
VDD
µA
kΩ
VREFIN = VDD = 3.6 V (per DAC channel)
0
0
1±.6
1±.6
AD5629R/AD5669R
Reference Tempco3
1.2±7
1.253 1.2±7
1.253
V
TA = 25°C
±15
7.5
ppm/°C LFCSP, TSSOP
±5
±15
7.5
±15
WLCSP
kΩ
Reference Output Impedance
LOGIC INPUTS3
Input Current
±3
0.ꢀ
2
±3
0.ꢀ
µA
V
V
All digital inputs
VDD = 3 V
VDD = 3 V
Input Low Voltage, VINL
Input High Voltage, VINH
Pin Capacitance
2
3
3
pF
Rev. E | Page 5 of 32
AD5629R/AD5669R
Data Sheet
A Grade1
Typ Max
B Grade1
Typ Max
Parameter
Min
Min
Unit
Conditions/Comments
POWER REQUIREMENTS
VDD
2.7
3.6
2.7
3.6
V
All digital inputs at 0 or VDD,
DAC active, excludes load current
VIH = VDD and VIL = GND
Internal reference off
IDD (Normal Mode)±
VDD = 2.7 V to 3.6 V
1.0
1.ꢀ
1.5
2.25
1.0
1.7
1.5
2.25
mA
mA
Internal reference on
IDD (All Power-Down Modes)5
VDD = 2.7 V to 3.6 V
0.2
1
0.2
1
µA
VIH = VDD and VIL = GND
1 Temperature range is −±0°C to +105°C, typical at 25°C.
2 Linearity calculated using a reduced code range of the AD5629R (Code 32 to Code ±06±) and the AD5669R (Code 512 to 65,02±). Output unloaded.
3 Guaranteed by design and characterization; not production tested.
± Interface inactive. All DACs active. DAC outputs unloaded.
5 All eight DACs powered down.
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN = VDD. All specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter 1, 2
Min
Typ
2.5
1.2
±
Max
Unit
µs
Conditions/Comments 3
Output Voltage Settling Time
Slew Rate
Digital-to-Analog Glitch Impulse
7
¼ to ¾ scale settling to ±2 LSB
V/µs
nV-s
nV-s
nV-s
dB
nV-s
nV-s
nV-s
kHz
1 LSB change around major carry (see Figure 35)
From Code 5990± to Code 59903
19
Digital Feedthrough
Reference Feedthrough
Digital Crosstalk
0.1
−90
0.2
0.±
0.ꢀ
320
−ꢀ0
120
100
VREFIN = 2 V ± 0.1 V p-p, frequency = 10 Hz to 20 MHz
Analog Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
Output Noise Spectral Density
VREFIN = 2 V ± 0.2 V p-p
VREFIN = 2 V ± 0.1 V p-p, frequency = 10 kHz
DAC code = 0xꢀ±00, 1 kHz
dB
nV/√Hz
nV/√Hz
DAC code = 0xꢀ±00, 10 kHz
1 Guaranteed by design and characterization; not production tested.
2 See the Terminology section.
3 Temperature range is −±0°C to +105°C, typical at 25°C.
Rev. E | Page 6 of 32
Data Sheet
AD5629R/AD5669R
I2C TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, fSCL = 400 kHz, unless otherwise noted.
Table 4.
Parameter Conditions
Min
Max
100
±00
Unit
kHz
kHz
μs
μs
μs
μs
ns
ns
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
ns
ns
ns
ns
ns
ns
Description
1
fSCL
t1
Standard mode
Fast mode
Standard mode
Fast mode
Serial clock frequency
±
tHIGH, SCL high time
tLOW, SCL low time
0.6
±.7
1.3
250
100
0
t2
Standard mode
Fast mode
t3
Standard mode
Fast mode
tSU;DAT, data setup time
tHD;DAT, data hold time
t±
Standard mode
Fast mode
3.±5
0.9
0
t5
Standard mode
Fast mode
±.7
0.6
±
0.6
±.7
1.3
±
tSU;STA, setup time for a repeated start condition
tHD;STA, hold time (repeated) start condition
tBUF, bus-free time between a stop and a start condition
tSU;STO, setup time for a stop condition
tRDA, rise time of SDA signal
t6
Standard mode
Fast mode
t7
Standard mode
Fast mode
tꢀ
Standard mode
Fast mode
0.6
t9
Standard mode
Fast mode
1000
300
300
300
1000
300
t10
t11
t11A
Standard mode
Fast mode
Standard mode
Fast mode
tFDA, fall time of SDA signal
tRCL, rise time of SCL signal
Standard mode
1000
tRCL1, rise time of SCL signal after a repeated start condition and
after an acknowledge bit
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
300
300
300
ns
ns
ns
ns
ns
ns
t12
t13
t1±
tFCL, fall time of SCL signal
LDAC pulse width low
10
10
300
Falling edge of ninth SCL clock pulse of last byte of a valid write to
the LDAC falling edge
Fast mode
Standard mode
Fast mode
300
20
20
0
ns
ns
ns
ns
t15
CLR pulse width low
2
tSP
Fast mode
50
Pulse width of spike suppressed
1 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on the EMC
behavior of the part.
2 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode or less than 10 ns for high speed mode.
Rev. E | Page 7 of 32
AD5629R/AD5669R
Data Sheet
t11
t12
t6
t2
t6
SCL
t1
t3
t5
t10
t8
t4
t9
SDA
t7
P
S
S
P
t14
t13
LDAC*
CLR
t15
*ASYNCHRONOUS LDAC UPDATE MODE.
Figure 2. Serial Write Operation
Rev. E | Page 8 of 32
Data Sheet
AD5629R/AD5669R
ABSOLUTE MAXIMUM RATINGS
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
TA = 25°C, unless otherwise noted.
Table 5.
Parameter
Rating
VDD to GND
−0.3 V to +7 V
Digital Input Voltage to GND
VOUT to GND
VREFIN/VREFOUT to GND
Operating Temperature Range
Industrial
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
ESD CAUTION
−±0°C to +105°C
−65°C to +150°C
+150°C
Storage Temperature Range
Junction Temperature (TJ MAX
)
Power Dissipation
(TJ MAX − TA)/θJA
Thermal Impedance, θJA
16-Lead TSSOP (±-Layer Board)
16-Lead LFCSP (±-Layer Board)
Reflow Soldering Peak Temperature
Pb Free
112.6°C/W
30.±°C/W
260°C
Rev. E | Page 9 of 32
AD5629R/AD5669R
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AD5629R/AD5669R
V
1
2
3
4
12 GND
DD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
LDAC
A0
SCL
V
V
A
C
11
10
9
V
V
B
D
OUT
OUT
OUT
TOP VIEW
(Not to Scale)
SDA
GND
OUT
V
DD
AD5629R/
AD5669R
TOP VIEW
(Not to Scale)
V
E
V
F
OUT
OUT
V
V
A
C
V
V
V
V
B
D
F
OUT
OUT
OUT
OUT
OUT
OUT
V
E
OUT
V
G
H
OUT
V
/V
REFIN REFOUT
CLR
NOTES
1. EXPOSED PAD MUST BE TIED TO GND.
Figure 4. 16-Lead TSSOP (RU-16)
Figure 3. 16-Lead LFCSP (CP-16-17)
BALL A1
INDICATOR
1
2
3
4
GND SCL
SDA
A0
A
V
V
B LDAC
V
V
A
OUT
OUT
DD
B
C
D
F V
D V
E V
C
G
OUT
OUT
OUT
OUT
OUT
V
H
CLR
V
V
REF
OUT
TOP VIEW
(BALL SIDE DOWN)
Not to Scale
Figure 5. 16-Ball WLCSP
Rev. E | Page 10 of 32
Data Sheet
AD5629R/AD5669R
Table 6. Pin Function Descriptions
Pin No.
LFCSP
TSSOP
WLCSP
Mnemonic
Description
15
1
B2
LDAC
Pulsing this pin low allows any or all DAC registers to be updated if the input registers
have new data. This allows all DAC outputs to simultaneously update. Alternatively,
this pin can be tied permanently low.
16
1
2
3
A±
B3
A0
VDD
Address Input. Sets the least significant bit of the 7-bit slave address.
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V. Decouple the
supply with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
2
3
±
5
6
±
5
6
7
ꢀ
B±
C±
C3
D±
D3
VOUT
VOUT
VOUT
VOUT
A
C
E
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation.
The AD5629R/AD5669R have a common pin for reference input and reference
output. When using the internal reference, this is the reference output pin. When
using an external reference, this is the reference input pin. The default for this pin is
as a reference input.
G
VREFIN/VREFOUT
7
9
D2
CLR
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all
LDAC pulses are ignored. When CLR is activated, the input register and the DAC
register are updated with the data contained in the CLR code register—zero scale,
midscale, or full scale. The default setting clears the output to 0 V.
ꢀ
9
10
11
12
13
10
11
12
13
1±
15
D1
C1
C2
B1
A1
A3
VOUT
VOUT
VOUT
VOUT
GND
SDA
H
F
D
B
Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Parts.
Serial Data Input. This is used in conjunction with the SCL line to clock data into or
out of the 32-bit input shift register. It is a bidirectional, open-drain data line that
should be pulled to the supply with an external pull-up resistor.
1±
17
16
A2
SCL
Serial Clock Line. This is used in conjunction with the SDA line to clock data into or
out of the 32-bit input shift register.
The exposed pad must be tied to GND.
N/A
N/A
Exposed Pad
(EPAD)
Rev. E | Page 11 of 32
AD5629R/AD5669R
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
10
0.20
0.15
0.10
0.05
0
V
= 5V
V
= 5V
DD
EXT REF = 5V
= 25°C
DD
EXT REF = 5V
= 25°C
8
6
T
T
A
A
4
2
0
–2
–4
–6
–8
–10
–0.05
–0.10
–0.15
–0.20
0
0
0
10k
20k
30k
CODES
40k
50k
60k 65535
0
500
1000 1500 2000 2500 3000 3500
CODES
4095
Figure 6. INL AD5669R—External Reference
Figure 9. DNL AD5629R—External Reference
1.0
0.8
10
5
V
= 5V
V
= 5V
DD
EXT REF = 5V
= 25°C
DD
INT REF = 2.5V
= 25°C
T
T
A
A
0.6
0.4
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–5
–10
500
1000 1500 2000 2500 3000 3500
CODES
4095
0
10k
20k
30k
CODES
40k
50k
60k 65535
Figure 7. INL AD5629R—External Reference
Figure 10. INL AD5669R-2—Internal Reference
1.0
0.8
1.0
0.5
V
= 5V
EXT REF = 5V
= 25°C
V
= 5V
DD
DD
INT REF = 2.5V
= 25°C
T
T
A
A
0.6
0.4
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.5
–1.0
10k
20k
30k
CODES
40k
50k
60k 65535
0
500
1000 1500 2000 2500 3000 3500
CODES
4095
Figure 8. DNL AD5669R—External Reference
Figure 11. INL AD5629R-2—Internal Reference
Rev. E | Page 12 of 32
Data Sheet
AD5629R/AD5669R
1.0
1.0
0.5
V
= 5V
V
= 3V
DD
INT REF = 2.5V
= 25°C
DD
INT REF = 1.25V
T = 25°C
A
T
A
0.5
0
0
–0.5
–1.0
–0.5
–1.0
0
10k
20k
30k
CODES
40k
50k
60k 65535
0
500
1000 1500 2000 2500 3000 3500
CODES
4095
Figure 12. DNL AD5669R-2—Internal Reference
Figure 15. INL AD5629R-1—Internal Reference
0.20
0.15
0.10
0.05
0
1.0
0.5
V
= 5V
DD
INT REF = 2.5V
= 25°C
V
= 3V
DD
INT REF = 1.25V
= 25°C
T
A
T
A
0
–0.05
–0.10
–0.15
–0.20
–0.5
–1.0
0
500
1000 1500 2000 2500 3000 3500
CODES
4095
0
10k
20k
30k
CODES
40k
50k
60k 65535
Figure 13. DNL AD5629R-2— Internal Reference
Figure 16. DNL AD5669R-1—Internal Reference
10
8
0.20
0.15
0.10
0.05
0
V
= 3V
V
= 3V
DD
INT REF = 1.25V
= 25°C
DD
INT REF = 1.25V
T = 25°C
A
T
A
6
4
2
0
–2
–4
–6
–8
–10
–0.05
–0.10
–0.15
–0.20
0
10k
20k
30k
CODES
40k
50k
60k 65535
0
500
1000 1500 2000 2500 3000 3500
CODES
4095
Figure 14. INL AD5669R-1—Internal Reference
Figure 17. DNL AD5629R-1—Internal Reference
Rev. E | Page 13 of 32
AD5629R/AD5669R
Data Sheet
0
1.95
1.90
1.85
1.80
1.75
1.70
1.65
1.60
1.55
V
= 5V
DD
T
= 25°C
A
–0.05
–0.10
–0.15
–0.20
–0.25
–0.30
OFFSET ERROR
FULL-SCALE ERROR
GAIN ERROR
ZERO-CODE ERROR
–40 –25 –10
5
20
35
50
65
80
95 110 125
2.7
3.1
3.5
3.9
4.3
(V)
4.7
5.1
5.5
TEMPERATURE (°C)
V
DD
Figure 18. Gain Error and Full-Scale Error vs. Temperature
Figure 21. Zero-Code Error and Offset Error vs. Supply Voltage
21
18
15
12
9
6
V
= 5V
DD
5
4
3
2
1
0
OFFSET ERROR
ZERO-CODE ERROR
6
3
0
–40 –25 –10
5
20
35
50
65
80
95 110 125
0.85
0.90
0.95
1.00
1.05
I
WITH EXTERNAL REFERENCE (mA)
TEMPERATURE (°C)
DD
Figure 22. IDD Histogram with External Reference
Figure 19. Zero-Code Error and Offset Error vs. Temperature
18
–0.16
–0.17
–0.18
–0.19
–0.20
–0.21
–0.22
–0.23
–0.24
–0.25
–0.26
T
= 25°C
A
FULL-SCALE ERROR
16
14
12
10
8
6
4
GAIN ERROR
2
0
2.7
3.1
3.5
3.9
4.3
(V)
4.7
5.1
5.5
1.65
1.70
1.75
1.80
1.85
1.90
I
WITH INTERNAL REFERENCE (mA)
V
DD
DD
Figure 23. IDD Histogram with Internal Reference
Figure 20. Gain Error and Full-Scale Error vs. Supply Voltage
Rev. E | Page 14 of 32
Data Sheet
AD5629R/AD5669R
0.4
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
T = 25°C
A
T
= 25°C
A
0.3
0.2
V
= 5V
DD
0.1
V
= 3V, INT REF = 1.25V
DD
0
V
= 3V
DD
–0.1
–0.2
–0.3
–0.4
–0.5
V
= 5V, INT REF = 2.5V
DD
–10
–8
–6
–4
–2
0
2
4
6
8
10
0.03
0.03
0
10k
20k
30k
40k
50k
60k
SOURCE/SINK CURRENT (mA)
DIGITAL CODES (Decimal)
Figure 24. Headroom at Rails vs. Source and Sink
Figure 27. Supply Current vs. Code
6
5
2.0
V
= 5V
DD
T = 25°C
A
INT REF = 2.5V
T
FULL SCALE
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
= 25°C
A
4
3/4 SCALE
V
V
= 5.5V
DD
3
MIDSCALE
1/4 SCALE
= 3.6V
DD
2
1
0
ZERO CODE
–1
–0.03
–0.02
–0.01
0
0.01
0.02
–40 –25 –10
5
20
35
50
65
80
95 110 125
SOURCE AND SINK CURRENT (A)
TEMPERATURE (°C)
Figure 25. AD5669R-2 Source and Sink Capability
Figure 28. Supply Current vs. Temperature
1.48
1.46
1.44
1.42
1.40
1.38
1.36
1.34
4.0
T
= 25°C
V
= 3V
A
DD
INT REF = 1.25V
T
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
= 25°C
A
FULL SCALE
3/4 SCALE
MIDSCALE
1/4 SCALE
ZERO CODE
–0.5
–1.0
2.7
3.1
3.5
3.9
4.3
(V)
4.7
5.1
5.5
–0.03
–0.02
–0.01
0
0.01
0.02
V
SOURCE AND SINK CURRENT (A)
DD
Figure 26. AD5669R-1 Source and Sink Capability
Figure 29. Supply Current vs. Supply Voltage
Rev. E | Page 15 of 32
AD5629R/AD5669R
Data Sheet
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
= 5V
DD
EXT REF = 5V
= 25°C
2.3
T
= 25°C
A
T
A
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
V
DD
V
= 5V
DD
V
A
OUT
V
= 3V
DD
–0.5
–0.0010
–0.0006
–0.0002
0.0002
0.0006
0.0010
TIME (s)
0
0.5
1.0
1.5
2.0
2.5
3.0
(V)
3.5
4.0
4.5
5.0
V
LOGIC
Figure 30. Supply Current vs. Logic Input Voltage
Figure 33. Power-On Reset to Midscale
5.5
TH
24 CLK RISING EDGE
6
V
= 5V
DD
EXT REF = 5V
= 25°C
V
= 5V
DD
EXT REF = 5V
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
T
A
T
= 25°C
A
5
4
3
2
1
0
V
A
OUT
–0.5
–10
–5
0
5
10
–2
0
2
4
6
8
TIME (µs)
TIME (µs)
Figure 31. Full-Scale Settling Time, 5 V
Figure 34. Exiting Power-Down to Midscale
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
= 5V
DD
T
V
= 5V
DD
EXT REF = 5V
= 25°C
EXT REF = 5V
T
= 25°C
A
T
A
V
DD
V
A
OUT
3
TH
24 CLK RISING EDGE
V
A
OUT
4
–0.5
–0.0010
–0.0006
–0.0002
0.0002
0.0006
0.0010
M400ns
17.0%
A
CH4
1.50V
B
CH3 10.0mV
CH4 5.0V
T
TIME (s)
W
Figure 32. Power-On Reset to 0 V
Figure 35. Digital-to-Analog Glitch Impulse (Negative)
Rev. E | Page 16 of 32
Data Sheet
AD5629R/AD5669R
20
15
0.0010
EXT REF = 2.5V
DAC CODE = 0xFF00
V
= 5V
DD
EXT REF = 5V
= 25°C
T
A
0.0005
0
10
5
0
–0.0005
–0.0010
–0.0015
–5
–10
–15
–20
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
10
TIME (µs)
TIME (s)
Figure 36. Analog Crosstalk
Figure 39. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference
0.0020
0.0015
0.0010
0.0005
0
20
V
= 5V
INT REF = 1.25V
DAC CODE = 0xFF00
DD
EXT REF = 5V
= 25°C
15
T
A
10
5
0
–5
–0.0005
–0.0010
–0.0015
–10
–15
–20
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
9
10
TIME (µs)
TIME (s)
Figure 37. DAC-to-DAC Crosstalk
Figure 40. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference
6
800
V
= 5.5V
V
= 5.5V
DD
DAC CODE = 0x8400
DD
EXT REF = 5V
700
600
500
400
300
200
100
0
DAC CODE = 0xFF00
4
2
0
V
= 2.5V
REF
–2
–4
–6
–8
V
= 1.25V
REF
100
1k
10k
100k
1M
0
1
2
3
4
5
6
7
8
9
10
FREQUENCY (Hz)
TIME (s)
Figure 41. Noise Spectral Density, Internal Reference
Figure 38. 0.1 Hz to 10 Hz Output Noise Plot, External Reference
Rev. E | Page 17 of 32
AD5629R/AD5669R
Data Sheet
0
10
0
V
= 5.5V
DD
EXT REF = 5V
= 25°C
T
–20
–40
A
V
= 2V ± 0.1V p-p
REF
FREQUENCY = 10kHz
–10
–20
–30
–40
–50
–60
–70
–80
–60
–80
CH A
CH B
CH C
CH D
CH E
CH F
CH G
CH H
–3dB
–100
–120
–140
V
= 5.5V
DD
EXT REF = 5V
= 25°C
T
A
V
= 2V ± 0.2V p-p
REF
0
2000
4000
6000
8000
10,000
10
100
1k
1k0
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 42. Total Harmonic Distortion
Figure 45. Multiplying Bandwidth
1.2510
1.2508
1.2506
1.2504
1.2502
1.2500
1.2498
1.2496
1.2494
1.2492
1.2490
V
= 5.5V
DD
9
8
7
6
5
4
3
2
1
0
T
= 25°C
A
V
= EXTERNAL REFERENCE = 5V
DD
V
= EXTERNAL REFERENCE = 3V
DD
–40
25
105
TEMPERATURE (°C)
0
1
2
3
4
5
6
7
8
9
10
CAPACITIVE LOAD (nF)
Figure 43. Settling Time vs. Capacitive Load
Figure 46. 1.25 V Reference Temperature Coefficient vs. Temperature
2.503
2.502
2.501
2.500
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
EXT REF = 5V
2.499
2.498
2.497
2.496
2.495
V
A
OUT
CLR PULSE
105
25
–40
–0.5
–10
TEMPERATURE (°C)
–5
0
5
10
TIME (µs)
CLR
Figure 44. Hardware
Figure 47. 2.5 V Reference Temperature Coefficient vs. Temperature
Rev. E | Page 18 of 32
Data Sheet
AD5629R/AD5669R
TERMINOLOGY
Digital-to-Analog Glitch Impulse
Relative Accuracy
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s and
is measured when the digital input code is changed by 1 LSB at
the major carry transition (0x7FFF to 0x8000). Figure 35 shows
a typical digital-to-analog glitch impulse plot.
For the DAC, relative accuracy, or integral nonlinearity (INL), is
a measure of the maximum deviation in LSBs from a straight line
passing through the endpoints of the DAC transfer function.
Figure 6, Figure 7, Figure 10, Figure 11, Figure 14, and Figure 15
show plots of typical INL vs. code.
Differential Nonlinearity
DC Power Supply Rejection Ratio (PSRR)
Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of 1 LSB
maximum ensures monotonicity. This DAC is guaranteed
monotonic by design. Figure 8, Figure 9, Figure 12, Figure 13,
Figure 16, and Figure 17 show plots of typical DNL vs. code.
PSRR indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUT to
a change in VDD for full-scale output of the DAC. VREF is held at
2 V, and VDD is varied 10%. It is measured in decibels.
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is measured
with a full-scale output change on one DAC (or soft power-down
and power-up) while monitoring another DAC kept at midscale.
It is expressed in microvolts.
Offset Error
Offset error is a measure of the difference between the actual
V
OUT and the ideal VOUT, expressed in millivolts in the linear
region of the transfer function. Offset error is measured on the
AD5669R between Code 512 and Code 65024 loaded into the
DAC register. It can be negative or positive and is expressed in
millivolts.
DC crosstalk due to load current change is a measure of the
impact that a change in load current on one DAC has on another
DAC kept at midscale. It is expressed in microvolts per milliamp.
Zero-Code Error
Zero-code error is a measure of the output error when zero
code (0x0000) is loaded into the DAC register. Ideally, the
output should be 0 V. The zero-code error is always positive
because the output of the DAC cannot go below 0 V. It is due to
a combination of the offset errors in the DAC and output
amplifier. Zero-code error is expressed in millivolts. Figure 19
shows a plot of typical zero-code error vs. temperature.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of a DAC from the digital input pins of the
device, but is measured when the DAC is not being written to. It
is specified in nV-s and measured with a full-scale change on
the digital input pins, that is, from all 0s to all 1s or vice versa.
Digital Crosstalk
Gain Error
Digital crosstalk is the glitch impulse transferred to the output
of one DAC at midscale in response to a full-scale code change
(all 0s to all 1s or vice versa) in the input register of another DAC.
It is measured in standalone mode and is expressed in nV-s.
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal, expressed as a percentage of the full-scale range.
Zero-Code Error Drift
Analog Crosstalk
Zero-code error drift is a measure of the change in zero-code
error with a change in temperature. It is expressed in µV/°C.
Analog crosstalk is the glitch impulse transferred to the output
of one DAC due to a change in the output of another DAC. It is
measured by loading one of the input registers with a full-scale
Gain Error Drift
LDAC
code change (all 0s to all 1s or vice versa) while keeping
Gain error drift is a measure of the change in gain error with
changes in temperature. It is expressed in (ppm of full-scale
range)/°C.
LDAC
high and then pulsing
low and monitoring the output of
the DAC whose digital code has not changed. The area of the
glitch is expressed in nV-s.
Full-Scale Error
Full-scale error is a measure of the output error when full-scale
code (0xFFFF) is loaded into the DAC register. Ideally, the
output should be VREF − 1 LSB. Full-scale error is expressed as
a percentage of the full-scale range. Figure 18 shows a plot of
typical full-scale error vs. temperature.
Rev. E | Page 19 of 32
AD5629R/AD5669R
Data Sheet
DAC-to-DAC Crosstalk
Total Harmonic Distortion (THD)
DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
output change of another DAC. This includes both digital and
analog crosstalk. It is measured by loading one of the DACs
with a full-scale code change (all 0s to all 1s or vice versa) with
Total harmonic distortion is the difference between an ideal
sine wave and its attenuated version using the DAC. The sine
wave is used as the reference for the DAC, and the THD is a
measure of the harmonics present on the DAC output. It is
measured in decibels.
LDAC
low and monitoring the output of another DAC. The
energy of the glitch is expressed in nV-s.
Multiplying Bandwidth
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.
Rev. E | Page 20 of 32
Data Sheet
AD5629R/AD5669R
THEORY OF OPERATION
DIGITAL-TO-ANALOG CONVERTER (DAC) SECTION
RESISTOR STRING
The AD5629R/AD5669R are fabricated on a CMOS process.
The architecture consists of a string of DACs followed by an
output buffer amplifier. Each part includes an internal
1.25 V/2.5 V, 5 ppm/°C reference with an internal gain of 2.
Figure 48 and Figure 49 show block diagrams of the DAC
architecture.
The resistor string section is shown in Figure 50. It is simply a
string of resistors, each of value R. The code loaded into the
DAC register determines at which node on the string the
voltage is tapped off to be fed into the output amplifier. The
voltage is tapped off by closing one of the switches connecting
the string to the amplifier. Because it is a string of resistors, it
is guaranteed monotonic.
V
/V
REFIN REFOUT
R
INTERNAL
REFERENCE
1
OUTPUT
AMPLIFIER
GAIN = ×2
REF (+)
R
DAC
REGISTER
RESISTOR
STRING
V
OUT
REF (–)
TO OUTPUT
R
AMPLIFIER
1
CAN BE OVERDRIVEN
BY V .
/V
REFIN REFOUT
GND
Figure 48. DAC Architecture for Internal Reference Configuration
R
R
V
/V
REFIN REFOUT
REF
BUFFER
R
R
OUTPUT
AMPLIFIER
GAIN = ×2
Figure 50. Resistor String
REF (+)
INTERNAL REFERENCE
RESISTOR
STRING
V
OUT
The AD5629R/AD5669R have an on-chip reference with an
internal gain of 2. The AD5629R-1/AD5669R-1 have a 1.25 V,
5 ppm/°C reference, giving a full-scale output of 2.5 V or the
AD5629R-2/AD5629R-3/AD5669R-2/AD5669R-3 have a 2.5 V,
5 ppm/°C reference, working between a supply from 4.5 V to
5.5 V giving a full-scale output of 5 V. The on-board reference
is off at power-up, allowing the use of an external reference. The
internal reference is enabled via a write to the control register
(see Table 8).
REF (–)
GND
Figure 49. DAC Architecture for External Reference Configuration
Because the input coding to the DAC is straight binary, the ideal
output voltage when using an external reference is given by
D
VOUT VREFIN
2N
The internal reference associated with each part is available at
the VREFOUT pin. A buffer is required if the reference output is
used to drive external loads. When using the internal reference,
it is recommended that a 100 nF capacitor be placed between
the reference output and GND for reference stability.
The ideal output voltage when using the internal reference is
given by
D
VOUT 2VREFOUT
2N
Individual channel power-down is not supported while using
the internal reference.
where:
D = decimal equivalent of the binary code that is loaded to the
DAC register as follows:
0 to 4095 for AD5629R (12 bits).
0 to 65,535 for AD5669R (16 bits).
N = the DAC resolution.
Rev. E | Page 21 of 32
AD5629R/AD5669R
Data Sheet
address corresponding to the transmitted address responds
by pulling SDA low during the ninth clock pulse (this is
termed the acknowledge bit). At this stage, all other devices
on the bus remain idle while the selected device waits for
data to be written to or read from its shift register.
2. Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge
bit). The transitions on the SDA line must occur during
the low period of SCL and remain stable during the high
period of SCL.
3. When all data bits have been read or written, a stop
condition is established. In write mode, the master pulls
the SDA line high during the 10th clock pulse to establish
a stop condition. In read mode, the master issues a no
acknowledge for the ninth clock pulse (that is, the SDA
line remains high). The master brings the SDA line low
before the 10th clock pulse and then high during the 10th
clock pulse to establish a stop condition.
OUTPUT AMPLIFIER
The output buffer amplifier can generate rail-to-rail voltages
on its output, which gives an output range of 0 V to VDD. The
amplifier is capable of driving a load of 2 kΩ in parallel with
1000 pF to GND. The source and sink capabilities of the output
amplifier can be seen in Figure 25 and Figure 26. The slew rate
is 1.5 V/μs with a ¼ to ¾ scale settling time of 10 μs.
SERIAL INTERFACE
The AD5629R/AD5669R have 2-wire I2C-compatible serial
interfaces (refer to The I2C-Bus Specification, Version 2.1,
January 2000, available from Philips Semiconductor). The
AD5629R/AD5669R can be connected to an I2C bus as a slave
device under the control of a master device. See Figure 2 for a
timing diagram of a typical write sequence.
The AD5629R/AD5669R support standard (100 kHz) and fast
(400 kHz) modes. High speed operation is only available on
selected models. See the Ordering Guide for a full list of
models. Support is not provided for 10-bit addressing and
general call addressing.
WRITE OPERATION
When writing to the AD5629R/AD5669R, the user must begin
The AD5629R/AD5669R each have a 7-bit slave address.
The parts have a slave address whose five MSBs are 10101,
and the two LSBs are set by the state of the A0 address pin,
which determines the state of the A0 and A1 address bits.
W
with a start command followed by an address byte (R/ = 0),
after which the DAC acknowledges that it is prepared to receive
data by pulling SDA low. The AD5629R/AD5669R require two
bytes of data for the DAC and a command byte that controls
various DAC functions. Three bytes of data must, therefore, be
written to the DAC, the command byte followed by the most
significant data byte and the least significant data byte, as shown in
Figure 51. After these data bytes are acknowledged by the
AD5629R/AD5669R, a stop condition follows.
The facility to make hardwired changes to the A0 pin allows the
user to incorporate up to three of these devices on one bus, as
outlined in Table 7.
Table 7. ADDR Pin Settings
A0 Pin Connection
A1
0
A0
0
READ OPERATION
VDD
NC
GND
1
1
0
1
When reading data back from the AD5629R/AD5669R, the
user begins with a start command followed by an address byte
W
(R/ = 1), after which the DAC acknowledges that it is prepared
The 2-wire serial bus protocol operates as follows:
to transmit data by pulling SDA low. Three bytes of data are then
read from the DAC, the first two of which are both acknowledged
by the master as shown in Figure 52. A stop condition follows.
1. The master initiates data transfer by establishing a start
condition when a high-to-low transition on the SDA line
occurs while SCL is high. The following byte is the address
byte, which consists of the 7-bit slave address. The slave
1
9
1
9
SCL
1
0
1
0
1
A1
A0
R/W
ACK. BY
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16
SDA
ACK. BY
START BY
MASTER
AD5629R/AD5669R
AD5629R/AD5669R
FRAME 1
SLAVE ADDRESS
FRAME 2
COMMAND BYTE
1
9
1
9
SCL
(CONTINUED)
SDA
(CONTINUED)
DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB7
DB6 DB5 DB4
DB3
DB2
DB1
DB0
DB8
STOP BY
MASTER
ACK. BY
AD5629R/AD5669R
ACK. BY
AD5629R/AD5669R
FRAME 3
MOST SIGNIFICANT
DATA BYTE
FRAME 4
LEAST SIGNIFICANT
DATA BYTE
Figure 51. I2C Write Operation
Rev. E | Page 22 of 32
Data Sheet
AD5629R/AD5669R
1
9
1
9
SCL
1
0
1
0
1
A1
A0
R/W
ACK. BY
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16
SDA
ACK. BY
MASTER
START BY
MASTER
AD5629R/AD5669R
FRAME 1
SLAVE ADDRESS
FRAME 2
COMMAND BYTE
1
9
1
9
SCL
(CONTINUED)
SDA
(CONTINUED)
DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB7
DB6 DB5 DB4
DB3
DB2
DB1
DB0
DB8
STOP BY
MASTER
ACK. BY
MASTER
NO ACK.
FRAME 3
MOST SIGNIFICANT
DATA BYTE
FRAME 4
LEAST SIGNIFICANT
DATA BYTE
Figure 52. I2C Read Operation
Table 8. Command Definitions
Command
INPUT SHIFT REGISTER
The input shift register is 24 bits wide. Data is loaded into the
device as a 24-bit word under the control of a serial clock input,
SCL. The input register contents for this operation is shown in
Figure 53 and Figure 54. The eight MSBs make up the command
byte. DB23 to DB20 are the command bits, C3, C2, C1, and C0,
that control the mode of operation of the device (see Table 9 for
details). The last four bits of the first byte are the address bits,
A3, A2, A1, and A0, (see Table 9 for details). The rest of the bits
are the 16-/12-bit data-word.
C3 C2 C1 C0 Description
0
0
0
0
0
0
0
0
1
0
1
0
Write to Input Register n
Update DAC Register n
Write to Input Register n; update all
(software LDAC)
0
0
0
0
0
1
1
1
–
1
0
1
1
1
1
0
0
0
–
1
1
0
0
1
1
0
0
1
–
1
1
0
1
0
1
0
1
0
–
1
Write to and update DAC Channel n
Power down/power up DAC
Load clear code register
Load LDAC register
The AD5669R data-word comprises the 16-bit input code (see
Figure 53) while the AD5629R data word is comprised of 12-
bits followed by four don’t cares (see Figure 54).
Reset (power-on reset)
Set up internal REF register
Enable multiple byte mode
Reserved
Reserved
Reserved
MULTIPLE BYTE OPERATION
Multiple byte operation is supported on the AD5629R/AD5669R.
Command 1001 is reserved for multiple byte operation (see
Table 8) A 2-byte operation is useful for applications that
require fast DAC updating and do not need to change the
command byte. The S bit (DB22) in the command register
can be set to 1 for the 2-byte mode of operation. For standard
3-byte and 4-byte operation, the S bit (DB22) in the command
byte should be set to 0.
Table 9. Address Commands
Address (n)
A3
0
A2
0
A1
0
A0
0
Selected DAC Channel
DAC A
0
0
0
1
DAC B
0
0
1
0
DAC C
0
0
1
1
DAC D
0
1
0
0
DAC E
0
1
0
1
DAC F
0
1
1
0
DAC G
0
1
1
1
DAC H
1
1
1
1
All DACs
Rev. E | Page 23 of 32
AD5629R/AD5669R
Data Sheet
INTERNAL REFERENCE REGISTER
POWER-ON RESET
The internal reference is available on all versions. The on-board
reference is off at power-up by default. The on-board reference
can be turned off or on by a user-programmable internal REF
register by setting Bit DB0 high or low (see Table 10). DB1
selects the internal reference value. Command 1000 is reserved
for setting the internal REF register (see Table 8). Table 11
shows how the state of the bits in the input shift register
corresponds to the mode of operation of the device.
The AD5629R/AD5669R contain a power-on reset circuit that
controls the output voltage during power-up. The AD5629R/
AD5669R DAC output powers up to 0 V and the AD5669R-3
DAC output powers up to midscale. The output remains powered
up at this level until a valid write sequence is made to the DAC.
This is useful in applications where it is important to know the
state of the output of the DAC while it is in the process of powering
up. There is also a software executable reset function that resets
the DAC to the power-on reset code. Command 0111 is reserved
LDAC
for this reset function (see Table 8). Any events on
CLR
or
during power-on reset are ignored.
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
COMMAND
DAC ADDRESS
DAC DATA
DAC DATA
COMMAND BYTE
DATA HIGH BYTE
DATA LOW BYTE
Figure 53. AD5669R Input Register Contents
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C3 C2 C1 C0 A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X
X
X
X
COMMAND
DAC ADDRESS
DAC DATA
DAC DATA
COMMAND BYTE
DATA HIGH BYTE
DATA LOW BYTE
Figure 54. AD5629R Input Register Contents
Rev. E | Page 24 of 32
Data Sheet
AD5629R/AD5669R
The bias generator of the selected DAC(s), output amplifier,
resistor string, and other associated linear circuitry is shut down
when the power-down mode is activated. The internal reference
is powered down only when all channels are powered down.
However, the contents of the DAC register are unaffected when
in power-down. The time to exit power-down is typically 4 μs
for VDD = 5 V and for VDD = 3 V.
POWER-DOWN MODES
The AD5629R/AD5669R contain four separate modes of
operation. Command 0100 is reserved for the power-down
function (see Table 8). These modes are software-programmable
by setting two bits, Bit DB9 and Bit DB8, in the control register.
Table 12 shows how the state of the bits corresponds to the
mode of operation of the device. Any or all DACs (DAC H to
DAC A) can be powered down to the selected mode by setting
the corresponding eight bits (DB7 to DB0) to 1. See Table 13 for
the contents of the input shift register during power-down/power-
up operation.
Any combination of DACs can be powered up by setting PD1
and PD0 to 0 (normal operation). The output powers up to the
LDAC
value in the input register (
low) or to the value in the
LDAC
DAC register before powering down (
high).
CLEAR CODE REGISTER
When both bits are set to 0, the part works normally with its
normal power consumption of 1.3 mA at 5 V. However, for the
three power-down modes, the supply current falls to 0.4 μA at
5 V (0.2 μA at 3 V). Not only does the supply current fall, but
the output stage is also internally switched from the output of
the amplifier to a resistor network of known values. This has the
advantage that the output impedance of the part is known while
the part is in power-down mode. There are three different
options. The output is connected internally to GND through
either a 1 kΩ or a 100 kΩ resistor, or it is left open-circuited
(three-state). The output stage is illustrated in Figure 55.
CLR
The AD5629R/AD5669R have a hardware
pin that
input is falling edge
line low clears the contents of the
input register and the DAC registers to the data contained in
CLR
CLR
is an asynchronous clear input. The
CLR
sensitive. Bringing the
the user-configurable
register and sets the analog outputs
accordingly. This function can be used in system calibration to load
zero scale, midscale, or full scale to all channels together. These
clear code values are user-programmable by setting two bits, Bit
CLR
DB1 and Bit DB0, in the
control register (see Table 15).
The default setting clears the outputs to 0 V. Command 0101
is reserved for loading the clear code register (see Table 8).
RESISTOR
AMPLIFIER
V
OUT
The part exits clear code mode at the end of the next valid write
STRING DAC
CLR
to the part. If
is aborted.
is activated during a write sequence, the write
POWER-DOWN
CIRCUITRY
CLR
CLR
to when
The
pulse activation time (the falling edge of
RESISTOR
NETWORK
the output starts to change) is typically 280 ns. However, if
outside the DAC linear region, it typically takes 520 ns after
executing
Figure 55. Output Stage During Power-Down
CLR
for the output to start changing (see Figure 44).
See Table 14 for the contents of the input shift register during
the loading clear code register operation.
Table 10. Internal Reference Register
Internal REF Register (DB0)
Action
0
1
Reference off (default)
Reference on
Table 11. 32-Bit Input Shift Register Contents for Reference Set-Up Command
MSB
LSB
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15 to DB1
X
DB0
1
0
0
0
X
X
X
X
1/0
Command bits (C3 to C0)
Address bits (A3 to A0)—don’t cares
Don’t cares
Internal REF on/off
Rev. E | Page 25 of 32
AD5629R/AD5669R
Data Sheet
Table 12. Power-Down Modes of Operation
DB9
DB8
Operating Mode
Normal operation
Power-down modes
1 kΩ to GND
100 kΩ to GND
Three-state
0
0
0
1
1
1
0
1
Table 13. 32-Bit Input Shift Register Contents for Power-Down/Power-Up Function
MSB
LSB
DB23 DB22 DB21 DB20 DB19 to DB16
DB15 to DB10 DB9 DB8 DB7 to DB1
PD1 PD0 DAC H to DAC B
DB0
0
1
0
0
X
X
DAC A
Command bits (C3 to C0)
Address bits (A3 to A0)—
don’t cares
Don’t cares
Power-
down mode
Power-down/power-up channel selection—
set bit to 1 to select
Table 14. 32-Bit Input Shift Register Contents for Clear Code Function
MSB
LSB
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15 to DB2
X
DB1
DB0
0
1
0
1
X
X
X
X
CR1
CR0
Command bits (C3 to C0)
Address bits (A3 to A0)—don’t cares
Don’t cares
Clear code register
Table 15. Clear Code Register
Clear Code Register
DB1
CR1
0
DB0
CR0
0
Clears to Code
0x0000
0
1
0xꢀ000
1
0
0xFFFF
1
1
No operation
Rev. E | Page 26 of 32
Data Sheet
AD5629R/AD5669R
POWER SUPPLY BYPASSING AND GROUNDING
LDAC FUNCTION
When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the board.
The printed circuit board containing the AD5629R/AD5669R
should have separate analog and digital sections. If the AD5629R/
AD5669R are in a system where other devices require an
AGND-to-DGND connection, the connection should be made
at one point only. This ground point should be as close as
possible to the AD5629R/AD5669R.
The outputs of all DACs can be updated simultaneously using
LDAC
the hardware
pin.
Synchronous
LDAC
LDAC
The DAC registers are updated after new data is read in.
can be permanently low or pulsed as in Figure 2.
LDAC
Asynchronous
The outputs are not updated at the same time that the input
LDAC
The power supply to the AD5629R/AD5669R should be
bypassed with 10 µF and 0.1 µF capacitors. The capacitors
should be as physically close as possible to the device, with the
0.1 µF capacitor ideally right up against the device. The 10 µF
capacitors are the tantalum bead type. It is important that the
0.1 µF capacitor have low effective series resistance (ESR) and
low effective series inductance (ESI), such as is typical of
common ceramic types of capacitors. This 0.1 µF capacitor
provides a low impedance path to ground for high frequencies
caused by transient currents due to internal logic switching.
registers are written to. When
goes low, the DAC
registers are updated with the contents of the input register.
Alternatively, the outputs of all DACs can be updated simulta-
LDAC
neously using the software
function by writing to Input
Register n and updating all DAC registers. Command 0011 is
LDAC
reserved for this software
function.
register gives the user extra flexibility and control
LDAC LDAC
LDAC
An
over the hardware
to 0 for a DAC channel means that this channel’s update is
controlled by the pin. If this bit is set to 1, this channel
pin. Setting the
bit register
The power supply line should have as large a trace as possible to
provide a low impedance path and reduce glitch effects on the
supply line. Clocks and other fast switching digital signals should
be shielded from other parts of the board by digital ground. Avoid
crossover of digital and analog signals if possible. When traces
cross on opposite sides of the board, ensure that they run at right
angles to each other to reduce feedthrough effects through the
board. The best board layout technique is the microstrip technique,
where the component side of the board is dedicated to the ground
plane only and the signal traces are placed on the solder side.
However, this is not always possible with a 2-layer board.
LDAC
updates synchronously; that is, the DAC register is updated
LDAC
after new data is read, regardless of the state of the
pin.
pin as being tied low. See Table 16
register mode of operation.
LDAC
It effectively sees the
LDAC
for the
This flexibility is useful in applications where the user wants
to simultaneously update select channels while the rest of the
channels are synchronously updating. Writing to the DAC
LDAC
using command 0110 loads the 8-bit
DB0). The default for each channel is 0, that is, the
works normally. Setting the bits to 1 means the DAC channel
LDAC
register (DB7 to
LDAC
pin
is updated regardless of the state of the
pin. See Table 17
LDAC
for the contents of the input shift register during the load
register mode of operation.
LDAC
Table 16.
Register
Load DAC Register
Bits (DB7 to DB0)
Pin
Operation
LDAC
LDAC
LDAC
1/0
X—don’t care
0
1
Determined by LDAC pin.
DAC channels update, overriding the LDAC pin. DAC channels see LDAC as 0.
Table 17. 32-Bit Input Shift Register Contents for
Register Function
LDAC
MSB
LSB
DB15
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 to DB8 DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
1
0
X
X
X
X
X
DAC H DAC G DAC F DAC E DAC D DAC C DAC B DAC A
LDAC LDAC
Command bits (C3 to C0)
Address bits (A3 to A0)—
don’t cares
Don’t
cares
Setting
bit to 1 overrides
pin
Rev. E | Page 27 of 32
AD5629R/AD5669R
Data Sheet
OUTLINE DIMENSIONS
4.10
4.00 SQ
3.90
0.35
0.30
0.25
PIN 1
PIN 1
INDICATOR
INDICATOR
13
16
0.65
BSC
12
1
EXPOSED
PAD
2.70
2.60 SQ
2.50
4
9
8
5
0.45
0.40
0.35
0.20 MIN
TOP VIEW
BOTTOM VIEW
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGC.
Figure 56. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-16-17)
Dimensions shown in millimeters
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 57. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
Rev. E | Page 2ꢀ of 32
Data Sheet
AD5629R/AD5669R
2.645
2.605 SQ
2.565
4
3
2
1
A
B
C
D
BALL A1
IDENTIFIER
1.50
REF
0.50
REF
TOP VIEW
(BALL SIDE DOWN)
BOTTOM VIEW
(BALL SIDE UP)
0.650
0.595
0.540
SIDE VIEW
COPLANARITY
0.05
0.340
0.320
0.300
SEATING
PLANE
0.270
0.240
0.210
Figure 58. 16-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-16-16)
Dimensions shown in millimeters
Rev. E | Page 29 of 32
AD5629R/AD5669R
Data Sheet
ORDERING GUIDE
Package
Option
Power-On
Reset to Code
Internal
ModelFF1
Temperature Range
Package Description
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead WLCSP
Accuracy
Reference
1.25 V
1.25 V
2.5 V
2.5 V
2.5 V
2.5 V
1.25 V
2.5 V
AD5629RARUZ-1
AD5629RARUZ-1-RL7
AD5629RBRUZ-2
AD5629RBRUZ-2-RL7
AD5629RACPZ-2-RL7
AD5629RACPZ-3-RL7
AD5629RBCPZ-1-RL7
AD5629RBCPZ-2-RL7
AD5629RBCBZ-1-RL7
AD5669RARUZ-1
−±0°C to +105°C
−±0°C to +105°C
−±0°C to +105°C
−±0°C to +105°C
−±0°C to +105°C
−±0°C to +105°C
−±0°C to +105°C
−±0°C to +105°C
−±0°C to +105°C
−±0°C to +105°C
−±0°C to +105°C
−±0°C to +105°C
−±0°C to +105°C
−±0°C to +105°C
−±0°C to +105°C
−±0°C to +105°C
−±0°C to +105°C
−±0°C to +105°C
−±0°C to +105°C
−±0°C to +105°C
−±0°C to +105°C
RU-16
RU-16
RU-16
RU-16
CP-16-17
CP-16-17
CP-16-17
CP-16-17
CB-16-16
RU-16
Zero
Zero
Zero
Zero
Zero
Midscale
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Midscale
Zero
Zero
Zero
Zero
Zero
Zero
±± LSB INL
±± LSB INL
±1 LSB INL
±1 LSB INL
±± LSB INL
±± LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
1.25 V
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead WLCSP
±32 LSB INL 1.25 V
±32 LSB INL 1.25 V
±16 LSB INL 2.5 V
±16 LSB INL 2.5 V
±32 LSB INL 2.5 V
±32 LSB INL 2.5 V
±16 LSB INL 1.25 V
±16 LSB INL 2.5 V
±16 LSB INL 1.25 V
±16 LSB INL 2.5 V
±16 LSB INL 1.25 V
±16 LSB INL 1.25 V
AD5669RARUZ-1-RL7
AD5669RBRUZ-2
RU-16
RU-16
RU-16
AD5669RBRUZ-2-RL7
AD5669RACPZ-2-RL7
AD5669RACPZ-3-RL7
AD5669RBCPZ-1-RL7
AD5669RBCPZ-2-RL7
AD5669RBCPZ-1500R7
AD5669RBCPZ-2500R7
AD5669RBCBZ-1-RL7
AD5669RBCBZ-1-R5
EVAL-AD5629RSDZ
EVAL-AD5669RSDZ
CP-16-17
CP-16-17
CP-16-17
CP-16-17
CP-16-17
CP-16-17
CB-16-16
CB-16-16
16-Lead WLCSP
Evaluation Board
Evaluation Board
1 Z = RoHS Compliant Part.
Rev. E | Page 30 of 32
Data Sheet
NOTES
AD5629R/AD5669R
Rev. E | Page 31 of 32
AD5629R/AD5669R
NOTES
Data Sheet
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2010–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08819-0-9/16(E)
Rev. E | Page 32 of 32
相关型号：
AD566AJR
IC PARALLEL, WORD INPUT LOADING, 0.25 us SETTLING TIME, 12-BIT DAC, PDSO28, PLASTIC, SOIC-28, Digital to Analog Converter
ADI
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