AD5547SRU-EP [ADI]

Dual-Current Output, Parallel Input; 双电流输出，并行输入


型号：	AD5547SRU-EP
厂家：	ADI
描述：	Dual-Current Output, Parallel Input 双电流输出，并行输入转换器数模转换器光电二极管
文件：	总12页 (文件大小：316K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Dual-Current Output, Parallel Input, 16-Bit

Multiplying DAC with 4-Quadrant Resistors

Data Sheet

AD5547-EP

FEATURES

Dual channel

FUNCTIONAꢀ BꢀOCK DIAGRAM

OFSA

COMA

REFA

16-bit resolution: AD5547-EP

2- or 4-quadrant, 6.8 MHz bandwidth multiplying DAC

1 ꢀSB DNꢀ

FBA

DAC A

INPUT

DAC A

DAC B

OUTA

D0 TO

D15

AGNDA

D0 TO D15

2 ꢀSB INꢀ

Operating supply voltage: 2.7 V to 5.5 V

ꢀow noise: 12 nV/√Hz

ꢀow power: I_DD= 10 μA maximum

0.5 μs settling time

Built-in R_FBfacilitates current-to-voltage conversion

Built-in 4-quadrant resistors allow 0 V to –10 V, 0 V to +10 V,

or 10 V outputs

AGNDB

DAC B

INPUT

OUTB

DAC A

DAC B

FBB

OFSB

POWER

RESET

A0, A1

ADDR

DECODE

AD5547-EP

DGND

RS MSB

LDAC

REFB

COMB

2 mA full-scale current 20ꢁ, with V_REF= 10 V

Extended automotive operating temperature range

−55°C to +125°C

Figure 1.

GENERAꢀ DESCRIPTION

Selectable zero-scale/midscale power-on presets

Compact 38-lead TSSOP package

The AD5547-EP is a dual precision, 16-bit, multiplying, low power,

current-output, parallel input, digital-to-analog converter (DAC). It

is designed to operate from a single +5 V supply with 1ꢀ V

multiplying references for 4-quadrant outputs with a 6.8 MHz

bandwidth.

ENHANCED PRODUCT FEATURES

Supports defense and aerospace applications (AQEC

standard)

Military temperature range (such as −55°C to +125°C).

Controlled manufacturing baseline

One assembly/test site

One fabrication site

Enhanced product change notification

Qualification data available on request

The built-in, 4-quadrant resistors facilitate resistance matching

and temperature tracking, which minimize the number of

components needed for multiquadrant applications. In addition,

the feedback resistor (R_FB) simplifies the I-to-V conversion with

an external buffer.

The AD5547-EP is available in a compact, 38-lead TSSOP

package and operates at the extended automotive temperature

range of −55°C to +125°C. Additional application and technical

information can be found in the AD5547 data sheet.

APPꢀICATIONS

Automatic test equipment

Instrumentation

Digitally controlled calibration

Digital waveform generation

VREF

–VREF

FBA

COMA

REFA

OFSA

ROFS RFB

IOUTA

VOUTA

16-BIT

DAC A

AD5547-EP

16-BIT DATA

AGNDA

–VREF TO +VREF

POWER-ON

RESET

WR LDAC RS

MSB A0, A1

(ONE CHANNEL SHOWN ONLY)

LDAC

MSB

A0, A1

Figure 2. 16-Bit 4-Quadrant Multiplying DAC with Minimum of External Components (Only One Channel Is Shown)

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD5547-EP

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Electrical Characteristics..............................................................3

Absolute Maximum Ratings ............................................................5

ESD Caution...................................................................................5

Pin Configuration and Function Descriptions..............................6

Typical Performance Characteristics ..............................................8

Outline Dimensions....................................................................... 10

Ordering Guide .......................................................................... 10

Enhanced Product Features ............................................................ 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

REVISION HISTORY

9/11—Revision 0: Initial Version

Rev. 0 | Page 2 of 12

Data Sheet

AD5547-EP

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

V_DD= 2.7 V to 5.5 V, I_OUT= virtual GND, GND = 0 V, V_REF= −10 V to +10 V, T_A= −55°C to +125°C, unless otherwise noted.

Table 1.

Parameter

Symbol

Test Conditions/Comments

Min Typ

Max

Unit

STATIC PERFORMANCE¹

Resolution

1 LSB = V_REF/2¹⁶= 153 μV at V_REF= 10 V

Bits

LSB

ppm/°C

Relative Accuracy

Differential Nonlinearity

Output Leakage Current

INL

DNL

I_OUT

±2

±1

±5

±±

Monotonic

Data = zero scale, T_A= 25°C

Data = zero scale, T_A= T_Amaximum

Data = full scale

Full-Scale Gain Error

Bipolar Mode Gain Error

Bipolar Mode Zero-Scale Error

Full-Scale Temperature Coefficient²TCV_FS

G_FSE

G_E

G_ZSE

±1

REFERENCE INPUT

V_REFRange

V_REF

REF

R1 and R2

Δ(R1 to R2)

R_FB, R_OFS

C_REF

−18

+18

±1.5

REF Input Resistance

R1 and R2 Resistance

R1-to-R2 Mismatch

Feedback and Offset Resistance

Input Capacitance²

ANALOG OUTPUT

±0.5

kΩ

Output Current

I_OUT

C_OUT

Data = full scale

Code dependent

200

Output Capacitance²

LOGIC INPUT AND OUTPUT

Logic Input Low Voltage

V_IL

V_DD= 5 V

V_DD= 3 V

V_DD= 5 V

V_DD= 3 V

0.8

0.±

Logic Input High Voltage

V_IH

2.±

2.1

Input Leakage Current

Input Capacitance²

I_IL

C_IL

μA

INTERFACE TIMING^{2, 3}

Data to WR Setup Time

See Figure 3

V_DD= 5 V

V_DD= 3 V

V_DD= 5 V

V_DD= 3 V

V_DD= 5 V

t_DS

t_DH

t_WR

Data to WR Hold Time

WR Pulse Width

V_DD= 3 V

V_DD= 5 V

V_DD= 3 V

V_DD= 5 V

V_DD= 3 V

V_DD= 5 V

V_DD= 3 V

LDAC Pulse Width

RS Pulse Width

t_LDAC

t_RS

WR to LDAC Delay Time

t_LWD

SUPPLY CHARACTERISTICS

Power Supply Range

Positive Supply Current

Power Dissipation

V_{DD RANGE}

I_DD

P_DISS

P_SS

2.7

5.5

μA

Logic inputs = 0 V

∆V_DD= ±5ꢀ

0.055 mW

0.003 ꢀ/ꢀ

Power Supply Sensitivity

Rev. 0 | Page 3 of 12

AD5547-EP

Data Sheet

Parameter

AC CHARACTERISTICS^±

Symbol

Test Conditions/Comments

Min Typ

Max

Unit

Output Voltage Settling Time

t_S

To ±0.1ꢀ of full scale, data cycles from zero scale

to full scale to zero scale

0.5

μs

Reference Multiplying Bandwidth

DAC Glitch Impulse

Multiplying Feedthrough Error

Digital Feedthrough

V_OUT/V_REF

Q_D

V_REF= 100 mV rms, data = full scale

V_REF= 0 V, midscale – 1 to midscale

V_REF= 100 mV rms, f = 10 kHz

WR = 1, LDAC toggles at 1 MHz

V_REF= 5 V p-p, data = full scale, f = 1 kHz

f = 1 kHz, BW = 1 Hz

6.8

MHz

nV-s

−3.5

−78

Total Harmonic Distortion

Output Noise Density

Analog Crosstalk

THD

e_N

C_AT

−10±

−95

nV/√Hz

Signal input at Channel A and measures the

output at Channel B, f = 1 kHz

¹All static performance tests (except I_OUT) are performed in a closed-loop system using an external precision OP97 I-to-V converter amplifier. The device R_FBterminal is

tied to the amplifier output. The +IN pin of the OP97 is grounded, and the I_OUTof the DAC is tied to the OP97’s −IN pin. Typical values represent average readings

measured at 25°C.

²Guaranteed by design; not subject to production testing.

³All input control signals are specified with t_R= t_F= 2.5 ns (10ꢀ to 90ꢀ of 3 V) and are timed from a voltage level of 1.5 V.

^±All ac characteristic tests are performed in a closed-loop system using an AD8038 I-to-V converter amplifier except for THD where the AD8065 was used.

Timing Diagram

t_WR

DATA

t_DH

t_DS

t_LWD

LDAC

t_LDAC

t_RS

Figure 3. AD5547-EP Timing Diagram

Rev. 0 | Page ± of 12

Data Sheet

AD5547-EP

ABSOLUTE MAXIMUM RATINGS

Table 2.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Parameter

Rating

V_DDto GND

R_FB, R_OFS, R1, R_COM, and VREF to GND

Logic Inputs to GND

V(I_OUT) to GND

Input Current to Any Pin except Supplies

Thermal Resistance (θ_JA)¹

–0.3 V to +8 V

–18 V to +18 V

–0.3 V to +8 V

–0.3 V to V_DD+ 0.3 V

±50 mA

Maximum Junction Temperature (T_{J MAX}

Operating Temperature Range

Storage Temperature Range

Lead Temperature

)

150°C

−55°C to +125°C

−65°C to +150°C

ESD CAUTION

Vapor Phase, 60 sec

Infrared, 15 sec

215°C

220°C

¹Package power dissipation = (T_{J MAX}− T_A)/θ_JA.

Rev. 0 | Page 5 of 12

AD5547-EP

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

38 D2

37 D3

36 D4

35 D5

34 D6

33 D7

32 D8

31 D9

30 D10

29 VDD

28 D11

27 D12

26 D13

25 D14

24 D15

OFSA

FBA

COMA

REFA

OUTA

AD5547-EP

AGNDA

DGND 10

TOP VIEW

(Not to Scale)

AGNDA 11

OUTB

REFB

COMB

FBB

22 MSB

21 LDAC

20 A1

OFSB

WR 18

A0 19

Figure 4. Pin Configuration

Table 3. Pin Function Descriptions

Pin No.

Mnemonic Description

1, 2, 2± to D0 to D15

Digital Input Data Bits D0 to D15. Signal level must be ≤ V_DD+ 0.3 V.

28, 30 to

R_OFSA

Bipolar Offset Resistor A. Accepts up to ±18 V. In 2-quadrant mode, R_OFSAties to R_FBA. In ±-quadrant mode, R_OFSA

ties to R_1Aand the external reference.

R_FBA

R_1A

Internal Matching Feedback Resistor A. Connects to the external op amp for I-to-V conversion.

±-Quandrant Resistor. In 2-quadrant mode, R_1Ashorts to the V_REFApin. In ±-quadrant mode, R_1Aties to R_OFSA. Do

not connect when operating in unipolar mode.

R_COMA

Center Tap Point of the Two ±-Quadrant Resistors, R_1Aand R_2A. In ±-quadrant mode, R_COMAties to the inverting

node of the reference amplifier. In 2-quadrant mode, R_COMAshorts to the associated V_REFApin. Do not connect if

operating in unipolar mode.

DAC A Reference Input in 2-Quadrant Mode, R2 Terminal in ±-Quadrant Mode. In 2-quadrant mode, V_REFAis the

reference input with constant input resistance vs. code. In ±-quadrant mode, V_REFAis driven by the external

reference amplifier.

V_REFA

I_OUTA

DAC A Current Output. Connects to the inverting terminal of external precision I-to-V op amp for voltage output.

AGNDA

DGND

AGNDB

I_OUTB

DAC A Analog Ground.

Digital Ground.

DAC B Analog Ground.

DAC B Current Output. Connects to inverting terminal of external precision I-to-V op amp for voltage output.

DAC B Reference Input Pin. Establishes DAC full-scale voltage. Constant input resistance vs. code. If configured

V_REFB

with an external op amp for ±-quadrant multiplying, V_REFBbecomes –V_REF

1±

R_COMB

Center Tap Point of the Two ±-Quadrant Resistors, R_1Band R_2B. In ±-quadrant mode, R_COMBties to the inverting

node of the reference amplifier. In 2-quadrant mode, R_COMBshorts to the V_REFBpin. Do not connect if operating in

unipolar mode.

±-Quandrant Resistor. In 2-quadrant mode, R_1Bshorts to the V_REFBpin. In ±-quadrant mode, R_1Bties to R_OFSB. Do not

connect if operating in unipolar mode.

R_1B

R_FBB

R_OFSB

Internal Matching Feedback Resistor B. Connects to external op amp for I-to-V conversion.

Bipolar Offset Resistor B. Accepts up to ±18 V. In 2-quadrant mode, R_OFSBties to R_FBB. In ±-quadrant mode, R_OFSB

ties to R_1Band an external reference.

Write Control Digital Input In, Active Low. WR transfers shift register data to the DAC register on the rising edge.

Signal level must be ≤V_DD+ 0.3 V.

Rev. 0 | Page 6 of 12

Data Sheet

AD5547-EP

Pin No.

Mnemonic Description

Address Pin 0. Signal level must be ≤V_DD+ 0.3 V.

Address Pin 1. Signal level must be ≤V_DD+ 0.3 V.

LDAC

MSB

Digital Input Load DAC Control. Signal level must be ≤V_DD+ 0.3 V.

Power-On Reset State. MSB = 0 corresponds to zero-scale reset; MSB = 1 corresponds to midscale reset. The

signal level must be ≤V_DD+ 0.3 V.

Active low resets both input and DAC registers. Resets to zero-scale if MSB = 0 and resets to midscale if MSB = 1.

Signal level must be ≤V_DD+ 0.3 V.

Positive Power Supply Input. The specified range of operation is 2.7 V to 5.5 V.

VDD

Table 4. Address Decoder Pins

Output Update

DAC A

None

DAC A and DAC B

DAC B

Table 5. Control Inputs

RS WR

LDAC Register Operation

Reset the output to 0 with MSB = 0; reset the output to midscale with MSB = 1.

Load the input register with data bits.

Load the DAC register with the contents of the input register.

The input and DAC registers are transparent.

When LDAC and WR are tied together and programmed as a pulse, the data bits are loaded into the input register

on the falling edge of the pulse and are then loaded into the DAC register on the rising edge of the pulse.

No register operation.

Rev. 0 | Page 7 of 12

AD5547-EP

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

1.0

= 5 V

= 25° C

0.8

0.6

0.4

0.2

–0.2

–0.4

–0.6

–0.8

–1.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536

CODE (Decimal)

LOGIC INPUT VOLTAGE V (V)

Figure 5. AD5547-EP Integral Nonlinearity Error

Figure 8. Supply Current vs. Logic Input Voltage

1.0

0.8

3.0

2.5

2.0

1.5

1.0

0.5

0.6

0.4

0x5555

0x8000

0.2

–0.2

–0.4

–0.6

–0.8

–1.0

0xFFFF

0x0000

8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536

CODE (Decimal)

10k

100k

10M

100M

CLOCK FREQUENCY (Hz)

Figure 6. AD5547-EP Differential Nonlinearity Error

Figure 9. AD5547-EP Supply Current vs. Clock Frequency

1.5

= 2.5 V

= 25° C

REF

= 5V ± 10%

= 10V

REF

1.0

0.5

INL

DNL

–0.5

–1.0

–1.5

100

10k

100k

SUPPLY VOLTAGE V

(V)

FREQUENCY (Hz)

Figure 10. Power Supply Rejection Ratio (PSRR) vs. Frequency

Figure 7. Linearity Error vs. Supply Voltage, V_DD

Rev. 0 | Page 8 of 12

Data Sheet

AD5547-EP

LDAC

–2

–4

–6

–8

–10

–12

–14

–16

OUT

CH1 5.00V CH2 2.00V M 200ns

A CH1 2.70V

B CH1 –6.20V

400.00ns

–18

10k

100k

10M

100M

FREQUENCY (Hz)

Figure 11. Settling Time from Full Scale to Zero Scale

Figure 13. AD5547-EP Unipolar Reference Multiplying Bandwidth

–3.85

–3.90

–3.95

–4.00

–4.05

–4.10

–4.15

–4.20

–20

–10

TIME (ns)

Figure 12. AD5547-EP Midscale Transition and Digital Feedthrough

Rev. 0 | Page 9 of 12

AD5547-EP

Data Sheet

OUTLINE DIMENSIONS

9.80

9.70

9.60

4.50

4.40

4.30

6.40 BSC

PIN 1

1.20

MAX

0.15

0.05

8°

0°

0.50

BSC

0.27

0.17

0.70

0.60

0.45

SEATING

PLANE

0.20

0.09

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-153-BD-1

Figure 14. 38-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-38)

Dimension s shown in millimeters

ORDERING GUIDE

Model¹

Resolution (Bits)

DNL (LSB)

INL (LSB)

Temperature Range

Package Description

Package Option

AD55±7SRU-EP

±1

±2

−55°C to +125°C

38-Lead TSSOP

RU-38

¹Z = RoHS Compliant Part.

Rev. 0 | Page 10 of 12

Data Sheet

NOTES

AD5547-EP

Rev. 0 | Page 11 of 12

AD5547-EP

NOTES

Data Sheet

registered trademarks are the property of their respective owners.

D10108-0-9/11(0)

Rev. 0 | Page 12 of 12

AD5547SRU-EP [ADI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E