AD5450YUJ_技术文档

PRELIMINARY TECHNICAL DATA

8/10/12/14-BitHighBandwidth

a

MultiplyingDACs withSerialInterface

AD5450/AD5451/AD5452/AD5453*

Preliminary Technical Data

FEATURES

F U NC T IO NAL B LO C K D IAG RAM

+2.5 V to +5.5 V Supply Operation

50MHz Serial Interface

10MHz Multiplying Bandw idth

±10V Reference Input

8-Lead TSOT & MSOP Packages

Pin Com patible 8, 10, 12 and 14 Bit Current Output DACs

Extended Tem perature range –40°C to +125°C

Guaranteed Monotonic

V

REF

DD

R

FB

R

AD5450/

8/10/12/14

BIT

R-2R DAC

AD5451/

AD5452/

AD5453

I

OUT1

DAC REGISTER

INPUT LATCH

Four Quadrant Multiplication

Pow er On Reset w ith brow n out detect

<5µA typical Current Consum ption

Power On

Reset

APPLICATIONS

Portable Battery Pow ered Applications

Waveform Generators

SYNC

SCLK

SDIN

CONTROL LOGIC &

INPUT SHIFT REGISTER

Analog Processing

GND

Instrum entation Applications

Program m able Am plifiers and Attenuators

Digitally-Controlled Calibration

Program m able Filters and Oscillators

Com posite Video

Ultrasound

Gain, offset and Voltage Trim m ing

G E NE R AL D E S C R IP T IO N

T he AD 5450/AD 5451/AD 5452/AD 5453 are C M OS 8,

10, 12 and 14-bit Current Output digital-to-analog

converters respectively.

T he applied external reference input voltage (V_REF

)

determines the full scale output current. An integrated

feedback resistor (R_FB) provides temperature tracking and

full scale voltage output when combined with an external

Current to Voltage precision amplifier.

T hese devices operate from a +2.5 V to 5.5 V power sup-

ply, making them suited to battery powered applications

and many other applications.

T he AD 5450/AD 5451/AD 5452/AD 5453 D AC s are

available in small 8-lead T SOT & MSOP packages.

T hese DACs utilize double buffered 3-wire serial interface

that is compatible with SPI^{T M}, QSPI^{T M}, MICROWIRE^{T M}

and most DSP interface standards.

On power-up, the internal shift register and latches are

filled with zeros and the DAC output is at zero scale.

As a result of manufacture on a CMOS sub micron

process, they offer excellent four quadrant multiplication

characteristics, with large signal multiplying bandwidths

of 10M H z.

*US Patent N umber 5,689,257

SPI and QSPI are trademarks of Motorola, Inc.

M ICROWIRE is a trademark of N ational Semiconductor Corporation.

REV. PrD Oct, 2003

Inform ation furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assum ed by Analog Devices for its

use, nor for any infringem ents of patents or other rights of third parties

which m ay result from its use. No license is granted by im plication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.

Tel: 781/ 329-4700

World Wide Web Site: http:/ / w w w.analog.com

Analog Devices, Inc., 2003

Fax: 781/ 326-8703

PRELIMINARY TECHNICAL DATA

1

AD5450/AD5451/AD5452/AD5453–SPECIFICATIONS

(V = 2.5 V to 5.5 V, V = +10 V, I_OUTx = O V. All specifications T_MINto T_MAXunless otherwise noted. DC performance measured with

DD

REF

OP1177, AC performance with AD9631 unless otherwise noted.)

P a r a m et er

M in

T yp

M a x

U n it s

C on d it ion s

ST AT IC

AD 5 4 5 0

P ERF O RM AN C E

Resolu tion

8

Bits

L S B

Relative Accuracy

D ifferential N onlinearity

AD 5 4 5 1

± 0 . 2 5

± ½

G uaranteed M onotonic

Resolu tion

1 0

± 0 . 2 5

± ½

Bits

L S B

Relative Accuracy

D ifferential N onlinearity

AD 5 4 5 2

Resolu tion

1 2

± 0 . 5

± ½

Bits

L S B

Relative Accuracy

D ifferential N onlinearity

AD 5 4 5 3

Resolu tion

1 4

± 2

± 1

± 2 . 4 4

± 1 . 2 2

Bits

L S B

m V

ppm FSR/°C

n A

Relative Accuracy

D ifferential N onlinearity

T otal U nadjusted Error

G ain Error

G ain Error T emp C oefficient²

O utput Leakage C urrent

± 5

± 1 0

± 5 0

Data = 0000_H, T _A= 25°C, I_{OUT 1}

Data = 0000_H, I_{OUT 1}

n A

Output Voltage Compliance Range

1 . 23

V

REF EREN C E IN P U T ²

Reference Input Range

V_REFInput Resistance

± 1 0

9 . 3

V

k Ω

8

1 2

Input resistance T C = -50ppm/°C

D IG IT AL IN PU T S²

Input H igh Voltage, V_IH

2 . 0

1 . 7

V

µA

p F

V_DD= 3.6 V to 5 V

V_DD= 2.5 V to 3.6 V

V_DD= 2.7 V to 5.5 V

V_DD= 2.5 V to 2.7 V

Input Low Voltage, V_IL

0 . 8

0 . 7

1

Input Leakage C urrent, I_IL

Input C apacitance

1 0

D YN AM IC

P ERF O RM AN C E ²

Reference MultiplyingBW

Output Voltage Settling T ime

10

MHz

V_REF= +/-3.5V, DAC loaded all 1s

V_REF= 10V, R_LOAD= 100Ω, C_LOAD= 15pF

DAC latch alternately loaded with 0s and 1s.

Measured to +/-16mV of FS

Measured to +/-4mV of FS

Measured to +/-1mV of FS

Interface delay time

Rise and Fall time, V_REF= 10V, R_LOAD=

AD5450

AD5451

AD5452

AD5453

1 0 0

1 1 0

1 6 0

1 8 0

2 0

n s

D igital D elay

10% to 90% D ettling T ime

4 0

3 0

1 0

100Ω, C_LOAD= 15pF

Digital to Analog Glitch Impulse

M ultiplying F eedthrough Error

3

n V-s

d B

1 LSB change around M ajor C arry, V_REF=0V

D AC latch loaded with all 0s.

Reference = 1M H z.

- 7 5

Reference = 10M H z.

O utput C apacitance

IOU T 1

5

p F

D AC Latches Loaded with all 0s

D AC Latches Loaded with all 1s

D AC Latches Loaded with all 0s

D AC Latches Loaded with all 1s

Feedthrough to D AC output with C S high

and Alternate Loading of all 0s and all 1s.

1 0

5

IOU T 2

D igital F eed throu gh

0 . 1

n V-s

–2–

REV. PrD

PRELIMINARY TECHNICAL DATA

AD5450/AD5451/AD5452/AD5453

(V = 2.5 V to 5.5 V, V = +10 V, I_OUTx = O V. All specifications T_MINto T_MAXunless otherwise noted. DC performance measured with

DD

REF

OP1177, AC performance with AD9631 unless otherwise noted.)

P a r a m e t e r

M in

T yp

M a x

U n it s

C on d it ion s

T otal H arm onic D istortion

D igital T H D , C lock = 1M H z

50kHz f_OUT

Output N oise Spectral D ensity

SF D R perform ance (Wideband)

U pdate = 1M H z

50kH z Fout

20kH z Fout

SF D R perform ance (N arrowBand)

50kH z Fout

20kH z Fout

- 8 0

d B

V_REF= 3.5 V pk-pk, All 1s loaded, f = 1kH z

7 5

2 5

d B

n V/√H z

@ 1kH z

U pdate = 1M H z, V_REF= 3.5V

7 8

d B

8 7

7 8

d B

Interm odulation D istortion

f1 = 20kH z, f2 = 25kH z, U pdate= 1M H z,

V_REF= 3.5V

P O WER

Power Supply Range

I_DD

Power Supply Sensitivity²

REQ U IREM EN T S

2 . 5

5 . 5

1

0.001

V

µA

% / %

Logic Inputs = 0 V or V_DD

∆V_DD= ± 5%

N O T E S

¹T emperature range is as follows:

Y Version: –40°C to + 125°C .

²Guaranteed by design and characterisation, not subject to production test.

Specifications subject to change without notice.

1

TIMINGCHARACTERISTICS

(V = +5 V, I_OUT2 = O V. All specifications T_MINto T_MAXunless otherwise noted.)

REF

P ar am eter

V_{D D}= 4.5 V to 5.5 V V_{D D}= 2.5 V to 5.5 V Units

C onditions/C om m ents

f_{SC LK}

t₁

t₂

t₃

t₄

t₅

t₆

t₇

t₈

50

20

8

5

4.5

5

M H z max M ax Clock frequency

ns min

SCLK Cycle time

SCLK H igh T ime

SCLK Low T ime

SYNC falling edge to SCLK active edge setup time

Data Setup T ime

Data H old T ime

SYNC rising edge to SCLK active edge

M inimum SYN C high time

30

N O T E S

¹See Figures 1. T emperature range is as follows:

Y Version: –40°C to + 125°C . G uaranteed by design and characterisation, not subject to

production test. All input signals are specified with tr =tf = 5ns (10% to 90% of V_DD

) and timed from a voltage level of (V_IL+ V_IH)/2.

Specifications subject to change without notice.

t

1

SCLK

t

2

3

t

8

t

7

t

4

SYNC

DIN

t

6

t

5

DB15

DB0

Figure 1. Tim ing Diagram .

REV. PrD

–3–

PRELIMINARY TECHNICAL DATA

AD5450/AD5451/AD5452/AD5453

2

ABSO LUT E MAXIMUM RAT INGS^1,

(T _A= +25°C unless otherwise noted)

V_DDto GND

V_REF,R_FBto GND

–0.3 V to +7 V

–12 V to +12 V

–0.3 V to +7 V

±10 mA

I

_OUT1 to GND

Input Current to any pin except supplies

Logic Inputs & Output³

-0.3V to V_DD+0.3 V

Operating T emperature Range

Industrial (Y Version)

Storage T emperature Range

Junction T emperature

–40°C to +125°C

–65°C to +150°C

+ 150°C

8 lead MSOP θ_JAT hermal Impedance

8 lead T SOT θ_JAT hermal Impedance

206°C /W

211°C /W

Lead T emperature, Soldering (10seconds)

IR Reflow, Peak T emperature (<20 seconds)

300°C

+ 235°C

NOTES

¹Stressesabove those listed under “Absolute Maximum Ratings” maycause permanent

damage to the device. Thisisa stressratingonlyand functionaloperation ofthe device

at these or any other conditions above those listed in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for

extended periodsmayaffect device reliability. Onlyone absolute maximum ratingmay

be applied at any one time.

²T ransient currents of up to 100mA will not cause SCR latchup.

³Overvoltages at SCLK, SYNC, DIN, will be clamped by internal diodes. Current

should be limited to the maximum ratings given.

O R D E R ING G U ID E

Tem perature Range P ackage D escription Br an din g P ackage O ption

Model

Resolution

INL

AD 5450YU J

8

±0.25

±0.5

±2

-40 ^oC to +125 ^oC

T S O T

M S O P

T S O T

M S O P

U J-8

RM -8

U J-8

RM -8

AD 5451YU J 10

AD 5452YU J 12

AD 5452YRM 12

AD 5453YU J 14

AD 5453YRM 14

±2

C AUTIO N

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD5450/AD5451/AD5452/AD5453 features proprietary ESD protection circuitry,

permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore,

proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

–4–

REV. PrD

PRELIMINARY TECHNICAL DATA

AD5450/AD5451/AD5452/AD5453

P IN F U NC T IO N D E SC R IP T IO N

M SO P

T SO T

Mn em on ic F u n ction

I_{O U T}1 DAC Current Output.

1

2

3

8

7

6

G N D

Ground Pin.

SC L K

Serial Clock Input. By default, data is clocked into the input shift register on the

falling edge of the serial clock input. Alternatively, by means of the serial control

bits, the device may be configured such that data is clocked into the shift register on

the rising edge of SCLK.

4

5

SD IN

Serial Data Input. Data is clocked into the 16-bit input register on the active edge of

the serial clock input. By default, on power up, data is clocked into the shift register

on the falling edge of SCLK. T he control bits allow the user to change the active

edge to rising edge.

5

6

4

3

S Y N C

Active Low Control Input. T his is the frame synchronization signal for the input

data. Data is loaded to the shift register on the active edge of the

following clocks.

V_{D D}

Positive power supply input. T hese parts can operate from a supply of +2.5 V to

+5.5 V.

7

8

2

1

V_{RE F}

R_{F B}

DAC reference voltage input pin.

DAC feedback resistor pin. Establish voltage output for the DAC by connecting to

external amplifier output.

P IN C O NF IG U R AT IO N

TSO T (UJ-8)

MSO P (RM-8)

IOUT1

GND

RFB

8

IOUT1

GND

RFB

8

7

6

5

1

2

1

2

3

4

AD5450/

AD5451/

AD5452/

AD5453

(Not to Scale)

AD5452/

AD5453

(Not to Scale)

VREF

7

VREF

SCLK

SDIN

V

SCLK

SDIN

3

4

6

5

DD

SYNC

REV. PrD

–5–

PRELIMINARY TECHNICAL DATA

AD5450/AD5451/AD5452/AD5453

T E R M I N O L O G Y

Rela tive Accu r a cy

Relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the

endpoints of the DAC transfer function. It is measured after adjusting for zero and full scale and is normally expressed in

LSBs or as a percentage of full scale reading.

D iffer en t ia l Non lin ea r it y

Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adja-

cent codes. A specified differential nonlinearity of -1 LSB max over the operating temperature range ensures monotonic-

ity.

G a in E r r or

Gain error or full-scale error is a measure of the output error between an ideal DAC and the actual device output. For

these DACs, ideal maximum output is V_REF– 1 LSB. Gain error of the DACs is adjustable to zero with external resis-

tance.

O u tp u t Lea ka ge C u r r en t

Output leakage current is current which flows in the DAC ladder switches when these are turned off. For the I_{OUT 1}termi-

nal, it can be measured by loading all 0s to the DAC and measuring the I_{OUT 1}current. Minimum current will flow in the

I_{OUT 2}line when the DAC is loaded with all 1s

O u t p u t C a p a cit a n ce

Capacitance from I_{OUT 1}or I_{OUT 2}to AGND.

O u tp u t C u r r en t Settlin g T im e

T his is the amount of time it takes for the output to settle to a specified level for a full scale input change. For these de-

vices, it is specifed with a 100 Ω resistor to ground. T he settling time specification includes the digital delay from SYNC

rising edge to the full scale output change.

D igital to Analog Glitch lm pulse

T he amount of charge injected from the digital inputs to the analog output when the inputs change state. T his is normally

specified as the area of the glitch in either pA-secs or nV-secs depending upon whether the glitch is measured as a current

or voltage signal.

D igit a l F eed t h r ou gh

When the device is not selected, high frequency logic activity on the device digital inputs may be capacitivelly coupled

through the device to show up as noise on the I_OUTpins and subsequently into the following circuitry. T his noise is digital

feedthrough.

M u ltip lyin g F eed th r ou gh E r r or

T his is the error due to capacitive feedthrough from the DAC reference input to the DAC I_{OUT 1}terminal, when all 0s are

loaded to the DAC.

T ota l H a r m on ic D istor tion (T H D )

T he DAC is driven by an ac reference. T he ratio of the rms sum of the harmonics of the DAC output to the fundamental

value is the T HD. Usually only the lower order harmonices are included, such as second to fifth.

2

T HD = 20log

√

(V₂+ V₃+ V₄+ V₅

)

V₁

D igita l In ter m od u la tion D istor tion

Second order intermodulation (IMD) measurements are the relative magnitudes of the fa and fb tones generated digitally

by the DAC and the second order products at 2fa-fb and 2fb-fa.

C om p lia n ce Volta ge Ra n ge

T he maximum range of (output) terminal voltage for which the device will provide the specified characteristics.

Sp u r iou s- F r ee D yn a m ic Ra n ge(SF D R)

It is the usable dynamic range of a DAC before spurious noise interferes or distorts the fundamental signal. SFDR is the

measure of difference in amplitude between the fundamental and the largest harmonically or nonharmonically related spur

from dc to full Nyquist bandwidth (half the DAC sampling rate or fs/2). Narrow band SFDR is a measure of SFDR over

an arbitrary window size, in this case 50% of hte fundamental. Digital SFDR is a measure of the usable dymanic range of

the DAC when the signal is a digitally generated sine wave.

–6–

REV. PrD

PRELIMINARY TECHNICAL DATA

Typical Performance Characteristics

AD5450/AD5451/AD5452/AD5453

TPC 2. INL vs. Code (10-Bit DAC)

TPC 5. DNL vs. Code (8-Bit DAC)

TPC 8. DNL vs. Code (14-Bit DAC)

TPC 3. INL vs. Code (12-Bit DAC)

TPC 6. DNL vs. Code (10-Bit DAC)

TPC 9. INL vs Reference Voltage

TPC 1. INL vs. Code (8-Bit DAC)

TPC 4. INL vs. Code (14-Bit DAC)

TPC 7. DNL vs. Code (12-Bit DAC)

REV. PrD

–7–

PRELIMINARY TECHNICAL DATA

AD5450/AD5451/AD5452/AD5453

TPC11. Linearity Errors vs. V_DD

TPC12. INL vs Code - Biased Mode

TPC10. DNL vs. Reference Voltage

TPC 14. INL Error vs. Reference -

Biased Mode

TPC 15. DNL Error vs. Reference -

Biased Mode

TPC 13. DNL vs Code - Biased Mode

TPC 17. Supply Current vs. Clock Freq

TPC 18. Logic Threshold vs Supply

Voltage

TPC 16. TUE vs Code

–8–

REV. PrD

PRELIMINARY TECHNICAL DATA

AD5450/AD5451/AD5452/AD5453

TPC 20. Reference Multiplying

Bandwidth - sm all signal

TPC 21. Reference Multiplying

Bandwidth - large signal

TPC 19. Supply Current vs Logic Input

Voltage

TPC 24. Settling Tim e

TPC 23. Reference Multiplying

Bandwidth - large signal

TPC 22. Reference Multiplying

Bandwidth - sm all signal

TPC 26. Power Supply Rejection vs

Frequency

TPC 27. Noise Spectral Density vs

Frequency

TPC 25. Midscale Transition and

Digital Feedthrough

REV. PrD

–9–

PRELIMINARY TECHNICAL DATA

AD5450/AD5451/AD5452/AD5453

TPC 28. TBD

TPC 29. TBD

TPC 30. TBD

–10–

REV. PrD

PRELIMINARY TECHNICAL DATA

AD5450/AD5451/AD5452/AD5453

similarly the AD5451 uses ten bits and ignores the four

LSBs, while the AD5450 uses eight bits and ignores the

last six bits.

G E NE R AL D E S C R IP T IO N

D AC S E C T IO N

T he AD5450, AD5451, AD5452 and AD5453 are 8, 10,

12 and 14 bit current output DACs consisting of a

segmented (4-Bits) inverting R-2R ladder configuration.

T he feedback resistor R_FBhas a value of R. T he value of R

is typically 9.3kΩ (minimum 8kΩ and maximum 12kΩ).

If I_{OUT 1}is kept at the same potential as GND, a constant

current flows in each ladder leg, regardless of digital input

code. T herefore, the input resistance presented at V_REFis

always constant and nominally of value R. T he DAC

output (I_OUT) is code-dependent, producing various

resistances and capacitances. External amplifier choice

should take into account the variation in impedance

generated by the DAC on the amplifiers inverting input

node.

D AC C ontr ol Bits C 1, C 0

Control bits C1 and C0 the user to load and update the

new DAC code and to change the active clock edge. By

default the shift register clocks data in on the falling edge,

this can be changed via the control bits. In this case, the

DAC core is inoperative until the next data frame. A

power cycle resets this back to default condition.

On chip power on reset circuitry ensures the device

powers on with zeroscale loaded to the DAC register and

I_{OU T}line.

TABLE III. D AC CO NTRO L BITS

C 1 C 0 Funtion Im plem ented

Access is provided to the V_REF, R_FB, and I_{OUT 1}terminals

of the DAC, making the device extremely versatile and

allowing it to be configured in several different operating

modes, for example, to provide a unipolar output and in

four quadrant multiplication in bipolar mode. Note that a

matching switch is used in series with the internal R_FB

feedback resistor. If users attempt to measure R_FB, power

must be applied to V_DDto achieve continuity.

0

1

0

1

0

1

Load and Update(Power On Default)

Reserved

Clock Data to shift register On Rising Edge

SYN C F u n c t io n

SYNC is an edge-triggered input that acts as a frame

synchronization signal and chip enable. Data can only be

transferred into the device while SYNC is low. T o start

the serial data transfer, SYNC should be taken low ob-

serving the minimum SYNC falling to SCLK falling

edge setup time, t₄.

After the falling edge of the 16th SCLK pulse, bring

SYNC high to transfer data from the input shift register to

the DAC register.

SE RIAL INT E RF AC E

T he AD5450/AD5451/AD5452/AD5453 have an easy to

use 3-wire interface which is compatible with SPI/QSPI/

MicroWire and DSP interface standards. Data is written

to the device in 16 bit words. T his 16-bit word consists of

2 control bits and either 8, 10 12, or 14 data bits as shown

in Figure 2. T he AD5453 uses all 14 bits of DAC data.

T he AD5452 uses twelve bits and ignores the two LSBs,

DB15 (MSB)

DB0 (LSB)

C1

C0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

X

DATA BITS

CONTROL BITS

Figure 2a. AD5450 8 bit Input Shift Register Contents

DB15 (MSB)

DB0 (LSB)

C1

C0 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

X

DATA BITS

CONTROL BITS

Figure 2b. AD5451 10 bit Input Shift Register Contents

DB15 (MSB)

C1 C0

DB0 (LSB)

DB9 DB8 DB7 DB6 DB5 DB4

DATA BITS

DB1 DB0

DB3 DB2

X

DB11 DB10

X

CONTROL BITS

Figure 2c. AD5452 12 bit Input Shift Register Contents

DB15 (MSB)

DB0 (LSB)

C1 C0

DB11 DB10 DB9 DB8 DB7 DB6

DATA BITS

DB3 DB2 DB1 DB0

DB5 DB4

DB13 DB12

CONTROL BITS

Figure 2c. AD5453 14 bit Input Shift Register Contents

REV. PrD

–11–

PRELIMINARY TECHNICAL DATA

AD5450/AD5451/AD5452/AD5453

With a fixed 10 V reference, the circuit shown above will

give an unipolar 0V to -10V output voltage swing. When

V_INis an ac signal, the circuit performs two-quadrant

multiplication.

C IR C U IT O P E R AT IO N

Un ipolar M ode

Using a single op amp, these devices can easily be

configured to provide 2 quadrant multiplying operation or

a unipolar output voltage swing as shown in Figure 3.

T he following table shows the relationship between digital

code and expected output voltage for unipolar operation.

(AD 5450, 8-Bit device).

When an output amplifier is connected in unipolar mode,

the output voltage is given by:

V_OUT= -D/2ⁿx V_REF

Table I. Unipolar Code Table

Where D is the fractional representation of the digital

word loaded to the DAC, and n is the number of bits.

D igital Input Analog O utput (V)

1111 1111

1000 0000

0000 0001

0000 0000

-V_REF(255/256)

-V_REF(128/256) = -V_REF/2

-V_REF(1/256)

D = 0 to 255 (8-Bit AD5450)

= 0 to 1023 (10-Bit AD5451)

= 0 to 4095 (12-Bit AD5452)

= 0 to 16383 (14-Bit AD5453)

-V_REF(0/256) = 0

Note that the output voltage polarity is opposite to the

V_REFpolarity for dc reference voltages.

B ip ola r O p er a tion

In some applications, it may be necessary to generate full

4-Quadrant multplying operation or a bipolar output

swing. T his can be easily accomplished by using another

external amplifier and some external resistors as shown in

Figure 4. In this circuit, the second amplifier A2 provides

a gain of 2. Biasing the external amplifier with an offset

from the reference voltage results in full 4-quadrant

multiplying operation. T he transfer function of this circuit

shows that both negative and positive output voltages are

created as the input data (D) is incremented from code

zero (V_OUT= - V_REF) to midscale (V_OUT- 0V ) to full

scale (V_OUT= + V_REF).

V

DD

R

2

C

1

RFB

IOUT1

GND

V

DD

V

A1

REF

V

REF AD5450/1/2/3

SYNC SCLK SDIN

R

1

V

= 0 to -V

REF

OUT

AGND

uController

V_OUT

=

(V_REFx D / 2^n-1

)

V_REF

-

NOTES:

1

R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.

Where D is the fractional representation of the digital

word loaded to the DAC and n is the resolution of the

D AC .

2

C1 PHASE COMPENSATION (1pF - 5pF) MAY BE REQUIRED

IF A1 IS A HIGH SPEED AMPLIFIER.

Figure 3. Unipolar Operation

D = 0 to 255 (8-Bit AD5450)

= 0 to 1023 (10-Bit AD5451)

= 0 to 4095 (12-Bit AD5452)

= 0 to 16383 (14-Bit AD5453)

T hese DACs are designed to operate with either negative

or positive reference voltages. T he V_DDpower pin is only

used by the internal digital logic to drive the DAC

switches’ ON and OFF states.

When V_INis an ac signal, the circuit performs four-

quadrant multiplication.

T hese DACs are also designed to accommodate ac refer-

ence input signals in the range of -10V to +10V.

T able II. shows the relationship between digital code and

the expected output voltage for bipolar operation

(AD 5450, 8-Bit device).

R3

20kΩ

R2

C1

V

DD

R5

20kΩ

RFB

IOUT1

GND

V

DD

R4

10kΩ

R1

V

AD5450/1/2/3

A1

REF

± 10V

V

REF

A2

V

= -V

to +V

REF

OUT

REF

SYNC SCLK SDIN

uController

AGND

R1 AND R2 ARE USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.

ADJUST R1 FOR V = 0V WITH CODE 10000000 LOADED TO DAC.

NOTES:

1

OUT

2

MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS

R3 AND R4.

3

C1 PHASE COMPENSATION (1pF-5pF) MAY BE REQUIRED

IF A1/A2 IS A HIGH SPEED AMPLIFIER.

Figure 4. Bipolar Operation (4 Quadrant Multiplication)

–12–

REV. PrD

PRELIMINARY TECHNICAL DATA

AD5450/AD5451/AD5452/AD5453

ratings of the device. In this type of application, the full

range of multiplying capability of the DAC is lost.

Table II. Bipolar Code Table

D igital Input Analog O utput (V)

P O SIT IVE O U T P U T VO LT AG E

1111 1111

1000 0000

0000 0001

0000 0000

+ V_REF(127/128)

0

-V_REF(127/128)

-V_REF(128/128)

Note that the output voltage polarity is opposite to the

V_REFpolarity for dc reference voltages. In order to achieve

a positive voltage output, an applied negative reference to

the input of the DAC is preferred over the output

inversion through an inverting amplifier because of the

resistors tolerance errors. T o generate a negative

reference, the reference can be level shifted by an op amp

such that the V_OUTand GND pins of the reference

become the virtual ground and -2.5V respectively as

shown in Figure 6.

S t a b ilit y

In the I-to-V configuration, the I_OUTof the DAC and the

inverting node of the op amp must be connected as close

as possible, and proper PCB layout techniques must be

employed. Since every code change corresponds to a step

function, gain peaking may occur if the op amp has

limited GBP and there is excessive parasitic capacitance at

the inverting node. T his parasitic capacitance introduces a

pole into the open loop response which can cause ringing

or instability in the closed loop applications circuit.

V

= 5V

DD

ADR03

V

OUT IN

GND

An optional compensation capacitor, C1 can be added in

parallel with R_FBfor stability as shown in figures 3 and 4.

T oo small a value of C1 can produce ringing at the

output, while too large a value can adversely affect the

settling time. C1 should be found empirically but 1-2pF is

generally adequate for the compensation.

+

5V

C

1

RFB

IOUT1

IOUT2

V

DD

-2.5V

V

REF

V

1/2 AD8552

OUT = 0 to +2.5V

GND

1/2 AD8552

-

5V

SING LE SU P P LY AP P LIC AT IO NS

NOTES:

1

ADDITIONAL PINS OMITTED FOR CLARITY

2

Voltage Switch in g Mode of O per ation

C1 PHASE COMPENSATION (1pF-5pF) MAY BE REQUIRED

IF A1 IS A HIGH SPEED AMPLIFIER.

Figure 5 shows these DACs operating in the voltage-

switching mode. T he reference voltage, V_INis applied to

the I_{OUT 1}pin, I_{OUT 2}is connected to AGND and the

output voltage is available at the V_REFterminal. In this

configuration, a positive reference voltage results in a

positive output voltage making single supply operation

possible. T he output from the DAC is voltage at a

constant impedance (the DAC ladder resistance). T hus an

op-amp is necessary to buffer the output voltage. T he

reference input no longer sees a constant input impedance,

but one that varies with code. So, the voltage input should

be driven from a low impedance source.

Figure 6. Positive Voltage output with m inim um of

com ponents.

AD D ING G AIN

In applications where the output voltage is required to be

greater than V_IN, gain can be added with an additional

external amplifier or it can also be achieved in a single

stage. It is important to take into consideration the effect

of temperature coefficients of the thin film resistors of the

DAC. Simply placing a resistor in series with the RFB

resistor will causing mis-matches in the T emperature

coefficients resulting in larger gain temperature coefficient

errors. Instead, the circuit of Figure 7 is a recommended

method of increasing the gain of the circuit. R1, R2 and

R3 should all have similar temperature coefficients, but

they need not match the temperature coefficients of the

DAC. T his approach is recommended in circuits where

gains of great than 1 are required.

V

DD

R

1

2

RFB

V

DD

V

OUT

IOUT1

IN

V

REF

GND

NOTES:

1

ADDITIONAL PINS OMITTED FOR CLARITY

2

C1 PHASE COMPENSATION (1pF-5pF) MAY BE REQUIRED

IF A1 IS A HIGH SPEED AMPLIFIER.

Figure 5. Single Supply Voltage Switching Mode Operation.

It is important to note that V_INis limited to low voltages

because the switches in the DAC ladder no longer have

the same source-drain drive voltage. As a result their on

resistance differs and this degrades the integral linearity of

the DAC. Also, V_INmust not go negative by more than

0.3V or an internal diode will turn on, exceeding the max

REV. PrD

–13–

PRELIMINARY TECHNICAL DATA

AD5450/AD5451/AD5452/AD5453

op amp through the DAC. Since only a fraction D of the

current into the V_REFterminal is routed to the I_{OUT 1}ter-

minal, the output voltage has to change as follows:

V

DD

Output Error Voltage Due to Dac Leakage

C

1

RFB

IOUT1

IOUT2

V

DD

= (Leakage x R)/D

R

2

V

IN

V

REF

V

OUT

where R is the DAC resistance at the V_REFterminal. For a

DAC leakage current of 10nA, R = 10 kilohm and a gain

(i.e., 1/D) of 16 the error voltage is 1.6mV.

R

3

GND

GAIN = R2 + R3

R2

R

2

NOTES:

1

R1 = R2R3

R2 + R3

R E F E R E NC E S E LE C T IO N

ADDITIONAL PINS OMITTED FOR CLARITY

2

C1 PHASE COMPENSATION (1pF-5pF) MAY BE REQUIRED

IF A1 IS A HIGH SPEED AMPLIFIER.

When selecting a reference for use with the AD5426 series

of current output DACs, pay attention to the references

output voltage temperature coefficient specification. T his

parameter not only affects the full scale error, but can also

affect the linearity (INL and DNL) performance. T he

reference temperature coefficient should be consistent with

the system accuracy specifications. For example, an 8-bit

system required to hold its overall specification to within

1LSB over the temperature range 0-50^oC dictates that the

maximum system drift with temperature should be less than

78ppm/^oC. A 14-Bit system with the same temperature

range to overall specification within 2LSBs requires a

maximum drift of 10ppm/^oC. By choosing a precision

reference with low output temperature coefficient this

error source can be minimized. T able IV. suggests some

of the suitable dc references available from Analog

Devices that are suitable for use with this range of current

output DACs.

Figure 7. Increasing Gain of Current Output DAC

USE D AS A D IVID E R O R P RO GRAMMABLE GAIN

E L E M E N T

Current Steering DACs are very flexible and lend

themselves to many different applications. If this type of

DAC is connected as the feedback element of an op-amp

and R_FBis used as the input resistor as shown in Figure 8,

then the output voltage is inversely proportional to the

digital input fraction D. For D = 1-2ⁿthe output voltage

is

V_OUT= -V_IN/D = -V_IN/(1-2^-n)

V

DD

V

IN

RFB

V

DD

AM P LIF IE R S E LE C T IO N

T he primary requirement for the current-steering mode is

an amplifier with low input bias currents and low input

offset voltage. T he input offset voltage of an op amp is

multiplied by the variable gain (due to the code dependent

output resistance of the DAC) of the circuit. A change in

this noise gain between two adjacent digital fractions

produces a step change in the output voltage due to the

amplifier’s input offset voltage. T his output voltage

change is superimposed upon the desired change in output

between the two codes and gives rise to a differential

linearity error, which if large enough could cause the

DAC to be non-monotonic.

V

IOUT1

REF

GND

V

OUT

NOTES:

1

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 8. Current Steering DAC used as a divider or

Program m able Gain Elem ent

T he input bias curent of an op amp also generates an

offset at the voltage output as a result of the bias current

flowing in the feedback resistor R_FB. Most op amps have

input bias currents low enough to prevent any significant

errors in 12-Bit applications, however for 14-Bit

applications some consideration should be given to

selecting an appropriate amplifier.

As D is reduced, the output voltage increases. For small

values of the digital fraction D, it is important to ensure

that the arnplifier does not saturate and also that the

required accuracy is met. For example, an eight bit DAC

driven with the binary code 10H (00010000), i.e., 16

decimal, in the circuit of Figure 8 should cause the output

voltage to be sixteen times V_IN. However, if the DAC has

a linearity specification of +/- 0.5LSB then D

can in fact have the weight anywhere in the range 15.5/256

to 16.5/256 so that the possible output voltage will be in

the range 15.5V_INto 16.5V_IN—an error of + 3% even

though the DAC itself has a maximum error of 0.2%.

Common mode rejection of the op amp is important in

voltage switching circuits, since it produces a code

dependent error at the voltage output of the circuit. Most

op amps have adequate common mode rejection for use at

8-, 10- and 12-Bit resolution.

Provided the DAC switches are driven from true wideband

low impedance sources (V_INand AGND) they settle

quickly. Consequently, the slew rate and settling time of a

voltage switching DAC circuit is determined largely by

the output op amp. T o obtain minimum settling time in

this configuration, it is important to minimize capacitance

DAC leakage current is also a potential error source in

divider circuits. T he leakage current must be

counterbalanced by an opposite current supplied from the

–14–

REV. PrD

PRELIMINARY TECHNICAL DATA

AD5450/AD5451/AD5452/AD5453

Table IV. Listing of suitable AD I P r ecision Refer ences r ecom m ended for use with AD 5450/1/2/3 D ACs.

Refer en ce O u tp u t Volta ge In itia l T oler a n ce

T em p er a tu r e D r ift

0.1H z to 10H z noise P a cka ge

AD R01

AD R02

AD R03

10 V

5 V

2.5 V

0.1%

0.2%

0.04%

3ppm /^oC

20µVp-p

10µVp-p

3.4µVp-p

SC 70, T SOT , SOIC

M SO P, SO IC

AD R425 5V

Table V. Listing of som e pr ecision AD I O p Am ps suitable for use with AD 5450/1/2/3 D ACs.

P ar t #

Max Supply Voltage V

V_{O S}( m a x ) µV I_B(m a x) n A

GBP MH z

Slew Rate V/µs

t_{SE T T LE}with AD 5453

O P 97

O P 1177

AD 8551 ± 6

±

20

18

25

60

5

0.1

2

0.05

0.9

1.3

1.5

0.2

0.7

0.4

Table VI. Listing of som e H igh Speed AD I O p Am ps suitable for use with AD 5450/1/2/3 D ACs.

Max Supply Voltage V BW @ A_CLMH z Slew Rate V/µs t_{SE T T LE}with AD 5453 V_{O S}( m a x ) µV I_B(m a x) n A

P ar t #

AD 8065 ± 12

AD 8021 ± 12

AD 8038 ± 5

AD 9631 ± 5

145

200

350

320

180

100

425

1300

1500

1000

3000

10000

0.01

1000

0.75

7000

Avoid crossover of digital and analog signals. T races on

opposite sides of the board should run at right angles to

each other. T his reduces the effects of feedthrough

through the board. A microstrip technique is by far the

best, but not always possible with a doublesided board. In

this technique, the component side of the board is

dedicated to ground plane while signal traces are placed

on the solder side.

at the V_REFnode (voltage output node in this application)

of the DAC. T his is done by using low inputs capacitance

buffer amplifiers and careful board design.

Most single supply circuits include ground as part of the

analog signal range, which in turns requires an

ampliferthat can handle rail to rail signals, there is a large

range of single supply amplifiers available from Analog

D evices.

It is good practice to employ compact, minimum lead

length PCB layout design. Leads to the input should be as

short as possible to minimize IR drops and stray

inductance.

P C B LAYO UT AND P O WE R SUP P LY D E C O UP LING

In any circuit where accuracy is important, careful

consideration of the power supply and ground return

layout helps to ensure the rated performance. T he printed

circuit board on which the AD5426/AD5432/AD5443 is

mounted should be designed so that the analog and digital

sections are separated, and cofined to certain areas of the

board. If the DAC is in a system where multiple devices

require an AGN D -to-D GN D connection, the connection

should be made at one point only. T he star ground point

should be established as close as possible to the device.

T he PCB metal traces between V_REFand R_FBshould also

be matched to minimize gain error. T o maximize on high

frequency performance, the I-to-V amplifier should be

located as close to the device as possible.

T hese DACs should have ample supply bypassing of 10

µF in parallel with 0.1 µF on the supply located as close

to the package as possible, ideally right up against the

device. T he 0.1 µF capacitor should have low Effective

Series Resistance (ESR) and Effective Series Inductance

(ESI), like the common ceramic types that provide a low

impedance path to ground at high frequencies, to handle

transient currents due to internal logic switching. Low

ESR 1 µF to 10 µF tantalum or electrolytic capacitors

should also be applied at the supplies to minimize

transient disturbance and filter out low frequency ripple.

Fast switching signals such as clocks should be shielded

with digital ground to avoid radiating noise to other parts

of the board, and should never be run near the reference

inputs.

REV. PrD

–15–

PRELIMINARY TECHNICAL DATA

AD5450/AD5451/AD5452/AD5453

O ver view of AD 54xx devices

P art #

Resolu tion # D AC s I N L

t _S

In ter fa ce

P a cka ge

F ea tu r es

AD 5403¹

8

2

1

2

±0.25 20n s

±0.25 60n s

±0.25 100ns Serial

±0.25 60n s

P arallel

C P -40

10 MHz BW, 17 ns CS Pulse Width, 4-

Quadrant M ultiplying Resistors

10 MH z BW, 50 MH z Serial, 4- Quadrant

M ultiplying Resistors

10 MH z BW, 50 MH z Serial, 4- Quadrant

M ultiplying Resistors

AD 5410¹

AD 5413¹

Serial

RU -16

RU -24

Serial

AD 5424

AD 5425

AD 5426

AD 5428²

AD 5429²

AD 5450²

AD 5404¹

8

1 0

1

2

1

2

P arallel

RU -16, C P-20 10 MHz BW, 17 ns CS Pulse Width

R M -1 0

RU -20

RU -10

R J-8

Byte Load,10 M H z BW, 50 M H z Serial

10 M H z BW, 50 M H z Serial

10 MHz BW, 17 ns CS Pulse Width

10 M H z BW, 50 M H z Serial

P arallel

±0.25 100ns Serial

10 M H z BW, 50 M H z Serial

± 0.5

25n s

P arallel

C P -40

10 MHz BW, 17 ns CS Pulse Width, 4-

Quadrant M ultiplying Resistors

10 MH z BW, 50 MH z Serial, 4- Quadrant

M ultiplying Resistors

10 MH z BW, 50 MH z Serial, 4- Quadrant

M ultiplying Resistors

AD 5411¹

AD 5414¹

1 0

1

2

Serial

RU -16

RU -24

R M -1 0

Serial

AD 5432

AD 5433

AD 5439²

AD 5440²

AD 5451²

AD 5405²

1 0

1 2

1

2

1

2

± 0.5

110ns Serial

70n s P arallel

110ns Serial

70n s P arallel

10 M H z BW, 50 M H z Serial

RU -20, C P-20 10 MHz BW, 17 ns CS Pulse Width

RU -16

RU -24

R J-8

10 M H z BW, 50 M H z Serial

10 MHz BW, 17 ns CS Pulse Width

10 M H z BW, 50 M H z Serial

10 MHz BW, 17 ns CS Pulse Width, 4-

Quadrant M ultiplying Resistors

10 MH z BW, 50 MH z Serial, 4- Quadrant

M ultiplying Resistors

10 MH z BW, 50 MH z Serial, 4- Quadrant

M ultiplying Resistors

10 M H z BW, 50 M H z Serial

±0.25 110ns Serial

± 1

120ns P arallel

160ns Serial

C P -40

AD 5412¹

AD 5415²

1 2

1

2

RU -16

RU -24

R M -1 0

AD 5443

AD 5445

AD 5447²

AD 5449²

AD 5452²

AD 5453²

1 2

1 4

1

2

1

± 1

± 0.5

± 2

160ns Serial

120ns P arallel

160ns Serial

180ns Serial

RU -20, C P-20 10 MHz BW, 17 ns CS Pulse Width

RU -24

RU -16

RJ-8, RM -8

10 MHz BW, 17 ns CS Pulse Width

10 M H z BW, 50 M H z Serial

¹F uture parts, contact factory for availability

²In development, contact factory for availability

O U T LINE D IM E NS IO NS

D imensions shown in inches and (mm).

8 Lead TSO T

(UJ- 8)

8 Lead MSO P

(RM - 8)

0.122 (3.10)

0.114 (2.90)

2.90 BSC

5

4

8

1

7

2

6

3

5

4

0.122 (3.10)

0.114 (2.90)

0.199 (5.05)

0.187 (4.75)

1.60 BSC

PIN 1

2.80 BSC

1

PIN 1

0.65 BSC

0.0256 (0.65) BSC

1.95 BSC

1.00

0.90

0.70

0.120 (3.05)

0.112 (2.84)

0.120 (3.05)

0.112 (2.84)

0.20

0.08

0.043 (1.09)

0.037 (0.94)

1.10 MAX

0.006 (0.15)

0.002 (0.05)

0.60

0.45

0.30

O

33

27

8

4

0

0.38

0.22

0.018 (0.46)

0.10 MAX

SEATING

PLANE

SEATING

PLANE

0.011 (0.28)

0.003 (0.08)

0.028 (0.71)

0.008 (0.20)

0.016 (0.41)

REV. PrD

–16–


型号：	AD5450YUJ
厂家：	ADI
描述：	8/10/12/14-Bit High Bandwidth Multiplying DACs with Serial Interface 8月10日/ 12/ 14位，高带宽，乘法DAC，串行接口
文件：	总16页 (文件大小：121K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD5450YUJ [ADI]

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