AD5248BRMZ2.5-RL7_技术文档

Dual, 256-Position, I²C-Compatible

Digital Potentiometers

Data Sheet

AD5243/AD5248

FEATURES

FUNCTIONAL BLOCK DIAGRAMS

A1

W1

B1

A2

W2

B2

2-channel, 256-position potentiometers

End-to-end resistance: 2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ

Compact 10-lead MSOP (3 mm × 4.9 mm) package

Fast settling time: t_S= 5 µs typical on power-up

Full read/write of wiper register

V

DD

Power-on preset to midscale

WIPER

REGISTER 1

REGISTER 2

Extra package address decode pins: AD0 and AD1 (AD5248 only)

Computer software replaces microcontroller in factory

programming applications

GND

AD5243

Single supply: 2.7 V to 5.5 V

Low temperature coefficient: 35 ppm/°C

Low power: I_DD= 6 µA maximum

SDA

SCL

PC INTERFACE

Wide operating temperature: −40°C to +125°C

Evaluation board available

Figure 1. AD5243

W1

B1

W2

B2

APPLICATIONS

Systems calibrations

Electronics level settings

V

Mechanical trimmers replacement in new designs

Permanent factory PCB setting

Transducer adjustment of pressure, temperature, position,

chemical, and optical sensors

DD

RDAC

REGISTER 1

RDAC

REGISTER 2

GND

RF amplifier biasing

Automotive electronics adjustment

Gain control and offset adjustment

AD0

AD1

ADDRESS

DECODE

AD5248

8

SDA

SCL

SERIAL INPUT

REGISTER

Figure 2. AD5248

GENERAL DESCRIPTION

The AD5243 and AD5248 provide a compact 3 mm × 4.9 mm

packaged solution for dual, 256-position adjustment applications.

The AD5243 performs the same electronic adjustment function as

a 3-terminal mechanical potentiometer, and the AD5248 performs

the same adjustment function as a 2-terminal variable resistor.

Available in four end-to-end resistance values (2.5 kΩ, 10 kΩ,

50 kΩ, and 100 kΩ), these low temperature coefficient devices

are ideal for high accuracy and stability-variable resistance

adjustments. The wiper settings are controllable through the

I²C-compatible digital interface. The AD5248 has extra package

address decode pins, AD0 and AD1, allowing multiple parts to

share the same I²C, 2-wire bus on a PCB. The resistance between

the wiper and either endpoint of the fixed resistor varies linearly

with respect to the digital code transferred into the RDAC latch.¹

Operating from a 2.7 V to 5.5 V power supply and consuming

less than 6 µA allows the AD5243/AD5248 to be used in portable

battery-operated applications.

For applications that program the AD5243/AD5258 at the factory,

Analog Devices, Inc., offers device programming software running

on Windows® NT/2000/XP operating systems. This software

effectively replaces the need for external I²C controllers, which

in turn enhances the time to market of systems. An AD5243/

AD5248 evaluation kit and software are available. The kit includes

a cable and instruction manual.

¹The terms digital potentiometer, VR, and RDAC are used interchangeably.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rightsof third parties that may result fromits use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks andregisteredtrademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

AD5243/AD5248

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Test Circuits..................................................................................... 12

Theory of Operation ...................................................................... 13

Programming the Variable Resistor and Voltage................... 13

Programming the Potentiometer Divider............................... 14

ESD Protection ........................................................................... 14

Terminal Voltage Operating Range ......................................... 14

Power-Up Sequence ................................................................... 14

Layout and Power Supply Bypassing ....................................... 14

Constant Bias to Retain Resistance Setting............................. 15

I²C Interface .................................................................................... 16

I²C Compatible, 2-Wire Serial Bus .......................................... 16

I²C Controller Programming.................................................... 18

Outline Dimensions....................................................................... 19

Ordering Guide .......................................................................... 19

Applications....................................................................................... 1

Functional Block Diagrams............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics: 2.5 kΩ Version................................. 3

Electrical Characteristics: 10 kΩ, 50 kΩ, and 100 kΩ

Versions.......................................................................................... 4

Timing Characteristics: All Versions......................................... 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configurations and Function Descriptions ........................... 7

Typical Performance Characteristics ............................................. 8

REVISION HISTORY

4/12—Rev. A to Rev. B

4/09—Rev. 0 to Rev. A

Changes to Rheostat Operation Section, Table 7, and

Changes to DC Characteristics—Rheostat Mode Parameter and

to DC Characteristics—Potentiometer Divider Mode Parameter,

Table 1 .................................................................................................3

Moved Figure 3 ..................................................................................5

Updated Outline Dimensions........................................................19

Changes to Ordering Guide...........................................................19

Table 8 ...............................................................................................13

Changes to Voltage Output Operation Section ...........................14

Deleted Evaluation Board Section and Figure 45, Renumbered

Sequentially ......................................................................................15

Changes to Table 13.........................................................................17

Updated Outline Dimensions........................................................19

Changes to Ordering Guide ...........................................................19

1/04—Revision 0: Initial Version

Rev. B | Page 2 of 20

Data Sheet

AD5243/AD5248

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS: 2.5 kΩ VERSION

V_DD= 5 V 10%, or 3 V 10%; V_A= V_DD; V_B= 0 V; −40°C < T_A< +125°C; unless otherwise noted.

Table 1.

Parameter

Symbol

Conditions

Min

Typ ¹

Max

Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resistor Differential Nonlinearity²

Resistor Integral Nonlinearity²

Nominal Resistor Tolerance³

Resistance Temperature Coefficient

Wiper Resistance

R-DNL

R-INL

∆R_AB

R_WB, V_A= no connect

T_A= 25°C

−2

−14

−20

0.1

2

+2

+14

+55

LSB

%

ppm/°C

Ω

(∆R_AB/R_AB)/∆T V_AB= V_DD, wiper = no connect

R_WB

35

160

Code = 0x00, V_DD= 5 V

200

DC CHARACTERISTICS—POTENTIOMETER

DIVIDER MODE⁴

Differential Nonlinearity⁵

Integral Nonlinearity⁵

DNL

INL

−1.5

−2

0.1

0.6

+1.5

+2

LSB

Voltage Divider Temperature Coefficient (∆V_W/V_W)/∆T

Code = 0x80

Code = 0xFF

Code = 0x00

15

−5.5

4.5

ppm/°C

LSB

Full-Scale Error

Zero-Scale Error

RESISTOR TERMINALS

Voltage Range⁶

V_WFSE

V_WZSE

−14

0

12

V_A, V_B, V_W

C_A, C_B

GND

V_DD

V

pF

Capacitance A, B⁷

f = 1 MHz, measured to GND,

code = 0x80

f = 1 MHz, measured to GND,

code = 0x80

45

60

Capacitance W⁷

C_W

pF

Shutdown Supply Current⁸

Common-Mode Leakage

DIGITAL INPUTS AND OUTPUTS

Input Logic High

Input Logic Low

Input Logic High

Input Logic Low

Input Current

Input Capacitance⁷

I_{A_SD}

I_CM

V_DD= 5.5 V

V_A= V_B= V_DD/2

0.01

1

µA

nA

V_IH

V_IL

V_IH

V_IL

I_IL

V_DD= 5 V

V_DD= 3 V

2.4

2.1

V

µA

pF

0.8

0.6

1

V_IN= 0 V or 5 V

C_IL

5

POWER SUPPLIES

Power Supply Range

Supply Current

V_{DD RANGE}

I_DD

P_DISS

2.7

5.5

6

30

V

V_IH= 5 V or V_IL= 0 V

V_IH= 5 V or V_IL= 0 V, V_DD= 5 V

V_DD= 5 V 10%, code = midscale

3.5

µA

µW

%/%

Power Dissipation⁹

Power Supply Sensitivity

DYNAMIC CHARACTERISTICS¹⁰

Bandwidth, −3 dB

Total Harmonic Distortion

V_WSettling Time

PSS

0.02

0.08

BW

THD_W

t_S

Code = 0x80

4.8

0.1

1

MHz

%

µs

V_A= 1 V rms, V_B= 0 V, f = 1 kHz

V_A= 5 V, V_B= 0 V, 1 LSB error band

R_WB= 1.25 kΩ, R_S= 0

Resistor Noise Voltage Density

e_{N_WB}

3.2

nV/√Hz

¹Typical specifications represent average readings at 25°C and V_DD= 5 V.

²Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic.

³V_A= V_DD, V_B= 0 V, wiper (V_W) = no connect.

⁴Specifications apply to all VRs.

⁵INL and DNL are measured at V_Wwith the RDAC configured as a potentiometer divider similar to a voltage output digital-to-analog converter (DAC). V_A= V_DDand V_B= 0 V.

DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions.

⁶Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.

⁷Guaranteed by design, but not subject to production test.

⁸Measured at the A terminal. The A terminal is open circuited in shutdown mode.

⁹P_DISSis calculated from (I_DD× V_DD). CMOS logic level inputs result in minimum power dissipation.

¹⁰All dynamic characteristics use V_DD= 5 V.

Rev. B | Page 3 of 20

AD5243/AD5248

Data Sheet

ELECTRICAL CHARACTERISTICS: 10 kΩ, 50 kΩ, AND 100 kΩ VERSIONS

V_DD= 5 V 10%, or 3 V 10%; V_A= V_DD; V_B= 0 V; −40°C < T_A< 125°C; unless otherwise noted.

Table 2.

Parameter

Symbol

Conditions

Min

Typ¹

Max

Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resistor Differential Nonlinearity²

Resistor Integral Nonlinearity²

Nominal Resistor Tolerance³

Resistance Temperature Coefficient

Wiper Resistance

R-DNL

R-INL

∆R_AB

(∆R_AB/R_AB)/∆T

R_WB

R_WB, V_A= no connect

T_A= 25°C

V_AB= V_DD, wiper = no connect

Code = 0x00, V_DD= 5 V

−1

−2.5

−20

0.1

0.25

+1

+2.5

+20

LSB

%

ppm/°C

Ω

35

160

200

DC CHARACTERISTICS—POTENTIOMETER

DIVIDER MODE⁴

Differential Nonlinearity⁵

Integral Nonlinearity⁵

Voltage Divider Temperature Coefficient

Full-Scale Error

DNL

INL

(∆V_W/V_W)/∆T

V_WFSE

V_WZSE

−1

0.1

0.3

15

−1

1

+1

LSB

ppm/°C

LSB

Code = 0x80

Code = 0xFF

Code = 0x00

−2.5

0

2.5

Zero-Scale Error

RESISTOR TERMINALS

Voltage Range⁶

V_A, V_B, V_W

C_A, C_B

GND

V_DD

V

pF

Capacitance A, B⁷

f = 1 MHz, measured to GND,

code = 0x80

f = 1 MHz, measured to GND,

code = 0x80

45

60

Capacitance W⁷

C_W

pF

Shutdown Supply Current⁸

Common-Mode Leakage

DIGITAL INPUTS AND OUTPUTS

Input Logic High

Input Logic Low

Input Logic High

Input Logic Low

Input Current

Input Capacitance

I_{A_SD}

I_CM

V_DD= 5.5 V

V_A= V_B= V_DD/2

0.01

1

µA

nA

V_IH

V_IL

V_IH

V_IL

I_IL

V_DD= 5 V

V_DD= 3 V

2.4

2.1

V

µA

pF

0.8

0.6

1

V_IN= 0 V or 5 V

C_IL

5

POWER SUPPLIES

Power Supply Range

Supply Current

Power Dissipation

Power Supply Sensitivity

DYNAMIC CHARACTERISTICS

Bandwidth, −3 dB

V_{DD RANGE}

I_DD

P_DISS

2.7

5.5

6

30

V

µA

µW

V_IH= 5 V or V_IL= 0 V

V_IH= 5 V or V_IL= 0 V, V_DD= 5 V

V_DD= 5 V 10%, code = midscale

3.5

PSS

0.02

0.08 %/%

BW

THD_W

R_AB= 10 kΩ/50 kΩ/100 kΩ, code = 0x80

V_A= 1 V rms, V_B= 0 V, f = 1 kHz,

R_AB= 10 kΩ

600/100/40

0.1

kHz

%

Total Harmonic Distortion

V_WSettling Time

Resistor Noise Voltage Density

t_S

e_{N_WB}

V_A= 5 V, V_B= 0 V, 1 LSB error band

R_WB= 5 kΩ, R_S= 0

2

9

µs

nV/√Hz

¹Typical specifications represent average readings at 25°C and V_DD= 5 V.

²Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic.

³V_A= V_DD, V_B= 0 V, wiper (V_W) = no connect.

⁴Specifications apply to all VRs.

⁵INL and DNL are measured at V_Wwith the RDAC configured as a potentiometer divider similar to a voltage output DAC. V_A= V_DDand V_B= 0 V.

DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions.

⁶Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.

⁷Guaranteed by design, but not subject to production test.

⁸Measured at the A terminal. The A terminal is open circuited in shutdown mode.

Rev. B | Page 4 of 20

Data Sheet

AD5243/AD5248

TIMING CHARACTERISTICS: ALL VERSIONS

V_DD= 5 V ꢀ1%, or 3 V ꢀ1%ꢁ V_A= V_DDꢁ V_B= 1 Vꢁ −41°C < T_A< +ꢀ25°Cꢁ unless otherwise noted.

Table 3.

Parameter

I²C INTERFACE TIMING CHARACTERISTICS¹

Symbol

Conditions

Min

Typ

Max

Unit

SCL Clock Frequency

Bus-Free Time Between Stop and Start, t_BUF

Hold Time (Repeated Start), t_HD;STA

f_SCL

t₁

t₂

0

1.3

0.6

400

kHz

μs

After this period, the first clock pulse is

generated.

Low Period of SCL Clock, t_LOW

High Period of SCL Clock, t_HIGH

t₃

t₄

t₅

t₆

t₇

t₈

t₉

t₁₀

1.3

0.6

μs

ns

μs

Setup Time for Repeated Start Condition, t_SU;STA

2

Data Hold Time, t_HD;DAT

0.9

Data Setup Time, t_SU;DAT

100

0.6

Fall Time of Both SDA and SCL Signals, t_F

Rise Time of Both SDA and SCL Signals, t_R

Setup Time for Stop Condition, t_SU;STO

300

¹See the timing diagrams for the locations of measured values (that is, see Figure 3 and Figure 45 to Figure 48).

²The maximum t_HD:DATmust be met only if the device does not stretch the low period (t_LOW) of the SCL signal.

t₂

t₈

t₆

t₉

SCL

SDA

t₁₀

t₄

t₇

t₅

t₂

t₃

t₉

t₈

t₁

P

S

P

Figure 3. I²C Interface Detailed Timing Diagram

Rev. B | Page 5 of 20

AD5243/AD5248

Data Sheet

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Table 4.

Parameter

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rating

V_DDto GND

V_A, V_B, V_Wto GND

Terminal Current, Ax to Bx, Ax to Wx, Bx to Wx¹

Pulsed

Continuous

Digital Inputs and Output Voltage to GND

Operating Temperature Range

Maximum Junction Temperature (T_JMAX

−0.3 V to +7 V

V_DD

20 mA

5 mA

0 V to 7 V

−40°C to +125°C

150°C

−65°C to +150°C

300°C

)

ESD CAUTION

Storage Temperature

Lead Temperature (Soldering, 10 sec)

Thermal Resistance, θ_JAfor 10-Lead MSOP²

230°C/W

¹The maximum terminal current is bound by the maximum current handling

of the switches, the maximum power dissipation of the package, and the

maximum applied voltage across any two of the A, B, and W terminals at a

given resistance.

²The package power dissipation is (T_JMAX− T_A)/θ_JA

.

Rev. B | Page 6 of 20

Data Sheet

AD5243/AD5248

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1

2

3

4

5

1

2

3

4

5

10

9

10

9

W1

B2

W1

B1

A1

B1

AD0

W2

B2

8

W2

AD5243

TOP VIEW

A2

AD5248

TOP VIEW

AD1

SDA

SCL

7

GND

SDA

SCL

GND

6

V

DD

Figure 4. AD5243 Pin Configuration

Figure 5. AD5248 Pin Configuration

Table 5. AD5243 Pin Function Descriptions

Table 6. AD5248 Pin Function Descriptions

No.

Mnemonic Description

1

B1

B1 Terminal.

1

B1

B1 Terminal.

2

3

4

5

A1

A1 Terminal.

W2 Terminal.

Digital Ground.

Positive Power Supply.

Serial Clock Input. Positive-edge

triggered.

Serial Data Input/Output.

A2 Terminal.

B2 Terminal.

2

AD0

Programmable Address Bit 0 for Multiple

Package Decoding.

W2 Terminal.

Digital Ground.

Positive Power Supply.

Serial Clock Input. Positive-edge

triggered.

Serial Data Input/Output.

Programmable Address Bit 1 for Multiple

Package Decoding.

B2 Terminal.

W1 Terminal.

W2

GND

V_DD

SCL

3

4

5

6

W2

GND

V_DD

6

SCL

7

8

9

10

SDA

A2

B2

7

8

SDA

AD1

W1

W1 Terminal.

9

10

B2

W1

Rev. B | Page 7 of 20

AD5243/AD5248

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

2.0

0.5

0.4

T

= 25°C

R

= 10kΩ

A

AB

R

= 10kΩ

AB

1.5

1.0

0.3

V

= 2.7V

DD

0.2

0.5

0.1

V

= 2.7V; T = –40°C, +25°C, +85°C, +125°C

A

DD

0

V

= 5.5V

DD

–0.1

–0.2

–0.3

–0.4

–0.5

–1.0

–1.5

–2.0

0

32

64

96

128

160

192

224

256

0

32

64

96

128

160

192

224

256

CODE (DECIMAL)

Figure 9. DNL vs. Code vs. Temperature

Figure 6. R-INL vs. Code vs. Supply Voltages

0.5

0.4

1.0

0.8

T

R

= 25°C

T

R

= 25°C

A

= 10kΩ

AB

0.3

0.6

0.2

0.4

V

= 2.7V

DD

V = 5.5V

DD

0.1

0.2

0

V

= 2.7V

–0.1

–0.2

–0.3

–0.4

–0.5

–0.2

–0.4

–0.6

–0.8

–1.0

DD

V

= 5.5V

DD

0

32

64

96

128

160

192

224

256

0

32

64

96

128

160

192

224

256

CODE (DECIMAL)

Figure 7. R-DNL vs. Code vs. Supply Voltages

Figure 10. INL vs. Code vs. Supply Voltages

0.5

0.4

0.5

0.4

= 10kΩ

T

R

= 25°C

R

A

AB

= 10kΩ

AB

0.3

V

= 5.5V

DD

T

= –40°C, +25°C, +85°C, +125°C

A

0.2

0.1

V

= 2.7V

DD

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.1

–0.2

–0.3

–0.4

–0.5

V

= 5.5V

DD

V

= 2.7V

DD

T

= –40°C, +25°C, +85°C, +125°C

A

0

32

64

96

128

160

192

224

256

0

32

64

96

128

160

192

224

256

CODE (DECIMAL)

Figure 8. INL vs. Code vs. Temperature

Figure 11. DNL vs. Code vs. Supply Voltages

Rev. B | Page 8 of 20

Data Sheet

AD5243/AD5248

2.0

4.50

3.75

3.00

2.25

1.50

0.75

0

R

= 10kΩ

R

= 10kΩ

AB

1.5

1.0

V

= 2.7V

DD

= –40°C, +25°C, +85°C, +125°C

T

A

0.5

0

V

= 2.7V, V = 2.7V

A

DD

V

= 5.5V

DD

= –40°C, +25°C, +85°C, +125°C

–0.5

–1.0

–1.5

–2.0

T

A

V

= 5.5V, V = 5.0V

A

DD

0

32

64

96

128

160

192

224

256

–40 –25 –10

5

20

35

50

65

80

95 110 125

CODE (DECIMAL)

TEMPERATURE (°C)

Figure 12. R-INL vs. Code vs. Temperature

Figure 15. Zero-Scale Error vs. Temperature

10

0.5

0.4

R

= 10kΩ

AB

0.3

V

= 5V

DD

0.2

V

= 2.7V, 5.5V; T = –40°C, +25°C, +85°C, +125°C

A

DD

0.1

1

0

–0.1

–0.2

–0.3

–0.4

–0.5

= 3V

DD

0.1

–40

0

32

64

96

128

160

192

224

256

–7

26

59

92

125

TEMPERATURE (°C)

CODE (DECIMAL)

Figure 13. R-DNL vs. Code vs. Temperature

Figure 16. Supply Current vs. Temperature

120

100

80

2.0

1.5

R

= 10kΩ

R

= 10kΩ

AB

1.0

0.5

60

V

= 2.7V

DD

= –40°C TO +85°C, –40°C TO +125°C

T

A

0

V

= 5.5V, V = 5.0V

A

DD

40

V

= 5.5V

DD

= –40°C TO +85°C, –40°C TO +125°C

–0.5

–1.0

–1.5

–2.0

T

A

20

V

= 2.7V, V = 2.7V

A

DD

0

–20

0

32

64

96

128

160

192

224

256

–40 –25 –10

5

20

35

50

65

80

95 110 125

CODE (DECIMAL)

TEMPERATURE (°C)

Figure 17. Rheostat Mode Tempco ΔR_WB/ΔT vs. Code

Figure 14. Full-Scale Error vs. Temperature

Rev. B | Page 9 of 20

AD5243/AD5248

Data Sheet

50

40

30

0

–6

R

= 10kΩ

AB

0x80

0x40

0x20

0x10

–12

–18

–24

–30

–36

–42

–48

–54

–60

V

T

= 2.7V

DD

= –40°C TO +85°C, –40°C TO +125°C

20

10

A

0x08

0x04

0x02

0x01

0

–10

–20

–30

V

= 5.5V

DD

= –40°C TO +85°C, –40°C TO +125°C

T

A

0

32

64

96

128

160

192

224

256

1k

10k

100k

FREQUENCY (Hz)

1M

CODE (DECIMAL)

Figure 18. Potentiometer Mode Tempco ΔV_WB/ΔT vs. Code

Figure 21. Gain vs. Frequency vs. Code, R_AB= 50 kΩ

0

–6

0

–6

0x80

0x40

0x20

0x40

0x20

0x10

–12

–18

–24

–30

–36

–42

–48

–54

–60

–12

–18

–24

–30

–36

–42

–48

–54

–60

0x10

0x08

0x04

0x02

0x01

0x08

0x04

0x02 0x01

10k

100k

FREQUENCY (Hz)

1M

10M

1k

10k

100k

FREQUENCY (Hz)

1M

Figure 19. Gain vs. Frequency vs. Code, R_AB= 2.5 kΩ

Figure 22. Gain vs. Frequency vs. Code, R_AB= 100 kΩ

0

–6

0

–6

0x80

0x40

–12

–18

–24

–30

–36

–42

–48

–54

–60

–12

–18

–24

–30

–36

–42

–48

–54

–60

100kΩ

60kHz

50kΩ

0x20

0x10

0x08

0x04

120kHz

10kΩ

570kHz

2.5kΩ

2.2MHz

0x02

0x01

1k

10k

100k

FREQUENCY (Hz)

1M

1k

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 20. Gain vs. Frequency vs. Code, R_AB= 10 kΩ

Figure 23. –3 dB Bandwidth at Code = 0x80

Rev. B | Page 10 of 20

Data Sheet

AD5243/AD5248

10

T

= 25°C

A

1

V

= 5.5V

DD

V

W2

0.1

V

= 2.7V

DD

W1

0.01

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

DIGITAL INPUT VOLTAGE (V)

Figure 24. Supply Current vs. Digital Input Voltage

Figure 27. Analog Crosstalk

V

W

SCL

Figure 25. Digital Feedthrough

Figure 28. Midscale Glitch, Code 0x80 to Code 0x7F

V

W

V

W2

SCL

W1

Figure 26. Digital Crosstalk

Figure 29. Large-Signal Settling Time

Rev. B | Page 11 of 20

AD5243/AD5248

TEST CIRCUITS

Data Sheet

Figure 30 through Figure 36 illustrate the test circuits that define the test conditions used in the product specification tables (see Table 1

and Table 2).

DUT

+15V

A

V+ = V

DD

1LSB = V+/2

DUT

W

N

V

IN

A

B

AD8610

–15V

V

B

OUT

V+

OFFSET

GND

V

MS

2.5V

Figure 30. Test Circuit for Potentiometer Divider Nonlinearity Error

(INL, DNL)

Figure 34. Test Circuit for Gain vs. Frequency

0.1V

R

=

SW

NO CONNECT

DUT

I

SW

CODE = 0x00

DUT

W

I

W

A

W

I

SW

0.1V

B

V

MS

V

TO V

DD

SS

Figure 31. Test Circuit for Resistor Position Nonlinearity Error

(Rheostat Operation: R-INL, R-DNL)

Figure 35. Test Circuit for Incremental On Resistance

NC

DUT

I

= V /R

DD NOMINAL

W

A

B

I

CM

A

B

V

DD

V

W

V

MS2

GND

V

R

= [V

MS1

– V ]/I

MS2 W

CM

W

V

MS1

NC NC = NO CONNECT

Figure 32. Test Circuit for Wiper Resistance

Figure 36. Test Circuit for Common-Mode Leakage Current

V

A

V+ = V ± 10%

DD

∆V

MS

DUT

W

PSRR (dB) = 20 LOG

(

)

DD

∆V

%

A

B

MS

DD

∆V

DD

PSS (%/%) =

V+

V

MS

Figure 33. Test Circuit for Power Supply Sensitivity (PSS, PSSR)

Rev. B | Page 12 of 20

Data Sheet

AD5243/AD5248

THEORY OF OPERATION

The general equation determining the digitally programmed

output resistance between W and B is

The AD5243/AD5248 are 256-position, digitally controlled

variable resistor (VR) devices.

D

256

An internal power-on preset places the wiper at midscale

during power-on, which simplifies the fault condition recovery

at power-up.

R

_WB(D) 

 R_AB 2 R_W

(1)

where:

D is the decimal equivalent of the binary code loaded in the

8-bit RDAC register.

PROGRAMMING THE VARIABLE RESISTOR AND

VOLTAGE

Rheostat Operation

R

_ABis the end-to-end resistance.

R_Wis the wiper resistance contributed by the on resistance of

The nominal resistance of the RDAC between Terminal A and

Terminal B is available in 2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ.

The nominal resistance (R_AB) of the VR has 256 contact points

accessed by the wiper terminal and the B terminal contact. The

8-bit data in the RDAC latch is decoded to select one of the 256

possible settings.

the internal switch.

In summary, if R_ABis 10 kΩ and the A terminal is open circuited,

the following output resistance, R_WB, is set for the indicated

RDAC latch codes.

Table 7. Codes and Corresponding R_WBResistance

D (Dec)

R_WB(Ω)

10,281

5380

359

Output State

A

255

128

1

Full scale (R_AB− 1 LSB + 2 × R_W)

Midscale

1 LSB + 2 × R_W

W

B

0

320

Zero scale (wiper contact resistance)

Figure 37. Rheostat Mode Configuration

Assuming that a 10 kΩ part is used, the first connection of the

wiper starts at the B terminal for Data 0x00. Because there is

a 160 Ω wiper contact resistance, such a connection yields a

minimum of 320 Ω (2 × 160 Ω) resistance between Terminal W

and Terminal B. The second connection is the first tap point,

which corresponds to 359 Ω (R_WB= R_AB/256 + 2 × R_W= 39 Ω +

2 × 160 Ω) for Data 0x01. The third connection is the next tap

point, representing 398 Ω (2 × 39 Ω + 2 × 160 Ω) for Data 0x02,

and so on. Each LSB data value increase moves the wiper up the

resistor ladder until the last tap point is reached at 10,281 Ω

(R_AB+ 2 × R_W).

Note that in the zero-scale condition, a finite wiper resistance of

320 Ω is present. Care should be taken to limit the current flow

between W and B in this state to a maximum pulse current of no

more than 20 mA. Otherwise, degradation or possible destruction

of the internal switch contact may occur.

Similar to the mechanical potentiometer, the resistance of the

RDAC between Wiper W and Terminal A also produces a

digitally controlled complementary resistance, R_WA. When these

terminals are used, the B terminal can be opened. Setting the

resistance value for R_WAstarts at a maximum value of resistance

and decreases as the data loaded in the latch increases in value.

The general equation for this operation is

A

R

S

256  D

256

R_WA(D) 

 R_AB 2 R_W

(2)

R

D7

D6

D5

D4

D3

D2

D1

D0

S

When R_ABis 10 kΩ and the B terminal is open circuited, the

output resistance, R_WA, is set according to the RDAC latch

codes, as listed in Table 8.

S

W

Table 8. Codes and Corresponding R_WAResistance

D (Dec)

R_WA(Ω)

Output State

255

128

1

359

5320

10,280

10,320

Full scale

Midscale

1 LSB + 2 × R_W

Zero scale

R

RDAC

S

LATCH

AND

DECODER

0

B

Typical device-to-device matching is process-lot dependent and

may vary by up to 30ꢀ. Because the resistance element is pro-

cessed in thin-film technology, the change in R_ABwith temperature

has a very low temperature coefficient of 35 ppm/°C.

Figure 38. AD5243 Equivalent RDAC Circuit

Rev. B | Page 13 of 20

AD5243/AD5248

Data Sheet

PROGRAMMING THE POTENTIOMETER DIVIDER

TERMINAL VOLTAGE OPERATING RANGE

Voltage Output Operation

The AD5243/AD5248 V_DDand GND power supply defines the

boundary conditions for proper 3-terminal digital potentiometer

operation. Supply signals present on the A, B, and W terminals

that exceed V_DDor GND are clamped by the internal forward-

biased diodes (see Figure 42).

The digital potentiometer easily generates a voltage divider at

wiper to B and wiper to A, proportional to the input voltage at

A to B. Unlike the polarity of V_DDto GND, which must be

positive, voltage across A to B, W to A, and W to B can be at

either polarity.

V

DD

V

I

A

W

B

W

V

O

B

GND

Figure 39. Potentiometer Mode Configuration

Figure 42. Maximum Terminal Voltages Set by V_DDand GND

If ignoring the effect of the wiper resistance for approximation,

connecting the A terminal to 5 V and the B terminal to ground

produces an output voltage at the wiper to B, starting at 0 V up

to 1 LSB less than 5 V. Each LSB of voltage is equal to the voltage

applied across Terminal A and Terminal B divided by the

256 positions of the potentiometer divider. The general equation

defining the output voltage at V_Wwith respect to ground for any

valid input voltage applied to Terminal A and Terminal B is

POWER-UP SEQUENCE

Because the ESD protection diodes limit the voltage compliance

at the A, B, and W terminals (see Figure 42), it is important to

power V_DD/GND before applying voltage to the A, B, and W

terminals; otherwise, the diode is forward-biased such that V_DD

is powered unintentionally and may affect the rest of the user’s

circuit. The ideal power-up sequence is in the following order:

GND, V_DD, digital inputs, and then V_A, V_B, and V_W. The relative

order of powering V_A, V_B, V_W, and the digital inputs is not

important, as long as they are powered after V_DD/GND.

D

256 − D

V_W(D) =

V_A+

V_B

(3)

256

Operation of the digital potentiometer in the divider mode

results in more accurate operation over temperature. Unlike in

the rheostat mode, the output voltage is dependent mainly on

the ratio of the internal resistors, R_WAand R_WB, not on the

absolute values. Therefore, the temperature drift reduces to

15 ppm/°C.

LAYOUT AND POWER SUPPLY BYPASSING

It is a good practice to employ compact, minimum lead length

layout design. The leads to the inputs should be as direct as

possible with a minimum conductor length. Ground paths

should have low resistance and low inductance.

Similarly, it is also good practice to bypass the power supplies with

quality capacitors for optimum stability. Supply leads to the device

should be bypassed with disc or chip ceramic capacitors of 0.01 µF

to 0.1 µF. Low ESR 1 µF to 10 µF tantalum or electrolytic capacitors

should also be applied at the supplies to minimize any transient

disturbance and low frequency ripple (see Figure 43). In addition,

note that the digital ground should be joined remotely to the

analog ground at one point to minimize the ground bounce.

ESD PROTECTION

All digital inputs are protected with a series of input resistors

and parallel Zener ESD structures, as shown in Figure 40 and

Figure 41. This applies to the SDA, SCL, AD0, and AD1 digital

input pins (AD5248 only).

340Ω

LOGIC

GND

Figure 40. ESD Protection of Digital Pins

V

DD

+

C3

10µF

C1

0.1µF

A, B, W

AD5243

GND

Figure 41. ESD Protection of Resistor Terminals

Figure 43. Power Supply Bypassing

Rev. B | Page 14 of 20

Data Sheet

AD5243/AD5248

This demonstrates that constantly biasing the potentiometer

can be a practical approach. Most portable devices do not

require the removal of batteries for the purpose of charging.

Although the resistance setting of the AD5243/AD5248 is lost

when the battery needs replacement, such events occur rather

infrequently such that this inconvenience is justified by the

lower cost and smaller size offered by the AD5243/AD5248. If

total power is lost, the user should be provided with a means to

adjust the setting accordingly.

CONSTANT BIAS TO RETAIN RESISTANCE SETTING

For users who desire nonvolatility but cannot justify the addi-

tional cost of an EEMEM, the AD5243/AD5248 can be considered

low cost alternatives by maintaining a constant bias to retain the

wiper setting. The AD5243/AD5248 are designed specifically for

low power applications, allowing low power consumption even

in battery-operated systems. The graph in Figure 44 demonstrates

the power consumption from a 3.4 V, 450 mAhr Li-Ion cell phone

battery connected to the AD5243/AD5248. The measurement

over time shows that the device draws approximately 1.3 µA

and consumes negligible power. Over a course of 30 days, the

battery is depleted by less than 2%, the majority of which is due

to the intrinsic leakage current of the battery itself.

110

108

T

= 25°C

A

106

104

102

100

98

96

94

92

90

0

5

10

15

20

25

30

DAYS

Figure 44. Battery Operating Life Depletion

Rev. B | Page 15 of 20

AD5243/AD5248

Data Sheet

I²C INTERFACE

I²C COMPATIBLE, 2-WIRE SERIAL BUS

The 2-wire, I²C-compatible serial bus protocol operates as follows:

SDA line must occur during the low period of SCL and

remain stable during the high period of SCL (see Figure 45

and Figure 46).

1. The master initiates data transfer by establishing a start

condition, which is when a high-to-low transition on the

SDA line occurs while SCL is high (see Figure 45). The

following byte is the slave address byte, which consists of

3. In the read mode, the data byte follows immediately after the

acknowledgment of the slave address byte. Data is transmitted

over the serial bus in sequences of nine clock pulses (a slight

difference with the write mode, where there are eight data bits

followed by an acknowledge bit). Similarly, the transitions

on the SDA line must occur during the low period of SCL and

remain stable during the high period of SCL (see Figure 47

and Figure 48).

the slave address followed by an R/ bit (this bit deter-

W

mines whether data is read from or written to the slave

device). The AD5243 has a fixed slave address byte,

whereas the AD5248 has two configurable address bits,

AD0 and AD1 (see Figure 10).

Note that the channel of interest is the one that is previously

selected in write mode. If users need to read the RDAC

values of both channels, they need to program the first

channel in write mode and then change to read mode to

read the first channel value. After that, the user must return

the device to write mode with the second channel selected

and read the second channel value in read mode. It is not

necessary for users to issue the Frame 3 data byte in write

mode for subsequent readback operation. Users should refer

to Figure 47 and Figure 48 for the programming format.

The slave whose address corresponds to the transmitted

address responds by pulling the SDA line low during the

ninth clock pulse (this is called the acknowledge bit). At

this stage, all other devices on the bus remain idle while the

selected device waits for data to be written to or read from

its serial register. If the R/ bit is high, the master reads

W

from the slave device. On the other hand, if the R/ bit is

W

low, the master writes to the slave device.

2. In the write mode, the second byte is the instruction byte.

The first bit (MSB) of the instruction byte is the RDAC

subaddress select bit. A logic low selects Channel 1 and a

logic high selects Channel 2.

4. After all data bits have been read or written, a stop condition

is established by the master. A stop condition is defined as

a low-to-high transition on the SDA line while SCL is high.

In write mode, the master pulls the SDA line high during

The second MSB, SD, is a shutdown bit. A logic high causes

an open circuit at Terminal A while shorting the wiper to

Terminal B. This operation yields almost 0 Ω in rheostat

mode or 0 V in potentiometer mode. It is important to

note that the shutdown operation does not disturb the

contents of the register. When the AD5243 or AD5248 is

brought out of shutdown, the previous setting is applied to

the RDAC. In addition, during shutdown, new settings can

be programmed. When the part is returned from shutdown,

the corresponding VR setting is applied to the RDAC.

^thclock pulse to establish a stop condition (see Figure

the 10

45 and Figure 46). In read mode, the master issues a no

acknowledge for the ninth clock pulse (that is, the SDA line

remains high). The master then brings the SDA line low

before the 10^thclock pulse, which goes high to establish a

stop condition (see Figure 47 and Figure 48).

A repeated write function provides the user with the flexibility

of updating the RDAC output multiple times after addressing

and instructing the part only once. For example, after the

RDAC has acknowledged its slave address and instruction

bytes in write mode, the RDAC output updates on each

successive byte. If different instructions are needed, however,

the write/read mode must restart with a new slave address,

instruction, and data byte. Similarly, a repeated read function

of the RDAC is also allowed.

The remainder of the bits in the instruction byte are don’t

care bits (see Figure 10).

After acknowledging the instruction byte, the last byte in

write mode is the data byte. Data is transmitted over the

serial bus in sequences of nine clock pulses (eight data bits

followed by an acknowledge bit). The transitions on the

Rev. B | Page 16 of 20

Data Sheet

AD5243/AD5248

Write Mode

Table 9. AD5243 Write Mode

S

0

1

0

1

W

A

A0 SD

X

A

D7 D6 D5 D4 D3 D2 D1 D0

A

P

Slave address byte

Instruction byte

Data byte

Table 10. AD5248 Write Mode

S

0

1

0

1

AD1 AD0

W

A

A0 SD

X

A

D7 D6 D5 D4 D3 D2 D1 D0

Slave address byte

Instruction byte

Data byte

Read Mode

Table 11. AD5243 Read Mode

S

0

1

0

1

R

A

D7

D6

D5

D4

D3

D2

D1

D0

A

P

Slave address byte

Data byte

Table 12. AD5248 Read Mode

S

0

1

0

1

AD1

AD0

R

A

D7

D6

D5

D4

D3

D2

D1

D0

A

P

Slave address byte

Data byte

Table 13. SDA Bits Descriptions

Bit

Description

S

P

A

Start condition.

Stop condition.

Acknowledge.

AD0, AD1

Package pin-programmable address bits.

X

Don’t care.

W

R

Write.

Read.

A0

SD

RDAC subaddress select bit.

Shutdown connects wiper to B terminal and open circuits the A terminal. It does not change the

contents of the wiper register.

D7, D6, D5, D4, D3, D2, D1, D0

Data bits.

Rev. B | Page 17 of 20

AD5243/AD5248

Data Sheet

I²C CONTROLLER PROGRAMMING

Write Bit Patterns

1

9

1

9

1

9

SCL

0

1

0

1

R/W

A0 SD

X

D7 D6 D5 D4 D3 D2 D1 D0

SDA

ACK BY

AD5243

ACK BY

AD5243

ACK BY

AD5243

START BY

MASTER

FRAME 2

INSTRUCTION BYTE

FRAME 3

DATA BYTE

STOP BY

MASTER

FRAME 1

SLAVE ADDRESS BYTE

Figure 45. Writing to the RDAC Register—AD5243

1

0

9

1

9

1

9

SCL

SDA

1

0

1

AD1 AD0 R/W

A0 SD

X

D7 D6 D5 D4 D3 D2 D1 D0

ACK BY

AD5248

ACK BY

AD5248

ACK BY

AD5248

START BY

MASTER

STOP BY

MASTER

FRAME 2

INSTRUCTION BYTE

FRAME 3

DATA BYTE

FRAME 1

SLAVE ADDRESS BYTE

Figure 46. Writing to the RDAC Register—AD5248

Read Bit Patterns

1

9

1

9

SCL

0

1

0

1

R/W

D7 D6 D5 D4 D3 D2 D1 D0

SDA

ACK BY

AD5243

NO ACK

BY MASTER

START BY

MASTER

FRAME 2

RDAC REGISTER

FRAME 1

SLAVE ADDRESS BYTE

STOP BY

MASTER

Figure 47. Reading Data from a Previously Selected RDAC Register in Write Mode—AD5243

1

0

9

1

9

SCL

SDA

1

0

1

AD1 AD0 R/W

D7 D6 D5 D4 D3 D2 D1 D0

NO ACK

BY MASTER

ACK BY

AD5248

START BY

MASTER

FRAME 2

RDAC REGISTER

STOP BY

MASTER

FRAME 1

SLAVE ADDRESS BYTE

Figure 48. Reading Data from a Previously Selected RDAC Register in Write Mode—AD5248

5V

Multiple Devices on One Bus (Applies Only to AD5248)

R

P

Figure 49 shows four AD5248 devices on the same serial bus.

Each has a different slave address because the states of their

AD0 and AD1 pins are different. This allows each device on the

bus to be written to or read from independently. The master

device output bus line drivers are open-drain pull-downs in a

fully I²C-compatible interface.

SDA

SCL

MASTER

5V

SDA SCL

AD1

SDA SCL

AD1

SDA SCL

AD1

SDA SCL

AD1

AD0

AD5248

Figure 49. Multiple AD5248 Devices on One I²C Bus

Rev. B | Page 18 of 20

Data Sheet

AD5243/AD5248

OUTLINE DIMENSIONS

3.10

3.00

2.90

10

1

6

5

5.15

4.90

4.65

3.10

3.00

2.90

PIN 1

IDENTIFIER

0.50 BSC

0.95

0.85

0.75

15° MAX

1.10 MAX

0.70

0.55

0.40

0.15

0.05

0.23

0.13

6°

0°

0.30

0.15

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-BA

Figure 50. 10-Lead Mini Small Outline Package [MSOP]

(RM-10)

Dimensions shown in millimeters

ORDERING GUIDE

Model^{1, 2}

R_AB

Temperature

Package Description

Package Option

Branding

D0L

AD5243BRM2.5

AD5243BRM10

AD5243BRM10-RL7

AD5243BRM50

AD5243BRM50-RL7

AD5243BRM100

AD5243BRM100-RL7

AD5243BRMZ2.5

AD5243BRMZ2.5-RL7

AD5243BRMZ10

AD5243BRMZ10-RL7

AD5243BRMZ50

AD5243BRMZ50-RL7

AD5243BRMZ100

AD5243BRMZ100-RL7

EVAL-AD5243SDZ

AD5248BRM2.5

AD5248BRM2.5-RL7

AD5248BRM10

AD5248BRM10-RL7

AD5248BRM50

AD5248BRM50-RL7

AD5248BRM100

AD5248BRM100-RL7

AD5248BRMZ2.5

AD5248BRMZ2.5-RL7

AD5248BRMZ10

AD5248BRMZ10-RL7

AD5248BRMZ50

AD5248BRMZ50-RL7

AD5248BRMZ100

AD5248BRMZ100-RL7

2.5 kΩ

10 kΩ

50 kΩ

100 kΩ

2.5 kΩ

10 kΩ

50 kΩ

100 kΩ

−40°C to +125°C

10-Lead MSOP

Evaluation Board

10-Lead MSOP

RM-10

D0M

D0N

D0P

D9X

D0M

D0N

D0P

2.5 kΩ

10 kΩ

50 kΩ

100 kΩ

2.5 kΩ

10 kΩ

50 kΩ

100 kΩ

−40°C to +125°C

RM-10

D1F

D1G

D1H

D1J

D1F

D8Z

D90

D91

¹Z = RoHS Compliant Part.

²The evaluation board is shipped with the 10 kΩ R_ABresistor option; however, the board is compatible with all available resistor value options.

Rev. B | Page 19 of 20

AD5243/AD5248

NOTES

Data Sheet

Purchase of licensed I²C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I²C

Patent Rights to use these components in an I²C system, provided that the system conforms to the I²C Standard Specification as defined by Philips.

registered trademarks are the property of their respective owners.

D04109-0-4/12(B)

Rev. B | Page 20 of 20


型号：	AD5248BRMZ2.5-RL7
厂家：	ADI
描述：	Dual, 256-Position, I2C-Compatible Digital Potentiometers 双通道， 256位， I2C兼容数字电位器转换器电位器数字电位计电阻器光电二极管
文件：	总20页 (文件大小：803K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD5248BRMZ2.5-RL7 [ADI]

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