AD5220BRM10_技术文档

Increment/Decrement

Digital Potentiometer

a

AD5220

FEATURES

FUNCTIONAL BLOCK DIAGRAM

128 Position

Potentiometer Replacement

10 k⍀, 50 k⍀, 100 k⍀

Very Low Power: 40 ␮A Max

Increment/Decrement Count Control

V

DD

CLK

D

E

C

O

D

E

A

CS

EN

UP/

DOWN

CNTR

7

W

B

APPLICATIONS

U/D

RS

GND

POR

40

Mechanical Potentiometer Replacement

Remote Incremental Adjustment Applications

Instrumentation: Gain, Offset Adjustment

Programmable Voltage-to-Current Conversion

Programmable Filters, Delays, Time Constants

Line Impedance Matching

H

AD5220

+5V

CS

UP/DOWN

Power Supply Adjustment

U/D

CLK

GENERAL DESCRIPTION

The AD5220 provides a single channel, 128-position digitally

controlled variable resistor (VR) device. This device performs

the same electronic adjustment function as a potentiometer or

variable resistor. These products were optimized for instrument

and test equipment push-button applications. A choice between

bandwidth or power dissipation are available as a result of the

wide selection of end-to-end terminal resistance values.

INCREMENT

AD5220

Figure 1. Typical Push-Button Control Application

UPCOUNT DETAIL

The AD5220 contains a fixed resistor with a wiper contact that

taps the fixed resistor value at a point determined by a digitally

controlled UP/DOWN counter. The resistance between the

wiper and either end point of the fixed resistor provides a con-

stant resistance step size that is equal to the end-to-end resis-

tance divided by the number of positions (e.g., R_STEP= 10 kΩ/

128 = 78 Ω). The variable resistor offers a true adjustable value

of resistance, between the A terminal and the wiper, or the B

terminal and the wiper. The fixed A-to-B terminal resistance of

10 kΩ, 50 kΩ, or 100 kΩ has a nominal temperature coefficient

of 800 ppm/°C.

V

= 5.5V

= 0V

DD

A

V

WB

50mV/DIV

B

f = 100kHz

CLK

5V/DIV

Figure 2a. Stair-Step Increment Output

The chip select CS, count CLK and U/D direction control

inputs set the variable resistor position. These inputs that con-

trol the internal UP/DOWN counter can be easily generated

with mechanical or push button switches (or other contact closure

devices). External debounce circuitry is required for the nega-

tive-edge sensitive CLK pin. This simple digital interface elimi-

nates the need for microcontrollers in front panel interface designs.

V

= 5.5V

= 0V

COUNT

DD

00 v 3F v 00

H

A

B

f = 60kHz

V

WR

The AD5220 is available in both surface mount (SO-8) and the

8-lead plastic DIP package. For ultracompact solutions selected

models are available in the thin µSOIC package. All parts are

guaranteed to operate over the extended industrial temperature

range of –40°C to +85°C. For 3-wire, SPI compatible inter-

face applications, see the AD7376/AD8400/AD8402/AD8403

products.

f

= 60kHz

CLK

Figure 2b. Full-Scale Up/Down Count

REV. 0

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

AD5220–SPECIFICATIONS

(V_DD= +3 V ؎ 10% or +5 V ؎ 10%, V_A= +V_DD, V_B= 0 V, –40؇C < T_A< +85؇C unless

otherwise noted)

ELECTRICAL CHARACTERISTICS

Parameter

Symbol

Conditions

Min

Typ¹

Max

Units

DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs

Resistor Differential NL²

R-DNL

R_WB, V_A= NC, R_AB= 10 kΩ

R_WB, V_A= NC, R_AB= 50 kΩ or 100 kΩ

R_WB, V_A= NC, R_AB= 10 kΩ

R_WB, V_A= NC, R_AB= 50 kΩ or 100 kΩ

T_A= +25°C

–1

–0.5

–1

–0.5

–30

±0.4

±0.1

±0.5

±0.1

+1

+0.5

+1

+0.5

+30

LSB

%

Resistor Nonlinearity²

R-INL

Nominal Resistor Tolerance

Resistance Temperature Coefficient

Wiper Resistance

∆R

∆R_AB/∆T

R_W

V_AB= V_DD, Wiper = No Connect

I_W= V_DD/R, V_DD= +3 V or +5 V

800

40

ppm/°C

Ω

100

DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications Apply to All VRs

Resolution

N

INL

7

–1

–0.5

–1

–0.5

Bits

Integral Nonlinearity³

R_AB= 10 kΩ

R_AB= 50 kΩ, 100 kΩ

R_AB= 10 kΩ

R_AB= 50 kΩ, 100 kΩ

Code = 40_H

Code = 7F_H

±0.5

±0.2

±0.4

±0.1

20

+1

+0.5

+1

LSB

ppm/°C

LSB

Differential Nonlinearity Error³

DNL

+0.5

Voltage Divider Temperature Coefficient ∆V_W/∆T

Full-Scale Error

Zero-Scale Error

V_WFSE

V_WZSE

–2

0

–0.5

+0.5

0

+1

Code = 00_H

RESISTOR TERMINALS

Voltage Range⁴

V_A,V_B,V_W

C_A,C_B

C_W

0

V_DD

V

Capacitance⁵A, B

f = 1 MHz, Measured to GND, Code = 40_H

V_A= V_B= V_W

10

48

7.5

pF

nA

Capacitance⁵W

Common-Mode Leakage

I_CM

DIGITAL INPUTS AND OUTPUTS

Input Logic High

Input Logic Low

V_IH

V_IL

I_IL

V_DD= +5 V/+3 V

V_IN= 0 V or +5 V

2.4/2.1

2.7

V

µA

pF

0.8/0.6

±1

Input Current

Input Capacitance⁵

C_IL

5

POWER SUPPLIES

Power Supply Range

Supply Current

V_DD

I_DD

P_DISS

PSS

5.5

40

200

0.015

V

µA

µW

%/%

V_IH= +5 V or V_IL= 0 V, V_DD= +5 V

15

75

0.004

Power Dissipation⁶

Power Supply Sensitivity

DYNAMIC CHARACTERISTICS^{5, 7, 8}

Bandwidth –3 dB

BW_10K

BW_50K

R_AB= 10 kΩ, Code = 40_H

R_AB= 50 kΩ, Code = 40_H

650

142

69

kHz

%

BW_100K R_AB= 100 kΩ, Code = 40_H

THD_W

t_S

Total Harmonic Distortion

V_WSettling Time

V_A=1 V rms + 2.5 V dc, V_B= 2.5 V dc, f = 1 kHz

V_A= V_DD, V_B= 0 V, 50% of Final Value,

10K/50K/100K

0.002

0.6/3/6

14

µs

nV/√Hz

Resistor Noise Voltage

e_NWB

R_WB= 5 kΩ, f = 1 kHz

INTERFACE TIMING CHARACTERISTICS Applies to All Parts^{5, 9}

Input Clock Pulsewidth

CS to CLK Setup Time

CS Rise to Clock Hold Time

U/D to Clock Fall Setup Time

t_CH, t_CL

t_CSS

t_CSH

Clock Level High or Low

25

20

10

ns

t_UDS

NOTES

¹Typicals represent average readings at +25°C and V_DD= +5 V.

²Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 29 test circuit.

³INL and DNL are measured at V_Wwith the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V_A= V_DDand V_B= 0 V.

DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See Figure 28 test circuit.

⁴Resistor terminals A, B, W have no limitations on polarity with respect to each other.

⁵Guaranteed by design and not subject to production test.

⁶P_DISSis calculated from (I_DD× V_DD). CMOS logic level inputs result in minimum power dissipation.

⁷Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest band-

width. The highest R value results in the minimum overall power consumption.

⁸All dynamic characteristics use V_DD= +5 V.

⁹See timing diagrams for location of measured values. All input control voltages are specified with t_R= t_F= 1 ns (10% to 90% of V_DD) and timed from a voltage level

of 1.6 V. Switching characteristics are measured using both V_DD= +3 V or +5 V.

Specifications subject to change without notice.

–2–

REV. 0

AD5220

ABSOLUTE MAXIMUM RATINGS*

(T_A= +25°C, unless otherwise noted)

PIN CONFIGURATION

V_DDto GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V

V_A, V_B, V_Wto GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, V_DD

A_X–B_X, A_X–W_X, B_X–W_X. . . . . . . . . . . . . . . . . . . . . . ±20 mA

Digital Input Voltage to GND . . . . . . . . . . . 0 V, V_DD+ 0.3 V

Operating Temperature Range . . . . . . . . . . . –40°C to +85°C

Maximum Junction Temperature (T_JMAX) . . . . . . . .+150°C

Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . .+300°C

Package Power Dissipation . . . . . . . . . . . . . . (T_Jmax–T_A)/θ_JA

Thermal Resistance θ_JA

1

2

3

4

8

7

6

5

V

CLK

DD

AD5220

TOP VIEW

(Not to Scale)

U/D

A1

CS

B1

W1

GND

P-DIP (N-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103°C/W

SOIC (SO-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158°C/W

µSOIC (RM-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W

*Stresses above those listed under Absolute Maximum Ratings may cause

permanent damage to the device. This is a stress rating only; functional operation

of the device at these or any other conditions above those indicated in the

operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

PIN FUNCTION DESCRIPTIONS

Description

No. Name

1

2

3

4

5

6

7

8

CLK

U/D

A1

Serial Clock Input, Negative Edge Triggered

UP/DOWN Direction Increment Control

Terminal A1

Table I. Truth Table

CS

CLK U/D

Operation

L

H

t

H

L

Wiper Increment Toward Terminal A

Wiper Decrement Toward Terminal B

Wiper Position Fixed

GND

W1

Ground

Wiper Terminal

X

B1

Terminal B1

CS

Chip Select Input, Active Low

Positive Power Supply

V_DD

1

0

CS

t_CSS

t_CL

t_CH

t_CSH

1

0

CLK

t_UDS

1

0

U/D

Figure 3. Detail Timing Diagram

ORDERING GUIDE

Package Descriptions

Model

k⍀

Temperature Range

Package Options

AD5220BN10

AD5220BR10

AD5220BRM10

AD5220BN50

AD5220BR50

AD5220BRM50

AD5220BN100

AD5220BR100

AD5220BRM100

10

50

100

–40°C to +85°C

8-Lead Plastic DIP

8-Lead (SOIC)

8-Lead µSOIC

8-Lead Plastic DIP

8-Lead (SOIC)

8-Lead µSOIC

8-Lead Plastic DIP

8-Lead (SOIC)

8-Lead µSOIC

N-8

SO-8

RM-8

N-8

SO-8

RM-8

N-8

SO-8

RM-8

NOTE

The AD5220 die size is 37 mil × 54 mil, 1998 sq mil; 0.938 mm × 1.372 mm, 1.289 sq mm. Contains 754 transistors. Patent Number 5495245 applies.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD5220 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD

WARNING!

ESD SENSITIVE DEVICE

precautions are recommended to avoid performance degradation or loss of functionality.

REV. 0

–3–

–Typical Performance Characteristics

AD5220

48

40

32

24

16

6

100

SS = 300 UNITS

V

R

= 5.5V

= 50k⍀

DD

V

= +2.7V

DD

AB

T

= +25؇C

5

4

3

2

1

0

A

75

50

7F

H

25

40

H

08

H

01

8

0

20

H

02

H

04

H

10

R

H

WB

WA

0

20

40

60

80

100

– ␮A

120

20

28

36

44

52

60

32

64

96

128

CONDUCTION CURRENT, I

WIPER RESISTANCE – ⍀

WB

CODE – Decimal

Figure 4. Wiper to End Terminal

Resistance vs. Code

Figure 5. Resistance Linearity vs.

Conduction Current

Figure 6. Wiper Contact Resistance

0.5

0.4

T

V

= +25؇C

T

V

= +25؇C

A

0.4

0.3

0.4

0.3

= +5.5V

DD

0.3

0.2

10k⍀ VERSION

100k⍀ VERSION

50k⍀ VERSION

0.2

50k⍀ VERSION

0.2

100k⍀ VERSION

50k⍀ VERSION

0.1

0.0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.1

–0.2

–0.3

–0.4

–0.5

–0.1

–0.2

–0.3

–0.4

–0.5

T

= +25؇C

A

V

= +5.5V

DD

10k⍀ VERSION

= +5.5V

= 0V

100k⍀ VERSION

A

B

10k⍀ VERSION

0

16

32

48

64

80 96 112 128

0

16

32

48

64

80 96 112 128

16

32

48

64

80 96 112 128

CODE – Decimal

Figure 7. R-DNL Relative Resistance

Step Position Nonlinearity Error vs.

Code

Figure 8. R-INL Resistance Non-

linearity Error vs. Supply Voltage

Figure 9. Potentiometer Divider INL

Error vs. Code

100

0.5

0.600

T

= +25؇C

CODE = 40

H

A

0.4

0.3

V

= +5.5V

R

= 50k⍀

DD

AB

A

0.525

0.450

0.375

0.300

0.255

0.150

100k⍀ VERSION

= +5.5V

= 0V

V

= V

A

B

DD

80

0.2

100k⍀ VERSION

50k⍀ VERSION

60

0.1

0.0

50k⍀ VERSION

40

–0.1

–0.2

–0.3

–0.4

–0.5

20

10k⍀ VERSION

0.075

0.000

10k⍀ VERSION

0

–40

–15

10

35

60

85

0

16

32

48

64

80 96 112 128

2.00 2.50 3.00 3.50 4.00 4.50 5.00 5.50 6.00

TEMPERATURE – ؇C

CODE – Decimal

SUPPLY VOLTAGE – V

Figure 10. Potentiometer Divider

DNL Error vs. Code

Figure 11. Potentiometer Divider

INL Error vs. Supply Voltage

Figure 12. Nominal Resistance vs.

Temperature

–4–

REV. 0

AD5220

6

0

60

53

46

39

32

25

18

11

4

60

53

46

39

32

25

18

11

4

00

H

–55؇C < T < +85؇C

A

V

= +5.5V

V

= +5.5V

DD

R

MEASURED

40

H

WB

–6

–12

–18

–24

–30

–36

–42

V

= NO CONNECT

A

20

10

08

04

H

10k⍀ VERSION

H

50k⍀ AND 100k⍀ VERSION

02

01

H

DATA = 40_H

V_DD= +5V

–

+

A

B

W

OP42

V_IN= V = 100mV rms

–3

–10

–3

–10

–48

–54

A

+

–

2.5V

V_B= +2.5V

0

16

32

48

64

80 96 112 128

16

32

48

64

80 96 112 128

1k

10k

100k

1M

FREQUENCY – Hz

CODE – Decimal

Figure 15. 10 kΩ Gain vs. Frequency

vs. Code

Figure 13. ∆V_WB/∆T Potentiometer

Mode Tempco (10 kΩ and 50 kΩ)

Figure 14. ∆R_WB/∆T Rheostat

6

00

H

00

H

0

40

20

10

08

H

40

–6

–12

–18

–24

–30

–36

–42

H

–6

–12

–18

–24

–30

–36

–42

20

H

10

08

04

02

01

04

02

01

H

20mV/

DIV

V

WB

V

= +5.5V

DD

DATA = 40

H

–

+

–

+

= V = 0V

A

B

A

B

A

B

V

= +5V

W

V

= +5V

W

DD

OP42

f = 100kHz

–48

–54

–48

–54

= V = 100mV rms

A

= V = 100mV rms

A

IN

B

+

–

IN

B

+

–

2.5V

= +2.5V

1k

10k

100k

FREQUENCY – Hz

1M

1k

10k

100k

1M

TIME 2␮s / DIV

FREQUENCY – Hz

Figure 18. Digital Feedthrough

Figure 16. 50 kΩ Gain vs. Frequency

Figure 17. 100 kΩ Gain vs. Fre-

vs. Code

quency vs. Code

1.00

–5.8

–5.9

T

V

= +25؇C

A

10k⍀

50k⍀

= +5.0V

DD

OFFSET GND = +2.5V

= 10k⍀

–6.0

–6.1

0.10

0.01

R

AB

100k⍀

DATA = 40

H

150mV

–6.2

–6.3

V

= +5V

DD

NONINVERTING

TEST CKT 32

= V = 50mV rms

IN

B

100mV

A

V

WB

= +2.5V

–

50mV

0mV

–6.4

–6.5

A

W

+

V

= +5.5V DATA

DD

OP42

B

0.001

0.0001

40 v 3F

+

–

= +5.5V

= 0V

H

A

B

2.5V

–6.6

INVERTING

TEST CKT 31

5V

0V

f = 100kHz

–6.7

–6.8

CLK

100k

10

100

1k

FREQUENCY – Hz

10k

10

100

1k

10k

100k

1M

TIME 500ns / DIV

FREQUENCY – Hz

Figure 20. Total Harmonic Distortion

Plus Noise vs. Frequency

Figure 19. Midscale Transition Glitch

Figure 21. Normalized Gain Flatness

vs. Frequency

REV. 0

–5–

AD5220

80

60

40

20

0

80

400

350

300

T

= +25؇C

A

DATA = 3F

H

SEE FIGURE 34

FOR TEST CIRCUIT

V

T

= 0V

= +25؇C

B

A

60

40

V

= +2.7V

DD

250

200

V

= +5.5V

DD

A

V

= +5.5V

DD

150

100

V

= +2.7V

DD

V

T

= +5V DC ؎1V p-p AC

DD

= +25؇C

A

= +2.7V

A

20

0

CODE = 40

H

C

= 10pF

L

50

0

V

= 4V, V = 0V

A

B

0

1

2

3

4

5

6

1k

10k

100k

1M

1k

10k

100k

1M

10M

V

– Volts

B

FREQUENCY – Hz

CLOCK FREQUENCY – Hz

Figure 24. Incremental Wiper

Contact Resistance vs. V_B

Figure 22. Power Supply Rejection

vs. Frequency

Figure 23. I_DDSupply Current vs.

Clock Frequency

0.10

10

T

= +25؇C

LOGIC = 0V OR V

DD

A

ALL LOGIC INPUT

PINS TIED TOGETHER

V

= +5.5V

D

1

0.1

V

= +5V

DD

0.01

V

= +3V

DD

V

= +3.3V

DD

0.001

0.01

0.001

0.0001

0

1.0

2.0

3.0

4.0

5.0

–40

–15

10

35

60

85

DIGITAL INPUT VOLTAGE – V

TEMPERATURE – ؇C

Figure 25. Supply Current vs. Tem-

perature I_DD

Figure 26. Supply Current vs. Input

Logic Voltage

–6–

REV. 0

Parametric Test Circuits–

AD5220

A

B

DUT

+5V

V+ = V

W

DUT

A

DD

V

~

IN

1LSB = V+/128

V

W

OP279

OUT

V+

OFFSET

GND

B

V

2.5V DC

MS

Figure 27. Potentiometer Divider Nonlinearity Error Test

Circuit (INL, DNL)

Figure 31. Inverting Programmable Gain Test Circuit

+5V

NO CONNECT

DUT

V

OP279

OUT

W

I

V

W

~

IN

A

W

OFFSET

GND

B

DUT

A

B

2.5V

V

MS

Figure 28. Resistor Position Nonlinearity Error (Rheostat

Operation; R-INL, R-DNL)

Figure 32. Noninverting Programmable Gain Test Circuit

+15V

A

W

I

=

V

/R

DD

NOMINAL

DUT

W

V

DUT

~

IN

A

V

W

V

OP42

OUT

V

B

OFFSET

GND

MS2

B

2.5V

R

= [V

– V

]/I

MS2

V

MS1

W

MS1

–15V

Figure 29. Wiper Resistance Test Circuit

Figure 33. Gain vs. Frequency Test Circuit

0.1V

V

A

R

=

SW

I

DUT

SW

V+ = V ± 10%

DD

CODE = ØØ

H

⌬V

W

MS

A

B

V

DD

PSRR (dB) = 20 LOG

⌬V

PSS (%/%) = –––––––

⌬V

(

–––––

)

W

⌬V

V+

~

B

DD

0.1V

I

%

SW

MS

V

MS

%

DD

0 TO V

DD

Figure 30. Power Supply Sensitivity Test Circuit (PSS,

PSRR)

Figure 34. Incremental ON Resistance Test Circuit

REV. 0

–7–

AD5220

OPERATION

Ax

R

The AD5220 provides a 128-position digitally controlled vari-

able resistor (VR) device. Changing the VR settings is accom-

plished by pulsing the CLK pin while CS is active low. The

direction of the increment is controlled by the U/D (UP/DOWN)

control input pin. When the wiper hits the end of the resistor

(Terminals A or B) additional CLK pulses no longer change

the wiper setting. The wiper position is immediately decoded

by the wiper decode logic changing the wiper resistance. Ap-

propriate debounce circuitry is required when push button

switches are used to control the count sequence and direction

of count. The exact timing requirements are shown in Figure 3.

The AD5220 powers ON in a centered wiper position exhibit-

S

D0

D1

D2

D3

D4

D5

D6

S

Wx

RDAC

UP/DOWN

CNTR

&

DECODE

R

S

Bx

ing nearly equal resistances of R_WAand R_WB

.

= R

/128

S

NOMINAL

Figure 38. AD5220 Equivalent RDAC Circuit

V

DD

CLK

D

A

EN

PROGRAMMING THE VARIABLE RESISTOR

CS

E

C

O

D

E

UP/

DOWN

CNTR

7

W

Rheostat Operation

The nominal resistance of the RDAC between terminals A and

B is available with values of 10 kΩ, 50 kΩ, and 100 kΩ. The

final three characters of the part number determine the nominal

resistance value, e.g., 10 kΩ =10; 50 kΩ = 50; 100 kΩ = 100.

The nominal resistance (R_AB) of the VR has 128 contact points

accessed by the wiper terminal, plus the B terminal contact. At

power ON the resistance from the wiper to either end Terminal

A or B is approximately equal. Clocking the CLK pin will in-

crease the resistance from the Wiper W to Terminal B by one

unit of R_Sresistance (see Figure 38). The resistance R_WBis

determined by the number of pulses applied to the clock pin.

Each segment of the internal resistor string has a nominal resis-

tance value of R_S= R_AB/128, which becomes 78 Ω in the case of

the 10 kΩ AD5220BN10 product. Care should be taken to limit

the current flow between W and B in the direct contact state to

a maximum value of 5 mA to avoid degradation or possible de-

struction of the internal switch contact.

B

U/D

RS

GND

POR

40

H

AD5220

Figure 35. Block Diagram

DIGITAL INTERFACING OPERATION

The AD5220 contains a three-wire serial input interface. The

three inputs are clock (CLK), CS and UP/DOWN (U/D). The

negative-edge sensitive CLK input requires clean transitions to

avoid clocking multiple pulses into the internal UP/DOWN

counter register, see Figure 35. Standard logic families work

well. If mechanical switches are used for product evaluation

they should be debounced by a flip-flop or other suitable

means. When CS is taken active low the clock begins to incre-

ment or decrement the internal UP/DOWN counter dependent

upon the state of the U/D control pin. The UP/DOWN counter

value (D) starts at 40_Hat system power ON. Each new CLK

pulse will increment the value of the internal counter by one

LSB until the full scale value of 3F_His reached as long as the

U/D pin is logic high. If the U/D pin is taken to logic low the

counter will count down stopping at code 00_H(zero-scale).

Additional clock pulses on the CLK pin are ignored when the

wiper is at either the 00_Hposition or the 3F_Hposition.

Like the mechanical potentiometer the RDAC replaces, it is

totally symmetrical (see Figure 38). The resistance between the

Wiper W and Terminal A also produces a digitally controlled

resistance R_WA. When these terminals are used the B–terminal

should be tied to the wiper.

The typical part-to-part distribution of R_BAis process lot depen-

dent having a ±30% variation. The change in R_BAwith tempera-

ture has a 800 ppm/°C temperature coefficient.

All digital inputs (CS, U/D, CLK) are protected with a series

input resistor and parallel Zener ESD structure shown in

Figure 36.

The R_BAtemperature coefficient increases as the wiper is pro-

grammed near the B-terminal due to the larger percentage con-

tribution of the wiper contact switch resistance, which has a

0.5%/°C temperature coefficient. Figure 14 shows the effect of

the wiper contact resistance as a function of code setting. An-

other performance factor influenced by the switch contact resis-

tance is the relative linearity error performance between the

10 kΩ, and the 50 kΩ or 100 kΩ versions. The same switch

contact resistance is used in all three versions. Thus the perfor-

mance of the 50 kΩ and 100 kΩ devices which have the least

impact on wiper switch resistance exhibits the best linearity

error, see Figures 7 and 8.

1k⍀

LOGIC

Figure 36. Equivalent ESD Protection Digital Pins

20⍀

A, B, W

GND

Figure 37. Equivalent ESD Protection Analog Pins

–8–

REV. 0

AD5220

PROGRAMMING THE POTENTIOMETER DIVIDER

Voltage Output Operation

APPLICATIONS INFORMATION

The negative-edge sensitive CLK pin does not contain any

internal debounce circuitry. This standard CMOS logic input

responds to fast negative edges and needs to be debounced

externally with an appropriate circuit designed for the type of

switch closure device being used. Good performance results at

the CLK input pin when the negative logic transition has a

minimum slew rate of 1 V/µs. A wide variety of standard circuits

can be used such as a one-shot multivibrator, Schmitt Triggered

gates, cross coupled flip-flops, or RC filters to drive the CLK

pin with uniform negative edges. This will prevent the digital

potentiometer from skipping output codes while counting due to

switch contact bounce.

The digital potentiometer easily generates an output voltage

proportional to the input voltage applied to a given terminal.

For example connecting A Terminal to +5 V and B Terminal to

ground produces an output voltage at the wiper which can be

any value starting at zero volts up to 1 LSB less than +5 V. Each

LSB of voltage is equal to the voltage applied across terminals

AB divided by the 128-position resolution of the potentiometer

divider. The general equation defining the output voltage with

respect to ground for any given input voltage applied to termi-

nals AB is:

V_W(D) = D/128 × V_AB+ V_B

(1)

D represents the current contents of the internal UP/DOWN

counter.

Operation of the digital potentiometer in the divider mode re-

sults in more accurate operation over temperature. Here the

output voltage is dependent on the ratio of the internal resistors,

not the absolute value, therefore, the drift improves to 20 ppm/°C.

REV. 0

–9–

AD5220

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

8-Lead Plastic DIP

(N-8)

0.430 (10.92)

0.348 (8.84)

8

5

0.280 (7.11)

0.240 (6.10)

1

4

0.325 (8.25)

0.300 (7.62)

0.060 (1.52)

0.015 (0.38)

PIN 1

0.195 (4.95)

0.115 (2.93)

0.210 (5.33)

MAX

0.130

(3.30)

MIN

0.160 (4.06)

0.115 (2.93)

0.015 (0.381)

0.008 (0.204)

SEATING

PLANE

0.100

(2.54)

BSC

0.022 (0.558)

0.014 (0.356)

0.070 (1.77)

0.045 (1.15)

8-Lead SOIC

(SO-8)

0.1968 (5.00)

0.1890 (4.80)

8

1

5

4

0.1574 (4.00)

0.1497 (3.80)

0.2440 (6.20)

0.2284 (5.80)

PIN 1

0.0688 (1.75)

0.0532 (1.35)

0.0196 (0.50)

؋

45؇

0.0098 (0.25)

0.0040 (0.10)

0.0099 (0.25)

8؇

0؇

0.0500

(1.27)

BSC

0.0192 (0.49)

0.0138 (0.35)

SEATING

PLANE

0.0098 (0.25)

0.0075 (0.19)

0.0500 (1.27)

0.0160 (0.41)

8-Lead ␮SOIC

(RM-8)

0.122 (3.10)

0.114 (2.90)

8

5

4

0.122 (3.10)

0.114 (2.90)

0.199 (5.05)

0.187 (4.75)

1

PIN 1

0.0256 (0.65) BSC

0.120 (3.05)

0.112 (2.84)

0.120 (3.05)

0.112 (2.84)

0.043 (1.09)

0.037 (0.94)

0.006 (0.15)

0.002 (0.05)

33؇

27؇

0.018 (0.46)

0.008 (0.20)

0.028 (0.71)

0.016 (0.41)

0.011 (0.28)

0.003 (0.08)

SEATING

PLANE

–10–

REV. 0


型号：	AD5220BRM10
厂家：	ADI
描述：	Increment/Decrement Digital Potentiometer 递增/递减数字电位计数字电位计
文件：	总10页 (文件大小：266K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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