AD2S83APZ [ADI]
Variable Resolution, Resolver-to-Digital Converter; 可变分辨率分解器数字转换器
| 型号： | AD2S83APZ |
| 厂家： | 
ADI |
| 描述： | Variable Resolution, Resolver-to-Digital Converter |
| 文件： | 总19页 (文件大小：188K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Variable Resolution,
Resolver-to-Digital Converter
a
AD2S83
FEATURES
Tracking R/D Converter
FUNCTIONAL BLOCK DIAGRAM
REFERENCE
High Accuracy Velocity Output
High Max Tracking Rate 1040 RPS (10 Bits)
44-Lead PLCC Package
10-, 12-, 14-, or 16-Bit Resolution Set by User
Ratiometric Conversion
I/P
OFFSET ADJUST
R9
HF FILTER
–12V
C3
+12V
R8
R3
R2
C2
C1
R1
BANDWIDTH
SELECTION
R4
Stabilized Velocity Reference
Dynamic Performance Set by User
Industrial Temperature Range
AC ERROR O/P
INTEGRATOR
I/P
C5
R5
DEMOD
O/P
C4
SIN
SIG
GND
A1
A2
PHASE
SENSITIVE
DETECTOR
SEGMENT
A3
R – 2R DAC
APPLICATIONS
DC and AC Servo Motor Control
Process Control
Numerical Control of Machine Tools
Robotics
Axis Control
SWITCHING
INTEGRATOR
VELOCITY
SIGNAL
O/P
COS
GND
R6
AD2S83
TRACKING
RATE
SELECTION
RIPPLE
CLOCK
VCO
I/P
16-BIT UP/DOWN COUNTER
OUTPUT DATA LATCH
VCO
+ DATA
TRANSFER
LOGIC
+12V
–12V
C7
VCO
O/P
R7
3K3
C6
390pF
SC2
DATA SC1
LOAD
ENABLE
BUSY DIRECTION INHIBIT
DIG
GND
5V
BYTE
SELECT
16
DATA BITS
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD2S83 is a monolithic 10-, 12-, 14-, or 16-bit tracking
resolver-to-digital converter.
High Accuracy Velocity Output. A precision analog velocity
signal with a typical linearity of 0.1% and reversion error less
than 0.3% is generated by the AD2S83. The provision of this
signal removes the need for mechanical tachogenerators used in
servo systems to provide loop stabilization and speed control.
The converter allows users to select their own resolution and dynamic
performance with external components. The converter allows users to
select the resolution to be 10, 12, 14, or 16 bits and to track
resolver signals rotating at up to 1040 revs per second (62,400 rpm)
when set to 10-bit resolution.
Resolution Set by User. Two control pins are used to select
the resolution of the AD2S83 to be 10, 12, 14 or 16 bits allow-
ing optimum resolution for each application.
The AD2S83 converts resolver format input signals into a paral-
lel natural binary digital word using a ratiometric tracking con-
version method. This ensures high noise immunity and tolerance
of long leads allowing the converter to be located remote from
the resolver.
Ratiometric Tracking Conversion. This technique provides
continuous output position data without conversion delay. It
also provides noise immunity and tolerance of harmonic distor-
tion on the reference and input signals.
The position output from the converter is presented via 3-state
output pins which can be configured for operations with 8- or
16-bit bus. BYTE SELECT, ENABLE and INHIBIT pins
ensure easy data transfer to 8- and 16-bit data bus, and outputs
are provided to allow for cycle or pitch counting in external
counters.
Dynamic Performance Set by the User. By selecting external
resistor and capacitor values the user can determine band-
width, maximum tracking rate and velocity scaling of the
converter to match the system requirements. The component
values are easy to select using the free component selection
software design aid.
A precise analog signal proportional to velocity is also available
and will replace a tachogenerator.
MODELS AVAILABLE
Information on the models available is given in the Ordering
Guide.
The AD2S83 operates over reference frequencies in the range
0 Hz to 20,000 Hz.
REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
(ꢀVS = ꢀ12 V dc ꢀ 5%; VL = 5 V dc ꢀ 10%; TA = –40ꢁC to +85ꢁC)
AD2S83–SPECIFICATIONS
Parameter
Conditions
Min
Typ
Max
Unit
SIGNAL INPUTS (SIN, COS)
Frequency1
0
1.8
20,000
2.2
150
Hz
V rms
nA
Voltage Level
Input Bias Current
Input Impedance
2.0
60
1.0
MΩ
REFERENCE INPUT (REF)
Frequency
Voltage Level
Input Bias Current
Input Impedance
0
1.0
20,000
8.0
150
Hz
V pk
nA
60
1.0
MΩ
PERFORMANCE
Repeatability
Allowable Phase Shift
Max Tracking Rate
1
+10
LSB
Degree
rps
rps
rps
(Signals to Reference)
10 Bits
12 Bits
–10
1040
260
65
14 Bits
16 Bits
User Selectable
16.25
rps
Bandwidth
ACCURACY
Angular Accuracy
Monotonicity
Missing Codes (16-Bit Resolution)
A, I
ꢀ
8 +1 LSB
arc min
Codes
Guaranteed Monotonic
A, I
4
VELOCITY SIGNAL
LINEARITY2, 3, 4
AD2S83AP
0 kHz–500 kHz
0.5 MHz–1 MHz
AD2S83IP
–40°C to +85°C
–40°C to +85°C
0.15
0.25
ꢀ
ꢀ
0.25
1.0
% FSR
% FSR
0 kHz–500 kHz
0.5 MHz–1 MHz
Reversion Error
AD2S83AP
–40°C to +85°C
–40°C to +85°C
0.25
0.25
ꢀ
ꢀ
0.5
1.0
% FSR
% FSR
–40°C to +85°C
–40°C to +85°C
0.5
1.0
3
ꢀ
ꢀ
1.0
1.5
% O/P
% O/P
mV
% FSR
V
AD2S83IP
DC Zero Offset5
Gain Scaling Accuracy
Output Voltage
Dynamic Ripple
1.5
ꢀ3
1 mA Load
Mean Value
8
1.0
% rms O/P
INPUT/OUTPUT PROTECTION
Analog Inputs
Analog Outputs
Overvoltage Protection
Short Circuit O/P Protection
8
8
V
mA
5.6
10.4
DIGITAL POSITION
Resolution
Output Format
Load
10, 12, 14, and 16
Bidirectional Natural Binary
Bits
3
LSTTL
INHIBIT6
Sense
Time to Stable Data
Logic LO to INHIBIT
240
35
390
490
110
ns
ns
ENABLE6
Logic LO Enables Position Output
Logic HI Outputs in High
Impedance State
ENABLE6/Disable Time
BYTE SELECT6
Sense
Logic HI
MS Byte DB1–DB8
LS Byte DB1–DB8
Logic LO
Time to Data Available
60
140
ns
SHORT CYCLE INPUTS
Internally Pulled High via
100 kΩ to +VS
SC1 SC2
0
0
1
1
0
1
0
1
10-Bit Resolution
12-Bit Resolution
14-Bit Resolution
16-Bit Resolution
–2–
REV. E
AD2S83
Parameter
Conditions
Min
Typ
Max
Unit
COMPLEMENT
Internally Pulled High via 100 kΩ
to +VS. Logic LO to Activate;
No Connect for Normal Operation
DATA LOAD
Sense
Internally Pulled High via 100 kΩ
to +VS. Logic LO Allows
150
300
ns
Data to be Loaded into the
Counters from the Data Lines
BUSY6, 7
Sense
Width
Load
Logic HI When Position O/P Changing
Use Additional Pull-Up (See Figure 2)
150
350
1
ns
LSTTL
DIRECTION6
Sense
Logic HI Counting Up
Logic LO Counting Down
Max Load
3
LSTTL
RIPPLE CLOCK6
Sense
Logic HI
All 1s to All 0s
All 0s to All 1s
Dependent on Input Velocity
Before Next Busy
Width
Reset
Load
300
2.0
ns
3
LSTTL
DIGITAL INPUTS
Input High Voltage, VIH
INHIBIT, ENABLE
V
V
DB1–DB16, Byte Select
VS = 11.4 V, VL = 5.0 V
INHIBIT, ENABLE
Input Low Voltage, VIL
0.8
DB1–DB16, Byte Select
VS = 12.6 V, VL = 5.0 V
DIGITAL INPUTS
Input High Current, IIH
INHIBIT, ENABLE
DB1–DB16
VS = 12.6 V, VL = 5.5 V
INHIBIT, ENABLE
DB1–DB16, Byte Select
VS = 12.6 V, VL = 5.5 V
ꢀ
ꢀ
100
100
µA
µA
Input Low Current, IIL
DIGITAL INPUTS
Low Voltage, VIL
ENABLE = HI
1.0
V
SC1, SC2, DATA LOAD
VS = 12.0 V, VL = 5.0 V
ENABLE = HI
SC1, SC2, DATA LOAD
VS = 12.0 V, VL = 5.0 V
Low Current, IIL
–400
µA
DIGITAL OUTPUTS
High Voltage, VOH
DB1–DB16
2.4
V
V
RIPPLE CLK, DIR
VS = 12.0 V, VL = 4.5 V
IOH = 100 µA
Low Voltage, VOL
DB1–DB16
0.4
RIPPLE CLK, DIR
VS = 12.0 V, VL = 5.5 V
IOL = 1.2 mA
NOTES
1Angular accuracy is not guaranteed <50 Hz reference frequency.
2Linearity derates from 500 kHz–1000 kHz @ 0.0017%/kHz.
3Refer to Definition of Linearity, “The AD2S83 as a Silicon Tachogenerator.”
4Worst case reversion error at temperature extremes.
5Velocity output offset dependent on value for R6.
6Refer to timing diagram.
7Busy pulse guaranteed up to a VCO rate of 900 kHz.
All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test.
Specifications subject to change without notice.
REV. E
–3–
(ꢀVS = ꢀ12 V dc ꢀ 5%; VL = 5 V dc ꢀ 10%; TA = –40ꢁC to +85ꢁC)
AD2S83–SPECIFICATIONS
Parameter
Conditions
Min
Typ
Max
Unit
THREE-STATE LEAKAGE
Current IL
DB1–DB16 Only
VS = 12.0 V, VL = 5.5 V
ꢀ
ꢀ
20
20
µA
µA
V
OL = 0 V
VS = 12.0 V, VL = 5.5 V
VOH = 5.0 V
RATIO MULTIPLIER
AC Error Output Scaling
10 Bit
12 Bit
14 Bit
16 Bit
177.6
44.4
11.1
mV/Bit
mV/Bit
mV/Bit
mV/Bit
2.775
PHASE SENSITIVE DETECTOR
Output Offset Voltage
Gain
In Phase
In Quadrature
Input Bias Current
Input Impedance
Input Voltage
12
mV
w.r.t. REF
w.r.t. REF
–0.882
1.0
–0.9
60
–0.918
0.02
150
V rms/V dc
V rms/V dc
nA
MΩ
V
8
INTEGRATOR
Open-Loop Gain
Dead Zone Current (Hysteresis)
Input Offset Voltage
Input Bias Current
At 10 kHz
57
90
60
100
1
63
110
5
dB
nA/LSB
mV
nA
60
150
Output Voltage Range
ꢀ8
V
VCO
Maximum Rate
VCO Rate
1.1
8.25
8.25
MHz
kHz/µA
kHz/µA
+ve DIR
–ve DIR
8.50
8.50
8.75
8.75
VCO Power Supply Sensitivity
Rate
+VS
–VS
+0.5
–0.5
%/V
%/V
mV
nA
nA/°C
Input Offset Voltage
Input Bias Current
Input Bias Current Tempco
Linearity of Absolute Rate
AD2S83AP
3
12
+0.22
50
0 kHz–500 kHz
0.5 MHz–1 MHz
AD2S83IP
0 kHz–500 kHz
0.5 MHz–1 MHz
Reversion Error
AD2S83AP
0.15
0.25
ꢀ0.25
ꢀ1.0
% FSR
% FSR
0.25
0.25
ꢀ0.5
ꢀ1.0
% FSR
% FSR
0.5
1.0
ꢀ1.0
ꢀ1.5
% Output
% Output
AD2S83IP
POWER SUPPLIES
Voltage Levels
+VS
–VS
+VL
Current
IS
+11.4
–11.4
+4.5
+12.6
–12.6
+VS
V
V
V
+5
VS @ 12 V
VS @ 12.6 V
+VL @ 5.0 V
12
19
0.5
ꢀ23
ꢀ30
ꢀ1.5
mA
mA
mA
IS
IL
All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test.
Specifications subject to change without notice.
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Option
Model
Accuracy
AD2S83AP
AD2S83IP
–40°C to +85°C
–40°C to +85°C
8 arc min
8 arc min
Plastic Leaded Chip Carrier P-44A
Plastic Leaded Chip Carrier P-44A
–4–
REV. E
AD2S83
PIN FUNCTION DESCRIPTIONS
ABSOLUTE MAXIMUM RATINGS1 (with respect to GND)
2
+VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13 V dc
2
P
in
–VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –13 V dc
Nos. Mnemonic
Description
+VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +VS
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13 V to –VS
SIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13 V to –VS
COS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13 V to –VS
Any Logical Input . . . . . . . . . . . . . . . . . . –0.4 V dc to +VL dc
Demodulator Input . . . . . . . . . . . . . . . . . . . . . . . +13 V to –VS
Integrator Input . . . . . . . . . . . . . . . . . . . . . . . . . . +13 V to –VS
VCO Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13 V to –VS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 800 mW
Operating Temperature
1
2
3
4
5
6
7
8
DEMOD O/P
REFERENCE I/P
AC ERROR O/P
COS
Demodulator Output
Reference Signal Input
Ratio Multiplier Output
Cosine Input
ANALOG GND
SIGNAL GND
SIN
Power Ground
Resolver Signal Ground
Sine Input
+VS
Positive Power Supply
Parallel Output Data
Logic Power Supply
Industrial (AP, IP) . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
10–25 DB1–DB16
26
27
+VL
ENABLE
Logic HI—Output Data Pins in
High Impedance State
Logic LO—Presents Active Data
to the Output Pins
CAUTION
1Absolute Maximum Ratings are those values beyond which damage to the device
may occur.
2Correct polarity voltages must be maintained on the +VS and –VS pins.
28
BYTE SELECT
Logic HI—Most Significant Byte to
DB1–DB8
Logic LO—Least Significant Byte
RECOMMENDED OPERATING CONDITIONS
Power Supply Voltage (+VS, –VS) . . . . . . . . . . 12 V dc 5%
Power Supply Voltage VL . . . . . . . . . . . . . . . . . +5 V dc 10%
Analog Input Voltage (SIN and COS) . . . . . . . 2 V rms 10%
Analog Input Voltage (REF) . . . . . . . . . . . . . . 1 V to 8 V peak
Signal and Reference Harmonic Distortion . . . . . . 10% (max)
Phase Shift Between Signal and Reference . . . 10 Degrees (max)
Ambient Operating Temperature Range
to DB1–DB8
30
31
INHIBIT
Logic LO Inhibits Data Transfer
to Output Latches
DIGITAL GND
Digital Ground
32, 33 SC2–SC1
Select Converter Resolution
Industrial (AP, IP) . . . . . . . . . . . . . . . . . . . –40°C to +85°C
34
DATA LOAD
Logic LO DB1–DB16 Inputs
Logic HI DB1–DB16 Outputs
PIN CONFIGURATION
35
36
COMPLEMENT
Active Logic LO
BUSY
Converter Busy, Data not Valid
While Busy HI
37
38
DIRECTION
Logic State Defines Direction of
Input Signal Rotation
RIPPLE CLOCK
Positive Pulse When Converter Output
Changes from 1s to All 0s or Vice Versa
4
6
5
3
2
1
44 43 42 41 40
39
40
41
42
43
44
–VS
Negative Power Supply
VCO Input
PIN 1
39
38
37
36
35
34
7
8
9
–V
S
SIN I/P
+V
IDENTIFIER
VCO I/P
VCO O/P
RIPPLE CLOCK
DIRECTION
BUSY
S
VCO Output
NC
INTEGRATOR O/P Integrator Output
(MSB) DB1 10
DB2 11
COMP
INTEGRATOR I/P
DEMOD I/P
Integrator Input
AD2S83
TOP VIEW
(Not to Scale)
DB3
12
DB4 13
DATA LOAD
Demodulator Input
33 SC1
32 SC2
14
15
16
17
DB5
DB6
DB7
DB8
31 DIGITAL GND
30
INHIBIT
29 NC
19
26
27 28
18
20 21 22 23 24 25
NC = NO CONNECT
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD2S83 feature proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. E
–5–
AD2S83
Bit Weight Table
When more than one converter is used on a card, separate de-
coupling capacitors should be used for each converter.
Binary
Resolution Degrees
Minutes
/Bit
Seconds
/Bit
Bits (N) (NN)
/Bit
The resolver connections should be made to the SIN and COS
inputs, REFERENCE INPUT and SIGNAL GROUND as
shown in Figure 11 and described in the Connecting the
Resolver section.
0
1
2
3
1
2
4
8
360.0
180.0
90.0
45.0
22.5
21600.0
10800.0
5400.0
2700.0
1350.0
1296000.0
648000.0
324000.0
162000.0
81000.0
The two signal ground wires from the resolver should be joined
at the SIGNAL GROUND pin of the converter to minimize the
coupling between the sine and cosine signals. For this reason it
is also recommended that the resolver is connected using indi-
vidually screened twisted pair cables with the sine, cosine and
reference signals twisted separately.
4
16
5
6
7
8
9
32
64
128
256
512
11.25
675.0
40500.0
20250.0
10125.0
5062.5
5.625
337.5
2.8125
1.40625
0.703125
168.75
84.375
42.1875
2531.25
SIGNAL GROUND and ANALOG GROUND are connected
internally. ANALOG GROUND and DIGITAL GROUND
must be connected externally and as close to the converter as
possible.
10
11
12
13
14
1024
2048
4096
8192
16384
0.3515625
0.1757813
0.0878906
0.0439453
0.0219727
21.09375
10.546875
5.273438
2.636719
1.318359
1265.625
632.8125
316.40625
158.20313
79.10156
The external components required should be connected as
shown in Figure 1.
15
16
17
18
32768
65536
131072
0.0109836
0.0054932
0.0027466
0.0013733
0.659180
0.329590
0.164795
0.082397
39.55078
19.77539
9.88770
4.94385
CONVERTER RESOLUTION
Two major areas of the AD2S83 specification can be selected by
the user to optimize the total system performance. The resolu-
tion of the digital output is set by the logic state of the inputs
SC1 and SC2 to be 10, 12, 14 or 16 bits; and the dynamic char-
acteristics of bandwidth and tracking rate are selected by the
choice of external components.
262144
CONNECTING THE CONVERTER
The power supply voltages connected to +VS and –VS pins
should be +12 V dc and –12 V dc and must not be reversed.
The voltage applied to VL can be +5 V dc to +VS.
The choice of the resolution will affect the values of R4 and R6
which scale the inputs to the integrator and the VCO respec-
tively (see Component Selection section). If the resolution is
changed, then new values of R4 and R6 must be switched into
the circuit.
It is recommended that the decoupling capacitors are connected
in parallel between the power lines +VS, –VS and ANALOG
GROUND adjacent to the converter. Recommended values are
100 nF (ceramic) and 10 µF (tantalum). Also capacitors of
100 nF and 10 µF should be connected between +VL and
DIGITAL GROUND adjacent to the converter.
Note: When changing resolution under dynamic conditions, do
it when the BUSY is low, i.e., when data is not changing.
REFERENCE
OFFSET ADJUST
I/P
R9
HF FILTER
–12V
+12V
C3
R3
R8
R2
C2
C1
R1
BANDWIDTH
SELECTION
R4
INTEGRATOR
I/P
C5
R5
C4
AC ERROR O/P
DEMOD
O/P
SIN
A1
A2
PHASE
SENSITIVE
DETECTOR
SIG GND
VELOCITY
SIGNAL
SEGMENT
SWITCHING
A3
R - 2R DAC
INTEGRATOR
O/P
COS
GND
R6
AD2S83
TRACKING
RATE
RIPPLE
CLOCK
VCO
I/P
16-BIT UP/DOWN COUNTER
OUTPUT DATA LATCH
SELECTION
VCO + DATA
TRANSFER
LOGIC
C7
150pF
+12V
–12V
VCO
O/P
R7
3K3
BYTE 5V DIG BUSY DIRECTION INHIBIT
SELECT
ENABLE
DATA SC1
LOAD
SC2
C6
390pF
16 DATA BITS
GND
Figure 1. Connection Diagram
–6–
REV. E
AD2S83
CONVERTER OPERATION
The direction of input rotation is indicated by the DIRECTION
(DIR) logic output. This direction data is always valid in advance
of a RIPPLE CLOCK pulse and, as it is internally latched, only
changing state (1 LSB min change in input) with a correspond-
ing change in direction.
When connected in a circuit such as shown in Figure 10, the
AD2S83 operates as a tracking resolver-to-digital converter.
The output will automatically follow the input for speeds up to
the selected maximum tracking rate. No convert command is
necessary as the conversion is automatically initiated by each
LSB increment, or decrement, of the input. Each LSB change of
the converter initiates a BUSY pulse.
Both the RIPPLE CLOCK pulse and the DIRECTION data
are unaffected by the application of the INHIBIT. The static
positional accuracy quoted is the worst case error that can occur
over the full operating temperature excluding the effects of
offset signals at the INTEGRATOR INPUT (which can be
trimmed out—see Figure 1), and with the following conditions:
input signal amplitudes are within 10% of the nominal; phase
shift between signal and reference is less than 10 degrees.
The AD2S83 is remarkably tolerant of input amplitude and
frequency variation because the conversion depends only on the
ratio of the input signals. Consequently there is no need for
accurate, stable oscillator to produce the reference signal. The
inclusion of the phase sensitive detector in the conversion loop
ensures high immunity to signals that are not phase or frequency
coherent or are in quadrature with the reference signal.
These operating conditions are selected primarily to establish a
repeatable acceptance test procedure which can be traced to
national standards. In practice, the AD2S83 can be used well
outside these operating conditions providing the above points
are observed.
SIGNAL CONDITIONING
The amplitude of the SINE and COSINE signal inputs should
be maintained within 10% of the nominal values if full perfor-
mance is required from the velocity signal.
VELOCITY SIGNAL
The digital position output is relatively insensitive to amplitude
variation. Increasing the input signal levels by more than 10%
will result in a loss in accuracy due to internal overload. Reduc-
ing levels will result in a steady decline in accuracy. With the
signal levels at 50% of the correct value, the angular error will
increase to an amount equivalent to 1.3 LSB. At this level the
repeatability will also degrade to 2 LSB and the dynamic response
will also change, since the dynamic characteristics are propor-
tional to the signal level.
The tracking converter technique generates an internal signal at
the output of the integrator (INTEGRATOR OUTPUT) that is
proportional to the rate of change of the input angle. This is a
dc analog output referred to as the VELOCITY signal.
It is recommended that the velocity output be buffered.
The sense is positive for an increasing angular input and nega-
tive for decreasing angular input. The full-scale velocity output
is 8 V dc. The output velocity scaling and tracking rate are a
function of the resolution of the converter; this is summarized
below.
The AD2S83 will not be damaged if the signal inputs are
applied to the converter without the power supplies and/or
the reference.
Max Tracking
Rate (rps)
Nominal Scaling
(rps/V dc)
Res
REFERENCE INPUT
The amplitude of the reference signal applied to the converter’s
input is not critical, but care should be taken to ensure it is kept
within the recommended operating limits.
10
12
14
16
1040
260
65
130
32.5
8.125
2.03
16.25
The AD2S83 will not be damaged if the reference is supplied to
the converter without the power supplies and/or the signal
inputs.
(Velocity O/P = 8 V dc nominal)
The output velocity can be suitably scaled and used to replace a
conventional DC tachogenerator. For more detailed information
see the AD2S83 as a Silicon Tachogenerator section.
HARMONIC DISTORTION
The amount of harmonic distortion allowable on the signal and
reference lines is 10%.
DC ERROR SIGNAL
Square waveforms can be used but the input levels should be
adjusted so that the average value is 1.9 V rms. (For example, a
square wave should be 1.9 V peak.) Triangular and sawtooth
waveforms should have a amplitude of 2 V rms.
The signal at the output of the phase sensitive detector
(DEMODULATOR OUTPUT) is the signal to be nulled by
the tracking loop and is, therefore, proportional to the error
between the input angle and the output digital angle. As the
converter is a Type 2 servo loop, the demodulator output signal
will increase if the output fails to track the input for any reason.
This is an indication that the input has exceeded the maximum
tracking rate of the converter or, due to some internal or exter-
nal malfunction, the converter is unable to reach a null. By con-
necting two external comparators, this voltage can be used as a
“built-in-test.”
Note: The figure specified of 10% harmonic distortion is for
calibration convenience only.
POSITION OUTPUT
The resolver shaft position is represented at the converter out-
put by a natural binary parallel digital word. As the digital posi-
tion output of the converter passes through the major carries,
i.e., all “1s” to all “0s” or the inverse, a RIPPLE CLOCK (RC)
logic output is initiated indicating that a revolution or a pitch of
the input has been completed.
REV. E
–7–
AD2S83
COMPONENT SELECTION
4. Maximum Tracking Rate (R6)
The following instructions describe how to select the external
components for the converter in order to achieve the required
bandwidth and tracking rate. In all cases the nearest “preferred
value” component should be used, and a 5% tolerance will not
degrade the overall performance of the converter. Care should
be taken that the resistors and capacitors will function over the
required operating temperature range. The components should
be connected as shown in Figure 1.
The VCO input resistor R6 sets the maximum tracking rate
of the converter and hence the velocity scaling as at the max
tracking rate, the velocity output will be 8 V.
Decide on your maximum tracking rate, “T,” in revolutions
per second. When setting the value for R6, it should be
remembered that the linearity of the velocity output is
specified across 0 kHz–500 kHz and 500 kHz–1000 kHz.
The following conversion can be used to determine the
corresponding rps:
Free PC compatible software is available to help users select the
optimum component values for the AD2S83, and display the transfer
gain, phase and small step response.
VCO Rate (Hz)
rps =
2N
For more detailed information and explanation, see the Circuit
Functions and Dynamic Performance section.
Note that “T” must not exceed the maximum tracking rate
or 1/16 of the reference frequency.
1. HF Filter (R1, R2, C1, C2)
The function of the HF filter is to remove any dc offset and
to reduce the amount of noise present on the signal inputs to
the AD2S83, reaching the Phase Sensitive Detector and
affecting the outputs. R1 and C2 may be omitted—in which
case R2 = R3 and C1 = C3, calculated below—but their use
is particularly recommended if noise from switch mode
power supplies and brushless motor drive is present.
6.81×1010
R6 =
Ω
T × n
where n = bits per revolution
= 1,024 for 10 bits resolution
= 4,096 for 12 bits
= 16,384 for 14 bits
= 65,536 for 16 bits
Values should be chosen so that
15kΩ ≤ R1= R2≤ 56kΩ
5. Closed-Loop Bandwidth Selection (C4, C5, R5)
a. Choose the closed-loop bandwidth (fBW) required
ensuring that the ratio of reference frequency to band-
width does not exceed the following guidelines:
1
C1= C2 =
2 π R1 fREF
and fREF = Reference Frequency
(Hz)
Resolution
Ratio of Reference Frequency/Bandwidth
2.5 : 1
10
12
14
16
This filter gives an attenuation of three times at the input to
the phase sensitive detector.
4
6
: 1
: 1
2. Gain Scaling Resistor (R4) (See Phase Sensitive Demodula-
7.5 : 1
tor section.)
If R1, C2 are used:
Typical values may be 100 Hz for a 400 Hz reference fre-
quency and 500 Hz to 1000 Hz for a 5 kHz reference
frequency.
EDC
100 × 10−9
1
3
R4 =
×
Ω
b.
Select C4 so that
21
C4 =
F
where 100 × 10–9 = current/LSB
If R1, C2 are not used:
R6 × fBW
2
EDC
with R6 in Ω and fBW, in Hz selected above.
R4 =
Ω
100 ×10–9
c.
C5 is given by
C5 = 5 × C4
where EDC
= 160 × 10–3 for 10 bits resolution
= 40 × 10–3 for 12 bits
d.
R5 is given by
= 10 × 10–3 for 14 bits
4
= 2.5 × 10–3 for 16 bits
R5 =
Ω
2 × π × fBW × C5
= Scaling of the DC ERROR in volts/LSB
6. VCO Phase Compensation
3. AC Coupling of Reference Input (R3, C3)
Select R3 and C3 so that there is no significant phase shift at
the reference frequency. That is,
The following values of C6 and R7 should be connected as
close as possible to the VCO output, Pin 41.
C6 = 390 pF, R7 = 3. 3 kΩ
R3 = 100 kΩ
7. VCO Optimization
1
C3 >
F
To optimize the performance of the VCO a capacitor, C7,
should be placed across the VCO input and output, Pins 40
and 41.
R3 × fREF
with R3 in Ω.
C7 = 150 pF
–8–
REV. E
AD2S83
8. Offset Adjust
BYTE SELECT Input
Offsets and bias currents at the integrator input can cause an
additional positional offset at the output of the converter of
1 arc minute typical, 5.3 arc minutes maximum. If this can be
tolerated, then R8 and R9 can be omitted from the circuit.
The BYTE SELECT input selects the byte of the position data
to be presented at the data output DB1 to DB8. The least sig-
nificant byte will be presented on data output DB9 to DB16
(with the ENABLE input taken to a logic “LO”) regardless of
the state of the BYTE SELECT pin. Note that when the AD2S83
is used with a resolution less than 16 bits the unused data lines
are pulled to a logic “LO.” A logic “HI” on the BYTE SELECT
input will present the eight most significant data bits on data
output DB1 and DB8. A logic “LO” will present the least sig-
nificant byte on data outputs 1 to 8, i.e., data outputs 1 to 8 will
duplicate data outputs 9 to 16.
If fitted, the following values of R8 and R9 should be used:
R8 = 4.7 MΩ, R9 = 1 MΩ potentiometer
To adjust the zero offset, ensure the resolver is disconnected
and all the external components are fitted. Connect the
COS pin to the REFERENCE INPUT and the SIN pin to
the SIGNAL GROUND and with the power and reference
applied, adjust the potentiometer to give all “0s” on the
digital output bits.
The operation of the BYTE SELECT has no effect on the con-
version process of the converter.
The potentiometer may be replaced with select on test resistors
if preferred.
RIPPLE CLOCK
As the output of the converter passes through the major carry,
i.e., all “1s” to all “0s” or the converse, a positive going edge on
the RIPPLE CLOCK (RC) output is initiated indicating that a
revolution, or a pitch, of the input has been completed.
DATA TRANSFER
To transfer data the INHIBIT input should be used. The data
will be valid 490 ns after the application of a logic “LO” to the
INHIBIT. This is regardless of the time when the INHIBIT is
applied and allows time for an active BUSY to clear. By using
the ENABLE input the two bytes of data can be transferred
after which the INHIBIT should be returned to a logic “HI”
state to enable the output latches to be updated.
The minimum pulsewidth of the ripple clock is 300 ns. RIPPLE
CLOCK is normally set high before a BUSY pulse and resets
before the next positive going edge of the next BUSY pulse.
The only exception to this is when DIR changes while the
RIPPLE CLOCK is high. Resetting of the RIPPLE clock will
only occur if the DIR remains stable for two consecutive posi-
tive BUSY pulse edges.
BUSY Output
The validity of the output data is indicated by the state of the
BUSY output. When the input to the converter is changing, the
signal appearing on the BUSY output is a series of pulses at
TTL level. A BUSY pulse is initiated each time the input moves
by the analog equivalent of one LSB and the internal counter is
incremented or decremented.
If the AD2S83 is being used in a pitch and revolution counting
application, the ripple and busy will need to be gated to prevent
false decrement or increment (see Figure 2).
RIPPLE CLOCK is unaffected by INHIBIT.
INHIBIT Input
5V
The INHIBIT logic input only inhibits the data transfer from
the up-down counter to the output latches and, therefore, does
not interrupt the operation of the tracking loop. Releasing the
INHIBIT automatically generates a BUSY pulse to refresh the
output data.
10kꢂ
1kꢂ
TO COUNTER
(CLOCK)
IN4148
RIPPLE
CLOCK
2N3904
0V
5V
5K1
ENABLE Input
The ENABLE input determines the state of the output data. A
logic “HI” maintains the output data pins in the high imped-
ance condition, and the application of a logic “LO” presents the
data in the latches to the output pins. The operation of the
ENABLE has no effect on the conversion process.
IN4148
BUSY
NOTE: DO NOT USE ABOVE CCT WHEN INHIBIT IS LOW.
Figure 2. Diode Transistor Logic N and Gate
REV. E
–9–
AD2S83
BUSY
V
H
t1
RIPPLE
CLOCK
V
L
V
t2
H
t3
t4
V
H
DATA
t5
V
L
INHIBIT
V
H
t6
t7
V
H
DIR
V
L
t8
t9
INHIBIT
V
L
V
ENABLE
L
t10
V
H
V
Z
DATA
t11
V
L
BYTE
SELECT
V
L
V
H
V
H
DATA
V
L
t12
t13
Figure 3. Digital Timing
Parameter TMIN
*
TMAX
*
Condition
BUSY WIDTH VH–VH
RIPPLE CLOCK VH to BUSY VH
RIPPLE CLOCK VL to Next BUSY VH
BUSY VH to DATA VH
t1
150
10
470
16
3
350
25
580
45
t2
t3
t4
t5
25
BUSY VH to DATA VL
t6
t7
t8
t9
t10
t11
t12
t13
70
485
515
–
40
35
60
60
140
625
670
490
110
110
140
125
INHIBIT VH to BUSY VH
MIN DIR VH to BUSY VH
MIN DIR VH to BUSY VH
INHIBIT VL to DATA STABLE
ENABLE VL to DATA VH
ENABLE VL to DATA VL
BYTE SELECT VL to DATA STABLE
BYTE SELECT VH to DATA STABLE
*ns
–10–
REV. E
AD2S83
DIRECTION Output
CIRCUIT FUNCTIONS AND DYNAMIC PERFORMANCE
The AD2S83 allows the user great flexibility in choosing the
dynamic characteristics of the resolver-to-digital conversion to
ensure the optimum system performance. The characteristics
are set by the external components shown in Figure 1. The
Component Selection section explains how to select desired
maximum tracking rate and bandwidth values. The following
paragraphs explain in greater detail the circuit of the AD2S83
and the variations in the dynamic performance available to the
user.
The DIRECTION (DIR) output indicates the direction of the
input rotation. Any change in the state of DIR precedes the
corresponding BUSY, DATA and RIPPLE CLOCK updates.
DIR can be considered as an asynchronous output and can
make multiple changes in state between two consecutive LSB
update cycles. This occurs when the direction of rotation of the
input changes but the magnitude of the rotation is less than 1 LSB.
COMPLEMENT
The COMPLEMENT input is an active low input and is inter-
nally pulled to +VS via 100 kΩ.
Loop Compensation
The AD2S83 (connected as shown in Figure 1) operates as a
Type 2 tracking servo loop where the VCO/counter combination
and Integrator perform the two integration functions inherent in
a Type 2 loop.
Strobing DATA LOAD and COMPLEMENT pins to logic LO
will set the logic HI bits of the AD2S83 counter to a LO state.
Those bits of the applied data which are logic LO will not
change the corresponding bits in the AD2S83 counter.
Additional compensation in the form of a pole/zero pair is
required to stabilize the loop.
For Example:
Initial Counter State
Applied Data Word
Counter State after DATA LOAD
1 0 1 0 1
1 1 0 0 0
1 1 0 0 0
This compensation is implemented by the integrator compo-
nents (R4, C4, R5, C5).
The overall response the converter is that of a unity gain second
order low-pass filter, with the angle of the resolver as the input
and the digital position data as the output.
Initial Counter State
Applied Data Word
Counter State after DATA LOAD and Complement
1 0 1 0 1
1 1 0 0 0
0 0 1 0 1
The AD2S83 does not have to be connected as tracking con-
verter, parts of the circuit can be used independently. This is
particularly true of the Ratio Multiplier which can be used as a
control transformer. (For more information contact Motion
Control Applications.)
In order to read the counter following a DATA LOAD, the
procedure below should be followed:
1. Place outputs in high impedance state (ENABLE = HI).
2. Present data to pins.
A block diagram of the AD2S83 is given in Figure 4.
3. Pull DATA LOAD and COMPLEMENT pins to ground.
4. Wait 100 ns.
5. Remove data from pins.
6. Remove outputs from high impedance state (ENABLE =
LO).
7. Read outputs.
C5
R5
C4
AC ERROR
SIN ꢃ SIN ꢅt
COS ꢃ SIN ꢅt
PHASE
R4
RATIO
MULTIPLIER
SENSITIVE
DEMODULATOR
A, SIN (ꢃ–ꢄ) SIN ꢅt
INTEGRATOR
CLOCK
DIGITAL
ꢄ
R6
VCO
DIRECTION
VELOCITY
Figure 4. Functional Diagram
REV. E
–11–
AD2S83
Phase Sensitive Demodulator
Ratio Multiplier
The phase sensitive demodulator is effectively ideal and devel-
ops a mean dc output at the DEMODULATOR OUTPUT
pin of
The ratio multiplier is the input section of the AD2S83. This
compares the signal from the resolver (angle θ) to the digital
(angle φ) held in the counter. Any difference between these
two angles results in an analog voltage at the AC ERROR
OUTPUT. This circuit function has historically been called a
“Control Transformer” as it was originally performed by an
electromechanical device known by that name.
2
π
2
×(DEMODULATOR INPUT rms voltage)
for sinusoidal signals in phase or antiphase with the reference
(for a square wave the DEMODULATOR OUTPUT voltage
will equal the DEMODULATOR INPUT). This provides a
signal at the DEMODULATOR OUTPUT which is a dc level
proportional to the positional error of the converter.
The AC ERROR signal is given by
A1 sin (θ–φ) sin ωt
where ω = 2 π fREF
fREF = reference frequency
DC Error Scaling = 160 mV/bit (10-bit resolution)
= 40 mV/bit (12-bit resolution)
A1 = the gain of the ratio multiplier stage = 14.5.
= 10 mV/bit (14-bit resolution)
So for 2 V rms inputs signals
= 2.5 mV/bit (16-bit resolution)
AC ERROR output in volts/(bit of error)
When the tracking loop is closed, this error is nulled to zero
unless the converter input angle is accelerating.
360
n
= 2 × sin
× A1
Integrator
where n = bits per rev
The integrator components (R4, C4, R5, C5) are external to the
AD2S83 to allow the user to determine the optimum dynamic
characteristics for any given application. The Component
Selection section explains how to select components for a
chosen bandwidth.
= 1,024 for 10-bit resolution
= 4,096 for 12-bit resolution
= 16,384 for 14-bit resolution
= 65,536 for 16-bit resolution
giving an AC ERROR output
Since the output from the integrator is fed to the VCO INPUT,
it is proportional to velocity (rate of change of output angle) and
can be scaled by selection of R6, the VCO input resistor. This is
explained in the Voltage Controlled Oscillator (VCO) section
below.
= 178 mV/bit @ 10-bit resolution
= 44.5 mV/bit @ 12-bit resolution
= 11.125 mV/bit @ 14-bit resolution
= 2.78 mV/bit @ 16-bit resolution
The ratio multiplier will work in exactly the same way whether
the AD2S83 is connected as a tracking converter or as a control
transformer, where data is preset into the counters using the
DATA LOAD pin.
To prevent the converter from “flickering” (i.e., continually
toggling by 1 bit when the quantized digital angle, φ, is not an
exact representation of the input angle, θ) feedback is internally
applied from the VCO to the integrator input to ensure that the
VCO will only update the counter when the error is greater than
or equal to 1 LSB. In order to ensure that this feedback “hys-
teresis” is set to 1 LSB the input current to the integrator must
be scaled to be 100 nA/bit. Therefore,
HF Filter
The AC ERROR OUTPUT may be fed to the PSD via a simple
ac coupling network (R2, C1) to remove any dc offset at this
point. Note, however, that the PSD of the AD2S83 is a wide-
band demodulator and is capable of aliasing HF noise down to
within the loop bandwidth. This is most likely to happen where
the resolver is situated in particularly noisy environments, and
the user is advised to fit a simple HF filter R1, C2 prior to the
phase sensitive demodulator.
DC Error Scaling (mV/bit )
R4 =
100 (nA/bit)
Any offset at the input of the integrator will affect the accuracy
of the conversion as it will be treated as an error signal and
offset the digital output. One LSB of extra error will be added
for each 100 nA of input bias current. The method of adjusting
out this offset is given in the Component Selection section.
The attenuation and frequency response of a filter will affect the
loop gain and must be taken into account in deriving the loop
transfer function. The suggested filter (R1, C1, R2, C2) is
shown in Figure 1 and gives an attenuation at the reference
frequency (fREF) of three times at the input to the phase sensitive
demodulator.
Voltage Controlled Oscillator (VCO)
The VCO is essentially a simple integrator feeding a pair of dc
level comparators. Whenever the integrator output reaches one
of the comparator threshold voltages, a fixed charge is injected
into the integrator input to balance the input current. At the
same time the counter is clocking either up or down, dependent
on the polarity of the input current. In this way the counter is
clocked at a rate proportional to the magnitude of the input
current of the VCO.
Values of components used in the filter must be chosen to
ensure that the phase shift at fREF is within the allowable signal
to reference phase shift of the converter.
–12–
REV. E
AD2S83
12
9
During the VCO reset period the input continues to be inte-
grated. The reset period is constant at 40 ns.
The VCO rate is fixed for a given input current by the VCO
scaling factor:
6
= 8.5 kHz/µA
3
The tracking rate in rps per µA of VCO input current can be
found by dividing the VCO scaling factor by the number of LSB
changes per rev (i.e., 4096 for 12-bit resolution).
0
–3
–6
The input resistor R6 determines the scaling between the con-
verter velocity signal voltage at the INTEGRATOR OUTPUT
pin and the VCO input current. Thus to achieve a 5 V output at
100 rps (6000 rpm) and 12-bit resolution the VCO input cur-
rent must be:
–9
–12
0.0
0.04
0.1
0.2
0.4
BW
1
2
FREQUENCY – f
(100 × 4096)/(8500) = 48.2 µA
Thus, R6 would be set to: 5/(48.2 × 10–6) = 103.7 kΩ
Figure 5. Gain Plot
180
135
90
The velocity offset voltage depends on the VCO input resistor,
R6, and the VCO bias current and is given by
Velocity Offset Voltage = R6 × (VCO bias current)
The temperature coefficient of this offset is given by
Velocity Offset Tempco = R6 × (VCO bias current tempco)
where the VCO bias current tempco is typically +0.22 nA/°C.
45
0
The maximum recommended rate for the VCO is 1.1 MHz
which sets the maximum possible tracking rate.
–45
–90
Since the minimum voltage swing available at the integrator
output is 8 V, this implies that the minimum value for R6 is
62 kΩ. As
–135
–180
0.0
0.04
0.1
0.2
0.4
1
2
1.1×106
BW
FREQUENCY – f
Max Current =
= 129 µA
= 62 kΩ
8.5 ×103
Figure 6. Phase Plot
8
MinValue R6 =
129×10–6
Transfer Function
By selecting components using the method outlined in the sec-
tion “Component Selection,” the converter will have a critically
damped time response and maximum phase margin. The
Closed-Loop Transfer Function is given by:
θOUT
θIN
14(1+ sN )
=
2
(sN + 2.4)(sN + 3.4 sN + 5.8)
where, sN, the normalized frequency variable is given by:
2
π
s
sN
=
f BW
and fBW is the closed-loop 3 dB bandwidth (selected by the
choice of external components).
The acceleration constant KA, is given approximately by
K A = 6 × ( fBW )2 sec–2
The normalized gain and phase diagrams are given in Figures 5
and 6.
REV. E
–13–
AD2S83
The small signal step response is shown in Figure 7. The time
from the step to the first peak is t1, and the t2 is the time from
the step until the converter is settled to 1 LSB. The times t1 and
t2 are given approximately by
The only effective way to compensate for dynamic loading
effects is to introduce a 2nd order term which will provide the
motor with an acceleration or deceleration demand signal (see
Figure 9).
1
f BW
t1 =
CONTROL
TERMS
MOTOR
5
R
POSITION
DEMAND
t2 =
×
f BW 12
+
–
where R = resolution, i.e., 10, 12, 14 or 16.
VELOCITY
ELECTRONICS
t2
ACTUAL
POSITION
FEEDBACK
POSITION
SOURCE
ELECTRONICS
Figure 9. Position Control and Velocity Control
Traditionally this would need to be implemented by using sepa-
rate position and speed feedback transducers, e.g., an encoder
or resolver and a dc tachogenerator. The AD2S83 can decode
the resolver to provide both velocity and position information.
TIME
t1
DC Tachogenerator
Figure 7. Small Step Response
The DC tachogenerator is a small permanent magnet dc
generator. The output is a dc voltage which is proportional to
the speed of the rotor and whose polarity is determined by the
direction of rotation. Physically they are similar to a resolver.
The large signal step response (for steps greater than 5 degrees)
applies when the error voltage exceeds the linear range of the
converter.
Typically the converter will take three times longer to reach the
first peak for a 179 degrees step.
Velocity Error Derivation
The velocity error is the difference between the synthesized dc
velocity demand derived from the actual and demand positions
and the feedback from the tachogenerator or the AD2S83. The
velocity demand is usually derived via a DAC so apart from any
quantization noise it is clean. The velocity feedback, therefore,
needs to be as close to a pure dc level as possible. The errors
which determine the quality of the resultant acceleration demand
to the motor are explained below.
In response to a velocity step, the velocity output will exhibit
the same time response characteristics as outlined above for the
position output.
THE AD2S83 AS A SILICON TACHOGENERATOR
Position Control Using the AD2S83
The AD2S83 has been optimized for use as a feedback device
for velocity as well as position. A traditional position control
loop shown below compares a demand position with an actual
to derive a position error and hence a velocity demand.
Linearity
Linearity is the maximum deviation from the ideal straight line
velocity characteristic. The line used is given by:
MOTOR
v = mx + c
POSITION
DEMAND
CONTROL
+
where
v = velocity
TERMS
–
m = gain scaling
x = dc voltage
c = zero velocity dc offset
ACTUAL
POSITION
POSITION
ELECTRONICS
Linearity is generally a function of the input velocity to the
tachogenerator or resolver.
FEEDBACK
SOURCE
Figure 8. Position Control
Reversion Error
Reversion or reversal error is an offset which is dependent on
the direction of rotation of the transducer; e.g., if 10 rps =
1.000 V dc, then –10 rps = 1.003 V dc with +0.3% reversion
error and FSO = 8 V dc.
Quality of control may be reduced if the load on a motor varies
dynamically. System reaction and compensation for a sudden
change in the loading depends on how rapidly the system can
update the velocity demand to the motor. This can cause rapid
acceleration of the motor until the loop updates with a new
velocity demand.
Zero Velocity DC Offset
This is a residual dc offset present at zero input velocity. This
can be externally nulled.
–14–
REV. E
AD2S83
Ripple Content
ACCELERATION ERROR
Ripple content is due to several factors. Tachogenerators suffer
from ripple due to the speed of rotation, commutator segments
and the number of poles. The resolver/RDC combination has a
predominant ripple at twice the resolver reference as a result of
the synchronous demodulator and at a frequency twice per
revolution due to the resolver windings mismatch.
A tracking converter employing a Type 2 servo loop does not
suffer any velocity lag, however, there is an additional error due
to acceleration. This additional error can be defined using the
acceleration constant KA of the converter.
Input Acceleration
K A
=
Error inOutput Angle
Motor torque pulsations which are a consequence of excessive
velocity ripple have a detrimental effect upon the quality of
speed control in servo systems.
The numerator and denominator must have consistent angular
units. For example if KA is in sec–2, then the input acceleration
may be specified in degrees/sec2 and the error output in degrees.
The resultant “cogging” effect will be particularly noticeable at
low speed and when the motor is in the low torque region.
KA does not define maximum input acceleration, only the error due
to acceleration. The maximum acceleration allowable before the
converter loses track is dependent on the angular accuracy
requirements of the system.
Other undesirable side effects such as the increase in acoustic
noise from a motor and a temperature rise in the motor stator
windings are possible results of the presence of torque ripple.
Angular Accuracy × KA = Degrees/sec2
For more detailed information of the causes and sources of
errors see the Velocity Errors section.
KA can be used to predict the output position error for a
given input acceleration. For example for an acceleration of
100 revs/sec2, KA = 2.7 × 106 sec–2 and 12-bit resolution.
AD2S83 COMPARISON WITH DC TACHOGENERATOR
Comparative tests of the AD2S83 and a dc tachogenerator were
carried out. The tachogenerator was connected at the nondrive
end of the motor shaft with the resolver located behind the drive
shaft of the motor. The AD2S83 was located remotely. The
AD2S83 was set up with a 200 Hz bandwidth, reference fre-
quency of 2.6 kHz and resolution of 14 bits.
Input acceleration [LSB/sec2]
Error in LSBs =
K A[sec–2
]
12
100 [rev/sec2 ] × 2
=
= 0.15 LSBs or 47.5 seconds of arc
2. 7 ×106
The comparative analysis can be summarized:
To determine the value of KA based on the passive components
used to define the dynamics of the converter the following
should be used.
AD2S83 DC Tacho Conditions
Linearity %
0.1
0.1
0–3600 rpm
4.04 ×1011
Reversion Error % FSO 0.3
0.25
K A
=
2n × R6 × R4 ×(C4 + C5)
Note the typical operating range of dc tachogenerator is
0 rpm-3600 rpm. The resolver/AD2S83 combination will oper-
ate up to speeds in excess of 10000 rpm.
Where n = resolution of the converter.
R4, R6 in ohms
C5, C4 in farads.
Ripple Effects
The comparative analysis of the output ripple from the tacho-
generator and the AD2S83 is illustrated below.
Minimization of the AD2S83 output ripple is discussed in detail
in the Velocity Errors section.
Other Factors
Other factors concerning choice of feedback source have to be
addressed. On average the MTBF of a tachogenerator is 347
days as opposed to typically 8 years for a resolver. Resolvers are
relatively insensitive to temperature whereas a tachogenerator
will be specified up to a maximum of 100°C with a 0.1%/°C
(above 25°C) degradation in output voltage. The brushless
resolver requires no preventative maintenance; the brushes on a
tachogenerator, however, will require periodic checking.
REV. E
–15–
AD2S83
VELOCITY ERRORS
SOURCES OF ERRORS
Some “ripple” or noise will always be present in the velocity
signal. Velocity signal ripple is caused by, or related to, the
following parameters. The resulting effects are generally addi-
tive. This means diagnosis needs to be an iterative process in
order to define the source of the error.
Integrator Offset
Additional inaccuracies in the conversion of the resolver signals
will result from an offset at the input to the integrator. This
offset will be treated as an error signal. The resulting angular
error will typically be 1 arc minute over the operating tempera-
ture range.
1.0 Reference Frequency
A ripple content at the reference frequency is superimposed
on the velocity signal output. The amplitude depends on
the loop bandwidth. This error is a function of a dc offset at
the input to Phase Sensitive Demodulator (PSD).
A description of how to adjust the zero offset is given in the
Component Selection section; the circuit required is shown in
Figure 1.
Differential Phase Shift
2.0 Resolver Inaccuracies
Phase shift between the sine and cosine signals from the resolver
is known as differential phase shift and can cause static error.
Some differential phase shift will be present on all resolvers as a
result of coupling. A small resolver residual voltage (quadrature
voltage) indicates a small differential phase shift. Additional
phase shift can be introduced if the sine channel wires and the
cosine channel wires are treated differently. For instance, differ-
ent cable lengths or different loads could cause differential phase
shift.
Impedance mismatch occur in the sine and cosine windings
of the resolver. These give rise to differential phase shift
between the sine and cosine inputs to the RDC and varia-
tions in the resolver output amplitudes.
2.1 Sine and Cosine Amplitude Mismatch
This is normally identified by the presence of asymmetrical
ripple voltages.
2.2 Differential Phase Shift between the Sine and Cosine Inputs
The frequency of this ripple is usually twice the input veloc-
ity, and the amplitude is proportional to the magnitude of
the velocity signal. The phase shift is normally induced
through the connections from the resolver to the converter.
Maintaining equal lengths of screened twisted pair cable
from the resolver to the AD2S83 will reduce the effects of
resistive imbalance, and therefore, reduce differential phase
shift.
The additional error caused by differential phase shift on the
input signals approximates to
Error = 0.53 a × b arc minutes
where a = differential phase shift (degrees).
b = signal to reference phase shift (degrees).
This error can be minimized by choosing a resolver with a small
residual voltage, ensuring that the sine and cosine signals are
handled identically and removing the reference phase shift (see
the Connecting the Resolver section). By taking these precau-
tions the extra error can be made insignificant.
3.0 LSB Update Ripple
LSB update noise occurs as the resolver rotates and the
digital outputs of the RDC are updated. For a correctly
scaled loop, this ripple component has a magnitude of
approximately 2 mV peak at 16-bit resolution.
Most resolvers exhibit a phase shift between the signal and the
reference. This phase shift will, however, give rise under
dynamic conditions to an additional error defined by:
3.1 Ripple due to the LSB rate given by:
LSB rate = N × Reference Frequency
Shaft Speed (rps)× Phase Shift (Degrees)
= Error Degrees
The PSD generates sums and differences of all its compo-
nent input frequencies, so when the LSB update rate is an
multiple of the reference frequency, a beat frequency is
generated. The magnitude of this ripple is a function of the
LSB weighting, i.e., ripple is less at 16 bits.
Reference Frequency
Under static operating conditions phase shift between the refer-
ence and the signal lines alone will not theoretically affect the
converter’s static accuracy.
4.0 Torque Ripple
For example, for a phase shift of 20 degrees, a shaft rotation of
22 rps and a reference frequency of 5 kHz, the converter will
exhibit an additional error of:
Torque ripple is a phenomenon associated with motors. An
ac motor naturally exhibits a sinusoidal back emf. In an
ideal system the current fed to the motor should, in order
to cancel, also be sinusoidal. In practice the current is often
trapezoidal. Consequently, the output torque from the motor
will not be smooth and torque ripple is created. If the load-
ing on a motor is constant, the velocity of the motor shaft
will vary as a result of the cyclic variation of motor torque.
The variation in velocity then appears on the velocity
output as ripple. This is not an error but a true velocity
variation in the system.
22 × 20
= 0.088 Degrees
5000
This effect can be eliminated by placing a phase shift in the
reference to the converter equivalent to the phase shift in the
resolver (see the Connecting the Resolver section).
Note: Capacitive and inductive crosstalk in the signal and reference
leads and wiring can cause similar problems.
–16–
REV. E
AD2S83
1
Offset Errors
PHASE LEAD = ARC TAN
C
PHASE LAG = ARC TAN 2ꢆfRC
2ꢆfRC
The limiting factor in the measuring of low or “creep” speeds is
the level of dc offset present at zero velocity. The zero velocity
dc offset at the output of the AD2S83 is a function of the input
bias current to the VCO and the value for the input resistor R6.
See “Circuit Functions and Dynamic Performance VCO.”
R
R
C
PHASE SHIFT
CIRCUITS
The offset can be minimized by reducing the maximum tracking
rate so reducing the value for R6. Offset is a function of tracking
rate and therefore resolution; the dc offset is lowest at 16 bits.
To increase the dynamic range of the velocity dynamic resolu-
tion switching can be employed. (Contact MCG Applications
for more information.)
Figure 10. Phase Shift Circuits
TYPICAL CIRCUIT CONFIGURATION
Figure 11 shows a typical circuit configuration for the AD2S83
with 12-bit resolution. Values of the external components have
been chosen for a reference frequency of 5 kHz and a maximum
tracking rate of 260 rps with a bandwidth of 520 Hz. Placing the
values for R4, R6, C4, and C5 in the equation for KA gives a
value of 1.65 × 106. The resistors are 0.125 W, 5% tolerance
preferred values. The capacitors are 100 V ceramic, 10% toler-
ance components.
CONNECTING THE RESOLVER
The recommended connection circuit is shown in Figure 11.
In cases where the reference phase relative to the input signals
from the resolver requires adjustment, this can be easily
achieved by varying the value of the resistor R2 of the HF filter
(see Figure 1).
For signal and reference voltages greater than 2 V rms a simple
voltage divider circuit of resistors can be used to generate the
correct signal level at the converter. Care should be taken to
ensure that the ratios of the resistors between the sine signal line
and ground and the cosine signal line and ground are the same.
Any difference will result in an additional position error.
Assume that R1 = R2 = R and C1 = C2 = C
1
and Reference Frequency =
.
2 π RC
For more information on resistive scaling of SIN, COS, and
REFERENCE converter inputs refer to the application note,
“Circuit Applications of the 2S81 and 2S80 Resolver-to-Digital
Converters.”
By altering the value of R2, the phase of the reference relative to
the input signals will change in an approximately linear manner
for phase shifts of up to 10 degrees.
Increasing R2 by 10% introduces a phase lag of two degrees.
Decreasing R2 by 10% introduces a phase lead of two degrees.
R9
1Mꢂ
R8
4.7Mꢂ
C2
2.2nF
R2
15kꢂ
C3
100nF
R3
100kꢂ
REFERENCE
INPUT
C1
2.2nF
VELOCITY
O/P
R5
C4
1.2nF
C5
6.2nF
R6
R4
200kꢂ
62kꢂ
130kꢂ
100nF
R1
15kꢂ
C7
150pF
COS HIGH
REF LOW
COS LOW
SIN LOW
RESOLVER
SIGNAL
C6
390pF
R7
100nF
3.3kꢂ
6
5
4
3
2
1
44 43 42 41 40
–12V
SIN HIGH
+12V
7
8
9
39
38
37
36
35
34
33
32
31
30
29
RIPPLE CLOCK
DIRECTION
BUSY
10
MSB
11
12
13
14
15
16
17
COMPLEMENT
DATA LOAD
AD2S83
TOP VIEW
(Not to Scale)
DATA
OUTPUT
0V
SC2
INHIBIT
18 19 20 21 22 23 24 25 26 27 28
DATA OUTPUT
NOTE: R7, C6 AND C7 SHOULD BE CONNECTED AS
CLOSE AS POSSIBLE TO THE CONVERTER PINS.
SIGNAL SCREENS SHOULD BE CONNECTED TO PIN 5.
Figure 11. Typical Circuit Configuration
REV. E
–17–
AD2S83
APPLICATIONS
OTHER PRODUCT
Control Transformer
AD2S90. Low-cost resolver-to-digital converter with outputs
which emulate optical encoders and a serial output for absolute
position information. Unlike the AD2S83, the AD2S90 requires
no external components to operate. The AD2S90 is built on
LC2MOS and packaged in a 20-lead PLCC.
The ratio multiplier of the AD2S83 can be used independently
of the loop integrators as a control transformer. In this mode,
the resolver inputs θ are multiplied by a digital angle φ, any
difference between φ and θ will be represented by the AC
ERROR output as Sin ωt sin (θ–φ) or the DEMOD output
as sin (θ–φ). To use the AD2S83 in this mode refer to the
“Control Transformer” application note.
AD2S80A/AD2S81A/AD2S82A. Monolithic resolver-to-digital
converter. The AD2S80/AD2S82A offer selectable 10, 12, 14,
16 bits of resolution. The AD2S81A has 12-bit resolution. All
devices have user selectable dynamics. The AD2S80A is available
in 40-lead DDIP, 44-lead LCC and is qualified to MIL-STD-
883B REV. E. The is available in a 44-lead PLCC, and the
AD2S81A in a 28-lead DDIP.
–18–
REV. E
AD2S83
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Plastic Leaded Chip Carrier (PLCC)
(P-44A)
0.180 (4.57)
0.165 (4.19)
0.056 (1.42)
0.042 (1.07)
0.048 (1.21)
0.042 (1.07)
0.025 (0.63)
0.015 (0.38)
0.048 (1.21)
0.042 (1.07)
6
40
39
7
PIN 1
IDENTIFIER
0.050
(1.27)
BSC
0.63 (16.00)
0.59 (14.99)
0.021 (0.53)
0.013 (0.33)
TOP VIEW
(PINS DOWN)
0.032 (0.81)
0.026 (0.66)
17
29
28
18
0.040 (1.01)
0.025 (0.64)
0.020
(0.50)
R
0.656 (16.66)
0.650 (16.51)
SQ
0.110 (2.79)
0.085 (2.16)
0.695 (17.65)
0.685 (17.40)
SQ
REV. E
–19–
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