AD1851RZ-J [ADI]
16-Bit/18-Bit, 16 3 FS PCM Audio DACs; 16位/ 18位， 16 3 FS PCM音频数模转换器
| 型号： | AD1851RZ-J |
| 厂家： | 
ADI |
| 描述： | 16-Bit/18-Bit, 16 3 FS PCM Audio DACs |
| 文件： | 总12页 (文件大小：200K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16-Bit/18-Bit, 16
؋
F S
a
PCM Audio DACs
AD1851/AD1861
FUNCTIO NAL BLO CK D IAGRAM
FEATURES
110 dB SNR
Fast Settling Perm its 16
؋
Oversam pling ؎3 V Output
Optional Trim Allow s Super-Linear Perform ance
؎5 V Operation
16-Pin Plastic DIP and SOIC Packages
Pin-Com patible w ith AD1856 & AD1860 Audio DACs
2s Com plem ent, Serial Input
–V
1
2
3
4
5
6
7
8
+V
S
16
15
S
LATCH
DAC
TRIM
DGND
SERIAL
INPUT
REGISTER
+V
L
14 MSB ADJ
NC
CLK
LE
I
I
13
12
11
OUT
OUT
AGND
SJ
CONTROL
LOGIC
APPLICATIONS
High-End Com pact Disc Players
Digital Audio Am plifiers
DAT Recorders and Players
Synthesizers and Keyboards
R
F
DATA
NC
10
9
AD1851/
AD1861
V
OUT
NC = NO CONNECT
P RO D UCT D ESCRIP TIO N
T he critical specifications of T HD+N and signal-to-noise ratio
are 100% tested for all devices.
T he AD1851/AD1861 is a monolithic PCM audio DAC. T he
AD1851 is a 16-bit device, while the AD1861 is an 18-bit de-
vice. Each device provides a voltage output amplifier, DAC,
serial-to-parallel register and voltage reference. T he digital por-
tion of the AD1851/AD1861 is fabricated with CMOS logic
elements that are provided by Analog Devices’ 2 µm ABCMOS
process. T he analog portion of the AD1851/AD1861 is fabri-
cated with bipolar and MOS devices as well as thin-film
resistors.
T he AD1851/AD1861 operates with ±5 V power supplies, mak-
ing it suitable for home use markets. T he digital supply, VL, can
be separated from the analog supplies, VS and –VS, for reduced
digital crosstalk. Separate analog and digital ground pins are
also provided. Power dissipation is 100 mW typical.
T he AD1851/AD1861 is available in either a 16-pin plastic DIP
or a 16-pin plastic SOIC package. Both packages incorporate
the industry standard pinout found on the AD1856 and
AD1860 PCM audio DACs. As a result, the AD1851/AD1861
is a drop-in replacement for designs where ±5 V supplies have
been used with the AD1856/AD1860. Operation is guaranteed
over the temperature range of –25°C to +70°C and over the
voltage supply range of ±4.75 V to ±5.25 V.
T his combination of circuit elements, as well as careful design
and layout techniques, results in high performance audio play-
back. Laser-trimming of the linearity error affords low total har-
monic distortion. An optional linearity trim pin is provided to
allow residual differential linearity error at midscale to be elimi-
nated. T his feature is particularly valuable for low distortion
reproductions of low amplitude signals. Output glitch is also
small, contributing to the overall high level of performance. T he
output amplifier achieves fast settling and high slew rates, pro-
viding a full ±3 V signal at load currents up to 8 mA. When
used in current output mode, the AD1851/AD1861 provides a
±1 mA output signal. T he output amplifier is short circuit
protected and can withstand indefinite shorts to ground.
P RO D UCT H IGH LIGH TS
l. AD1851 16-bit resolution provides 96 dB dynamic range.
AD1861 18-bit resolution provides 108 dB dynamic range.
2. No external components are required.
3. Operates with ±5 V supplies.
4. Space saving 16-pin SOIC and plastic DIP packages.
5. 100 mW power dissipation.
T he serial input interface consists of the clock, data and latch
enable pins. T he serial 2s complement data word is clocked into
the DAC, MSB first, by the external clock. T he latch enable
signal transfers the input word from the internal serial input
register to the parallel DAC input register. T he AD1851 input
clock can support a 12.5 MHz data rate, while the AD1861 in-
put clock can support a 13.5 MHz data rate. T his serial input
port is compatible with second generation digital filter chips
used in consumer audio products. T hese filters operate at over-
sampling rates of 2ϫ, 4ϫ, 8ϫ and 16ϫ sampling frequencies.
6. High input clock data rates and 1.5 µs settling time permits
2ϫ, 4ϫ, 8ϫ and 16ϫ oversampling.
7. ±3 V or ±1 mA output capability.
8. T HD + Noise and SNR are 100% tested.
9. Pin-compatible with AD1856 & AD1860 PCM audio DACs.
REV. A
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
(T @ +25؇C and ؎5 V supplies, unless otherwise noted)
A
AD1851/AD1861–SPECIFICATIONS
Min
Typ
Max
Units
DIGIT AL INPUT S
VIH
VIL
2.0
+VL
0.8
V
V
I
IH, VIH = VL
1.0
–10
µA
µA
IIL, VIL = 0.4
ACCURACY
Gain Error
±1
%
Midscale Output Voltage
±10
mV
DRIFT (0°C to +70°C)
T otal Drift
Bipolar Zero Drift
±25
±4
ppm of FSR/°C
ppm of FSR/°C
SET T LING T IME (T o ±0.0015% of FSR)
Voltage Output
6 V Step
1 LSB Step
Slew Rate
1.5
1.0
9
µs
µs
V/µs
Current Output
1 mA Step 10 Ω to 100 Ω Load
1 kΩ Load
350
350
ns
ns
OUT PUT
Voltage Output Configuration
Bipolar Range
Output Current
؎2.88
±8
±3.0
؎3.12
V
mA
Ω
Output Impedance
0.1
Short Circuit Duration
Current Output Configuration
Bipolar Range (±30%)
Output Impedance (±30%)
Indefinite to Common
±1.0
1.7
mA
kΩ
POWER SUPPLY
Voltage
+VL and +VS
–VS
4.75
–5.25
5.25
–4.75
V
V
T EMPERAT URE RANGE
Specification
Operation
0
–25
–60
+25
+70
+70
+100
°C
°C
°C
Storage
WARM-UP T IME
1
min
Specifications subject to change without notice.
16-BIT
LATCH
16-BIT
DAC
16-BIT
LATCH
16-BIT
DAC
–V
1
+V
S
–V
+V
S
16
1
16
S
S
DGND
2
DGND
TRIM
15
14
TRIM
2
3
15
14
SERIAL
INPUT
REGISTER
SERIAL
INPUT
REGISTER
+V
L
+V
MSB ADJ
L
3
4
MSB ADJ
I
I
NC
I
NC
I
4
OUT
13
12
OUT
OUT
13
12
OUT
AGND
CLK
LE
AGND
CLK
LE
5
6
5
6
CONTROL
LOGIC
CONTROL
LOGIC
11 SJ
11 SJ
R
DATA
NC
10
F
DATA
NC
R
7
8
10
F
7
8
V
V
OUT
9
OUT
AD1851
9
AD1851
NC = NO CONNECT
NC = NO CONNECT
AD1851 Functional Block Diagram
AD1861 Functional Block Diagram
–2–
REV. A
AD1851/AD1861
AD1851
Min
Typ
Max
Units
RESOLUT ION
16
Bits
T OT AL HARMONIC DIST ORT ION + NOISE
0 dB, 990.5 Hz
AD1851N-J, R-J
AD1851N, R
0.003
0.004
0.004
0.008
%
%
–20 dB, 990.5 Hz
AD1851N-J, R-J
AD1851N, R
0.009
0.009
0.016
0.040
%
%
–60 dB, 990.5 Hz
AD1851N-J, R-J
AD1851N, R
0.9
0.9
1.6
4.0
%
%
D-RANGE* (With A-Weight Filter)
–60 dB, 990.5 Hz AD1851N, R
AD1851N-J, R-J
88
96
dB
dB
SIGNAL-T O-NOISE RAT IO
107
110
dB
MAXIMUM CLOCK INPUT FREQUENCY
12.5
MHz
ACCURACY
Differential Linearity Error
±0.001
% of FSR
Bits
MONOT ONICIT Y
14
POWER SUPPLY
Current
+I
–I
10.0
–10.0
100
13.0
–15.0
mA
mA
mW
Power Dissipation
AD1861
Min
Typ
Max
18
Units
RESOLUT ION
Bits
T OT AL HARMONIC DIST ORT ION + NOISE
0 dB, 990.5 Hz
AD1861N-J, R-J
AD1861N, R
0.003
0.004
0.004
0.008
%
%
–20 dB, 990.5 Hz
AD1861N-J, R-J
AD1861N, R
0.009
0.009
0.016
0.040
%
%
–60 dB, 990.5 Hz
AD1861N-J, R-J
AD1861N, R
0.9
0.9
1.6
4.0
%
%
D-RANGE* (With A-Weight Filter)
–60 dB, 990.5 Hz AD1861N, R
AD1861N-J, R-J
88
96
dB
dB
SIGNAL-T O-NOISE RAT IO
107
110
dB
MAXIMUM CLOCK INPUT FREQUENCY
13.5
MHz
ACCURACY
Differential Linearity Error
±0.001
% of FSR
Bits
MONOT ONICIT Y
15
POWER SUPPLY
Current
+I
–I
10.0
–10.0
100
13.0
–15.0
mA
mA
mW
Power Dissipation
*T ested in accordance with EIAJ T est Standard CP-307.
Specifications subject to change without notice.
REV. A
–3–
AD1851/AD1861
ABSO LUTE MAXIMUM RATINGS*
P IN D ESCRIP TIO NS
VL to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 6.50 V
VS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 6.50 V
–VS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –6.50 V to 0 V
Digital Inputs to DGND . . . . . . . . . . . . . . . . . . . –0.3 V to VL
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3 V
Short Circuit . . . . . . . . . . . . . . . . . Indefinite Short to Ground
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C, 10 sec
Storage T emperature . . . . . . . . . . . . . . . . . . –60°C to +100°C
1
2
3
4
5
6
7
8
–VS
DGND
VL
NC
CLK
LE
DAT A
NC
VOUT
RF
Analog Negative Power Supply
Logic Ground
Logic Positive Power Supply
No Connection
Clock Input
Latch Enable Input
Serial Data Input
No Internal Connection*
Voltage Output
Feedback Resistor
Summing Junction
Analog Ground
Current Output
MSB Adjustment T erminal
MSB T rimming Potentiometer T erminal
Analog Positive Power Supply
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
9
10
11
12
13
14
15
16
SJ
AGND
IOUT
MSB ADJ
T RIM
VS
O RD ERING GUID E
P ackage
Model
Resolution
TH D + N
O ption*
*Pin 8 has no internal connection; -VL from AD1856 or AD1860 socket can be
safely applied.
AD1851N
AD1851N-J
AD1851R
AD1851R-J
AD1861N
AD1861N-J
AD1861R
16 Bits
16 Bits
16 Bits
16 Bits
18 Bits
18 Bits
18 Bits
18 Bits
0.008%
0.004%
0.008%
0.004%
0.008%
0.004%
0.008%
0.004%
N-16
N-16
R-16
R-16
N-16
N-16
R-16
R-16
AD1861R-J
*N = Plastic DIP Package; R = Small Outline (SOIC) Package.
CAUTIO N
ESD (electrostatic discharge) sensitive device. T he digital control inputs are diode protected;
however, permanent damage may occur on unconnected devices subject to high energy electro-
static fields. Unused devices must be stored in conductive foam or shunts. T he protective foam
should be discharged to the destination socket before devices are inserted .
WARNING!
ESD SENSITIVE DEVICE
Typical Performance
10
175
150
1
125
–60dB
100
0.1
75
0.01
50
25
–20dB
0dB
0.001
2
4
6
8
10
12
14
–30 –20 –10
0
10
20 30 40
50 60 70 80 90
CLOCK FREQUENCY – MHz
TEMPERATURE – °C
Power Dissipation vs. Clock Frequency
THD vs. Tem perature
–4–
REV. A
AD1851/AD1861
R
TO TAL H ARMO NIC D ISTO RTIO N
F
T otal harmonic distortion plus noise (T HD+N) is defined as
the ratio of the square root of the sum of the squares of the val-
ues of the first 19 harmonics and noise to the value of the funda-
mental input frequency. It is usually expressed in percent (%).
I
DAC
REFERENCE
OUT
AUDIO
OUTPUT
T HD+N is a measure of the magnitude and distribution of lin-
earity error, differential linearity error, quantization error and
noise. T he distribution of these errors may be different, depend-
ing on the amplitude of the output signal. T herefore, to be most
useful, T HD+N should be specified for both large (0 dB) and
small signal amplitudes (–20 dB and –60 dB).
INPUT LATCH
SERIAL-TO-PARALLEL
CONVERSION
CLOCK
LE
DATA
T he T HD+N figure of an audio DAC represents the amount of
undesirable signal produced during reconstruction and playback
of an audio waveform. T his specification, therefore, provides a
direct method to classify and choose an audio DAC for a
desired level of performance.
Figure 1. AD1851/AD1861 Functional Block Diagram
FUNCTIO NAL D ESCRIP TIO N
T he AD1851/AD1861 is a complete monolithic PCM audio
DAC. No additional external components are required for op-
eration. As shown in Figure 1 above, each chip contains a volt-
age reference, an output amplifier, a DAC, an input latch and a
parallel input register.
SETTLING TIME
Settling time is the time required for the output of the DAC to
reach and remain within a specified error band about its final
value, measured from the digital input transition. It is a primary
measure of dynamic performance.
T he voltage reference consists of a bandgap circuit and buffer
amplifier. T his combination of elements produces a reference
voltage that is unaffected by changes in temperature and age.
T he DAC output voltage, which is derived from the reference
voltage, is also unaffected by these environmental changes.
MID SCALE ERRO R
Midscale error, or bipolar zero error, is the deviation of the ac-
tual analog output from the ideal output (0 V) when the 2s
complement input code representing half scale is loaded in the
input register.
T he output amplifier uses both MOS and bipolar devices to
produce low offset, high slew rate and optimum settling time.
When combined with the on-chip feedback resistor, the output
op amp converts the output current of the AD1851/AD1861 to
a voltage output.
D -RANGE D ISTO RTIO N
D-range distortion is equal to the value of the total harmonic
distortion + noise (T HD+N) plus 60 dB when a signal level of
–60 dB below full scale is reproduced. D-range is tested with a
1 kHz input sine wave. T his is measured with a standard A-
weight filter as specified by EIAJ Standard CP-307.
T he DAC uses a combination of segmented decoder and R-2R
architecture to achieve consistent linearity and differential lin-
earity. T he resistors which form the ladder structure are fabri-
cated with silicon chromium thin film. Laser-trimming of these
resistors further reduces linearity error, resulting in low output
distortion.
SIGNAL-TO -NO ISE RATIO
T he signal-to-noise ratio (SNR) is defined as the ratio of the
amplitude of the output when a full-scale output is present to
the amplitude of the output with no signal present. T his is mea-
sured with a standard A-weight filter as specified by EIAJ
Standard CP-307.
T he input register and serial-to-parallel converter are fabricated
with CMOS logic gates. T hese gates allow the achievement of
fast switching speeds and low power consumption. T his contrib-
utes to the overall low power dissipation of the AD1851/
AD1861.
REV. A
–5–
AD1851/AD1861
However, three separate voltage supplies are not necessary for
good circuit performance. For example, Figure 3 illustrates a
system where only a single positive and a single negative supply
are available.
Analog Circuit Considerations
GRO UND ING RECO MMEND ATIO NS
T he AD1851/AD1861 has two ground pins, designated Analog
and Digital ground. T he analog ground pin is the “high quality”
ground reference point for the device. T he analog ground pin
should be connected to the analog common point in the system.
T he output load should also be connected to that same point.
In this example, the positive logic and positive analog supplies
must both be connected to +5 V, while the negative analog sup-
ply will be connected to –5 V. Performance would benefit from
a measure of isolation between the supplies introduced by using
simple low pass filters in the individual power supply leads.
T he digital ground pin returns ground current from the digital
logic portions of the AD1851/AD1861 circuitry. T his pin
should be connected to the digital common point in the system.
+5V
+5V
16
3
As illustrated in Figure 2, the analog and digital grounds should
be connected together at one point in the system.
+V
L
+V
S
AD1851/AD1861
5V
+
+5V
–V
DGND
2
AGND
12
S
1
3
16
+V
+V
ANALOG
GROUND
DIGITAL
GROUND
L
S
–5V
AD1851/AD1861
–V
DGND
2
S
AGND
12
Figure 3. Alternate Recom m ended Schem atic
1
As with most linear circuits, changes in the power supplies will
affect the output of the DAC. Analog Devices recommends that
well regulated power supplies with less than 1% ripple be incor-
porated into the design of any system using the AD1851/AD1861.
DIGITAL
GROUND
ANALOG
GROUND
5V
–
Figure 2. Recom m ended Circuit Schem atic
O P TIO NAL MSB AD JUSTMENT
Use of an optional adjustment circuit allows residual differential
linearity error around midscale to be eliminated. T his error is
especially important when low amplitude signals are being re-
produced. In those cases, as the signal amplitude decreases, the
ratio of the midscale differential linearity error to the signal am-
plitude increases, thereby increasing T HD.
P O WER SUP P LIES AND D ECO UP LING
T he AD1851/AD1861 has three power supply input pins. T he
±VS supplies provide the supply voltages to operate the linear
portions of the DAC including the voltage reference, output am-
plifier and control amplifier. T he ±VS supplies are designed to
operate at ±5 V.
T herefore, for best performance at low output levels, the op-
tional MSB adjust circuitry shown in Figure 4 may be used to
improve performance. T he adjustment should be made with a
small signal input (–20 dB or –60 dB).
T he +VL supply operates the digital portions of the chip includ-
ing the input shift register and the input latching circuitry. T he
+VL supply is designed to operate at +5 V.
Decoupling capacitors should be used on all power supply pins.
Furthermore, good engineering practice suggests that these ca-
pacitors be placed as close as possible to the package pins as
well as to the common points. T he logic supply, +VL, should be
decoupled to digital common, while the analog supplies, ±VS,
should be decoupled to analog common.
–V
1
TRIM
15
S
470kΩ
100kΩ
200kΩ
14
MSB
ADJUST
T he use of three separate power supplies will reduce feedthrough
from the digital portion of the system to the linear portion of the
system, thus contributing to improved performance.
Figure 4. Optional THD Adjust Circuit
–6–
REV. A
AD1851/AD1861
AD 1861 D IGITAL CIRCUIT CO NSID ERATIO NS
AD 1861 Input D ata
AD 1851 D IGITAL CIRCUIT CO NSID ERATIO NS
AD 1851 Input D ata
Data is transmitted to the AD1861 in a bit stream composed of
18-bit words with a serial, MSB first format. T hree signals
must be present to achieve proper operation. T hey are the
Data, Clock and Latch Enable (LE) signals. Input data bits are
clocked into the input register on the rising edge of the Clock
signal. T he LSB is clocked in on the 18th clock pulse. When all
data bits are loaded, a low-going Latch Enable pulse updates
the DAC input. Figure 7 illustrates the general signal require-
ments for data transfer to the AD1861.
Data is transmitted to the AD1851 in a bit stream composed of
16-bit words with a serial, MSB first format. T hree signals
must be present to achieve proper operation. T hey are the
Data, Clock and Latch Enable (LE) signals. Input data bits are
clocked into the input register on the rising edge of the Clock
signal. T he LSB is clocked in on the 16th clock pulse. When all
data bits are loaded, a low-going Latch Enable pulse updates
the DAC input. Figure 5 illustrates the general signal require-
ments for data transfer to the AD1851.
CLOCK
CLOCK
L
S
B
M
S
B
M
S
B
L
S
B
DATA
DATA
LATCH
LATCH
Figure 5. Signal Requirem ents for AD1851
Figure 7. Signal Requirem ents for AD1861
Figure 6 illustrates the specific timing requirements that must
be met in order for the data transfer to be accomplished prop-
erly. T he input pins of the AD1851 are both T T L and 5 V
CMOS compatible. T he input requirements illustrated in Fig-
ures 5 and 6 are compatible with data outputs provided by
popular DSP filter chips used in digital audio playback systems.
T he AD1851 input clock can run at a 12.5 MHz rate. T his
clock rate will allow data transfer rates for 2ϫ, 4ϫ or 8ϫ or
16ϫ oversampling reconstructions.
Figure 8 illustrates the specific timing requirements that must
be met in order for the data transfer to be accomplished prop-
erly. T he input pins of the AD1861 are both T T L and 5 V
CMOS compatible. T he input requirements illustrated in Fig-
ures 7 and 8 are compatible with data outputs provided by
popular DSP filter chips used in digital audio playback systems.
T he AD1861 input clock can run at a 13.5 MHz rate. T his
clock rate will allow data transfer rates for 2ϫ, 4ϫ or 8ϫ or
16ϫ oversampling reconstructions.
>30ns
>30ns
DATA
DATA
>15ns
>40ns
>15ns
>15ns
>15ns
>40ns
CLOCK
LATCH
CLOCK
LATCH
>30ns
>30ns
>80.0ns
>30ns
>30ns
>74.1ns
>15ns
>15ns
>40ns
>40ns
>40ns
>40ns
Figure 6. Tim ing Relationships of AD1851 Input Signals
Figure 8. Tim ing Relationships of AD1861 Input Signals
REV. A
–7–
AD1851/AD1861
AP P LICATIO NS
Figures 9 through 12 show connection diagrams for the
AD1851 and AD1861 and the Yamaha YM3434 and the NPC
SM5813AP/APT digital filter chips.
LEFT
OUTPUT
CLK
X1
+5V
CLK
LOW
PASS
FILTER
OUT
LATCH
ST 16/18
DLO
BCO
DATA AD1851
WCO
DRO
YM3434
DATA
LOW
PASS
FILTER
LATCH
CLK
OUT
RIGHT
OUTPUT
AD1851
Figure 9. AD1851 with Yam aha YM3434 Digital Filter
+5V
LEFT
OUTPUT
CLK
X1
CLK
LOW
PASS
FILTER
OUT
LATCH
DATA
ST 16/18
DLO
BCO
AD1861
YM3434
WCO
DRO
DATA
LOW
PASS
LATCH
OUT
FILTER
RIGHT
OUTPUT
CLK
AD1861
Figure 10. AD1861 with Yam aha YM3434 Digital Filter
–8–
REV. A
AD1851/AD1861
+5V
LEFT
OUTPUT
CLK
X1
CLK
LOW
PASS
FILTER
LATCH
DATA
OUT
COB
OW20
AD1851
DOL
BCKO
WCKO
DOR
SM5813AP/APT
DATA
LATCH
CLK
OW18
+5V
LOW
PASS
OUT
FILTER
RIGHT
OUTPUT
AD1851
Figure 11. AD1851 with NPC SM5813AP/APT Digital Filter
+5V
LEFT
OUTPUT
CLK
X1
CLK
LOW
PASS
FILTER
OUT
LATCH
COB
OW20
AD1861
DATA
DOL
BCKO
WCKO
SM5813AP/APT
DATA
LATCH
CLK
DOR
OW18
LOW
PASS
FILTER
OUT
RIGHT
OUTPUT
AD1861
Figure 12. AD1861 with NPC SM5813AP/APT Digital Filter
REV. A
–9–
AD1851/AD1861
O TH ER D IGITAL AUD IO CO MP O NENTS AVAILABLE
FRO M ANALO G D EVICES
16-BIT
DAC
18-BIT
DAC
16-BIT
LATCH
+V
18-BIT
LATCH
+V
16
S
–V
–V
S
1
16
S
1
S
DGND
DGND
TRIM
TRIM
2
3
15
14
2
3
15
14
SERIAL
INPUT
SERIAL
INPUT
+V
L
+V
L
MSB ADJ
MSB ADJ
REGISTER
REGISTER
I
I
I
I
4
5
6
13
4
5
6
13
OUT
OUT
OUT
OUT
NC
NC
12 AGND
12 AGND
CLK
CLK
CONTROL
LOGIC
CONTROL
LOGIC
11
11
LE
SJ
LE
SJ
R
F
R
F
DATA
7
8
10
9
DATA
7
8
10
9
–V
L
V
–V
L
V
OUT
OUT
AD1856
AD1860
NC = NO CONNECT
NC = NO CONNECT
AD 1856 16-BIT AUD IO D AC
AD 1860 18-BIT AUD IO D AC
Complete, No External Components Required
0.0025% T HD
Complete, No External Components Required
0.0025% T HD+N
Low Cost
16-Pin DIP or SOIC Package
Standard Pinout
108 dB Signal-to-Noise Ratio
16-Pin DIP or SOIC Package
Standard Pinout
–V
AD1864
+V
S
1
24
23
S
–V
–V
16
15
14
13
1
2
+V
S
S
TRIM
2
3
TRIM
MSB
REFERENCE
VOLTAGE
REFERENCE
REFERENCE
NR2
ADJ
S
MSB
22
I
OUT
4
I
TRIM
21
20
19
3
OUT
AGND
SJ
AGND
SJ
5
6
+V
L
NR1
4
5
AGND
12
11
CLK
R
F
7
R
F
18
17
INPUT
AND
DIGITAL
OFFSET
–
+
–
+
20-BIT
DAC
V
V
I
8
9
OUT
OUT
6
7
LE
OUT
–V
L
+V
L
16
15
R
F
10
9
DATA
DR
10
18-BIT
D/A
18-BIT
D/A
DL
18-BIT
LATCH
18-BIT
LATCH
DGND
8
–V
L
LR 11
CK 12
AD1862
LL
14
13
DGND
NC = NO CONNECT
AD 1862 20-BIT AUD IO D AC
119 dB Signal-to-Noise Ratio
0.0016% T HD+N
AD 1864 D UAL 18-BIT AUD IO D AC
Complete, No External Components
0.0025% T HD+N
102 dB D-Range Performance
±1 dB Gain Linearity
16-Pin DIP
108 dB Signal-to-Noise Ratio
Cophased Outputs
24-Pin Package
–10–
REV. A
AD1851/AD1861
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
N (P lastic D IP ) P ackage
R (SO IC Sur face Mount) P ackage
16
9
0.299
(7.60)
0.419
(10.65)
1
8
PIN
1
0.030
(0.75)
0.050 (1.27)
0.413 (10.50)
0.104
(2.650)
0.019
(0.49)
0.012
(0.30)
0.013
(0.32)
0.042
(1.07)
REV. A
–11–
–12–
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