SSM2166S-REEL7 [ADI]
Microphone Preamplifier with Variable Compression and Noise Gating; 麦克风前置放大器，可变压缩和噪声选通
| 型号： | SSM2166S-REEL7 |
| 厂家： | 
ADI |
| 描述： | Microphone Preamplifier with Variable Compression and Noise Gating |
| 文件： | 总20页 (文件大小：549K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Microphone Preamplifier with
Variable Compression and Noise Gating
SSM2166
SSM2166 can be programmed with a fixed gain of up to 20 dB;
this gain is in addition to the variable gain in other compression
FEATURES
Complete microphone conditioner in a 14-lead SOIC package
Single 5 V operation
Adjustable noise gate threshold
Compression ratio set by external resistor
Automatic limiting feature—prevents ADC overload
Adjustable release time
settings. The input buffer can also be configured for front-end
gains of 0 dB to 20 dB. A downward expander (noise gate) prevents
amplification of noise or hum. This results in optimized signal
levels prior to digitization, thereby eliminating the need for
additional gain or attenuation in the digital domain that may
add noise or impair accuracy of speech recognition algorithms.
The compression ratio and time constants are set externally. A
high degree of flexibility is provided by the VCA gain, rotation
point, and noise gate adjustment pins.
Low noise and distortion
Power-down feature
20 kHz bandwidth ( 1 dBꢀ
APPLICATIONS
The SSM2166 is an ideal companion product for audio codecs
used in computer systems, such as the AD1845. The SSM2166 is
available in a 14-lead SOIC package and is guaranteed for
operation over the extended industrial temperature range of
−40°C to +85°C.
Microphone preamplifiers/processors
Computer sound cards
Public address/paging systems
Communication headsets
Telephone conferencing
10
Guitar sustain effects generators
Computerized voice recognition
Surveillance systems
COMP RATIO = 10:1
COMP RATIO = 2:1
0
–10
–20
Karaoke and DJ mixers
GENERAL DESCRIPTION
COMP RATIO = 1:1
The SSM2166 integrates a complete and flexible solution for
conditioning microphone inputs in computer audio systems. It
is also excellent for improving vocal clarity in communications
and public address systems. A low noise, voltage-controlled
amplifier (VCA) provides a gain that is dynamically adjusted by
a control loop to maintain a set compression characteristic. The
compression ratio is set by a single resistor and can be varied
from 1:1 to over 15:1 relative to a user-defined rotation point;
signals above the rotation point are limited to prevent overload
and to eliminate popping. In the 1:1 compression setting, the
–30
–40
–50
–60
–70
–60
–50
–40
–30
–20
–10
0
INPUT (dBu)
Figure 1. Compression and Gating Characteristics with 10 dB of Fixed Gain (The
Gain Adjust Pin Can Be Used to Vary This Fixed Gain Amount)
FUNCTIONAL BLOCK DIAGRAM AND TYPICAL SPEECH APPLICATION
V+
R1
10kΩ
10µF
+
10µF (OPTIONAL)
+
V+
VCA
VCA
R
BUF OUT
BUFFER
IN
GAIN
ADJUST
5
3
4
14
2
1kΩ
2.3kΩ
–IN
6
7
OUTPUT
0.1µF
13
9
VCA
1kΩ
AUDIO
+IN
NOISE GATE
SET
500kΩ
17kΩ
R2
10kΩ
LEVEL
DETECTOR
CONTROL
11
+
1µF
SSM2166
ROTATION
SET
12
1
8
10
POWER DOWN
GND
AVG CAP
COMP RATIO SET
+
22µF
25kΩ
Figure 2.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©1996–2008 Analog Devices, Inc. All rights reserved.
SSM2166
TABLE OF CONTENTS
Features .............................................................................................. 1
Signal Path......................................................................................8
Level Detector................................................................................9
Control Circuitry........................................................................ 10
Power-Down Feature ................................................................. 12
PCB Layout Considerations...................................................... 12
Evaluation Board ............................................................................ 13
Evaluation Board Examples ...................................................... 14
Evaluation Board Setup Procedure.......................................... 15
Test Equipment Setup................................................................ 15
Setup Summary .......................................................................... 16
Outline Dimensions....................................................................... 17
Ordering Guide .......................................................................... 17
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram and Typical Speech Application...... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Typical Performance Characteristics ............................................. 6
Theory of Operation ........................................................................ 8
Applications Information............................................................ 8
REVISION HISTORY
7/08—Rev. C to Rev. D
Added Figure 19 ............................................................................. 10
Deleted Figure 14 and Figure 17 .................................................. 12
Deleted Other Versions Section ................................................... 13
Changes to Figure 26...................................................................... 13
Changes to Figure 27...................................................................... 14
Changes to Test Equipment Section ............................................ 15
Added Table 6 ................................................................................. 16
Added Table 7 ................................................................................. 16
Updated Outline Dimensions....................................................... 17
Changes to Ordering Guide.......................................................... 17
Changes to Figure 4 through Figure 9 ........................................... 6
Changes to Figure 11 and Figure 12............................................... 7
Changes to Figure 19...................................................................... 10
Changes to Figure 26...................................................................... 13
Added Top Branding Revision Reflecting Die Replacement
Table ................................................................................................. 17
5/08—Rev. B to Rev. C
Updated Format..................................................................Universal
Changes to Features Section and General Description
Section................................................................................................ 1
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 4
Deleted TPC 3; Renumbered Sequentially.................................... 4
Changes to Table 4, Pin 8 Description Column ........................... 5
Changes to Figure 5, Figure 6, Figure 8, and Figure 9 ................. 6
Change to Figure 11 ......................................................................... 7
Changes to Signal Path Section ...................................................... 9
3/03—Rev. A to Rev. B
Deleted PDIP Package .......................................................Universal
Change to General Description.......................................................1
Changes to Thermal Characteristics...............................................2
Changes to Ordering Guide.............................................................2
Deleted 14-Lead PDIP, Outline Dimensions.............................. 15
Updated 14-Lead Narrow-Body SOIC, Outline Dimensions... 15
Rev. D | Page 2 of 20
SSM2166
SPECIFICATIONS
V+ = 5 V, f = 1 kHz, RL = 100 kΩ, RGATE = 600 kΩ, RROT PT = 3 kΩ, RCOMP = 0 Ω, R1 = 0 Ω, R2 = ∞ Ω, TA = 25°C, unless otherwise noted;
IN = 300 mV rms.
V
Table 1.
Parameter
Symbol
Conditions
Min Typ
Max Unit
nV/√Hz
AUDIO SIGNAL PATH
Voltage Noise Density
Noise
Total Harmonic Distortion and
Noise
en
15:1 Compression
20 kHz bandwidth, VIN = GND
17
−109
0.25
dBu1
THD + N Second and third harmonics, VIN = −20 dBu,
22 kHz low-pass filter
0.5
%
Input Impedance
Output Impedance
Load Drive
ZIN
ZOUT
180
75
kΩ
Ω
kΩ
nF
Resistive
Capacitive
5
2
Buffer
Input Voltage Range
Output Voltage Range
VCA
1% THD
1% THD
1
1
V rms
V rms
Input Voltage Range
Output Voltage Range
Gain Bandwidth Product
CONTROL SECTION
VCA Dynamic Gain Range
VCA Fixed Gain Range
Compression Ratio, Minimum
Compression Ratio, Maximum
1% THD
1% THD
1
1.4
30
V rms
V rms
MHz
1:1 compression, VCA gain = 60 dB
60
dB
dB
−60 to +19
1:1
15:1
See Figure 19 for RCOMP/RROT PT, rotation
point = 100 mV rms
Control Feedthrough
15:1 compression, rotation point = −10 dBu,
R2 = 1.5 kΩ
5
mV
POWER SUPPLY
Supply Voltage Range
Supply Current
Quiescent Output Voltage Level
Power Supply Rejection Ratio
POWER DOWN
V+
ISY
4.5
5.5
10
V
mA
V
7.5
2.2
50
PSRR
dB
Supply Current
Pin 12 = V+2
10
100
μA
1 0 dBu = 0.775 V rms.
2 Normal operation for Pin 12 is 0 V.
Rev. D | Page 3 of 20
SSM2166
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 2.
Table 3.
Parameter
Rating
Supply Voltage
10 V
Package Type
θJA
θJC
Unit
Audio Input Voltage
Supply voltage
−40°C to +85°C
−65°C to +150°C
150°C
14-Lead SOIC
120
36
°C/W
Operating Temperature Range
Storage Temperature Range
Junction Temperature (TJ)
Lead Temperature (Soldering, 60 sec)
ESD CAUTION
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. D | Page 4 of 20
SSM2166
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND
1
2
3
4
5
6
7
14 V+
GAIN ADJUST
13 OUTPUT
VCA
IN
12 POWER DOWN
11 ROTATION SET
10 COMP RATIO SET
SSM2166
VCA
TOP VIEW
R
(Not to Scale)
BUF OUT
–IN
9
8
NOISE GATE SET
AVG CAP
AUDIO +IN
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
Ground.
1
2
GND
GAIN ADJUST
VCA Gain Adjust Pin. A resistor from this pin to ground sets the fixed gain of the VCA. To check the setting of
this pin, make sure the compression ratio set pin (Pin 10) is grounded for no compression. The gain can be
varied from 0 dB to 20 dB. For 20 dB, leave the pin open. For 0 dB of fixed gain, a typical resistor value is
approximately 1 kΩ. For 10 dB of fixed gain, the resistor value is approximately 2 kΩ to 3 kΩ. For resistor values
<1 kΩ, the VCA can attenuate or mute (see Figure 6).
3
4
VCAIN
VCAR
VCA Input Pin. A typical connection is a 10 μF capacitor from the buffer output pin (Pin 5) to this pin.
Inverting Input to the VCA. This input can be used as a nonground reference for the audio input signal (see the
Applications Information section).
5
6
BUF OUT
−IN
Input Buffer Amplifier Output Pin. This pin must not be loaded by capacitance to ground.
Inverting Input to the Buffer. A 10 kΩ feedback resistor, R1, from the buffer output (Pin 5) to this input pin and
a resistor, R2, from this pin through a 1 μF capacitor to ground give gains of 6 dB to 20 dB for R2 = 10 kΩ to 1.1 kΩ.
7
8
AUDIO +IN
AVG CAP
Input Audio Signal. The input signal should be ac-coupled (0.1 μF typical) into this pin.
Detector Averaging Capacitor. A capacitor, 1 μF to 22 μF, to ground from this pin is the averaging capacitor
for the detector circuit.
9
NOISE GATE SET
Noise Gate Threshold Set Point. A resistor to V+ sets the level below which input signals are downward
expanded. For a 0.7 mV threshold, the resistor value is approximately 380 kΩ. Increasing the resistor value
reduces the threshold (see Figure 5).
10
11
COMP RATIO SET Compression Ratio Set Pin. A resistor to ground from this pin sets the compression ratio, as shown in Figure 2.
Figure 19 gives resistor values for various rotation points.
ROTATION SET
Rotation Point Set Pin. This pin is set by adding a resistor to the positive supply. This resistor together with
the gain adjust pin determines the onset of limiting. A typical value for this resistor is 17 kΩ for a 100 mV
rotation point. Increasing the resistor value reduces the level at which limiting occurs (see Figure 9).
12
POWER DOWN
Power-Down Pin. Connect this pin to ground for normal operation. Connect this pin to the positive supply
for power-down mode.
13
14
OUTPUT
V+
Output Signal.
Positive Supply, 5 V Nominal.
Rev. D | Page 5 of 20
SSM2166
TYPICAL PERFORMANCE CHARACTERISTICS
0
5
1
T
= 25°C
COMP RATIO = 15:1
A
COMP RATIO = 10:1
V+ = 5V
COMP RATIO = 5:1
–10
–20
COMPRESSION RATIO = 1:1
NOISE GATE SETTING ≈ 550µV rms
ROTATION SET ≈ 1V rms
GAIN ADJUST = 1.25kΩ
COMP RATIO = 2:1
–30
V
FREQUENCY = 1kHz
IN
COMP RATIO = 1:1
R
= 10kΩ
L
–40
–50
R
= 100kΩ
L
T
= 25°C
A
V+ = 5V
= 300mV rms @ 1kHz
V
–60
–70
–80
IN
= 100kΩ
R
L
0.1
NOISE GATE SETTING ≈ 550µV rms
ROTATION SET ≈ 300mV rms
GAIN ADJUST = 1.25kΩ
0.05
0.01
–80
–70
–60
–50
–40
–30
–20
–10
0
0.1
INPUT VOLTAGE (V rms)
1
INPUT (dBu)
Figure 4. Output vs. Input Characteristics
Figure 7. THD + N (%) vs. Input (V rms)
100
10
1
10
T
= 25°C
T
= 25°C
A
A
V+ = 5V
= 100kΩ
V+ = 5V
= 77.5mV rms @ 1kHz
R
V
L
IN
COMPRESSION RATIO = 1:1
COMPRESSION RATIO = 2:1
ROTATION SET ≈ 700mV rms
GAIN ADJUST = 1.56kΩ
NOISE GATE SETTING ≈ 550µV rms
ROTATION SET ≈ 1V rms
GAIN ADJUST = 156kΩ
1
MEASUREMENT FILTER BW: 20Hz TO 20kHz
0.1
0.1
0.01
0
50 100 150 200 250 300 350 400 450 500 550 600 650
(kΩ)
10
100
1k
10k
30k
R
GATE
FREQUENCY (Hz)
Figure 5. Noise Gate vs. RGATE (Pin 9 to V+)
Figure 8. THD + N (%) vs. Frequency (Hz)
20
18
16
14
12
10
8
1
0.1
T
= 25°C
A
V+ = 5V
V
R
= 77.5mV rms @ 1kHz
= 100kΩ
IN
6
4
2
0
L
NOISE GATE SETTING ≈ 550µV rms
ROTATION SET ≈ 1V rms
COMPRESSION RATIO = 1:1
0.01
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90
RESISTOR (kΩ)
GAIN ADJUST RESISTOR (kΩ)
R
ROT PT
Figure 6. VCA Gain vs. RGAIN (Pin 2 to GND)
Figure 9. Rotation Point vs. RROT PT (Pin 11 to V+)
Rev. D | Page 6 of 20
SSM2166
5µV
1s
20mV
100
90
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• • • •
100
90
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• • • •
T
C
= 25°C
= 2.2µF
A
T
= 25°C
A
10
10
AVG
• SYSTEM GAIN = 0dB
COMPRESSION RATIO = 15:1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• • • •
NOISE BW =20kHz
0%
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• • • •
0%
R
= 10kΩ
L
COMPRESSION RATIO = 1:1
10µs
Figure 10. Wideband Peak-to-Peak Output Noise
Figure 13. Small Signal Transient Response
80
60
40
20
200mV
G = 60dB
G = 40dB
100
90
•
•
•
•
•
•
•
•
•
•
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•
•
•
•
•
•
•
•
• • • •
G = 20dB
0
–20
–40
T
C
= 25°C
= 2.2µF
A
10
AVG
SYSTEM GAIN =0dB
ROTATION SET ≈ 1V rms
= 30kΩ
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• • • •
0%
R
COMP
NOISE GATE SETTING ≈ 550µV rms
= 1mV rms
R
= 10kΩ
L
COMPRESSION RATIO = 1:1
V
10µs
IN
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 11. VCA Gain Bandwidth Curves vs. Frequency
Figure 14. Large Signal Transient Response
–10
–20
–30
–40
R
R
R
R
= 0Ω
COMP
= 1.24kΩ
= 500kΩ
GAIN
GATE
ROT PT
= 1.74kΩ
V+ = 5V ± 1V p-p
–50
–60
–70
V+ = 5V ± 0.5V p-p
–80
20
100
1k
10k
30k
FREQUENCY (Hz)
Figure 12. PSRR vs. Frequency
Rev. D | Page 7 of 20
SSM2166
THEORY OF OPERATION
Figure 15 illustrates a typical transfer characteristic for the
SSM2166 where the output level in decibels is plotted as a
function of the input level in decibels. The dotted line indicates
the transfer characteristic for a unity-gain amplifier. For input
signals in the range of VDE (downward expansion) to VRP (rotation
point), an r dB change in the input level causes a 1 dB change in
the output level. Here, r is defined as the compression ratio. The
compression ratio can be varied from 1:1 (no compression) to
over 15:1 via a single resistor, RCOMP. Input signals above VRP
are compressed with a fixed compression ratio of approximately
15:1. This region of operation is the limiting region. Varying the
compression ratio has no effect on the limiting region. The break-
point between the compression region and the limiting region is
referred to as the limiting threshold or the rotation point and is
user specified in the SSM2166. The term “rotation point” derives
from the observation that the straight line in the compression
region rotates about this point on the input/output characteristic as
the compression ratio is changed.
APPLICATIONS INFORMATION
The SSM2166 is a complete microphone signal conditioning
system on a single integrated circuit. Designed primarily for voice-
band applications, this integrated circuit provides amplification,
rms detection, limiting, variable compression, and downward
expansion. An integral voltage-controlled amplifier (VCA)
provides up to 60 dB of gain in the signal path with approximately
30 kHz bandwidth. Additional gain is provided by an input
buffer, op amp circuit that can be set anywhere from 0 dB to 20 dB
for a total signal path gain of up to 80 dB. The device operates
on a single 5 V supply, accepts input signals up to 1 V rms, and
produces output signal levels >1 V rms (3 V p-p) into loads >5 kΩ.
The internal rms detector has a time constant set by an external
capacitor.
The SSM2166 contains an input buffer and automatic gain
control (AGC) circuit for audio-band and voice-band signals.
Circuit operation is optimized by providing a user-adjustable
time constant and compression ratio. A downward expansion
(noise gating) feature eliminates circuit noise in the absence of
an input signal. The SSM2166 allows the user to set the downward
expansion threshold, the limiting threshold (rotation point), the
input buffer fixed gain, and the internal VCA nominal gain at
the rotation point. The SSM2166 also features a power-down
mode and muting capability.
The gain of the system with an input signal level of VRP is fixed
by RGAIN, regardless of the compression ratio, and is the nominal
gain of the system. The nominal gain of the system can be
increased by the user via the on-board VCA by up to 20 dB.
Additionally, the input buffer of the SSM2166 can be configured
to provide fixed gains of 0 dB to 20 dB with R1 and R2.
Input signals below VDE are downward expanded; that is, a
−1 dB change in the input signal level causes approximately a
−3 dB change in the output level. As a result, the gain of the
system is small for very small input signal levels, even though it
may be quite large for small input signals above VDE. The down-
ward expansion threshold, VDE, is set externally by the user via
SIGNAL PATH
Figure 16 illustrates the block diagram of the SSM2166. The
audio input signal is processed by the input buffer and then
by the VCA. The input buffer presents an input impedance of
approximately 180 kΩ to the source. A dc voltage of approximately
1.5 V is present at AUDIO +IN (Pin 7), requiring the use of a
blocking capacitor (C1) for ground referenced sources. A 0.1 μF
capacitor is a good choice for most audio applications. The input
buffer is a unity-gain stable amplifier that can drive the low
impedance input of the VCA.
RGATE at Pin 9 (NOISE GATE SET). The SSM2166 provides an
active high, CMOS-compatible digital input whereby a power-
down feature reduces the device supply current to less than 100 μA.
LIMITING
THRESHOLD
(ROTATION POINT)
LIMITING
REGION
The VCA is a low distortion, variable-gain amplifier (VGA)
whose gain is set by the side-chain control circuitry. The input
to the VCA is a virtual ground in series with approximately 1 kΩ.
An external blocking capacitor (C6) must be used between the
buffer output and the VCA input. The 1 kΩ impedance between
amplifiers determines the value of this capacitor, which is typically
between 1 μF and 10 μF. An aluminum electrolytic capacitor is
an economical choice. The VCA amplifies the input signal current
flowing through C6 and converts this current to a voltage at the
OUTPUT pin (Pin 13). The net gain from input to output can
be as high as 60 dB (without additional buffer gain), depending
on the gain set by the control circuitry.
COMPRESSION
REGION
DOWNWARD
EXPANSION
THRESHOLD
(NOISE GATE)
VCA GAIN
1
r
DOWNWARD
EXPANSION
REGION
1
1
V
V
RP
DE
INPUT (dB)
Figure 15. General Input/Output Characteristics
Rev. D | Page 8 of 20
SSM2166
The gain of the VCA at the rotation point is set by the value of a
resistor, RGAIN, connected between Pin 2 and GND. The relationship
between the VCA gain and RGAIN is shown in Figure 6. The AGC
range can be as high as 60 dB. The VCAIN pin (Pin 3) is the non-
inverting input terminal to the VCA. The inverting input of the
VCA is available at the VCAR pin (Pin 4) and exhibits an input
impedance of 1 kΩ, as well. As a result, this pin can be used for
differential inputs or for the elimination of grounding problems
by connecting a capacitor whose value equals that used in series
with the VCAIN pin to ground (see Figure 26 for more details).
LEVEL DETECTOR
The SSM2166 incorporates a full-wave rectifier and true rms
level detector circuit whose averaging time constant is set by
an external capacitor connected to the AVG CAP pin (Pin 8).
For optimal low frequency operation of the level detector
down to 10 Hz, the value of the capacitor should be 2.2 μF.
Some experimentation with larger values for the AVG CAP
may be necessary to reduce the effects of excessive low frequency
ambient background noise. The value of the averaging capacitor
affects sound quality: too small a value for this capacitor may
cause a pumping effect for some signals, while too large a value
may result in slow response times to signal dynamics. Electrolytic
capacitors are recommended for lowest cost and should be in
the range of 2 μF to 47 μF. Capacitor values from 18 μF to 22 μF
have been found to be more appropriate in voice-band applications
where capacitors on the low end of the range seem more
appropriate for music program material.
The output impedance of the SSM2166 is typically less than 75 Ω,
and the external load on Pin 13 should be >5 kΩ. The nominal
output dc voltage of the device is approximately 2.2 V. Use a
blocking capacitor for grounded loads.
The bandwidth of the SSM2166 is quite wide at all gain settings.
The upper 3 dB point is approximately 30 kHz at gains as high as
60 dB (using the input buffer for additional gain, circuit bandwidth
is unaffected). The gain bandwidth (GBW) plots are shown in
Figure 11. The lower 3 dB cutoff frequency of the SSM2166 is
set by the input impedance of the VCA (1 kΩ) and C6. While the
noise of the input buffer is fixed, the input referred noise of the
VCA is a function of gain. The VCA input noise is designed to
be a minimum when the gain is at a maximum, thereby optimizing
the usable dynamic range of the part. A plot of wideband peak-
to-peak output noise is shown in Figure 10.
The rms detector filter time constant is approximately given by
10 × CAVG milliseconds, where CAVG is in μF. This time constant
controls both the steady-state averaging in the rms detector as
well as the release time for compression; that is, the time it takes
for the system gain to react when a large input is followed by
a small signal. The attack time, the time it takes for the gain to
be reduced when a small signal is followed by a large signal, is
controlled partly by the AVG CAP value but is mainly controlled by
internal circuitry that speeds up the attack for large level changes.
This limits overload time to less than 1 ms in most cases.
C6
C7
10µF
10µF (OPTIONAL)
+
+
V+
VCA
VCA
BUF OUT
BUFFER
IN
R
R1
10kΩ
14
5
3
4
1kΩ
1kΩ
–IN
6
7
OUTPUT
V
13
2
VCA
OUT
AUDIO
+IN
V+
GAIN ADJUST
C1
0.1µF
R2
R
GAIN
10kΩ
SSM2166
R
GATE
+
1µF
RMS
LEVEL
DETECTOR
NOISE GATE SET
CONTROL
CIRCUIT
9
R
ROT PT
ROTATION SET
POWER DOWN
11
12
1
8
10
GND
AVG CAP
COMP
RATIO SET
+
C
AVG
2.2µF
R
COMP
Figure 16. Functional Block Diagram and Typical Application
Rev. D | Page 9 of 20
SSM2166
The performance of the rms level detector is illustrated for a
Compression Ratio
C
AVG of 2.2 μF in Figure 17 and for a CAVG of 22 μF in Figure 18.
Changing the scaling of the control signal fed to the VCA
causes a change in the circuit compression ratio, r. This effect is
shown in Figure 20. The compression ratio can be set by
connecting a resistor between the COMP RATIO SET pin (Pin
10) and GND. Lowering RCOMP gives smaller compression ratios
as shown in Figure 19, with values of approximately 17 kΩ or
less resulting in a compression ratio of 1:1. AGC performance is
achieved with compression ratios between 2:1 and 15:1 and is
dependent on the application. A 100 kΩ potentiometer can be
used to allow this parameter to be adjusted. On the evaluation
board (see Figure 26), an optional resistor can be used to set the
compression equal to 1:1 when the wiper of the potentiometer
is at its full counterclockwise (CCW) position.
In each of these images, the input signal to the SSM2166 (not
shown) is a series of tone bursts in six successive 10 dB steps.
The tone bursts range from −66 dBV (0.5 mV rms) to −6 dBV
(0.5 V rms). As shown in Figure 17 and Figure 18, the attack
time of the rms level detector is dependent only on CAVG, but the
release times are linear ramps whose decay times are dependent
on both CAVG and the input signal step size. The rate of release is
approximately 240 dB/s for a CAVG of 2.2 μF and 12 dB/s for a
CAVG of 22 μF.
100mV
100
90
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• • • •
–6dBV
COMPRESSION
RATIO
ROTATION POINT
100mV rms
300mV rms
1V rms
1:1
0.1
0.1
0.1
2:1
8.7
8.7
8.7
10:1
45
15:1
395
N/A
N/A
5:1
19.4
19.4
19.4
45
–66dBV
–85dBV
45
TYPICAL R
COMP
VALUES IN kΩ.
10
0%
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• • • •
Figure 19. Compression Ratio vs. RCOMP (Pin 10 to GND)
100ms
15:1
5:1
Figure 17. RMS Level Detector Performance with CAVG = 2.2 μF
100mV
1s
VCA GAIN
2:1
1:1
100
90
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
–6dBV
1
–66dBV
–85dBV
1
10
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• • • •
0%
V
V
DE
RP
INPUT (dB)
Figure 20. Effect of Varying the Compression Ratio
Figure 18. RMS Level Detector Performance with CAVG = 22 μF
Rotation Point
CONTROL CIRCUITRY
An internal dc reference voltage in the control circuitry, used to
set the rotation point, is user specified, as illustrated in Figure 9.
The effect on rotation point is shown in Figure 21. By varying a
resistor, RROT PT, connected between the positive supply and the
ROTATION SET pin (Pin 11), the rotation point may be varied
by approximately 20 mV rms to 1 V rms. From Figure 21, the
rotation point is inversely proportional to RROT PT. For example, a 1
kΩ resistor would typically set the rotation point at 1 V rms,
whereas a 55 kΩ resistor would typically set the rotation point
at approximately 30 mV rms.
The output of the rms level detector is a signal proportional to
the log of the true rms value of the buffer output with an added
dc offset. The control circuitry subtracts a dc voltage from this
signal, scales it, and sends the result to the VCA to control the
gain. The gain control of the VCA is logarithmic—a linear change
in the control signal causes a decibel change in gain. It is this
control law that allows linear processing of the log rms signal to
provide the flat compression characteristic on the input/output
characteristic shown in Figure 15.
Rev. D | Page 10 of 20
SSM2166
Because limiting occurs for signals larger than the rotation point
(VIN > VRP), the rotation point effectively sets the maximum output
signal level. It is recommended that the rotation point be set at
the upper extreme of the range of typical input signals so that
the compression region covers the entire desired input signal
range. Occasional larger signal transients are then attenuated by
the action of the limiter.
The gain of the VCA can be reduced below 0 dB by making
GAIN smaller than 1 kΩ. Switching Pin 2 through 330 Ω or less
R
to GND mutes the output. Either a switch connected to ground or a
transistor can be used, as shown in Figure 23. To avoid audible
clicks when using the mute feature, a capacitor (C5) can be
connected from Pin 2 to GND. The value of the capacitor is
arbitrary and should be determined empirically, but a 0.01 μF
capacitor is a good starting value.
VCA
GAIN
SSM2166
2
r:1
VCA
GAIN
GAIN ADJUST
330Ω
R
GAIN
VCA
GAIN
C5
MUTE
(CLOSED SWITCH)
NOTES
1. ADDITIONAL CIRCUIT DETAILS OMITTED
FOR CLARITY.
1
1
Figure 23. Details of Mute Option
Downward Expansion Threshold
V
V
V
V
RP3
DE
RP1 RP2
INPUT (dB)
The downward expansion threshold, or noise gate, is deter-
mined via a second reference voltage internal to the control
circuitry. This second reference can be varied in the SSM2166
using a resistor, RGATE, connected between the positive supply
and the NOISE GATE SET pin (Pin 9). The effect of varying this
threshold is shown in Figure 24. The downward expansion
threshold can be set between 300 μV rms and 20 mV rms by
varying the resistance value between Pin 9 and the supply
voltage. Like the ROTATION SET pin, the downward expansion
threshold is inversely proportional to the value of this resistance:
setting this resistance to 1 MΩ sets the threshold at approximately
250 μV rms, whereas a 10 kΩ resistance sets the threshold at
approximately 20 mV rms. This relationship is illustrated in
Figure 5. A potentiometer network is provided on the evaluation
board for this adjustment. In general, the downward expansion
threshold should be set at the lower extreme of the desired range of
the input signals so that signals below this level are attenuated.
Figure 21. Effect of Varying the Rotation Point
VCA Gain Setting and Muting
The maximum gain of the SSM2166 is set by the GAIN ADJUST
pin (Pin 2) via RGAIN. This resistor, with a range of 1 kΩ to
20 kΩ, causes the nominal VCA gain to vary from 0 dB to
approximately 20 dB, respectively. Setting the VCA gain to its
maximum can also be achieved by leaving the GAIN ADJUST
pin in an open condition (no connect). Figure 22 illustrates the
effect on the transfer characteristic by varying this parameter.
For low level signal sources, the VCA should be set to maximum
gain using a 20 kΩ resistor.
r:1
VCA GAIN
r:1
VCA GAIN
1
1
V
V
RP
DE
INPUT (dB)
1
1
Figure 22. Effect of Varying the VCA Gain Setting
V
V
DE2
RP
V
V
DE3
INPUT (dB)
DE1
Figure 24. Effect of Varying the Downward Expansion (Noise Gate) Threshold
Rev. D | Page 11 of 20
SSM2166
•
When using high impedance sources (≥5 kΩ), system gains
in excess of 60 dB are not recommended. This configuration
is rarely appropriate because virtually all high impedance
inputs provide larger amplitude signals that do not require
as much amplification. When using high impedance sources,
however, it can be advantageous to shunt the source with a
capacitor to ground at the input pin of the IC (Pin 7) to
lower the source impedance at high frequencies, as shown
in Figure 25. A capacitor with a value of 1000 pF is a good
starting value and sets a low-pass corner at 31 kHz for 5 kΩ
sources. In applications where the source ground is not as
clean as would be desirable, a capacitor (illustrated as C7
on the evaluation board) from the VCAR input to the source
ground may prove beneficial. This capacitor is used in
addition to the grounded capacitor (illustrated as C2 on the
evaluation board) used in the feedback around the buffer,
assuming that the buffer is configured for gain.
POWER-DOWN FEATURE
The supply current of the SSM2166 can be reduced to less than
100 μA by applying an active high, 5 V CMOS-compatible input
to the POWER DOWN pin (Pin 12). In this state, the input and
output circuitry of the SSM2166 assumes a high impedance
state; as such, the potentials at the input pin and the output pin are
determined by the external circuitry connected to the SSM2166.
The SSM2166 takes approximately 200 ms to settle from a power-
down to power-on command. For power-on to power-down,
the SSM2166 requires more time, typically less than 1 second.
Cycling the power supply to the SSM2166 can result in quicker
settling times: the off-to-on settling time of the SSM2166 is less
than 200 ms, while the on-to-off settling time is less than 1 ms.
In either implementation, transients may appear at the output of
the device. To avoid these output transients, use mute control of
the VCA gain as previously mentioned.
PCB LAYOUT CONSIDERATIONS
Because the SSM2166 is capable of wide bandwidth operation
and can be configured for as much as 80 dB of gain, special care
must be exercised in the layout of the PCB that contains the IC
and its associated components. The following recommendations
should be considered and/or followed:
C1
0.1µF
AUDIO +IN
7
AUDIO +IN
(R > 5kΩ)
C
S
X
1000pF
SSM2166
NOTES
1. ADDITIONAL CIRCUIT DETAILS OMITTED
FOR CLARITY.
•
In some high system gain applications, the shielding of input
wires to minimize possible feedback from the output of the
SSM2166 back to the input circuit may be necessary.
Figure 25. Circuit Configuration for Use with High Impedance Signal Sources
The value of C7 should be the same as C6, which is the capacitor
value used between BUF OUT and VCAIN. This connection
makes the source ground noise appear as a common-mode signal
to the VCA, allowing the common-mode noise to be rejected by
the VCA differential input circuitry. C7 can also be useful in
reducing ground loop problems and in reducing noise coupling
from the power supply by balancing the impedances connected
to the inputs of the internal VCA.
•
A single-point (star) ground implementation is recom-
mended in addition to maintaining short lead lengths and
PCB runs. The evaluation board layout shown in Figure 27,
Figure 28, and Figure 29 demonstrates the single-point
grounding scheme. In applications where an analog ground
and a digital ground are available, the SSM2166 and its
surrounding circuitry should be connected to the analog
ground of the system. Because of these recommendations,
wire-wrap board connections and grounding
implementations should be avoided.
•
The internal buffer of the SSM2166 was designed to drive only
the input of the internal VCA and its own feedback network.
Stray capacitive loading to ground from the BUF OUT pin in
excess of 5 pF to 10 pF can cause excessive phase shift and
can lead to circuit instability.
Rev. D | Page 12 of 20
SSM2166
on the SSM2166 by connecting the GAIN ADJUST pin (Pin 2)
through a 330 Ω resistance to ground. This is provided on the
evaluation board via R11 and S1. Capacitor C5, connected
between Pin 2 and ground and provided on the evaluation
board, can be used to avoid audible clicks when using the mute
function.
EVALUATION BOARD
A schematic diagram of the SSM2166 evaluation board is
illustrated in Figure 26. As a design aid, the layouts for the
topside silkscreen and the topside and backside metallization
layers are shown in Figure 27, Figure 28, and Figure 29. Although
not shown to scale, the finished dimension of the evaluation
board is 3.5 inches by 3.5 inches and comes complete with pin
sockets and a sample of the SSM2166.
To configure the SSM2166 input buffer for gain, provisions for
R1, R2, and C2 have been included. To configure the input buffer
for unity-gain operation, R1 and R2 are removed and a direct
connection is made between the −IN pin (Pin 6) and the BUF OUT
pin (Pin 5).
Signal sources are connected to the SSM2166 through a 1/8-inch
phone jack where a 0.1 μF capacitor couples the input signal
to the AUDIO +IN pin (Pin 7). As shown in Figure 26 and in
microphone applications, the phone jack shield can be optionally
connected to the ground plane of the board (Jumper J1 inserted
into the board socket for Pin 1 and Pin 2) or to the VCAR input
at Pin 4 (J1 inserted into the board socket for Pin 1 and Pin 3).
If the signal source is a waveform or function generator, the
phone jack shield should be connected to ground.
The output stage of the SSM2166 is capable of driving >1 V rms
(3 V p-p) into >5 kΩ loads and is externally available through
an RCA phono jack provided on the board. If the output of the
SSM2166 is required to drive a lower load resistance or an audio
cable, the on-board OP113 can be used. To use the OP113 buffer,
insert Jumper J4 into the board socket for Pin 4 and Pin 5 and
insert Jumper J5 into the board socket for Pin 6 and Pin 7. If the
output buffer is not required, remove Jumper J5 and insert Jumper
J4 into board socket Pin 5 and Pin 7.
For ease in making adjustments for all configuration parameters,
single-turn potentiometers are used throughout. Optional
Jumper J2 connects the COMP RATIO SET pin to ground and
sets the SSM2166 for no compression (that is, compression ratio
= 1:1). Optional Jumper J3 connects the POWER DOWN (Pin
12) input to ground for normal operation. J3 can be replaced by
an open-drain logic buffer for a digitally controlled shutdown
function. An output signal mute function can be implemented
There are no blocking capacitors either on the input or at
the output of the buffer. As a result, the output dc level of the
buffer matches the output dc level of the SSM2166, which is
approximately 2.3 V. A dc blocking capacitor can be inserted at
Pin 6 and Pin 7. An evaluation board and setup procedure
is available from a Analog Devices, Inc., sales representative.
+V
C3
0.1µF
NOISE GATE ADJ
ROTATION
PT ADJ
R12
C6
10µF
+
100kΩ
R1
10kΩ
R4
500Ω
R8
500Ω
R3
50kΩ
R7
1MΩ
J3
CW
CCW
5
3
11
14
V+
9
12
BUF OUT VCA
ROTATION
SET
NOISE GATE POWER DOWN
SET
IN
SSM2166
6
GND
1
–IN
R2
10kΩ
AUDIO +IN VCA
AVG CAP
8
GAIN ADJUST
2
COMP RATIO SET
10
OUTPUT
13
R
7
4
C1
0.1µF
5
4
C2
1µF
MIC
PWR
C5
0.01µF
+
+
C4
22µF
R9
1kΩ
R11
330Ω
C7
10µF
INPUT
JACK
1/8"
R6
R10
20kΩ
COMP
RATIO
ADJ
1
GAIN
ADJ
CW
100kΩ
MUTE
PHONE
3
OP113
SWITCH
2
CW
6
7
OUTPUT
JACK
RCA
PHONO
Figure 26. Evaluation Board Schematic
Rev. D | Page 13 of 20
SSM2166
IC2
IC1
Figure 27. Evaluation Board Topside Silkscreen (Not to Scale)
Figure 29. Evaluation Board Backside Metallization (Not to Scale)
EVALUATION BOARD EXAMPLES
To illustrate how easy it is to program the SSM2166, a practical
example is provided. The SSM2166 was used to interface an
electret-type microphone to a postamplifier. The evaluation
board or the circuit configuration shown in Figure 26 can be
used. The signal from the microphone was measured under
actual conditions to vary from 1 mV to 15 mV. The postamplifier
requires no more than 500 mV at its input. The required gain
from the SSM2166 is, therefore
G
TOTAL = 20 × log(500/15) = 30 dB
The input buffer gain is set to 20 dB, and the VCA gain is adjusted
to 10 dB. The limiting or rotation point is set at 500 mV output.
A 2:1 compression ratio and a noise gate threshold that operates
below 100 μV is also used. These objectives are summarized in
Table 5. The transfer characteristic implemented is illustrated in
Figure 30.
Table 5. Objective Specifications
Figure 28. Evaluation Board Topside Metallization (Not to Scale)
Parameter
Input Range
Output Range
Limiting Level
Compression
Buffer Gain
VCA Gain
Value
1 mV to 15 mV
To 500 mV
500 mV
2:1
20 dB
10 dB
Noise Gate
100 μV
Rev. D | Page 14 of 20
SSM2166
Note that the SSM2166 processes the output of the buffer, which
in the previous example is 20 dB or 10 times the input level. Use
the oscilloscope to verify that the buffer is not being driven into
clipping with excessive input signals. In the application, take the
minimum gain in the buffer consistent with the average source
level as well as the crest factor (ratio of peak to rms).
Step 2: Initializing Potentiometers
With the power off, preset the potentiometers per Table 6.
Step 3: Testing Setup
With the power on, adjust the generator for an input level of
15 mV, 1 kHz. The output meter should indicate approximately
100 mV; if not, check the setup.
ROTATION POINT
Step 4: Adjusting the Rotation Point
Set the input level to 15 mV and observe the output on the
oscilloscope. Adjust R3, ROTATION PT ADJ, until the output
level just begins to drop, then reverse so that the output is 500 mV.
The limiting has been set to 500 mV.
500
COMPRESSION
LIMITING REGION
REGION
1
2
40
Step 5: Adjusting the VCA Gain
Set the input level to 15 mV. Adjust R10, GAIN ADJ, clockwise
(CW) for an output level of 500 mV. The VCA gain has been set
to 10 dB.
GATE THRESHOLD
Step 6: Adjusting the Compression Ratio
0.1
1.0
10
15
INPUT (mV)
Set the input signal for an output of 500 mV but not in limiting.
Note the value (around 15 mV). Next, reduce the input to 1/10
of the value noted (around 1.5 mV) for a change of −20 dB. Next,
adjust R6, COMP RATIO ADJ, CW until the output is 160 mV for
an output change of −10 dB. The compression, which is the
ratio of the output change to the input change, in decibels (dB),
has been set to 2:1.
Figure 30. Transfer Characteristic
EVALUATION BOARD SETUP PROCEDURE
When building a breadboard, keep the leads to Pin 3, Pin 4, and
Pin 5 short. An evaluation board is available from an Analog
Devices sales representative. The R and C designations refer to
the demonstration board schematic of Figure 26 and the parts
list in Table 7.
Step 7: Setting the Noise Gate
With the input set at 100 μV, observe the output on the oscilloscope
and adjust R7, NOISE GATE ADJ, CCW until the output drops
rapidly. Rock the control back and forth to find the knee. The
noise gate has been set to 100 μV. The range of the noise gate is
from 0.3 mV to over 0.5 mV relative to the output of the buffer.
To fit this range to the application, it may be necessary to attenuate
the input or apportion the buffer gain and VCA gain differently.
TEST EQUIPMENT SETUP
The recommended equipment and configuration are shown in
Figure 31. A low noise audio generator with a smooth output
adjustment range of 50 μV to 50 mV is a suitable signal source.
A 40 dB pad is useful to reduce the level of most generators by
100× to simulate the microphone levels. The input voltmeter
can be connected before the pad and need only go down to
10 mV. The output voltmeter should go up to 2 V. The oscilloscope
is used to verify that the output is sinusoidal and that no clipping
occurs in the buffer, and to set the limiting and noise gating
knees.
Step 8: Listening
At this time, it may be desirable to connect an electret micro-
phone to the SSM2166 and listen to the results. Be sure to include
the proper power for the internal FET of the microphone
(usually 2 V dc to 5 V dc through a 2.2 kΩ resistor). Experiment
with the settings to hear how the results change. Varying the
averaging capacitor, C4, changes the attack and decay times,
which are best determined empirically. The compression ratio
keeps the output steady over a range of microphone to speaker
distances, and the noise gate keeps the background sounds
subdued.
SSM2166
SIGNAL
OSCILLOSCOPE
EVALUATION
BOARD
GENERATOR
AC
AC
VOLTMETER
VOLTMETER
Figure 31. Test Equipment Setup
Step 1: Configure the Buffer
Step 9: Recording Values
The SSM2166 has an input buffer that can be used when the
overall gain required exceeds 20 dB, the maximum user-selectable
gain of the VCA. In the example, the desired output is 500 mV
for an input of ~15 mV, requiring a total gain of 30 dB. Set the
buffer gain at 20 dB and adjust the VCA for 10 dB. In the socket
pins provided on the evaluation board, insert R1 = 100 kΩ and
R2 = 11 kΩ. The buffer gain is set to 20 dB (×10).
With the power removed from the test fixture, measure and
record the values of all potentiometers, including any fixed
resistance in series with them. If the averaging capacitor, C4,
changes, also note its value.
Rev. D | Page 15 of 20
SSM2166
10× the input level. Use the oscilloscope to ensure that the
buffer is not being driven into clipping with the highest expected
input peaks. Always take the minimum gain in the buffer consis-
tent with the average source level and crest factor (ratio of peak
to rms). The wide program range of the SSM2166 makes it
useful in many applications other than microphone signal
conditioning.
SETUP SUMMARY
The transfer condition of Figure 2 has been implemented. For
inputs below the 100 ꢀV noise gate threshold, circuit and back-
ground noise is minimized. Above it, the output increases at a
rate of 1 dB for each 2 dB input increase until the 500 mV rotation
point is reached at an input of approximately 15 mV. For higher
inputs that drive the output beyond 500 mV, limiting occurs
and there is little further increase. The SSM2166 processes the
output of the buffer, which in the previous example is 20 dB, or
Table 6. Initial Potentiometer Settings
Function
Potentiometer Range
Initial Position Initial Resistance
Effect of Change
Gain Adjust (VCA)
Rotation Point
Compression Point R6
Noise Gate R7
R10
R3
0 kΩ to 20 kΩ
0 kΩ to 50 kΩ
0 kΩ to 100 kΩ CCW
0 kΩ to 1 MΩ CW
CCW
CCW
0 Ω
0 Ω
0 Ω
1 MΩ
0 dB; CW to increase VCA gain
1 V; CW to reduce rotation point
1:1; CW to increase compression
300 μV; CCW to increase threshold
Table 7. Demonstration Board Parts List
Component
Value
Description
R1
10 kΩ resistor
Feedback
R2
10 kΩ resistor
Input
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
C1
C2
C3
C4
C5
C6
C7
50 kΩ potentiometer
500 Ω resistor
0 Ω resistor
100 kΩ potentiometer
1 MΩ potentiometer
500 Ω resistor
1 kΩ resistor
20 kΩ potentiometer
330 Ω resistor
100 kΩ resistor
0.1 μF capacitor
1 μF capacitor
0.1 μF capacitor
2.2 μF to 22 μF capacitor
0.01 μF capacitor
10 μF capacitor
10 μF capacitor
SSM2166
Rotation point, adjust
Rotation point, fixed
Compression ratio, fixed
Compression ratio, adjust
Noise gate, adjust
Noise gate, fixed
Gain adjust, fixed
Gain adjust
Mute
Power-down, pull-up
Input dc block
Buffer low F, G = 1
+V bypass
Average capacitor
Mute click suppress
Coupling
VCA noise/dc balance
MIC preamp
Operational amplifier, output buffer
IC1
IC2
S1
OP113, IC
SPST, Switch
Mute
J1
J2
1/8-inch mini phone plug jumper
RCA female jumper
MIC input
Output jack
Rev. D | Page 16 of 20
SSM2166
OUTLINE DIMENSIONS
8.75 (0.3445)
8.55 (0.3366)
8
7
14
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
1.27 (0.0500)
BSC
0.50 (0.0197)
0.25 (0.0098)
45°
1.75 (0.0689)
1.35 (0.0531)
0.25 (0.0098)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
1.27 (0.0500)
0.40 (0.0157)
0.51 (0.0201)
0.31 (0.0122)
0.25 (0.0098)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012-AB
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 32. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-14)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model
SSM2166S
SSM2166S-REEL
SSM2166S-REEL7
SSM2166SZ1
SSM2166SZ-REEL1
SSM2166SZ-REEL71
Temperature Range
Package Description
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N
Package Option
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
R-14
R-14
R-14
R-14
R-14
R-14
1 Z = RoHS Compliant Part.
Top Branding Revision Reflecting Die Replacement
Original Die Revision
(Prior to Rev. C of Data Sheetꢀ
New Die Revision
(Rev. C to Current Revision of Data Sheetꢀ
Version
Pb-Free (RoHS) Version
Top Line 1: SSM
Top Line 2: 2166
Top Line 3: # XXXX2
Top Line 1: SSM
Top Line 2: 2166
Top Line 3: XXXX
Top Line 1: SSM
Top Line 2: 2166A1
Top Line 3: # XXXX2
SnPb Lead Finish Version
Top Line 1: SSM
Top Line 2: 2166A1
Top Line 3: XXXX
1 Letter A designates new die revision; refer to revised external component values in Figure 5, Figure 6, Figure 9, and Figure 19.
2 # designates RoHS version.
Rev. D | Page 17 of 20
SSM2166
NOTES
Rev. D | Page 18 of 20
SSM2166
NOTES
Rev. D | Page 19 of 20
SSM2166
NOTES
©1996–2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00357-0-7/08(Dꢀ
Rev. D | Page 20 of 20
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