SSM2122_15 [ADI]
DYNAMIC RANGE PROCESSOR/DUAL VCA;
| 型号： | SSM2122_15 |
| 厂家： | 
ADI |
| 描述： | DYNAMIC RANGE PROCESSOR/DUAL VCA |
| 文件： | 总12页 (文件大小：120K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SSM-2120/SSM-2122
DYNAMIC RANGE
®
PROCESSOR/ DUAL VCA
Precision Monolithics Inc.
FEATURES
GENERAL DESCRIPTION
• 0.01% THD at +10dBV In/Out
• 100dB VCA Dynamic Range
• Low VCA Control Feedthrough
• 100dB Level Detection Range
• Log/Antilog Control Paths
TheSSM-2120isamonolithicintegratedcircuitdesignedforthe
purpose of processing dynamic signals in various analog sys-
tems including audio. This “dynamic range processor” consists
of two VCAs and two level detectors (the SSM-2122 consists of
two VCAs only). These circuit blocks allow the user to logarith-
mically control the gain or attenuation of the signals presented
to the level detectors depending on their magnitudes. This al-
lowsthecompression, expansionorlimitingofACsignals, some
of the primary applications for the SSM-2120.
• Low External Component Count
APPLICATIONS
• Compressors
• Expanders
PIN CONNECTIONS
• Limiters
• AGC Circuits
• Voltage-Controlled Filters
• Noise Reduction Systems
• Stereo Noise Gates
THRESH 1
LOG AV 1
1
2
22 GND
21
V+
20 SIG
CON
OUT 1
3
OUT 2
SIG
4
19 +V
GND
OUT 1
1
2
3
4
5
6
7
8
16 GND
15 V+
C2
OUT 1
+V
C1
5
18
CFT 2
SIG
ORDERING INFORMATION
CFT 1
6
17 –V
+V
C1
14 SIG
C2
OUT 2
–V
C1
7
16 SIG
CFT 1
13 +V
C2
PACKAGE
IN 2
OPERATING
TEMPERATURE
RANGE
15
14
8
REC
–V
C1
12 CFT 2
SIG
IN 1
IN 2
PLASTIC
16-PIN
PLASTIC
22-PIN
REC
IN 1
9
CON
SIG
11 –V
C2
OUT 2
IN 1
10
I
10
13 LOG AV 2
12 THRESH 2
I
SIG
REF
REF
V–
IN 2
SSM2122P
SSM2120P
–10°C to +50°C
V– 11
9
GND
SSM-2120
22-PIN PLASTIC DIP
(P-Suffix)
SSM-2122
16-PIN PLASTIC DIP
(P-Suffix)
SIMPLIFIED SCHEMATIC (VCA Section Only)
V+
36kΩ
SIGNAL
OUT
CURRENT
MIRRORS
–
+
–V
C
+V
C
V+
V+
SIGNAL
INPUT
36kΩ
V+
I
REF
V–
The SSM-2120/SSM-2122 is mask work protected under the Semiconductor Chip
Protection Act of 1983.
5/90, Rev. B1
SSM-2120/SSM-2122 DYNAMIC RANGE PROCESSOR/DUAL VCA
ABSOLUTE MAXIMUM RATINGS
PACKAGE TYPE
ΘjA (Note 1)
ΘjC
UNITS
Supply Voltage ................................................................ ±18V
Operating Temperature Range ......................... –10° to +55°C
Junction Temperature ................................................. +150°C
Storage Temperature ...................................... –65° to +150°C
Maximum Current into Any Pin ....................................... 10mA
Lead Temperature Range (Soldering, 60 sec).............. 300°C
16-Pin Plastic DIP (P)
22-Pin Plastic DIP (P)
NOTE:
86
70
10
7
°C/W
°C/W
1. ΘjA isspecifiedforworstcasemountingconditions,i.e., ΘjA isspecifiedfordevice
in socket for P-DIP.
ELECTRICAL CHARACTERISTICS at VS = ±15V, TA = +25°C, IREF = 200µA, AV = 1, unless otherwise noted.
SSM-2120/SSM-2122
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLY
Supply Voltage Range
Positive Supply Current
Negative Supply Current
VCAs
±5
–
–
8
6
±18
10
8
V
mA
mA
–
Max ISIGNAL (In/Out)
Output Offset
±387
±400
±1
±413
µA
µA
–
±2
Control Feedthrough (Trimmed)
Gain Control Range
Control Sensitivity
RIN = ROUT = 36kΩ, AV ≤ 0dB ≤ –30dB
–
750
–
–
µV
Unity-Gain
–100
+40
dB
–
6
–
mV/dB
ppm/°C
kHz
dB
Gain Scale Factor Drift
Frequency Response
Off Isolation
–
–3300
250
100
0
–
–
Unity-Gain or Less
At 1kHz
–
–
–0.25
–
–
Current Gain
+VC = –VC = 0V
+10dBV IN/OUT
RE: 0dBV
+0.25
0.02
–
dB
THD (Unity-Gain)
0.005
–80
%
Noise (20kHz Bandwidth)
LEVEL DETECTORS (SSM-2120 ONLY)
Dynamic Range
–
dB
100
0.03
–
110
–
–
3000
16
dB
µAp-p
nA
Input Current Range
Rectifier Input Bias Current
Output Sensitivity (At LOG AV Pin)
Output Offset Voltage
4
–
3
–
mV/dB
mV
–
±0.5
±2
Frequency Response
IIN = 1mAp-p
IIN = 10µAp-p
–
–
–
1000
50
–
–
–
kHz
IIN = 1µAp-p
7.5
CONTROL AMPLIFIERS (SSM-2120 ONLY)
Input Bias Current
–
85
175
–
nA
Output Drive (Max Sink Current)
5.0
7.5
mA
Input Offset Voltage
–
±0.5
±2
mV
NOTE:
1. Specifications are subject to change; consult latest data sheet.
2
5/90, Rev. B1
SSM-2120/SSM-2122 DYNAMIC RANGE PROCESSOR/DUAL VCA
ThecurrentconsumptionoftheVCAswillbedirectlyproportional
toIREF whichisnominally200µA. Thedevicewilloperateatlower
current levels which will reduce the effective dynamic range of
the VCAs. With a 200µA reference current, the input and output
clip points will be ±400µA. In general:
VOLTAGE-CONTROLLED AMPLIFIERS
The two voltage-controlled amplifiers are full Class A current in/
currentoutdeviceswithcomplementarydB/Vgaincontrolports.
The control sensitivities are +6mV/dB and –6mV/dB. A resistor
divider (attenuator) is used to adapt the sensitivity of an external
control voltage to the range of the control port. It is best to use
200Ω or less for the attenuator resistor to ground.
ICLIP = ±2IREF
VCA OUTPUTS
The VCA outputs are designed to interface directly with the vir-
tual ground inputs of external operational amplifiers configured
as current-to-voltage converters. The outputs must operate at
virtual ground because of the output stage’s finite output imped-
ance. The power supplies and selected compliance range de-
termines the values of input and output resistors needed. As an
example, with ±15V supplies and ±400µA maximum input and
output current, choose RIN = ROUT = 36kΩ for an output compli-
ance range of ±14.4 V. Note that the signal path through the
VCA including the output current-to-voltage converter is nonin-
verting.
VCA INPUTS
The signal inputs behave as virtual grounds. The input current
compliancerangeisdeterminedbythecurrentintothereference
current pin.
REFERENCE PIN
The reference current determines the input and output current
compliance range of the VCAs. The current into the reference
pin is set by connecting a resistor to V+. The voltage at the refer-
ence pin is about two volts above V– and the current will be
V+
–
V– +2V
RREF
IREF
=
BLOCK DIAGRAM (SSM-2120)
SSM-2122
+V
C1
CON
V+ THRESH 1
OUT 1
REC
–
+
|I
|
IN 1
IN
FULL
WAVE
RECTIFIER
–
+
INPUT 1
OUTPUT 1
+
2V
–V
+V
CFT 1
C1
LOG AV 1
V–
C2
CON
V+ THRESH 2
OUT 2
REC
–
+
|I
|
IN 2
IN
FULL
WAVE
RECTIFIER
–
+
INPUT 2
OUTPUT 2
+
2V
–V
CFT 2
C2
LOG AV 2
V–
3
5/90, Rev. B1
SSM-2120/SSM-2122 DYNAMIC RANGE PROCESSOR/DUAL VCA
VCA PERFORMANCE
Figures 1a and 1b show the typical THD and noise performance
of the VCAs over ±20dB gain/attenuation. Full Class A opera-
tion provides very low THD.
a)
VCA THD PERFORMANCE
vs GAIN
(+10dBV IN/OUT @ 1kHz)
.03
.01
TRIMMING THE VCAs
The control feedthrough (CFT) pins are optional control
feedthrough null points. CFT nulling is usually required in appli-
cations such as noise gating and downward expansion. If trim-
ming is not used, leave the CFT pins open.
Trim Procedure
1) Apply a 100Hz sine wave to the control point attenuator. The
signal peaks should correspond to the control voltages which
induce the VCAs maximum intended gain and at least 30dB of
attenuation.
.003
2) Adjust the 50kΩ potentiometer for the minimum feedthrough.
–20
–10
0
10
20
(Trimmed control feedthrough is typically well under 1mVRMS
when the maximum gain is unity using 36kΩ input and output
resistors.)
GAIN (dB)
b)
VCA NOISE vs GAIN
(20kHz BANDWIDTH)
Applicationssuchascompressor/limiterstypicallydonotrequire
controlfeedthroughtrimmingbecausetheVCAoperatesatunity-
gain unless the signal is large enough to initiate gain reduction.
In this case the signal masks control feedthrough.
–70
This trim is ineffective for voltage-controlled filter applications.
–80
–90
LEVEL DETECTION CIRCUITS
TheSSM-2120containstwoindependentleveldetectioncircuits.
Each circuit contains a wide dynamic range full-wave rectifier,
logging circuit and a unipolar drive amplifier. These circuits will
accurately detect the input signal level over a 100dB range from
30nA to 3mA peak-to-peak.
LEVEL DETECTOR THEORY OF OPERATION
Referring totheleveldetectorblockdiagramofFigure2, theRE-
CIN input is an AC virtual ground. The next block implements the
full-wave rectification of the input current. This current is then
fed into a logging transistor (Q1) whose pair transistor (Q2) has a
fixed collector current of IREF. The LOG AV output is then:
–20
–10
0
10
20
GAIN (dB)
FIGURE 1: Typical THD and Noise Performance
39kΩ
1kΩ
THRESH
R
CON
V+
CON
OUT
R
IN
TO V
REC
C
IN
INPUT
–
+
|I
|
I
REF
IN
FULL
WAVE
RECTIFIER
–
+
200Ω
Q
2
Q
1
+
2V
V–
LOG AV
C
R
REF
AV
V–
FIGURE 2: Level Detector
4
5/90, Rev. B1
SSM-2120/SSM-2122 DYNAMIC RANGE PROCESSOR/DUAL VCA
IIN
kT
q
VLOG AV
=
ln
IREF
With the use of the LOG AV capacitor the output is then the log
of the average of the absolute value of IIN.
(TheunfilteredLOGAVoutputhasbroadflatplateauswithsharp
negativespikesatthezerocrossing. Thisreducesthe“work”that
theaveragingcapacitormustdo, particularlyatlowfrequencies.)
Note: It is natural to assume that with the addition of the averag-
ing capacitor, the LOG AV output would become the average of
the log of the absolute value of IIN. However, since the capaci-
tor forces an AC ground at the emitter of the output transistor,
the capacitor charging currents are proportional to the antilog
of the voltage at the base of the output transistor. Since the base
voltage of the output transistor is the log of the absolute value of
IIN, the log and antilog terms cancel, so the capacitor becomes a
linear integrator with a charging current directly proportional to
the absolute value of the input current. This effectively inverts
the order of the averaging and logging functions. The signal at
the output therefore is the log of the average of the absolute
value of IIN.
FIGURE 3: Detector Output
USING DETECTOR PINS RECIN, LOGAV, THRESH
AND CONOUT
When applying signals to RECIN (rectifier input) an input series
resistor should be followed by a low leakage blocking capacitor
since RECIN has a DC voltage of approximately 2.1V above
ground. Choose RIN for a ±1.5mA peak signal. For ±15V opera-
tion this corresponds to a value of 10kΩ.
FIGURE 4: Overlayed Detector Output
CAV. The attack time to final value is a function of the step size
increase. The chart of Figure 5 shows the values of total settling
times to within 5, 3, 2 and 1dB of final value with CAV = 10µF.
When step sizes exceed 40dB, the increase in settling time for
largerstepsisnegligible.Tocalculatetheattacktimetofinalvalue
A 1.5MΩ value of RREF from log average to –15V will establish a
10µA reference current in the logging transistor (Q1). This will
bias the transistor in the middle of the detector’s dynamic cur-
rent range in dB to optimize dynamic range and accuracy. The
LOG AV outputs are buffered and amplified by unipolar drive op
amps. The 39kΩ, 1kΩ resistor network at the THRESH pin pro-
vides a gain of 40.
foranyvalueofCAV, simplymultiplythevalueinthechartbyCAV
10µF.
/
The decay rates are linear ramps that are dependent on the cur-
rent out of the LOG AV pin (set by RREF) and the value of CAV
The integration or decay time of the circuit is derived from the
.
An attenuator from the CONOUT (control output) to the appropri-
ateVCAcontrolportestablishesthecontrolsensitivity.Use200Ω
for the attenuator resistor to ground and choose RCON for the
desired sensitivity. Care should be taken to minimize capacitive
loads on the control outputs CONOUT. If long lines or capacitive
loads are present, it is best to connect the series resistor RCON
as closely to the CONOUT pin as possible.
formula:
I REF × 333
Decrementation Rate (in dB/s) =
CAV
5dB
3dB
2dB
1dB
DYNAMIC LEVEL DETECTOR CHARACTERISTICS
Figures 3 and 4 show the dynamic performance of the level de-
tector to a change in signal level. The input to the detector (not
shown) is a series of 500ms tone bursts at 1kHz in successive
10dBV steps. The tone bursts start at a level of –60dBV (with RIN
=10k) and return to –60dBV after each successive 10dB step.
Tone bursts range from –60dBV to +10dBV. Figure 3 shows the
logarithmic level detector output. The output of the detector is
3mV/dB at LOG AV and the amplifier gain is 40 which yields
120mV/dB. Thus, the output at CONOUT is seen to increase by
1.2V for each 10dBV increase in input level.
10dB Step
20dB Step
30dB Step
40dB Step
50dB Step
60dB Step
11.28ms
16.65
21.46
26.83
28.33
27.79
30.19
35.56
46.09
51.46
52.96
53.42
18.15
37.06
18.61
37.52
(+144µs)
(+46µs)
DYNAMIC ATTACK AND DECAY RATES
Figure4showstheoutputlevelsoverlayedusingastoragescope.
The attack rate is determined by the step size and the value of
FIGURE 5: Settling Time (tS) for CAV = 10µF, tS′ = tS (CAV
10µF)
/
5
5/90, Rev. B1
SSM-2120/SSM-2122 DYNAMIC RANGE PROCESSOR/DUAL VCA
a) CONTROL CIRCUIT
b)
TYPICAL DOWNWARD EXPANDER
CONTROL CURVE
THRESHOLD
THRESHOLD CONTROL
R
R
IN
V+
L
V
T
+
REC
IN
IN
V–
MONO
OR R
R
T
–
+
CON
OUT
+
R
CON
39kΩ
|I
|
TO +V
IN
C
R
V
CON
LL
1kΩ
200Ω
–
+
+
2V
LOG AV
MONO – R = 10kΩ
IN
–
STEREO – R = 20kΩ
IN
C
AV
*
1.5MΩ
V–
V–
VV ((ddBB))
IN
*
LOWER LIMIT CAN BE FIXED BY CONNECTING
A RESISTOR R FROM REC TO GROUND
LL
IN
FIGURE 6: Noise Gate/Downward Expander Control Circuit and Typical Response.
a) CONTROL CIRCUIT
b)
TYPICAL COMPRESSOR/LIMITER
CONTROL CURVE
THRESHOLD
V+
THRESHOLD
CONTROL
V
T
*
R
PV
R
IN
V+
R
+
CON
L
TO –V
R
C
T
R
IN
REC IN
MONO
OR R
–
+
+
39kΩ
200Ω
CON
OUT
|I
|
IN
V
CON
1kΩ
–
THRESH
+
2V
LOG AV
–
MONO – R = 10kΩ
IN
+
STEREO – R = 20kΩ
IN
C
AV
1.5MΩ
V–
V–
V (dB)
IN
*
UPPER LIMIT CAN BE FIXED BY VALUE OF PULL UP
RESISTOR (R ) CONNECTED TO POSITIVE SUPPLY
PV
FIGURE 7: Compressor/Limiter Control Circuit and Typical Response.
APPLICATIONS
lar control output. This is typically used in noise gate, downward
expander, and dynamic filter applications. This potentiometer is
used in all applications to control the signal level versus control
voltage characteristics.
The following applications for the SSM-2120 use both the VCAs
and level detectors in conjunction to assimilate a variety of func-
tions.
In the noise gate, downward expander and compressor/limiter
applications, this potentiometer will establish the onset of the
control action. The sensitivity of the control action depends on
the value of RT.
The first section describes the arrangement of the threshold
control in each control circuit configuration. These control cir-
cuits form the foundation for the applications to follow which in-
cludethedownwardexpander, compressor/limiterandcompan-
dor.
For a positive unipolar control output add two diodes as shown
in Figure 7a. This is useful in compressor/limiter applications.
Figure 7b shows a typical response.
THRESHOLD CONTROL
Figure 6a shows the control circuit for a typical downward ex-
pander while Figure 6b shows a typical control curve. Here, the
threshold potentiometer adjusts VT to provide a negative unipo-
Bipolar control outputs can be realized by adding a resistor from
the op amp output to V+. This is useful in compandor circuits as
6
5/90, Rev. B1
SSM-2120/SSM-2122 DYNAMIC RANGE PROCESSOR/DUAL VCA
TYPICAL COMPANDOR
CONTROL CURVES
b)
a) CONTROL CIRCUIT
V+
GAIN
*
R
IN
V+
V
L
T
+
R
IN
REC
IN
R
V–
PV
MONO
OR R
R
T
–
+
+
V
< 0
V
T
= 0
V > 0
T
T
39kΩ
TO +V
OR –V
C
|I
|
IN
C
R
CON
OUT
LL
V
CON
200Ω
1kΩ
–
THRESH
+
2V
LOG AV
MONO – R = 10kΩ
IN
+
–
STEREO – R = 20kΩ
IN
C
AV
1.5MΩ
V–
*
V–
V
(dB)
IN
*
UPPER AND LOWER LIMITS CAN BE ESTABLISHED BY
VALUES OF R AND R , RESPECTIVELY
PV LL
FIGURE 8: Compandor Control Circuit and Typical Curves.
a) CONTROL CIRCUIT
b)
INPUT/OUTPUT CURVE
THRESHOLD EXP.
EXPANSION
THRESHOLD
COMPRESSION
THRESHOLD
FIGURE 6
+V
L
C
200Ω
MONO
OR R
V
(dB)
OUT
THRESHOLD COM.
FIGURE 7
–V
C
200Ω
V
(dB)
IN
FIGURE 9: Control Circuit for Stereo Compressor/Limiter with Noise Gating and Input/Output Curve
shown in Figure 8a, with its response in Figure 8b. The value of
the resistor RPV will determine the maximum output from the
control amplifier.
compressor/limiter which also acts as a downward expander for
noise gating. The output noise in the absence of a signal will be
dependent on the noise of the current-to-voltage converter am-
plifier if the expansion ratio is high enough.
STEREO COMPRESSOR/LIMITER
The two control circuits of Figures 6 and 7 can be used in con-
junction to produce composite control voltages. Figures 9a and
9b show this type of circuit and transfer function for a stereo
AsdiscussedintheThresholdControlsection, theuseofthecon-
trol circuit of Figure 5, including the RPV to V+ and two diodes,
yields positive unipolar control outputs.
7
5/90, Rev. B1
SSM-2120/SSM-2122 DYNAMIC RANGE PROCESSOR/DUAL VCA
200Ω
10pF
+V
C
10pF
200Ω
–V
36Ω
C
36kΩ
36kΩ
SIGNAL
INPUT
–
+
TRANSMISSION
OR
STORAGE
MEDIUM
36kΩ
2200pF
–
+
SIGNAL
OUTPUT
2200pF
47Ω
–V
C
V+
1µF
47Ω
+
+V
C
200Ω
10kΩ
V+
200Ω
V+
R
C
1µF
+
10kΩ
10kΩ
REC
39kΩ
IN
|I
|
IN
V+
R
E
1kΩ
–
+
REC
10kΩ
39kΩ
IN
|I
|
IN
LOG AV
1kΩ
–
+
1µF
4.7MΩ
V–
LOG AV
V–
1µF
4.7MΩ
V–
V–
FIGURE 10: Companding Noise Reduction System
COMPANDING NOISE REDUCTION SYSTEM
20
0
AcompletecompandingnoisereductionsystemisshowninFig-
ure 10. Normally, to obtain an overall gain of unity, the value of
RC is equal to RE. The values of RC/E will determine the compres-
sion/expansion ratio.
~
I
3µA
~
OVERALL
REF
RESPONSE
25dB
R
= 4.7MΩ
REF
2:1
EXPANSION
Table1showscompression/expansionratiosrangingfrom1.5:1
–20
–40
–60
–80
to full limiting with the corresponding values of RC/E
.
2:1
COMPRESSION
An example of a 2:1 compression/expansion ratio is plotted in
Figure 11. Note that signal compression increases gain for low
level signals and reduces gain for high levels while expansion
does the reverse. The net result for the system is the same as
the original input signal except that it has been compressed be-
fore being sent to a given medium and expanded after recovery.
The compression/expansion ratio needed depends on the me-
dium being used. As an extreme example, a household tape
player would require a higher compression/expansion ratio than
a professional stereo system.
–80
–40
–20
0
20
–60
INPUT SIGNAL LEVEL (dB)
FIGURE 11: Companding Noise Reduction with 2:1 Compres-
sion/Expansion Ratio
TABLE 1
GAIN
(REDUCTION
OR INCREASE)
(dB)
COMPRESSOR
ONLY
OUTPUT SIGNAL
INCREASE (dB)
EXPANDER
ONLY
∆VCONTROL
(mV/dB)
–
INPUT SIGNAL
INCREASE (dB)
COMPRESSION/
EXPANSION RATIO
OUTPUT SIGNAL
INCREASE (dB)
RC/E
Ω
20
20
20
20
20
20
20
20
6.67
10.00
13.33
15.00
16.00
17.33
18.00
20.00
13.33
10.00
6.67
5.00
4.00
2.67
2.00
0
22.67
30.00
33.33
35.00
36.00
37.33
38.00
40.00
1.5:1
11,800
7,800
5,800
5,133
4,800
4,415
4,244
3,800
2.0
3.0
4.0
4.5
4.8
5.2
5.4
6.0
2:1
3:1
4:1
5:1
7.5:1
10:1
AGC*/Limiter
*AGC for Compression Only
8
5/90, Rev. B1
SSM-2120/SSM-2122 DYNAMIC RANGE PROCESSOR/DUAL VCA
THRESHOLD
CONTROL
V+
V–
2.2µF
REC
10kΩ
IN
AUDIO
INPUT
|I
|
IN
9
F
≤ 20Hz
39kΩ
12kΩ
CON
160kΩ
THRESH
1
C
OUT
(WIDEBAND)
3
1kΩ
–
3.3µF
LOG AV
+
2
V–
1.5MΩ
160kΩ
V–
V+
CON
39kΩ
5.6kΩ
OUT
THRESH
12
14
3300pF
10kΩ
REC
IN
200Ω
|I
|
IN
15
F
= 5kHz
1kΩ
C
(HIGH FREQUENCY)
–
+
3.3µF
LOG AV
13
1.5MΩ
V–
V–
+V
C
5
36kΩ
36kΩ
100pF
SIG
36kΩ
SIG
OUT
IN
–
+
8
5
36kΩ
–
+
47Ω
2200pF
AUDIO
OUTPUT
–V
7
C
200Ω
FIGURE 12: Dynamic Noise Filter Circuit
DYNAMIC FILTER
Figure 12 shows a control circuit for a dynamic filter capable of
singleended(non-encode/decode)noisereduction.Suchcircuits
usually suffer from a loss of high-frequency content at low signal
levels because their control circuits detect the absolute amount
of highs present in the signal. This circuit, however, measures
wideband level as well as high-frequency band level to produce
a composite control signal combined in a 1:2 ratio respectively.
Theupperdetectorsenseswidebandsignalswithacutoffof20Hz
while the lower detector has a 5kHz cutoff to sense only high-
frequency band signals. This approach allows very good noise
masking with a minimum loss of “highs” when the signal level
goes below the threshold.
9
5/90, Rev. B1
SSM-2120/SSM-2122 DYNAMIC RANGE PROCESSOR/DUAL VCA
Figures 13a-c show the filter’s 3dB frequency response with the
thresholdpotentiometeratV+, centered, andV–. Datawastaken
byapplyinga300Hzsignaltothewidebanddetectoranda20kHz
signaltothehigh-frequencybanddetectorsimultaneously.These
figures correspond to filter characteristics for 50dB, 70dB and
90dBdynamicrangeprogramsourcematerial, respectively. The
system could thus treat signals from anything ranging from 1/4”
magnetic tape to high-performance compact disc players.
a) VTHRESH at V+
20
10
50.6
50.6 50.6
50.6 50.6 50.6
0
–10
17.8 26
26
26
Note that in Figure 13a the control circuit is designed so that the
minimumcutofffrequencyisabout1kHz. Thisoccursasthecon-
trol circuit detects the noise floor of the source material.
–20
–30
–40
6
8.3 11.7 11.7 11.7
1.9 2.75 3.9 5.5 5.5 5.5
1.0 1.2 1.7 2.4 2.4 2.4
Dynamic filtering limits the signal bandwidth to less than 1kHz
unlessenoughhighsaredetectedinthesignaltocoverthenoise
floor in the mid- and high-frequency range. In this case the filter
openstopassmoreoftheaudiobandasmorehighsaredetected.
The filter’s bandwidth can extend to 50kHz with a nominal signal
levelattheinput.Atothersignallevelswithvaryinghigh-frequency
content, thefilterwillclosetotherequiredbandwidth. Here, noise
outsidethebandisremovedwhiletheperceivednoiseismasked
by other signals within the band. Even in this system, however, a
certain amount of mid- and high-frequency components will be
lost, especially during transients at very low signal levels. This
circuit does not address low frequency noise such as “hum” and
“rumble.”
1.0
1.0
–50
1.0
1.0
1.0 1.0 1.1 1.1 1.1
–50 –40 –30 –20 –10
0
10
20
WIDEBAND SIGNAL LEVEL (dB)
b) VTHRESH Centered
20
10
50.6
50.6 50.6
0
50.6 50.6 50.6
–10
–20
–30
50.6 50.6 50.6 50.6
48 49.2 49.2 49.2 49.2
15.1 22
4.9 7.1 10
22
10
22
10
22
10
22
10
–40
–50
1.5 2.2 3.1 4.2 4.2 4.2 4.2 4.2
–50 –40 –30 –20 –10
0
10
20
WIDEBAND SIGNAL LEVEL (dB)
c) VTHRESH at V–
50.6
20
10
50.6 50.6
50.6 50.6 50.6
0
50.6 50.6 50.6 50.6
–10
–20
–30
–40
50.6 50.6 50.6 50.6 50.6
50.6 50.6 50.6 50.6 50.6 50.6
40
41
41
41
41
41
41
–50
12.3 17.3 17.8 17.8 17.8 17.8 17.8 17.8
–50 –40 –30 –20 –10
0
10
20
WIDEBAND SIGNAL LEVEL (dB)
FIGURE 13: 3dB Filter Response
10
5/90, Rev. B1
SSM-2120/SSM-2122 DYNAMIC RANGE PROCESSOR/DUAL VCA
200Ω
V+
12kΩ
THRESHOLD
+V
C
36kΩ
V–
160kΩ
39kΩ
12kΩ
CON
OUT
V+
–
+
SIGNAL
INPUT
SIGNAL
OUTPUT
R
REC
IN
IN1
+
1kΩ
47Ω
IN |I
|
IN
–
+
F
≤ 20Hz
–V
C
C
LOG AV
2200pF
200Ω
C
AV1
1.5MΩ
V–
DOWNWARD EXPANDER
V–
V+
160kΩ
1kΩ
200Ω
CON
OUT
39kΩ
5.6kΩ
F
= 5kHz
IN2
C
R
REC
IN
+V
C
36kΩ
+
IN |I
|
IN
–
+
36kΩ
LOG AV
100pF
C
–
+
AV2
36kΩ
1.5MΩ
V–
–
36kΩ
36kΩ
V–
–V
C
+
47Ω
2200pF
200Ω
NOISE FILTER
FIGURE 14: Dynamic Filter with Downward Expander
DYNAMIC FILTER WITH DOWNWARD EXPANDER
The dynamic filter and downward expander techniques used to-
gether can be employed more subtly to achieve a given level of
noise reduction than would be required if used individually. Up
to 30dB of noise reduction can be realized while preserving the
crisp highs with a minimum of transient side effects.
A composite single-ended noise reduction system can be real-
ized by a combination of dynamic filtering and a downward ex-
pander. As shown in Figure 14, the output from the wideband
detector can also be connected to the +VC control port of the
second VCA which is connected in series with the sliding filter.
Thiswillactasadownwardexpanderwithathresholdthattracks
that of the filter. Although both of these techniques are used for
noise reduction, each alone will pass appreciable amounts of
noise under some conditions. When used together, both con-
tribute distinct advantages while compensating for each other’s
deficiencies.
+20
–30
–40
–50
-60
+20
–30
Downward expansion uses a VCA controlled by the level detec-
tor. This section maintains dynamic range integrity for all levels
above the user adjustable threshold level. As the input level
decreases below the threshold, gain reduction occurs at an in-
creasing rate (see Figure 15). This technique reduces audible
noise in fade outs or low level signal passages by keeping the
standing noise floor well below the program material.
–45
–60
This technique by itself is less effective for signals with predomi-
nantly low frequency content such as a bass solo where wide-
band frequency noise would be heard at full level. Also, since
the level detector has a time constant for signal averaging, per-
cussive material can modulate the noise floor causing a “pump-
ing” or “breathing” effect.
–75
FIGURE 15: Typical Downward Expander I/O Characteristics
at –30dB Threshold Level (1:1.5 Ratio)
11
5/90, Rev. B1
SSM-2120/SSM-2122 DYNAMIC RANGE PROCESSOR/DUAL VCA
+15V
0.1µF
10pF
1
2
16
15
10pF
36kΩ
36kΩ
–
+
1/2
TL082
SIG
OUT 1
200Ω
220kΩ
200Ω
3
4
14
13
V+
–
1/2
SIG
OUT 2
TL082
+
200Ω
220kΩ
200Ω
50kΩ*
V+
SSM-2122
5
6
7
8
12
11
10
9
V–
50kΩ*
–V
C1
36kΩ
SIN
V–
IN 1
–V
C2
150kΩ
0.1µF
36kΩ
2000pF
V+
SIG
IN 2
47Ω
2000pF
47Ω
*
OPTIONAL CONTROL FEEDTHROUGH TRIM
–15V
FIGURE 16: SSM-2122 Basic Connection (Control Ports at 0V)
FADER AUTOMATION
TheSSM-2120canbeusedinfaderautomationsystemstoserve
two channels. The inverting control port is connected through
anattenuatortotheVCAcontrolvoltagesource.Thenoninverting
control port is connected to a control circuit (such as Figure 6)
whichsensestheinputsignalleveltotheVCA. Abovethethresh-
old voltage, which can be set quite low (for example –60dBV),
the VCA operates at its programmed gain. Below this threshold
the VCA will downward expand at a rate determined by the +VC
control port attenuator. By keeping the release time constant in
the 10 to 25ms range, the modulation of the VCA standing noise
floor (–80dB at unity-gain), can be kept inaudibly low.
ing as a unity-gain VCA with its noninverting control ports
grounded and access to the inverting control ports. This is typi-
cal for fader automation applications. Since this device is a pin-
out option of the SSM-2120, the VCAs will behave exactly as
described earlier in the VCA section.
The SSM-2122 can also be used with two or more op amps to
implementcomplexvoltage-controlledfilterfunctions.Biquadand
state-variable two-pole filters offering lowpass, bandpass and
highpass outputs can be realized. Higher order filters can also
be formed by connecting two or more such stages in series.
The SSM-2300 8-channel multiplexed sample-and-hold IC
makes an excellent controller for VCAs in automation systems.
Figure 16 shows the basic connection for the SSM-2122 operat-
5/90, Rev. B1
0590 0299G7M PRINTED IN USA
Precision Monolithics Inc. reserves the right to make changes leading to improved performance, reliability or manufacturability. Although every effort is made to ensure accuracy of the information
contained on this data sheet, PMI assumes no responsibility for circuitry unless entirely contained within a PMI product. The premium performance of this product is achieved through an advanced
processing technology. All PMI products are guaranteed to meet or exceed published specifications. © PMI 1990
Precision Monolithics Inc.
A Bourns Company
1500 Space Park Dr.
P.O. Box 58020
Santa Clara, CA
95052-8020
TWX 310-371-9541
FAX 408 727-1550
TEL 800 843-1515
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