OPZ249GPZ [ADI]
DUAL OP-AMP, 3600uV OFFSET-MAX, 4.7MHz BAND WIDTH, PDIP8, PLASTIC, MS-001, DIP-8;
| 型号： | OPZ249GPZ |
| 厂家： | 
ADI |
| 描述： | DUAL OP-AMP, 3600uV OFFSET-MAX, 4.7MHz BAND WIDTH, PDIP8, PLASTIC, MS-001, DIP-8 放大器 光电二极管 |
| 文件： | 总20页 (文件大小：431K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Precision JFET, High Speed,
Dual Operational Amplifier
Data Sheet
OP249
FEATURES
PIN CONFIGURATIONS
Fast slew rate: 22 V/µs typical
Settling time (0.01%): 1.2 µs maximum
Offset voltage: 200 µV typical
High open-loop gain: 1000 V/mV minimum
Low total harmonic distortion: 0.002% typical
OUT A
–IN A
+IN A
V–
1
2
3
4
8
7
6
5
V+
OP249
A
OUT B
–IN B
+IN B
B
Figure 1. 8-Lead CERDIP (Q-8) and
8-Lead PDIP (N-8)
APPLICATIONS
1
2
3
4
8
7
6
5
+IN A
V–
–IN A
OUT A
V+
Output amplifier for fast DACs
Signal processing
Instrumentation amplifiers
Fast sample-and-holds
Active filters
Low distortion audio amplifiers
Input buffer for ADCs
Servo controllers
A
+IN B
–IN B
OP249
B
OUT B
Figure 2. 8-Lead SOIC (R-8)
GENERAL DESCRIPTION
The OP249 is a high speed, precision dual JFET op amp, similar
to the popular single op amp. The OP249 outperforms available
dual amplifiers by providing superior speed with excellent dc
performance. Ultrahigh open-loop gain (1 kV/mV minimum),
low offset voltage, and superb gain linearity makes the OP249
the industry’s first true precision, dual high speed amplifier.
Symmetrical slew rate, even when driving large load, such as,
600 Ω or 200 pF of capacitance and ultralow distortion, make
the OP249 ideal for professional audio applications, active filters,
high speed integrators, servo systems, and buffer amplifiers.
With a slew rate of 22 V/µs typical and a fast settling time of less
than 1.2 µs maximum to 0.01%, the OP249 is an ideal choice for
high speed bipolar DAC and ADC applications. The excellent
dc performance of the OP249 allows the full accuracy of high
resolution CMOS DACs to be realized.
0.01
T
V
V
R
= 25°C
= ±15V
= 10V p-p
= 10kΩ
= 1
870ns
A
S
100
90
100
90
O
L
V
A
10
10
0%
0%
10mV
500ns
5V
1µs
0.001
20
100
1k
10k 20k
Figure 3. Fast Settling (0.01%)
Figure 4. Low Distortion, AV = 1, RL = 10 kΩ
Figure 5. Excellent Output Drive, RL = 600 Ω
Rev. H
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Tel: 781.329.4700 ©1989–2013 Analog Devices, Inc. All rights reserved.
Technical Support
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OP249
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................7
Applications Information.............................................................. 13
Open-Loop Gain Linearity ....................................................... 14
Offset Voltage Adjustment........................................................ 14
Settling Time............................................................................... 14
DAC Output Amplifier.............................................................. 15
Discussion on Driving ADCs ................................................... 16
Outline Dimensions....................................................................... 17
Ordering Guide .......................................................................... 18
Applications....................................................................................... 1
Pin Configurations ........................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics............................................................. 3
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
REVISION HISTORY
11/13—Rev. G to Rev. H
Changes to Figure 39 and Figure 41............................................. 13
9/01—Rev. D to Rev. E
Edits to Features and Pin Connections ..........................................1
Edits to Electrical Characteristics .............................................. 2, 3
Edits to Absolute Maximum Ratings, Package Type, and
Ordering Guide..................................................................................4
Deleted Wafer Test Limits and Dice Characteristics Section ......5
Edits to Typical Performance Characteristics................................8
Edits to Macro-Model Figure........................................................ 15
Edits to Outline Dimensions......................................................... 17
4/10—Rev. F to Rev. G
Changes to Features Section and General Description Section. 1
Changes to Offset Voltage Parameter, Table 1 .............................. 3
Deleted Long Term Offset Voltage Parameter and
Note 1, Table 1................................................................................... 3
Changes to Offset Voltage Parameter, Offset Voltage
Temperature Coefficient Parameter, and Note 1, Table 3 ........... 5
Delete OP249F Columns, Table 3................................................... 5
Changes to Offset Voltage Parameter and Offset Voltage
Temperature Coefficient Parameter, Table 4................................. 5
Inserted OP249F Columns, Table 4 ............................................... 5
Changes to Discussion on Driving ADCs Section..................... 16
Deleted Figure 52 and Figure 53................................................... 17
5/07—Rev. E to Rev. F
Updated Format..................................................................Universal
Changes to Table 1 ............................................................................ 3
Changes to Table 2............................................................................ 4
Changes to Table 3 and Table 4....................................................... 5
Changes to Table 5............................................................................ 6
Changes to Figure 31...................................................................... 11
Changes to Figure 37 and Figure 38............................................. 12
Deleted OP249 SPICE Macro-Model Section ............................ 14
Deleted Figure 18; Renumbered Sequentially ............................ 14
Deleted Table I ................................................................................ 15
Changes to Discussion on Driving ADCs Section..................... 17
Updated Outline Dimensions ....................................................... 18
Changes to Ordering Guide .......................................................... 19
Rev. H | Page 2 of 20
Data Sheet
OP249
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VS = 15 V, TA = 25°C, unless otherwise noted.
Table 1.
OP249A
Typ
0.2
OP249F
Typ
0.2
Parameter
Symbol Conditions
Min
Max Min
Max Unit
Offset Voltage
VOS
VCM = 0 V
0.75
0.9
mV
Offset Stability
1.5
1.5
µV/month
Input Bias Current
Input Offset Current
Input Voltage Range1
IB
IOS
IVR
VCM = 0 V, TA = 25°C
VCM = 0 V, TA = 25°C
30
6
12.5
75
25
30
6
12.5
75
25
pA
pA
V
11
80
11
V
V
−12.5
90
12
1400
12.5
–12.5
90
12
1200
12.5
Common-Mode Rejection
Power-Supply Rejection Ratio
Large Signal Voltage Gain
Output Voltage Swing
CMR
PSRR
AVO
VCM
=
11 V
80
31.6
dB
µV/V
V/mV
V
VS = 4.5 V to 18 V
VO = 10 V, RL = 2 kΩ
RL = 2 kΩ
50
1000
12.0
500
VO
12.0
V
−12.5
36
–12.5
36
V
mA
Short-Circuit Current Limit
ISC
Output shorted to
ground
20
50
7.0
20
50 mA
−33
5.6
22
4.7
0.9
55
–33
5.6
22
4.7
0.9
55
mA
Supply Current
ISY
No load, VO = 0 V
7.0
1.2
mA
V/µs
MHz
µs
Slew Rate
SR
GBW
tS
ΘM
ZIN
RO
RL = 2 kΩ, CL = 50 pF
18
3.5
18
3.5
Gain Bandwidth Product2
Settling Time
Phase Margin
Differential Input Impedance
Open-Loop Output Resistance
Voltage Noise
10 V step 0.01%3
0 dB gain
1.2
Degrees
Ω||pF
Ω
1012||6
35
1012||6
35
en p-p
en
0.1 Hz to 10 Hz
fO = 10 Hz
2
75
26
17
16
0.003
15
2
75
26
17
16
0.003
15
µV p-p
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
pA/√Hz
V
Voltage Noise Density
fO = 100 Hz
fO = 1 kHz
fO = 10 kHz
fO = 1 kHz
Current Noise Density
Voltage Supply Range
in
VS
4.5
18
4.5
18
1 Guaranteed by CMR test.
2 Guaranteed by design.
3 Settling time is sample tested.
Rev. H | Page 3 of 20
OP249
Data Sheet
VS = 15 V, TA = 25°C, unless otherwise noted.
Table 2.
OP249G
Typ
Parameter
Symbol
VOS
Conditions
Min
Max
2.0
75
Unit
mV
Offset Voltage
VCM = 0 V
0.4
40
10
Input Bias Current
Input Offset Current
Input Voltage Range1
IB
IOS
IVR
VCM = 0 V, TA = 25°C
VCM = 0 V TA = 25°C
pA
pA
V
25
12.5
11
76
V
V
dB
µV/V
V/mV
V
−12.0
90
12
1100
12.5
Common-Mode Rejection
Power Supply Rejection Ratio
Large Signal Voltage Gain
Output Voltage Swing
CMR
PSRR
AVO
VCM
=
11 V
VS = 4.5 V to 18 V
VO = 10 V; RL = 2 kΩ
RL = 2 kΩ
50
500
VO
12.0
V
−12.5
36
V
mA
Short-Circuit Current Limit
ISC
Output shorted to ground
20
50
mA
−33
5.6
22
4.7
0.9
55
mA
mA
Supply Current
Slew Rate
Gain Bandwidth Product2
Settling Time
ISY
SR
GBW
tS
ΘM
ZIN
No load; VO = 0 V
RL = 2 kΩ, CL = 50 pF
7.0
18
V/µs
MHz
µs
Degree
Ω||pF
Ω
μV p-p
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
pA/√Hz
V
10 V step 0.01%
0 dB gain
1.2
Phase Margin
Differential Input Impedance
Open-Loop Output Resistance
Voltage Noise
1012||6
RO
en p-p
en
35
2
75
26
17
16
0.003
15
0.1 Hz to 10 Hz
fO = 10 Hz
fO = 100 Hz
fO = 1 kHz
fO = 10 kHz
fO = 1 kHz
Voltage Noise Density
Current Noise Density
Voltage Supply Range
in
VS
4.5
18
1 Guaranteed by CMR test.
2 Guaranteed by design.
Rev. H | Page 4 of 20
Data Sheet
OP249
VS = ±±1 V, −11°C ≤ TA ≤ +±21°C for A grade, unless otherwise noted.
Table 3.
OP249A
Min Typ
Max
Parameter
Symbol
Conditions
VCM = 0 V
Unit
Offset Voltage
VOS
0.12
1.0
mV
Offset Voltage Temperature Coefficient
Input Bias Current1
TCVOS
IB
IOS
VCM = 0 V
1
4
0.04
12.5
10
20
4
μV/°C
nA
nA
V
Input Offset Current1
Input Voltage Range2
IVR
11
76
V
V
−12.5
110
5
1400
12.5
Common-Mode Rejection
Power Supply Rejection Ratio
Large Signal Voltage Gain
Output Voltage Swing
CMR
PSRR
AVO
VCM = 11 V
dB
μV/V
V/mV
V
VS = 4.5 V to 18 V
RL = 2 kΩ; VO = 10 V
RL = 2 kΩ
50
500
12
VO
V
−12.5
5.6
V
mA
Supply Current
ISY
No load, VO = 0 V
7.0
1 TA = 125°C.
2 Guaranteed by CMR test.
VS = ±±1 V, −40°C ≤ TA ≤ +81°C, unless otherwise noted.
Table 4.
OP249F
Typ
0.5
2.2
0.3
OP249G
Typ
1.0
6
0.5
Min
Max Min
Max
Parameter
Symbol
VOS
TCVOS
IB
IOS
IVR
Conditions
VCM = 0 V
VCM = 0 V
Unit
mV
μV/°C
nA
nA
V
Offset Voltage
Offset Voltage Temperature Coefficient
Input Bias Current1
Input Offset Current1
Input Voltage Range2
1.1
12
4.0
1.2
3.6
25
4.5
1.5
0.02
12.5
0.04
12.5
11
80
11
V
V
−12.5
90
7
1200
12.5
−12.5
95
10
1200
12.5
Common-Mode Rejection
Power Supply Rejection Ratio
Large Signal Voltage Gain
Output Voltage Swing
CMR
PSRR
AVO
VCM = 11 V
76
100
dB
μV/V
V/mV
V
V
V
VS = 4.5 V to 18 V
RL = 2 kΩ; VO = 10 V
RL = 2 kΩ
100
7.0
250
12
250
VO
12.0
−12.5
5.6
−12.5
5.6
Supply Current
ISY
No load, VO = 0 V
7.0
mA
1 TA = 85°C.
2 Guaranteed by CMR test.
Rev. H | Page 5 of 20
OP249
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter1
Supply Voltage
Input Voltage2
Differential Input Voltage2
Output Short-Circuit Duration
Storage Temperature Range
Operating Temperature Range
OP249A (Q)
OP249F (Q)
OP249G (N, R)
Junction Temperature Range
OP249A (Q), OP249F (Q)
OP249G (N, R)
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
18 V
18 V
36 V
Indefinite
−65°C to +175°C
−55°C to +125°C
−40°C to +85°C
−40°C to +85°C
Table 6. Thermal Resistance
1
Package Type
8-Lead CERDIP (Q)
8-Lead PDIP (N)
8-Lead SOIC (R)
θJA
134
96
θJC
12
37
41
Unit
°C/W
°C/W
°C/W
−65°C to +175°C
−65°C to +150°C
300°C
150
1 θJA is specified for worst-case mounting conditions, that is, θJA is specified for
device in socket for CERDIP and PDIP packages; θJA is specified for device
soldered to printed circuit board for SOIC package.
Lead Temperature (Soldering, 60 sec)
1 Absolute maximum ratings apply to packaged parts, unless otherwise noted.
2 For supply voltages less than 18 V, the absolute maximum input voltage is
equal to the supply voltage.
ESD CAUTION
Rev. H | Page 6 of 20
Data Sheet
OP249
TYPICAL PERFORMANCE CHARACTERISTICS
120
120
100
80
60
40
20
0
T
= 25°C
T
V
R
= 25°C
= ±15V
= 2kΩ
A
A
V
= ±15V
S
S
100
80
60
40
20
0
L
0
GAIN
45
+PSRR
90
–PSRR
PHASE
Θm = 55
135
180
225
–20
1k
10k
100k
1M
10M
100M
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 6. Open-Loop Gain, Phase vs. Frequency
Figure 9. Power Supply Rejection vs. Frequency
28
26
24
22
20
18
16
65
60
55
50
45
10
8
V
= ±15V
V
R
C
= ±15V
= 2kΩ
= 50pF
S
S
L
L
–SR
Θm
6
+SR
GBW
4
2
125
–75
–50
–25
0
25
50
75
100
–75
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 7. Phase Margin, Gain Bandwidth Product vs. Temperature
Figure 10. Slew Rate vs. Temperature
28
26
24
22
20
18
16
140
T
V
= 25°C
= ±15V
T
V
R
= 25°C
= ±15V
= 2kΩ
A
A
S
S
120
100
80
60
40
20
0
L
0
0.2
0.4
0.6
0.8
1.0
100
1k
10k
100k
1M
10M
DIFFERENTIAL INPUT VOLTAGE (V)
FREQUENCY (Hz)
Figure 8. Common-Mode Rejection vs. Frequency
Figure 11. Slew Rate vs. Differential Input Voltage
Rev. H | Page 7 of 20
OP249
Data Sheet
35
30
25
20
15
10
5
0.01
T
V
V
R
A
= 25°C
= ±15V
= 10V p-p
= 10kΩ
= 1
T
V
= 25°C
= ±15V
A
A
S
S
O
L
V
NEGATIVE
POSITIVE
0.001
0
100
200
300
400
500
20
100
1k
10k 20k
CAPACITIVE LOAD (pF)
Figure 12. Slew Rate vs. Capacitive Load
Figure 15. Distortion vs. Frequency
10
8
0.01
T
V
A
= 25°C
= ±15V
T
V
V
R
A
= 25°C
= ±15V
= 10V p-p
= 2kΩ
= 1
A
A
S
S
= 1
VCL
O
6
L
V
0.1%
4
0.01%
0.01%
2
0
–2
–4
–6
–8
–10
0.1%
400
0.001
0
200
600
800
1000
20
100
1k
10k 20k
SETTLING TIME (ns)
Figure 13. Step Size vs. Settling Time
Figure 16. Distortion vs. Frequency
100
80
60
40
20
0
T
V
= 25°C
= ±15V
A
0.01
S
T
V
V
R
= 25°C
= ±15V
= 10V p-p
= 600Ω
= 1
A
S
O
L
V
A
0
100
FREQUENCY (Hz)
1k
10k
0.001
20
100
1k
10k 20k
Figure 17. Distortion vs. Frequency
Figure 14. Voltage Noise Density vs. Frequency
Rev. H | Page 8 of 20
Data Sheet
OP249
500mV
1s
0.1
T
V
V
R
= 25°C
= ±15V
= 10V p-p
= 10kΩ
= 1
A
S
O
L
V
A
+1µV
–1µV
BANDWIDTH (0.1Hz TO 10Hz)
= 25°C, V = ±15V
0.01
20
T
100
1k
10k 20k
A
S
Figure 21. Low Frequency Noise
Figure 18. Distortion vs. Frequency
60
50
40
30
20
10
0
T
V
= 25°C
= ±15V
A
0.1
S
T
V
V
R
A
= 25°C
= ±15V
= 10V p-p
= 2kΩ
A
S
A
= 100
VCL
O
L
V
= 10
A
= 10
= 5
VCL
A
VCL
A
= 1
VCL
–10
–20
1k
10k
100k
1M
10M
100M
0.01
20
100
1k
10k 20k
FREQUENCY (Hz)
Figure 19. Distortion vs. Frequency
Figure 22. Closed-Loop Gain vs. Frequency
50
40
30
20
10
0
T
V
= 25°C
= ±15V
0.1
A
T
V
V
R
= 25°C
= ±15V
= 10V p-p
= 600kΩ
= 10
S
A
S
O
L
V
A
A
= 1
VCL
A
= 10
VCL
A
= 100
10k
VCL
100
1k
100k
1M
10M
0.01
20
100
1k
10k 20k
FREQUENCY (Hz)
Figure 20. Distortion vs. Frequency
Figure 23. Closed-Loop Output Impedance vs. Frequency
Rev. H | Page 9 of 20
OP249
Data Sheet
30
25
20
15
10
5
20
15
T
R
= 25°C
= 2kΩ
A
L
10
5
0
AD8512
–5
–10
–15
–20
OP249
AD712
0
1k
1M
10M
500
10k
0
±5
±10
±15
±20
125
20
FREQUENCY (Hz)
SUPPLY VOLTAGE (V)
Figure 24. Output Voltage vs. Frequency
Figure 27. Output Voltage Swing vs. Supply Voltage
90
80
70
60
50
40
30
20
10
0
6.0
5.8
5.6
5.4
5.2
V
R
V
= ±15V
= 2kΩ
V
= ±15V
S
S
NO LOAD
L
= 100mV p-p
IN
A
= 1
VCL
NEGATIVE EDGE
A
= 1
VCL
POSITIVE EDGE
A
= 5
VCL
0
100
200
300
400
–75
–50
–25
0
25
50
75
100
LOAD CAPACITANCE (pF)
TEMPERATURE (°C)
Figure 25. Small Overshoot vs. Load Capacitance
Figure 28. Supply Current vs. Temperature
16
14
12
10
8
6.0
5.8
5.6
5.4
5.2
5.0
T
= 25°C
= ±15V
A
V
S
+V
= |–V |
OHM
OHM
T
= +25°C
A
T
= +125°C
= –55°C
A
6
T
4
A
2
0
100
1k
LOAD RESISTANCE (Ω)
0
5
10
SUPPLY VOLTAGE (V)
15
Figure 29. Supply Current vs. Supply Voltage
Figure 26. Maximum Output Voltage Swing vs. Load Resistance
Rev. H | Page 10 of 20
Data Sheet
OP249
180
10k
1k
100
10
1
T
V
= 25°C
= ±15V
A
V
V
= ±15V
S
160
140
120
100
80
S
= 0V
CM
415 × OP249
(830 OP AMPS)
60
40
20
0
–1000 –800 –600 –400 –200
0
200 400 600 800 1000
–75
–50
–25
0
25
50
75
100
125
V
(µV)
TEMPERATURE (°C)
OS
Figure 30. VOS Distribution (N-8)
Figure 33. Input Bias Current vs. Temperature
300
270
240
210
180
150
120
90
4
3
2
1
10
10
10
10
10
T
V
= 25°C
= ±15V
A
V
= ±15V
S
S
–40°C TO +85°C
(830 OP AMPS)
60
30
0
0
0
2
4
6
8
10 12 14 16 18 20 22 24
TCV (µV/°C)
–15
–10
–5
0
5
10
15
OS
COMMON-MODE VOLTAGE (V)
Figure 31. TCVOS Distribution (N-8)
Figure 34. Bias Current vs. Common-Mode Voltage
50
40
30
20
10
0
50
T
V
= 25°C
= ±15V
A
V
= ±15V
S
S
40
30
20
10
0
0
1
2
3
4
5
0
2
4
6
8
10
TIME AFTER POWER APPLIED (Minutes)
TIME AFTER POWER APPLIED (Minutes)
Figure 32. Offset Voltage Warm-Up Drift
Figure 35. Bias Current Warm-Up Drift
Rev. H | Page 11 of 20
OP249
Data Sheet
80
80
60
40
20
0
T
V
= 25°C
V
= ±15V
A
S
= 0V
CM
SOURCE
60
40
20
0
SINK
–75
–50
–25
0
25
50
75
100
125
–75
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 36. Input Offset Current vs. Temperature
Figure 38. Short-Circuit Output Current vs. Junction Temperature
12000
10000
8000
6000
4000
2000
0
V
= ±15V
S
R
R
= 10kΩ
= 2kΩ
L
L
–75
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 37. Open-Loop Gain vs. Temperature
Rev. H | Page 12 of 20
Data Sheet
OP249
APPLICATIONS INFORMATION
V+
+IN
100
90
V
OUT
–IN
10
0%
5V
1µs
A) OP249
100
90
V–
Figure 39. Simplified Schematic (1/2 OP249)
10
0%
2
5V
1µs
1/2
OP249
1
B) LT1057
3
+3V
5kΩ
Figure 41. Large-Signal Transient Response,
AV = 1, VIN = 20 V p-p, ZL = 2 kΩ//200 pF, VS = 15 V
The OP249 was carefully designed to provide symmetrically
matched slew characteristics in both the negative and positive
directions, even when driving a large output load.
+18V
6
5
8
1/2
OP249
7
The slewing limitation of the amplifier determines the maximum
frequency at which a sinusoidal output can be obtained without
significant distortion. However, it is important to note that the
nonsymmetric slewing typical of previously available JFET
amplifiers adds a higher series of harmonic energy content to
the resulting response—and an additional dc output component.
Examples of potential problems of nonsymmetric slewing behavior
can be in audio amplifier applications, where a natural low dis-
tortion sound quality is desired and in servo or signal processing
systems where a net dc offset cannot be tolerated. The linear
and symmetric slewing feature of the OP249 makes it an ideal
choice for applications that exceed the full power bandwidth
range of the amplifier.
4
+3V
5kΩ
–18V
Figure 40. Burn-In Circuit
The OP249 represents a reliable JFET amplifier design,
featuring an excellent combination of dc precision and high
speed. A rugged output stage provides the ability to drive a
600 Ω load and still maintain a clean ac response. The OP249
features a large signal response that is more linear and symmetric
than previously available JFET input amplifiers. Figure 41
compares the large signal response of the OP249 to other
industry-standard dual JFET amplifiers.
Typically, the slewing performance of the JFET amplifier is
specified as a number of V/µs. There is no discussion on the
quality, that is, linearity and symmetry of the slewing response.
Rev. H | Page 13 of 20
OP249
Data Sheet
R4
+V
R3
V
IN
100
90
1/2
OP249
V
OUT
R1
200kΩ
R5
50kΩ
R2
31Ω
R2
R1
V
ADJUST RANGE = ±V
OS
–V
Figure 44. Offset Adjustment for Inverting Amplifier Configuration
+V
10
R5
0%
R1
200kΩ
R4
R3
50kΩ
50mV
1µs
1/2
V
R2
33Ω
OUT
OP249
Figure 42. Small-Signal Transient Response,
AV = 1, ZL = 2 kΩ||100 pF, No Compensation, VS = 15 V
–V
R2
R1
V
ADJUST RANGE = ±V
OS
GAIN =
R5
V
IN
As with most JFET input amplifiers, the output of the OP249
can undergo phase inversion if either input exceeds the specified
input voltage range. Phase inversion does not damage the
amplifier, nor does it cause an internal latch-up condition.
V
OUT
R5
R4 + R2
= 1 +
V
IN
1 +
IF R2 << R4
=
R4
Figure 45. Offset Adjustment for Noninverting Amplifier Configuration
Supply decoupling should be used to overcome inductance and
resistance associated with supply lines to the amplifier. A 0.1 µF
and a 10 µF capacitor should be placed between each supply pin
and ground.
In Figure 44, the offset adjustment is made by supplying a small
voltage at the noninverting input of the amplifier. Resistors R1
and R2 attenuate the potentiometer voltage, providing a 2.5 mV
(with VS = 15 V) adjustment range, referred to the input.
Figure 45 shows the offset adjustment for the noninverting
amplifier configuration, also providing a 2.5 mV adjustment
range. As shown in the equations in Figure 45, if R4 is not much
greater than R2, a resulting closed-loop gain error must be
accounted for.
OPEN-LOOP GAIN LINEARITY
The OP249 has both an extremely high open-loop gain of
1 kV/mV minimum and constant gain linearity, which enhances its
dc precision and provides superb accuracy in high closed-loop
gain applications. Figure 43 illustrates the typical open-loop
gain linearity—high gain accuracy is assured, even when
driving a 600 Ω load.
SETTLING TIME
The settling time is the time between when the input signal begins
to change and when the output permanently enters a prescribed
error band. The error bands on the output are 5 mV and 0.5 m V,
respectively, for 0.1% and 0.01% accuracy.
OFFSET VOLTAGE ADJUSTMENT
The inherent low offset voltage of the OP249 makes offset
adjustments unnecessary in most applications. However, where
a lower offset error is required, balancing can be performed
with simple external circuitry, as shown in Figure 44 and Figure 45.
Figure 46 shows the settling time of the OP249, which is typically
870 ns. Moreover, problems in settling response, such as thermal
tails and long-term ringing, are nonexistent.
VERTICAL 50µV/DIV
INPUT VARIATION
870ns
100
90
10
0%
10mV
500ns
HORIZONTAL 5V/DIV
OUTPUT CHARGE
Figure 46. Settling Characteristics of the OP249 to 0.01%
Figure 43. Open-Loop Gain Linearity; Variation in Open-Loop Gain Results in
Errors in High Closed-Loop Gain Circuits; RL = 600 Ω, VS = 15 V
Rev. H | Page 14 of 20
Data Sheet
OP249
Because the DAC output capacitance appears at the inputs of
DAC OUTPUT AMPLIFIER
the op amp, it is essential that the amplifier be adequately
compensated. Compensation increases the phase margin and
ensures an optimal overall settling response. The required lead
compensation is achieved with Capacitor C in Figure 48.
Unity-gain stability, a low offset voltage of 300 μV typical, and a
fast settling time of 870 ns to 0.01%, makes the OP249 an ideal
amplifier for fast DACs.
For CMOS DAC applications, the low offset voltage of the OP249
results in excellent linearity performance. CMOS DACs, such as
the PM7545, typically have a code-dependent output resistance
variation between 11 kΩ and 33 kΩ. The change in output
resistance, in conjunction with the 11 kΩ feedback resistor, results
in a noise gain change, which causes variations in the offset
error, increasing linearity errors. The OP249 features low offset
voltage error, minimizing this effect and maintaining 12-bit
linearity performance over the full-scale range of the converter.
V
DD
75Ω
0.1µF
C
+15V
33pF
0.1µF
18
20
V
R
DD
FB
OUT
1
2
2
8
1
REFERENCE
1/2
19
V
V
PM7545
1
REF
OUT
OR V
OP249
IN
500Ω
3
AGND
4
0.1µF
DGND
3
DB TO DB
11
0
–15V
12
DATA INPUT
Figure 47. Fast Settling and Low Offset Error of the OP249 Enhances CMOS DAC Performance—Unipolar Operation
R4
20kΩ
1%
V
DD
R5
10kΩ
1%
75Ω
0.1µF
C
+15V
33pF
18
20
0.1µF
1
V
R
DD
R3
10kΩ
1%
FB
8
1
2
2
OUT
1
1/2
OP249
REFERENCE
19
V
5
6
PM7545
REF
OR V
IN
500Ω
1/2
OP249
3
AGND
V
7
OUT
DGND
DB TO DB
0.1µF
4
11
0
3
12
DATA INPUT
–15V
Figure 48. Fast Settling and Low Offset Error of the OP249 Enhances CMOS DAC Performance—Bipolar Operation
Rev. H | Page 15 of 20
OP249
Data Sheet
A
B
4µs
4µs
100
90
100
90
10
10
0%
0%
500mV
1µs
C = 5pF
500mV
1µs
C = 15pF
RESPONSE IS GROSSLY UNDERDAMPED,
AND EXHIBITS RINGING
FAST RISE TIME CHARACTERISTICS, BUT AT EXPENSE
OF SLIGHT PEAKING IN RESPONSE
Figure 49. Effect of Altering Compensation from Circuit in Figure 47—PM7545 CMOS DAC with 1/2 OP249, Unipolar Operation;
Critically Damped Response Is Obtained with C ≈ 33 pF
+15V
0.1µF
Figure 49 illustrates the effect of altering the compensation on
the output response of the circuit in Figure 47. Compensation is
required to address the combined effect of the output capacitance
of the DAC, the input capacitance of the op amp, and any stray
capacitance. Slight adjustments to the compensation capacitor may
be required to optimize settling response for any given application.
8
3
2
1/2
1
7A13 PLUG-IN
7A13 PLUG-IN
OP249
4
0.1µF
*
–15V
The settling time of the combination of the current output DAC
and the op amp can be approximated by
1kΩ
300pF
|V
REF
1kΩ
|
ΔI
=
OUT
+15V
2
2
tS TOTAL =
(
tS DAC
)
+
(
tS AMP
)
1.5kΩ
2N3904
10µF
TTL INPUT
The actual overall settling time is affected by the noise gain of
the amplifier, the applied compensation, and the equivalent
input capacitance at the input of the amplifier.
1N4148
2N2907
1kΩ
1.8kΩ
+15V
220Ω
0.47µF
0.01µF
DISCUSSION ON DRIVING ADCs
0.1µF
*
Settling characteristics of op amps also include the ability of the
amplifier to recover, that is, settle, from a transient current output
load condition. An example of this includes an op amp driving
the input from a SAR-type ADC. Although the comparison
point of the converter is usually diode clamped, the input swing
of plus-and-minus a diode drop still gives rise to a significant
modulation of input current. If the closed-loop output impedance
is low enough and bandwidth of the amplifier is sufficiently
large, the output settles before the converter makes a comparison
decision, which prevents linearity errors or missing codes.
V
REF
*DECOUPLE CLOSE TOGETHER ON GROUND
PLANE WITH SHORT LEAD LENGTHS.
Figure 50. Transient Output Impedance Test Fixture
As seen in Figure 51, the OP249 has an extremely fast recovery
of 247 ns (to 0.01%) for a 1 mA load transient. The performance
makes it an ideal amplifier for data acquisition systems.
247.4ns
100
90
Figure 50 shows a settling measurement circuit for evaluating
recovery from an output current transient. An output disturbing
current generator provides the transient change in output load
current of 1 mA.
10
0%
2mV
2V
100ns
Figure 51. Transient Recovery Time of the OP249 from
a 1 mA Load Transient to 0.01%
Rev. H | Page 16 of 20
Data Sheet
OP249
OUTLINE DIMENSIONS
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
8
1
5
4
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
PLANE
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 52. 8-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-8)
Dimensions shown in inches and (millimeters)
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 53. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
Rev. H | Page 17 of 20
OP249
Data Sheet
0.005 (0.13)
MIN
0.055 (1.40)
MAX
8
5
0.310 (7.87)
0.220 (5.59)
1
4
0.100 (2.54) BSC
0.405 (10.29) MAX
0.320 (8.13)
0.290 (7.37)
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
MAX
0.150 (3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.023 (0.58)
0.014 (0.36)
15°
0°
0.070 (1.78)
0.030 (0.76)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 54. 8-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-8)
Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Model1
OP249AZ
OP249FZ
OP249GP
Temperature Range
Package Description
8-Lead CERDIP
8-Lead CERDIP
8-Lead PDIP
Package Option
−55°C to +125°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Q-8
Q-8
N-8
N-8
R-8
R-8
R-8
R-8
R-8
R-8
OP249GPZ
OP249GS
8-Lead PDIP
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
OP249GS-REEL
OP249GS-REEL7
OP249GSZ
OP249GSZ-REEL
OP249GSZ-REEL7
1 Z = RoHS Compliant Part.
For military processed devices, see the standard microcircuit drawings (SMD) available at www.dscc.dla.mil/programs/milspec/default.asp.
Table 7.
SMD Part Number
5962-9151901M2A
5962-9151901MPA
Analog Devices, Inc. Equivalent
OP249ARCMDA
OP249AZMDA
Rev. H | Page 18 of 20
Data Sheet
NOTES
OP249
Rev. H | Page 19 of 20
OP249
NOTES
Data Sheet
©1989–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00296-0-11/13(H)
Rev. H | Page 20 of 20
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