OP482GPZ [ADI]
Dual/Quad, Low Power, High Speed JFET Operational Amplifiers; 双/四路，低功耗，高速JFET运算放大器
| 型号： | OP482GPZ |
| 厂家： | 
ADI |
| 描述： | Dual/Quad, Low Power, High Speed JFET Operational Amplifiers |
| 文件： | 总16页 (文件大小：317K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual/Quad, Low Power, High Speed
JFET Operational Amplifiers
Data Sheet
OP282/OP482
FEATURES
PIN CONNECTIONS
High slew rate: 9 V/µs
Wide bandwidth: 4 MHz
Low supply current: 250 µA/amplifier maximum
Low offset voltage: 3 mV maximum
Low bias current: 100 pA maximum
Fast settling time
OUT A
–IN A
+IN A
V–
1
2
3
4
8
7
6
5
V+
OUT B
–IN B
OP282
+IN B
Figure 1. 8-Lead, Narrow-Body SOIC (S-Suffix) [R-8]
Common-mode range includes V+
Unity-gain stable
14-ball wafer level chip scale for quad
OUT A
–IN A
+IN A
V–
1
2
3
4
8
7
6
5
V+
OP282
OUT B
–IN B
+IN B
TOP VIEW
(Not to Scale)
APPLICATIONS
Figure 2. 8-Lead MSOP [RM-8]
Active filters
Fast amplifiers
Integrators
Supply current monitoring
1
2
3
4
5
6
7
14 OUT D
OUT A
–IN A
+IN A
V+
–IN D
+IN D
13
12
– +
+
–
GENERAL DESCRIPTION
OP482
11 V–
The OP282/OP482 dual and quad operational amplifiers feature
excellent speed at exceptionally low supply currents. The slew
rate is typically 9 V/µs with a supply current of less than 250 µA
per amplifier. These unity-gain stable amplifiers have a typical
gain bandwidth of 4 MHz.
+IN C
+IN B
10
9
– +
+
–
–IN C
–IN B
OUT B
OUT C
8
Figure 3. 14-Lead PDIP (P-Suffix) [N-14]
The JFET input stage of the OP282/OP482 ensures that the bias
current is typically a few picoamps and is less than 500 pA over
the full temperature range. The offset voltage is less than 3 mV
for the dual amplifier and less than 4 mV for the quad amplifier.
OUT A
–IN A
+IN A
V+
OUT D
–IN D
+IN D
1
2
3
4
5
6
7
14
13
12
11
10
9
V–
OP482
With a wide output swing (within 1.5 V of each supply), low
power consumption, and high slew rate, the OP282/OP482 are
ideal for battery-powered systems or power-restricted applica-
tions. An input common-mode range that includes the positive
supply makes the OP282/OP482 an excellent choice for high-
side signal conditioning.
+IN C
+IN B
–IN B
OUT B
–IN C
OUT C
8
Figure 4. 14-Lead, Narrow-Body SOIC (S-Suffix) [R-14]
BALL A1 CORNER
1
2
3
The OP282/OP482 are specified over the extended industrial
temperature range. The OP282 is available in the standard
8-lead, narrow SOIC and MSOP packages. The OP482 is
available in the PDIP and narrow SOIC packages, as well as
a 14-ball WLCSP.
OUT D
OUT A
–IN D
A
B
C
D
E
F
+IN D
V–
–IN A
V+
+IN A
+IN B
–IN C
+IN C
OUT C
–IN B
OUT B
G
H
J
TOP VIEW (BALL SIDE DOWN)
Not to Scale
Figure 5. 14-Ball WLCSP [CB-14-2]
Rev. I
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©1991–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
OP282/OP482
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................4
Typical Performance Characteristics ..............................................5
Applications Information.............................................................. 12
High-Side Signal Conditioning ................................................ 12
Phase Inversion........................................................................... 12
Active Filters ............................................................................... 12
Programmable State Variable Filter ......................................... 13
Outline Dimensions....................................................................... 14
Ordering Guide .......................................................................... 16
Applications....................................................................................... 1
General Description......................................................................... 1
Pin Connections ............................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics............................................................. 3
Absolute Maximum Ratings............................................................ 4
Thermal Resistance ...................................................................... 4
REVISION HISTORY
9/13—Rev. H to Rev. I
Added Figure 5 through Figure 20; Renumbered
Successive Figures..............................................................................5
Updated Figure 21 and Figure 22....................................................7
Updated Figure 23 and Figure 27....................................................8
Updated Figure 29 .............................................................................9
Updated Figure 35 and Figure 36................................................. 10
Updated Figure 43 .......................................................................... 11
Changes to Applications Information ......................................... 12
Changes to Figure 44...................................................................... 12
Deleted OP282/OP482 Spice Macro Model Section ....................9
Deleted Figure 4.................................................................................9
Deleted OP282 Spice Marco Model............................................. 10
Updated Outline Dimensions....................................................... 14
Changes to Ordering Guide.......................................................... 14
Changes to Figure 5.......................................................................... 1
Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 16
9/10—Rev. G to Rev. H
Added WLCSP....................................................................Universal
Changes to Features Section............................................................ 1
Changes to General Description Section ...................................... 1
Added Figure 5; Renumbered Sequentially .................................. 1
Changes to Large-Signal Voltage Gain Parameter, Table 1 ......... 3
Changes to Table 2, Thermal Resistance Section, and Table 3 ... 4
Change to Figure 30 ......................................................................... 9
Added Figure 53.............................................................................. 16
Changes to Ordering Guide .......................................................... 16
10/02—Rev. D to Rev. E
7/08—Rev. F to Rev. G
Edits to 8-Lead Epoxy DIP (P-Suffix) Pin......................................1
Edits to Ordering Guide ...................................................................3
Edits to Outline Dimensions......................................................... 11
Changes to Phase Inversion Section ............................................ 12
Deleted Figure 45............................................................................ 12
Added Figure 45 and Figure 46..................................................... 12
Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 16
9/02—Rev. C to Rev. D
Edits to 14-Lead SOIC (S-Suffix) Pin .............................................1
Replaced 8-Lead SOIC (S-Suffix)................................................. 11
10/04—Rev. E to Rev. F
4/02—Rev. B to Rev. C
Deleted 8-Lead PDIP .........................................................Universal
Added 8-Lead MSOP .........................................................Universal
Changes to Format and Layout.........................................Universal
Changes to Features.......................................................................... 1
Changes to Pin Configurations....................................................... 1
Changes to General Description .................................................... 1
Changes to Specifications................................................................ 3
Changes to Absolute Maximum Ratings ....................................... 4
Changes to Table 3............................................................................ 4
Wafer Test Limits Deleted ................................................................2
Edits to Absolute Maximum Ratings..............................................3
Dice Characteristics Deleted............................................................3
Edits to Ordering Guide ...................................................................3
Edits to Figure 1.................................................................................7
Edits to Figure 3.................................................................................8
20-Position Chip Carrier (RC Suffix) Deleted ........................... 11
Rev. I | Page 2 of 16
Data Sheet
OP282/OP482
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
At VS = 15.0 V, TA = 25°C, unless otherwise noted; applies to both A and G grades.
Table 1.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
0.2
0.2
3
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
OP282
3
4.5
4
mV
mV
mV
mV
pA
pA
pA
pA
V
OP282, −40°C ≤ TA ≤ +85°C
OP482
OP482, −40°C ≤ TA ≤ +85°C
VCM = 0 V
VCM = 0 V1
6
Input Bias Current
IB
100
500
50
250
+15
Input Offset Current
IOS
VCM = 0 V
VCM = 0 V1
1
Input Voltage Range
Common-Mode Rejection Ratio
Large-Signal Voltage Gain
−11
70
20
CMRR
AVO
−11 V ≤ VCM ≤ +15 V, −40°C ≤ TA ≤ +85°C
RL = 10 kΩ, VO = 13.5 V
RL = 10 kΩ, −40°C ≤ TA ≤ +85°C
90
dB
V/mV
V/mV
µV/°C
pA/°C
15
Offset Voltage Drift
Bias Current Drift
ΔVOS/ΔT
ΔIB/ΔT
10
8
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Short-Circuit Limit
VOH
VOL
ISC
RL = 10 kΩ
RL = 10 kΩ
Source
Sink
f = 1 MHz
13.5
3
13.9
−13.9
10
−12
200
V
V
mA
mA
Ω
−13.5
−8
Open-Loop Output Impedance
POWER SUPPLY
ZOUT
Power Supply Rejection Ratio
Supply Current/Amplifier
Supply Voltage Range
DYNAMIC PERFORMANCE
Slew Rate
Full-Power Bandwidth
Settling Time
Gain Bandwidth Product
Phase Margin
PSRR
ISY
VS
VS = 4.5 V to 18 V, −40°C ≤ TA ≤ +85°C
VO = 0 V, −40°C ≤ TA ≤ 85°C
25
210
316
250
18
µV/V
µA
V
4.5
7
SR
BWP
tS
GBP
ØM
RL = 10 kΩ
1% distortion
To 0.01%
9
V/µs
kHz
µs
MHz
Degrees
125
1.6
4
55
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
en p-p
en
in
0.1 Hz to 10 Hz
f = 1 kHz
1.3
36
0.01
µV p-p
nV/√Hz
pA/√Hz
1 The input bias and offset currents are characterized at TA = TJ = 85°C. Bias and offset currents are guaranteed but not tested at −40°C.
Rev. I | Page 3 of 16
OP282/OP482
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 2.
THERMAL RESISTANCE
Parameter
Rating
θJA is specified for the worst-case conditions, that is, a device in
socket for PDIP. θJA is specified for a device soldered in the circuit
board for SOIC_N, MSOP, and WLCSP packages. This was
measured using a standard 4-layer board.
Supply Voltage
Input Voltage
18 V
18 V
36 V
Indefinite
−65°C to +150°C
−40°C to +85°C
−65°C to +150°C
300°C
Differential Input Voltage1
Output Short-Circuit Duration
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature (Soldering 60 sec)
Table 3.
Package Type
θJA
142
120
83
112
70
θJC
45
45
39
35
16
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
8-Lead MSOP [RM]
8-Lead SOIC_N (S-Suffix) [R]
14-Lead PDIP (P-Suffix) [N]
14-Lead SOIC_N (S-Suffix) [R]
14-Ball WLCSP [CB]1, 2
1 For supply voltages less than 18 V, the absolute maximum input voltage is
equal to the supply voltage.
1 Simulated thermal numbers per JESD51-9.
2 Junction-to-board thermal resistance.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. I | Page 4 of 16
Data Sheet
OP282/OP482
TYPICAL PERFORMANCE CHARACTERISTICS
80
60
70
60
180
135
90
V
= ±15V
= 25°C
V
= ±15V
T = 25°C
A
S
S
T
A
50
A
A
= 100
VCL
40
40
30
= 10
VCL
20
45
20
10
A
= 1
VCL
0
0
0
–10
–20
–30
–45
–20
–90
10M
–40
1k
10k
100k
1M
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 6. OP282 Open-Loop Gain and Phase vs. Frequency
Figure 9. OP282 Closed-Loop Gain vs. Frequency
45
30
25
20
15
10
5
V
R
= ±15V
= 10kΩ
V
= ±15V
= 10kΩ
= 50pF
S
L
S
R
L
40
35
30
25
20
15
10
5
C
L
–SR
+SR
0
0
–75
–50
–25
0
25
50
75
100
125
–75
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 7. OP282 Open-Loop Gain vs. Temperature
Figure 10. OP282 Slew Rate vs. Temperature
80
70
60
50
40
30
20
10
0
1000
100
10
V
V
= ±15V
= 0V
V
R
V
A
= ±15V
= 2kΩ
S
S
CM
L
= 100mV p-p
IN
= 1
VCL
= 25°C
T
A
+OS
–OS
1
0.1
0
100
200
300
400
500
–75
–50
–25
0
25
50
75
100
125
LOAD CAPACITANCE (pF)
TEMPERATURE (°C)
Figure 8. OP282 Small-Signal Overshoot vs. Load Capacitance
Figure 11. OP282 Input Bias Current vs. Temperature
Rev. I | Page 5 of 16
OP282/OP482
Data Sheet
1000
20
15
T
R
= 25°C
= 10kΩ
V
T
= ±15V
= 25°C
A
S
L
A
V
OH
10
100
10
5
0
–5
–10
–15
–20
V
OL
1
10
0
±5
±10
SUPPLY VOLTAGE (V)
±15
±20
100
FREQUENCY (Hz)
1k
10k
Figure 12. OP282 Voltage Noise Density vs. Frequency
Figure 15. OP282 Output Voltage Swing vs. Supply Voltage
1000
100
10
1000
100
10
V
T
= ±15V
= 25°C
V
T
= ±15V
= 25°C
S
S
A
A
A
= 100
VCL
VCL
A
= 10
= 1
1
1
A
VCL
0.1
0.1
100
–15
–10
–5
0
5
10
15
1k
10k
100k
1M
COMMON-MODE VOLTAGE (V)
FREQUENCY (Hz)
Figure 13. OP282 Input Bias Current vs. Common-Mode Voltage
Figure 16. OP282 Closed-Loop Output Impedance vs. Frequency
480
480
475
470
465
460
455
450
T
= 25°C
A
475
470
465
460
455
450
0
±5
±10
±15
±20
–50
–25
0
25
50
75
100
125
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
Figure 14. OP282 Supply Current vs. Supply Voltage
Figure 17. OP282 Supply Current vs. Temperature
Rev. I | Page 6 of 16
Data Sheet
OP282/OP482
16
30
25
20
15
10
5
V
T
= ±15V
= 25°C
V
T
R
= ±15V
= 25°C
= 10kΩ
= 1
S
S
A
A
14
12
10
8
L
V
A
OL
VCL
V
OH
6
4
2
0
100
0
100
1k
LOAD RESISTANCE (Ω)
10k
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 18. OP282 Absolute Output Voltage vs. Load Resistance
Figure 21. OP282 Maximum Output Swing vs. Frequency
140
140
V
T
= ±15V
= 25°C
V
= ±15V
T = 25°C
A
S
S
A
120
100
80
120
100
80
+PSRR
60
60
40
40
20
20
–PSRR
0
0
–20
–40
–60
–20
–40
–60
100
1k
10k
100k
1M
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 19. OP282 PSRR vs. Frequency
Figure 22. OP282 CMRR vs. Frequency
14
12
10
8
200
160
120
80
V
T
= ±15V
= 25°C
V
S
= ±15V
= 25°C
S
T
A
A
300 × OP282
(600 OP AMPS)
SINK
SOURCE
6
4
40
2
0
0
–50
–25
0
25
50
75
100
125
–2000
–1200
–400
0
400
(µV)
1200
2000
TEMPERATURE (°C)
V
OS
Figure 20. OP282 Short-Circuit Current vs. Temperature
Figure 23. OP282 VOS Distribution, SOIC_N Package
Rev. I | Page 7 of 16
OP282/OP482
Data Sheet
70
60
50
40
30
20
10
0
400
360
320
280
240
200
160
120
80
A
= 1
V
= ±15V
VCL
NEGATIVE EDGE
S
V
R
= ±15V
= 2kΩ
= 100mV p-p
S
300 × OP282
(600 OP AMPS)
L
V
IN
A
= 1
VCL
POSITIVE EDGE
40
0
0
4
8
12
16
20
24
28
32
36
300
LOAD CAPACITANCE (pF)
0
100
200
400
500
TCV (µV/°C)
OS
Figure 24. OP282 TCVOS Distribution, SOIC_N Package
Figure 27. OP482 Small-Signal Overshoot vs. Load Capacitance
80
60
40
20
0
60
0
V
T
= ±15V
= 25°C
V
T
= ±15V
= 25°C
S
S
A
A
50
40
A
VCL
= 100
= 10
= 1
45
30
90
A
VCL
20
135
180
10
A
VCL
0
–10
–20
1k
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 25. OP482 Open-Loop Gain and Phase vs. Frequency
Figure 28. OP482 Closed-Loop Gain vs. Frequency
35
25
20
15
10
5
–SR
V
R
= ±15V
= 10kΩ
S
L
30
25
20
15
10
5
V
R
C
= ±15V
= 10kΩ
= 50pF
S
L
L
+SR
0
–75
0
–75
–50
–25
0
25
50
C)
75
100
125
–50
–25
0
25
50
75
100
125
TEMPERATURE (
°
TEMPERATURE (°C)
Figure 26. OP482 Open-Loop Gain vs. Temperature
Figure 29. OP482 Slew Rate vs. Temperature
Rev. I | Page 8 of 16
Data Sheet
OP282/OP482
1000
1000
100
10
V
T
= ±15V
= 25°C
V
V
= ±15V
S
S
= 0V
A
CM
100
10
1.0
0.1
1
0.1
–75
–50
–25
0
25
50
75
100
125
–15
–10
–5
0
5
10
15
TEMPERATURE (°C)
COMMON-MODE VOLTAGE (V)
Figure 33. OP482 Input Bias Current vs. Common-Mode Voltage
Figure 30. OP482 Input Bias Current vs. Temperature
1.15
60
55
50
45
40
5.0
4.5
4.0
3.5
3.0
T
= 25°C
V
R
= ±15V
= 10kΩ
A
S
L
1.10
1.05
1.00
0.95
0.90
0.85
GBW
Ø
M
0
±5
±10
±15
±20
–75
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
Figure 31. OP482 Phase Margin and Gain Bandwidth Product vs.
Temperature
Figure 34. OP482 Relative Supply Current vs. Supply Voltage
80
20
R
T
= 10kΩ
= 25°C
V
T
= ±15V
= 25°C
L
S
A
A
70
60
50
40
30
20
10
0
15
10
5
0
–5
–10
–15
–20
10
100
FREQUENCY (Hz)
1k
10k
0
±5
±10
±15
±20
SUPPLY VOLTAGE (V)
Figure 32. OP482 Voltage Noise Density vs. Frequency
Figure 35. OP482 Output Voltage Swing vs. Supply Voltage
Rev. I | Page 9 of 16
OP282/OP482
Data Sheet
600
500
400
300
200
100
0
100
80
60
40
20
0
V
T
= ±15V
= 25°C
V = ±15V
S
V = 100mV
S
+PSRR
–PSRR
Δ
A
T
= 25°C
A
A
= 100
VCL
A
= 10
VCL
A
= 1
VCL
20
100
1k
10k
FREQUENCY (Hz)
100k
1M
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 39. OP482 Power Supply Rejection Ratio (PSRR) vs. Frequency
Figure 36. OP482 Closed-Loop Output Impedance vs. Frequency
20
1.20
V
= ±15V
V
= ±15V
S
S
SINK
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
15
10
5
SOURCE
0
–75
–50
–25
0
25
50
C)
75
100
125
–75
–50
–25
0
25
50
C)
75
100
125
TEMPERATURE (
°
TEMPERATURE (
°
Figure 37. OP482 Relative Supply Current vs. Temperature
Figure 40. OP482 Short-Circuit Current vs. Temperature
16
14
12
10
8
30
V
T
= ±15V
= 25°C
V
T
A
= ±15V
= 25°C
S
S
A
A
= 1
VCL
= 10kΩ
25
R
L
POSITIVE
SWING
20
15
10
5
NEGATIVE
SWING
6
4
2
0
100
0
1k
10k
10k
100k
FREQUENCY (Hz)
1M
1k
LOAD RESISTANCE (Ω)
Figure 41. OP482 Maximum Output Swing vs. Frequency
Figure 38. OP482 Maximum Output Voltage vs. Load Resistance
Rev. I | Page 10 of 16
Data Sheet
OP282/OP482
100
80
60
40
20
0
320
280
240
200
160
120
80
V
= ±15V
= 25°C
S
40
T
A
V
= 100mV
CM
0
–20
100
1k
10k
100k
1M
0
4
8
12
16
OS
20
24
28
32
TCV (µV/°C)
FREQUENCY (Hz)
Figure 42. OP482 Common-Mode Rejection Ratio (CMRR) vs. Frequency
Figure 44. OP482 TCVOS Distribution, PDIP Package
700
V
= ±15V
= 25°C
S
T
A
600
500
400
300
200
100
0
300 × OP482
(1200 OP AMPS)
–2000 –1600 –1200 –800 –400
0
400 800 1200 1600 2000
V
(µV)
OS
Figure 43. OP482 VOS Distribution, PDIP Package
Rev. I | Page 11 of 16
OP282/OP482
Data Sheet
APPLICATIONS INFORMATION
The OP282 and OP482 are dual and quad JFET op amps that
are optimized for high speed at low power. This combination
makes these amplifiers excellent choices for battery-powered or
low power applications that require above average performance.
Applications benefiting from this performance combination
include telecommunications, geophysical exploration, portable
medical equipment, and navigational instrumentation.
amp against phase reversal. R1, D2, and D3 limit the input
current when the input exceeds the supply rail. The resistor
should be selected to limit the amount of input current below
the absolute maximum rating.
V+
D2
R1
OP282/
OP482
IN5711
10kΩ
V
IN
D1
IN5711
V+
V–
HIGH-SIDE SIGNAL CONDITIONING
V
OUT
D3
IN5711
Many applications require the sensing of signals near the positive
rail. OP282 and OP482 were tested and are guaranteed over a
common-mode range (−11 V ≤ VCM ≤ +15 V) that includes the
positive supply.
V–
Figure 46. Phase Reversal Solution Circuit
One application where such sensing is commonly used is in the
sensing of power supply currents. Therefore, the OP282/OP482
can be used in current sensing applications, such as the partial
circuit shown in Figure 45. In this circuit, the voltage drop across
a low value resistor, such as the 0.1 Ω shown here, is amplified
and compared to 7.5 V. The output can then be used for current
limiting.
V
= ±15V
S
15V
0.1Ω
2
500k
Ω
100k
Ω
R
L
V
OUT
100k
500k
Ω
1/2
OP282
V
IN
TIME (200µs/DIV)
Ω
Figure 47. No Phase Reversal
ACTIVE FILTERS
Figure 45. High-Side Signal Conditioning
The wide bandwidth and high slew rates of the OP282/OP482
make either one an excellent choice for many filter applications.
PHASE INVERSION
Most JFET input amplifiers invert the phase of the input signal
if either input exceeds the input common-mode range. For the
OP282/OP482, a negative signal in excess of 11 V causes phase
inversion. This is caused by saturation of the input stage, leading
to the forward-biasing of a gate-drain diode. Phase reversal in
the OP282/OP482 can be prevented by using Schottky diodes to
clamp the input terminals to each other and to the supplies. In
the simple buffer circuit shown in Figure 46, D1 protects the op
There are many active filter configurations, but the four most
popular configurations are Butterworth, elliptic, Bessel, and
Chebyshev. Each type has a response that is optimized for a
given characteristic, as shown in Table 4.
Table 4. Active Filter Configurations
Type
Selectivity
Moderate
Good
Best
Poor
Overshoot
Good
Moderate
Poor
Phase
Amplitude (Pass Band)
Maximum flat
Equal ripple
Amplitude (Stop Band)
Butterworth
Chebyshev
Elliptic
Nonlinear
Linear
Equal ripple
Equal ripple
Bessel (Thompson)
Best
Rev. I | Page 12 of 16
Data Sheet
OP282/OP482
This cutoff frequency can now be expressed as
PROGRAMMABLE STATE VARIABLE FILTER
1
D1
The circuit shown in Figure 48 can be used to accurately
program the Q, the cutoff frequency (fC), and the gain of a two-
pole state variable filter. OP482 devices have been used in this
design because of their high bandwidths, low power, and low
noise. This circuit takes only three packages to build because of
the quad configuration of the op amps and DACs.
fC
=
2πR1C1 256
where D1 is the digital code for the DAC.
The gain of this circuit is set by adjusting D3. The gain equation is
R4 D3
R5 256
Gain =
The DACs shown are used in the voltage mode; therefore, many
values are dependent on the accuracy of the DAC only and not
on the absolute values of the DAC’s resistive ladders. This
makes this circuit unusually accurate for a programmable filter.
DAC 2 is used to set the Q of the circuit. Adjusting this DAC
controls the amount of feedback from the band-pass node to
the input summing node. Note that the digital value of the
DAC is in the numerator; therefore, zero code is not a valid
operating point.
Adjusting DAC 1 changes the signal amplitude across R1; therefore,
the DAC attenuation times R1 determines the amount of signal
current that charges the integrating capacitor, C1.
R2 256
Q =
R3 D2
R7
2k
Ω
R4
2k
Ω
V
IN
C1
1000pF
R5
2k
1/4
Ω
1/4
DAC8408
OP482
1/4
C1
1000pF
R1
2k
OP482
1/4
Ω
1/4
DAC8408
OP482
1/4
R1
2k
OP482
1/4
Ω
1/4
DAC8408
OP482
1/4
OP482
HIGH PASS
LOW
PASS
BAND PASS
R6
2k
Ω
R3
2k
Ω
R2
2k
Ω
1/4
1/4
DAC8408
OP482
1/4
OP482
Figure 48. Programmable State Variable Filter
Rev. I | Page 13 of 16
OP282/OP482
Data Sheet
OUTLINE DIMENSIONS
3.20
3.00
2.80
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.80
0.55
0.40
0.15
0.05
0.23
0.09
6°
0°
0.40
0.25
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 49. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 50. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
S-Suffix (R-8)
Dimensions shown in millimeters and (inches)
Rev. I | Page 14 of 16
Data Sheet
OP282/OP482
0.775 (19.69)
0.750 (19.05)
0.735 (18.67)
14
1
8
7
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.110 (2.79)
0.015 (0.38)
GAUGE
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
PLANE
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.070 (1.78)
0.050 (1.27)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 51. 14-Lead Plastic Dual In-Line Package [PDIP]
P-Suffix (N-14)
Dimension shown in inches and (millimeters)
8.75 (0.3445)
8.55 (0.3366)
8
7
14
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
1.27 (0.0500)
0.50 (0.0197)
0.25 (0.0098)
45°
BSC
1.75 (0.0689)
1.35 (0.0531)
0.25 (0.0098)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
1.27 (0.0500)
0.40 (0.0157)
0.51 (0.0201)
0.31 (0.0122)
0.25 (0.0098)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012-AB
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 52. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
S-Suffix (R-14)
Dimensions shown in millimeters and (inches)
Rev. I | Page 15 of 16
OP282/OP482
Data Sheet
1.165
1.128
1.090
0.347
BSC
0.347
BSC
3
2
1
A
B
BALL A1
IDENTIFIER
0.20
BSC
C
D
2.160
2.123
2.085
1.60
REF
E
F
G
H
J
0.40
BSC
TOP VIEW
(BALL SIDE DOWN)
BOTTOM VIEW
(BALL SIDE UP)
0.694
REF
0.415
0.400
0.385
0.645
0.600
0.555
END VIEW
COPLANARITY
0.05
0.230
0.200
0.170
SEATING
PLANE
0.287
0.267
0.247
Figure 53. 14-Ball Wafer Level Chip Scale Package [WLCSP]
CB-14-2
Controlling dimensions are millimeters
ORDERING GUIDE
Model1
OP282ARMZ
OP282ARMZ-REEL
OP282GS
OP282GS-REEL
OP282GS-REEL7
OP282GSZ
OP282GSZ-REEL
OP282GSZ-REEL7
OP482ACBZ-RL
OP482ACBZ-R7
OP482GPZ
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
8-Lead MSOP
8-Lead MSOP
Package Option
RM-8
RM-8
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
CB-14-2
Branding
A0B
A0B
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
14-Ball WLCSP
14-Ball WLCSP
14-Lead PDIP
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N
A2J
A2J
CB-14-2
P-Suffix (N-14)
S-Suffix (R-14)
S-Suffix (R-14)
S-Suffix (R-14)
S-Suffix (R-14)
S-Suffix (R-14)
S-Suffix (R-14)
OP482GS
OP482GS-REEL
OP482GS-REEL7
OP482GSZ
OP482GSZ-REEL
OP482GSZ-REEL7
1 Z = RoHS Compliant Part.
©1991–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00301-0-9/13(I)
Rev. I | Page 16 of 16
相关型号：
©2020 ICPDF网 联系我们和版权申明