LTM4678Y [ADI]
Dual 25A or Single 50A μModule Regulator with Digital Power System Management;
| 型号： | LTM4678Y |
| 厂家： | 
ADI |
| 描述： | Dual 25A or Single 50A μModule Regulator with Digital Power System Management |
| 文件： | 总124页 (文件大小：6431K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTM4678
Dual 25A or Single 50A µModule Regulator
with Digital Power System Management
FEATURES
DESCRIPTION
The LTM®4678 is a dual 25A or single 50A step-down
µModule® (power module) DC/DC regulator featuring
remoteconfigurabilityandtelemetry-monitoringofpower
managementparametersoverPMBus—anopenstandard
n
Dual Digitally Adjustable Analog Loops with Digital
Interface for Control and Monitoring
Wide Input Voltage Range: 4.5V to 16V
Output Voltage Range: 0.5V to 3.3V
n
n
n
n
n
n
n
n
n
n
n
n
2
0.5% Maximum DC Output Error Over Temperature
5% Current Readback Accuracy
I C-based digital interface protocol . The LTM4678
is comprised of digitally programmable analog control
loops, precision mixed-signal circuitry, EEPROM, power
MOSFETs, inductors and supporting components.
Sub-Milliohm DCR Current Sensing
Integrated Input Current Sense Amplifier
2
400kHz PMBus-Compliant I C Serial Interface
The LTM4678’s 2-wire serial interface allows outputs to
be margined, tuned and ramped up and down at program-
mable slew rates with sequencing delay times. True input
currentsense,outputcurrentsandvoltages,outputpower,
temperatures,uptimeandpeakvaluesarereadable.Custom
configuration of the EEPROM contents is not required. At
start-up,outputvoltages,switchingfrequency,andchannel
phaseangleassignmentscanbesetbypin-strappingresis-
tors. The LTpowerPlay® GUI and DC1613 USB-to-PMBus
converter and demo kits are available.
Supports Telemetry Polling Rates up to 125Hz
Integrated 16-Bit ∆Σ ADC
Constant Frequency Current Mode Control
Parallel and Current Share Up to 250A
16mm × 16mm × 5.86mm CoP-BGA Package
Readable Data:
n
Input and Output Voltages, Currents, and Temperatures
n
Running Peak Values, Uptime, Faults and Warnings
n
Onboard EEPROM Fault Log Record
Writable Data and Configurable Parameters:
n
The LTM4678 is offered in a 16mm × 16mm × 5.86mm
CoP-BGA package available with SnPb or RoHS compliant
terminal finish.
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. Patents including 5408150, 5481178, 5705919, 5929620, 6144194, 6177787, 6580258,
7420359, 8163643. Licensed under U.S. Patent 7000125 and other related patents worldwide.
Output Voltage, Voltage Sequencing and Margining
n
Digital Soft-Start/Stop Ramp, Program Analog Loop
n
OV/UV/OT, UVLO, Frequency and Phasing
APPLICATIONS
n
System Optimization, Characterization and Data Min-
ing in Prototype, Production and Field Environments
TYPICAL APPLICATION
Dual 25A µModule Regulator with Digital
Interface for Control and Monitoring*
Using PMBus and LTpowerPlay to Monitor Telemetry and Margin
VOUT0/VOUT1 During Load Pattern Tests, 10Hz Polling Rate, 12VIN
ꢀ
ꢁꢂꢃ0
Output Voltage Readback, V
Margined 7.5% Low
Input Current Readback
OUT
ꢀꢁꢂꢃ ꢄꢅ ꢆꢇꢃ
ꢂ
ꢄꢅꢆꢂꢇꢃꢄꢈꢉꢊ
ꢂꢋ ꢃꢁ ꢌꢍꢄ
ꢀ
ꢀꢁꢀ
ꢀꢁꢂ
ꢀꢁꢂ
ꢃꢁ0
0ꢁꢄ
0
ꢊꢁꢋ
ꢃꢁꢂ
0ꢁꢌ
0
ꢀꢁRꢂꢃ
ꢄꢅꢆꢇ ꢈꢂ ꢆꢅꢉꢆ ꢊ
ꢋꢂꢌꢌꢍꢋꢈ
ꢁꢂꢃ0
ꢀꢁ
ꢄ
ꢀ
ꢁꢂꢃꢂ0
R
ꢀꢁꢂꢀꢁ
ꢀꢁ0
0ꢁꢂ
0ꢁꢉ
ꢀꢁꢉ
ꢀꢁꢊ
ꢀꢁꢋ
ꢀꢀꢁꢂ
ꢀꢁ
ꢀ00ꢁꢂ
ꢀꢁ
ꢀꢁꢂꢃ0
ꢂ
ꢀꢁ
ꢀ
ꢀ
ꢇ
ꢊ ꢏꢇ
ꢎꢌ
ꢎꢌ
ꢄ
ꢀ
ꢁꢂꢃꢂ0
ꢐꢌꢑ ꢎꢌꢈꢇ
ꢈꢂꢒꢍꢈꢓꢍRꢔ
ꢋꢋ
ꢁꢂꢃ
ꢀ
ꢁꢂꢃꢄ
ꢁꢂ0
ꢀ
ꢁꢂꢃꢄ
ꢅ
ꢅꢆꢇꢂꢈꢃꢅꢉꢊꢋ
ꢂꢌ ꢃꢁ ꢍꢎꢅ
ꢀ00ꢁꢂ
ꢀꢁ
ꢂꢃ
ꢀ
ꢁꢂꢃꢂꢄ
0
ꢌ
ꢋ
ꢂ
ꢀꢕ
ꢒꢋꢊꢉ ꢆꢓ0ꢀꢔ
0
ꢋ
ꢂ
ꢔ
ꢃꢀ
Rꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅꢆ
ꢆꢍꢎꢏ ꢇꢐꢏꢑꢈ
ꢍꢅꢎꢏ ꢇꢐꢏꢑꢉ
ꢊꢂꢒꢌ ꢍꢈ0ꢃꢓ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢀꢃꢃ ꢄꢀꢁꢅRꢀꢆ
ꢀꢁ
Rꢀꢁ0
FAULT0
ꢅ
ꢀ
ꢁꢂꢃꢂꢄ
Output Current Readback, Varying Load Pattern
Power Stage Temperature Readback
ꢀꢁ
ꢂ0
ꢁ
ꢀꢁ
ꢂ0
ꢁ
ꢀ0
ꢁꢂ
ꢁꢃ
ꢁꢐ
ꢀ0
ꢁꢂ
ꢁꢃ
ꢁꢐ
ꢀꢁꢂꢃꢄ ꢅꢆꢄꢇRRꢂꢈꢄꢉ
FAULT1
ꢀꢁꢂꢃ
ꢁ
ꢀ ꢂꢃꢄꢅꢆꢇꢈ ꢀꢃꢉ ꢊꢀꢋꢌ ꢍꢅꢆꢇꢈ
ꢂꢎꢅꢅꢏꢐꢑ ꢄꢒꢋ ꢋꢎꢃꢉRꢎꢅ
ꢀꢍꢅꢀ ꢎR ꢎꢋꢌꢒR ꢆꢎꢏRꢑ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄRꢅꢂꢆꢇꢈꢉꢆꢅꢂ ꢉꢆꢊꢋꢌꢍꢈꢀꢋ
RꢋꢎꢆꢀꢉꢋR ꢏRꢆꢉꢋ ꢐRꢅꢉꢋꢃꢉꢆꢅꢂ
ꢀꢁꢂRꢃꢄCLK
ꢀꢁ
ALERT
ꢅꢏꢐꢏꢓꢒꢅꢒꢐꢋ ꢂꢎꢐꢋRꢎꢔꢔꢒR
ꢀꢁꢂꢃ ꢀꢁꢂ
ꢀꢁꢂꢃ ꢄꢅ0ꢆꢇ
0
0
ꢈꢉꢊR ꢋꢊꢌꢍꢎꢏꢄꢏ ꢋꢐRꢋꢑꢐ ꢒ ꢓꢏꢏ ꢉꢐꢔꢑRꢏ ꢀꢁ
0
ꢊ
ꢋ
ꢔ
ꢂꢀ
0
ꢑ
ꢀ
ꢕ
ꢐꢖ
ꢆꢃꢌꢍ ꢇꢎꢍꢏꢉ
ꢐꢋꢑꢒ ꢆꢈ0ꢂꢓ
ꢊꢒꢋꢈ ꢍꢓꢈꢄꢏ
ꢃꢀꢂꢔ ꢊꢆ0ꢐe
Rev 0
1
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LTM4678
TABLE OF CONTENTS
Features..................................................... 1
Applications ................................................ 1
Typical Application ........................................ 1
Description.................................................. 1
Table of Contents .......................................... 2
Absolute Maximum Ratings.............................. 4
Order Information.......................................... 4
Pin Configuration .......................................... 4
Electrical Characteristics................................. 5
Typical Performance Characteristics ..................12
Pin Functions..............................................15
Simplified Block Diagram ...............................19
Decoupling Requirements...............................19
Functional Diagram ......................................20
Test Circuits ...............................................21
Operation...................................................23
Power Module Introduction .....................................23
Power Module Overview, Major Features..................23
EEPROM with ECC ...................................................24
Power-Up and Initialization ......................................25
Soft-Start .................................................................26
Time-Based Sequencing ..........................................26
Voltage-Based Sequencing ......................................26
Shutdown ................................................................27
Light-Load Current Operation ..................................27
Switching Frequency and Phase ...............................28
PWM Loop Compensation .......................................28
Output Voltage Sensing ...........................................28
Table 3. FSWPH_CFG Pin Strapping Look-Up
Table to Set the LTM4678’s Switching Frequency
and Channel Phase-Interleaving Angle (Not
Applicable if MFR_CONFIG_ALL[6] = 1b) ............32
Table 4. ASEL Pin Strapping Look-Up Table to
Set the LTM4678’s Slave Address (Applicable
Regardless of MFR_CONFIG_ALL[6] Setting) ....33
Table 5. LTM4678 MFR_ADDRESS Command
Examples Expressed in 7- and 8-Bit Addressing ...... 33
Fault Detection and Handling ...................................33
Status Registers and ALERT Masking ....................34
Figure 5. LTM4678 Status Register Summary........35
Mapping Faults to FAULT Pins ...............................36
Power Good Pins ...................................................36
CRC Protection ......................................................36
Serial Interface .........................................................36
Communication Protection ....................................36
Device Addressing ...................................................36
Responses to V
and I /I
Faults ....................37
OUT
IN OUT
Output Overvoltage Fault Response .......................37
Output Undervoltage Response .............................38
Peak Output Overcurrent Fault Response ..............38
Responses to Timing Faults .....................................38
Responses to V OV Faults .....................................38
IN
Responses to OT/UT Faults ......................................38
Internal Overtemperature Fault Response ..............38
External Overtemperature and
Undertemperature Fault Response ......................39
Responses to Input Overcurrent and Output
INTV /EXTV Power ............................................28
CC
CC
Output Current Sensing and Sub Milliohm DCR
Current Sensing .....................................................29
Input Current Sensing ..............................................29
PolyPhase Load Sharing ..........................................29
External/Internal Temperature Sense .......................30
RCONFIG (Resistor Configuration) Pins ...................30
Table 1. VOUTn _CFG Pin Strapping Look-Up Table
for the LTM4678’s Output Voltage, Coarse Setting
(Not Applicable if MFR_CONFIG_ALL[6] = 1b) .....30
Table 2. VTRIMn_CFG Pin Strapping Look-Up
Undercurrent Faults ...............................................39
Responses to External Faults ...................................39
Fault Logging ...........................................................39
Bus Timeout Protection ...........................................39
2
Similarity Between PMBus, SMBus and I C
2-Wire Interface .....................................................40
PMBus Serial Digital Interface .................................40
Table 6. Abbreviations of Supported Data Formats ......41
Figure 6. PMBus Timing Diagram........................... 41
Figures 7 to 24 PMBus Protocols .............................42
Table for the LTM4678’s Output Voltage, Fine
Adjustment Setting (Not Applicable if MFR_
CONFIG_ALL[6] = 1b) ..........................................31
Rev 0
2
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LTM4678
TABLE OF CONTENTS
PMBus Command Summary ............................45
PMBus Commands ..................................................45
Table 7. PMBus Commands Summary (Note:
Typical Applications......................................72
PMBus Command Details ...............................77
Addressing and Write Protect...................................77
General Configuration Commands............................79
On/Off/Margin...........................................................80
PWM Configuration ..................................................82
Voltage......................................................................85
Input Voltage and Limits.........................................85
Output Voltage and Limits ......................................86
Output Current and Limits ........................................89
Input Current and Limits ........................................91
Temperature..............................................................92
Power Stage DCR Temperature Calibration.............92
Timing.......................................................................93
Timing—On Sequence/Ramp.................................93
Timing—Off Sequence/Ramp ................................94
Precondition for Restart .........................................95
Fault Response .........................................................95
Fault Responses All Faults......................................95
Fault Responses Input Voltage................................96
Fault Responses Output Voltage.............................96
Fault Responses Output Current.............................99
Fault Responses IC Temperature ..........................100
Fault Responses External Temperature................. 101
Fault Sharing........................................................... 102
Fault Sharing Propagation .................................... 102
Fault Sharing Response........................................104
Scratchpad..............................................................104
Identification........................................................... 105
Fault Warning and Status........................................106
MFR_INFO Data Contents:.................................... 112
Telemetry................................................................ 112
NVM Memory Commands ...................................... 116
Store/Restore ....................................................... 116
Fault Logging........................................................ 117
Block Memory Write/Read.................................... 121
Package Description ................................... 122
Table 22. LTM4678 BGA Pinout............................ 122
Package Photograph ................................... 124
Design Resources ...................................... 124
Related Parts............................................ 124
The Data Format Abbreviations are Detailed in
Table 8) ................................................................45
Table 8. Data Format Abbreviations .......................50
Applications Information ................................51
V to V
Step-Down Ratios ................................. 51
IN
OUT
Input Capacitors ...................................................... 51
Output Capacitors .................................................... 51
Light Load Current Operation ................................... 51
Switching Frequency and Phase ..............................52
Output Current Limit Programming .........................53
Minimum On-Time Considerations ...........................54
Variable Delay Time, Soft-Start and Output
Voltage Ramping ...................................................54
Digital Servo Mode ..................................................54
Soft Off (Sequenced Off) .........................................55
Undervoltage Lockout ..............................................56
Fault Detection and Handling ...................................56
Open-Drain Pins .......................................................56
Phase-Locked Loop and Frequency Synchronization .. 57
Input Current Sense Amplifier ..................................58
Programmable Loop Compensation ........................58
Checking Transient Response ..................................59
PolyPhase Configuration .......................................60
2
Connecting The USB to I C/SMBus/PMBus
Controller to the LTM4678 In System ....................60
LTpowerPlay: An Interactive GUI for Digital Power ...61
PMBus Communication and Command Processing ...61
Thermal Considerations and Output Current
Derating..................................................................63
Tables 10 thru 11: Output Current Derating...............66
Table 12. Channel Output Voltage vs Component
Selection, 0A to 12.5A/μs Load Step ........................
Output Capacitor-GRM32ER60G337ME05L,
330μF, 4V, X5R, Murata........................................67
Table 13. Channel Output Voltage vs Component
Selection, 0A to 12.5A/μs Load Step ....................68
Dual Phase Single Output Voltage vs Component
Selection, 25A to 50A/μs Load Step.....................68
Applications Information-Derating Curves............69
EMI Performance .....................................................70
Safety Considerations ..............................................70
Layout Checklist/Example ........................................70
Rev 0
3
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LTM4678
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
ꢙꢗꢝ ꢖꢚꢐꢜ
Terminal Voltages:
ꢠ
ꢡ
ꢖ
ꢖ
ꢖ
ꢗꢛꢕꢛꢀ
ꢗꢛꢕꢛꢀ
+
−
ꢔ
V
(Note 4), SV , I , I ...................... –0.3V to 18V
INn
IN IN IN
ꢖ
ꢎꢕꢑ
ꢛꢜꢀ
ꢗꢘꢙꢀ
+
+
−
(SV – I ), (I – I )........................... –0.3V to 0.3V
IN
IN
IN
IN
ꢓ
ꢒ
ꢑ
ꢐ
ꢙRꢚꢉ0ꢞ
ꢒꢏꢎ
ꢖ
SW0, SW1 .................. −1V to 18V, −5V to 18V Transient
ꢗꢘꢙꢀ
ꢒꢗꢉꢝꢀꢯ ꢜꢝ
ꢛꢍꢔRꢐꢞ
V
V
V
, INTV , EXTV ............................... –0.3V to 6V
OUTn
CC
CC
ꢎꢕꢑ
ꢛꢖ
ꢖ
ꢑꢑꢁꢄ
ꢚꢕ
ꢝꢎꢗꢗꢑꢀ
ꢏ
ꢙꢛꢕꢛꢀꢯ
ꢒꢗꢉꢝꢀꢰ ꢒꢊꢋ
+
+
, V
......................................... –0.3V to 6V
OSNS0
OSNS0
OSNS1
ꢖ
ꢖ
ꢖ
ꢗꢘꢙꢀꢞ
ꢒꢏꢎ
ꢎꢕꢑ
ꢛꢜꢝꢍꢞ ꢙRꢚꢉꢀꢞ ꢗꢘꢙ0ꢞ
−
−
ꢚꢕꢙꢖ
ꢖ
ꢑꢑꢂꢂ
, V
...................................... –0.3V to 0.3V
ꢒꢒ
ꢒꢏꢎ
ꢒꢏꢎ
ꢒꢏꢎ
OSNS1
RUNn, SDA, SCL, ALERT........................... –0.3V to 5.5V
FSWPH_CFG, VOUT0,1_CFG,
VTRIM0,1_CFG, ASEL ......................... –0.3V to 2.75V
FAULTn, SYNC, SHARE_CLK, WP,
PGOOD0, PGOOD1 ............................... −0.3V to 3.6V
COMPna, COMPnb, .................................. –0.3V to 2.7V
TSNS0a, TSNS1a ...................................... –0.3V to 2.2V
TSNS1b, TSNS1b ...................................... –0.3V to 0.8V
Temperatures
Internal Operating Temperature Range
(Notes 2, 13, 17, 18)............................... –40°C to 125°C
Storage Temperature Range .................. –55°C to 125°C
Peak Solder Reflow Package Body Temperature... 245°C
ꢖ
ꢖ
ꢚꢕꢀ
ꢐꢟꢙꢖ
ꢒꢒ
Rꢘꢕꢀ
ꢔꢛꢐꢊ
ꢏ
ꢛꢎꢕꢑ
ꢎꢕꢑ
FAULT1 Rꢘꢕ0
ꢎ
ꢍ
ꢌ
ꢚꢕ0
ALERT FAULT0
ꢒꢗꢉꢝ0ꢯ ꢛꢑꢔ
ꢠ
ꢚ
ꢝꢎꢗꢗꢑ0 ꢙꢛꢕꢛ0ꢯ ꢒꢗꢉꢝ0ꢰ ꢙꢛꢕꢛꢀꢰ ꢙꢛꢕꢛ0ꢰ ꢛꢒꢊ
ꢛꢱꢕꢒ
ꢚꢕ
ꢚꢕ
ꢡ
ꢎꢕꢑ
ꢚ
ꢋ
ꢊ
ꢖ
ꢎꢕꢑ
ꢗꢘꢙ0
ꢖ
ꢠ
ꢡ
ꢗꢘꢙ0
ꢛꢜ0
ꢁ
ꢖ
ꢖ
ꢗꢛꢕꢛ0 ꢗꢛꢕꢛ0
ꢉ
ꢀ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢀ0
ꢀꢀ
ꢀꢁ
ꢓꢎꢔ ꢝꢔꢒꢋꢔꢎꢐ
ꢀꢃꢃꢢꢊꢐꢔꢑ ꢣꢀꢅꢤꢤ ꢥ ꢀꢅꢤꢤ ꢥ ꢄꢦꢇꢅꢤꢤꢧ
ꢨ ꢁꢦꢄꢩꢒꢮꢜꢪ θ ꢨ ꢁꢩꢒꢮꢜꢪ θ ꢨ ꢆꢩꢒꢮꢜꢪ θ ꢨ ꢈꢩꢒꢮꢜ
ꢙ
ꢨ ꢀꢁꢄꢩꢒꢪ θ
ꢌꢒꢫꢬꢭ
ꢌꢉꢔꢟ
ꢌꢒꢯꢬꢫꢫꢬꢤ
ꢓꢔ ꢌꢔ
θ ꢖꢔꢊꢘꢐꢛ ꢑꢐꢙꢐRꢉꢚꢕꢐꢑ ꢝꢐR ꢌꢐꢛꢑꢄꢀꢢꢀꢁ
ꢜꢐꢚꢎꢍꢙ ꢨ ꢂꢦꢁ ꢎRꢔꢉꢛ
ORDER INFORMATION
PART MARKING*
PACKAGE
TYPE
MSL
RATING
TEMPERATURE RANGE
(See Note 2)
PART NUMBER
LTM4678EY#PBF
LTM4678IY#PBF
LTM4678IY
PAD OR BALL FINISH
SAC305 (RoHS)
SnPb (63/37)
DEVICE
FINISH CODE
LTM4678Y
LTM4678Y
LTM4678Y
e1
e0
BGA
4
–40°C to 125°C
Consult Marketing for parts specified with wider operating temperature ranges. *Device temperature grade is indicated by a label on the shipping container.
Pad or ball finish code is per IPC/JEDEC J-STD-609.
Rev 0
4
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LTM4678
ELECTRICAL CHARACTERISTICS The ldenotes the specifications which apply over the specified internal
operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUNn = 3.3V,
EXTVCC = 0, FREQUENCY_SWITCH = 350kHz and VOUTn commanded to 1.000V unless otherwise noted. Configured with factory-default
EEPROM settings and per Test Circuit 1, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
V
SV
Input DC Voltage
Test Circuit 1
Test Circuit 2; VIN_OFF < VIN_ON = 4V
5.75
4.5
16
5.75
V
V
INn,
IN
+
+
–
–
l
l
V
Range of Output Voltage Regulation V
V
Differentially Sensed on V
Differentially Sensed on V
/V
/V
Pin-Pair;
Pin-Pair;
0.5
0.5
3.3
3.3
V
V
OUTn
OUT0
OUT1
OSNS0
OSNS1
OSNS0
OSNS1
Commanded by Serial Bus or with Resistors Present at Start-
Up on V
OUTn_CFG
V
V
Output Voltage, Total Variation with (Note 5)
OUTn(DC)
l
l
Line and Load
Digital Servo Engaged (MFR_PWM_MODEn[6] = 1b)
0.995 1.000 1.005
0.985 1.000 1.015
V
V
Digital Servo Disengaged (MFR_PWM_MODEn[6] = 0b)
V
Commanded to 1.000V, V
Low Range
OUTn
OUTn
(MFR_PWM_MODEn[1] = 1b)
Undervoltage Lockout Threshold,
V
V
Falling
Rising
3.55
3.90
V
V
UVLO
INTVCC
INTVCC
When V < 4.3V
IN
Input Specifications
I
Input Inrush Current at
Start-Up
Test Circuit 1, V
=1V, V = 12V; No Load Besides
n
400
mA
INRUSH(VIN)
OUTn
IN
Capacitors; TON_RISE = 3ms
I
Input Supply Bias Current
Forced Continuous Mode, MFR_PWM_MODEn[0] = 1b
RUNn = 3.3V
Shutdown, RUN0 = RUN1 = 0V
Q(SVIN)
25
23
mA
mA
I
I
Input Supply Current in Pulse-
Skipping Mode Operation
Pulse-Skipping Mode, MFR_PWM_MODEn[0] = 0b,
OUTn
20
mA
S(VINn,PSM)
S(VINn,FCM)
I
= 100mA
Input Supply Current in Forced-
Continuous Mode Operation
Forced Continuous Mode, MFR_PWM_MODEn[0] = 1b
I
I
= 100mA
= 25A
50
2.4
mA
A
OUTn
OUTn
Output Specifications
Output Continuous Current Range (Note 6) Utilizing MFR_PWM_MODE[7] = 1 and
Using ~I = 34A for IOUT_OC_FAULT_LIMIT, Page 90
I
0
25
A
OUTn
OUT
∆V
Line Regulation Accuracy
Digital Servo Engaged (MFR_PWM_MODEn[6] = 1b)
Digital Servo Disengaged (MFR_PWM_MODEn[6] = 0b)
0.03
0.03
%/V
%/V
OUTn(LINE)
l
0.2
V
OUTn
SV and V Electrically Shorted Together and INTV
IN
INn
OUTn
CC
Open Circuit; I
= 0A, 5.0V ≤ V ≤ 16V, V
Low Range
IN
OUT
(MFR_PWM_MODEn[1] = 1b), FREQUENCY_SWITCH =
350kHz (Note 5)
∆V
Load Regulation Accuracy
Output Voltage Ripple
Digital Servo Engaged (MFR_PWM_MODEn[6] = 1b)
Digital Servo Disengaged (MFR_PWM_MODEn[6] = 0b)
OUTn
= 1b) (Note 5)
0.03
0.2
%
%
OUTn(LOAD)
l
l
0.5
V
OUTn
0A ≤ I
≤ 25A, V
Low Range, (MFR_PWM_MODEn[1]
OUT
V
10
mV
P-P
OUTn(AC)
f (Each
V
Ripple Frequency
OUTn
FREQUENCY_SWITCH Set to 350kHz (0xFABC)
325
350
375
kHz
S
Channel)
∆V
Turn-On Overshoot
TON_RISEn = 3ms (Note 12)
8
mV
ms
OUTn(START)
l
l
t
Turn-On Start-Up Time
Time from V Toggling from 0V to 12V to Rising Edge
30
START
IN
PGOODn. TON_DELAYn = 0ms, TON_RISEn = 3ms
t
Turn-On Delay Time
Time from First Rising Edge of RUNn to Rising Edge of
PGOODn . TON_DELAYn = 0ms, TON_RISEn = 3ms,
2.95
3.3
50
3.7
ms
mV
DELAY(0ms)
V
Having Been Established for at Least 70ms
IN
∆V
Peak Output Voltage Deviation for
Dynamic Load Step
Load: 0A to 12.5A and 12.5A to 0A at 12.5A/µs,
OUTn(LS)
V
= 1V, V = 12V (Note 12)
IN
OUTn
See Load Transient Graphs
Rev 0
5
For more information www.analog.com
LTM4678
ELECTRICAL CHARACTERISTICS The ldenotes the specifications which apply over the specified internal
operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUNn = 3.3V,
EXTVCC = 0, FREQUENCY_SWITCH = 350kHz and VOUTn commanded to 1.000V unless otherwise noted. Configured with factory-default
EEPROM settings and per Test Circuit 1, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
t
I
I
Settling Time for Dynamic Load
Step
Load: 0A to 12.5A and 12.5A to 0A at 12.5A/µs,
25
µs
SETTLE
V
= 1V, V = 12V (Note 12)
IN
OUTn
See Load Transient Graphs
Output Current Limit, Peak High
Range
Cycle-by-Cycle Inductor Peak Current Limit Inception,
40
A
OUTn(OCL_PK)
OUTn(OCL_AVG)
Utilizing MFR_PWM_MODE[7] = 1, Using ~I
IOUT_OC_FAULT_LIMIT, Page 90
= 34A for
OUT
Output Current Limit, Time
Averaged
Time-Averaged Output Inductor Current Limit Inception
35A; See I
Specification (Output Current
Readback Accuracy)
O-RB-ACC
Threshold, Commanded by IOUT_OC_FAULT_LIMIT (Note 12)
n
Utilizing MFR_PWM_MODE[7] = 1, Using ~I = 34A, Page 90
OUT
Control Section
–
+
l
l
V
V
V
Channel 0 Feedback Input Common
Mode Range
V
V
Valid Input Range (Referred to SGND)
Valid Input Range (Referred to SGND)
–0.1
–0.1
0.3
3.6
V
V
FBCM0
OSNS0
OSNS0
–
+
l
l
Channel 1 Feedback Input Common
Mode Range
V
V
Valid Input Range (Referred to SGND)
Valid Input Range (Referred to SGND)
0.3
3.6
V
V
FBCM1
OSNS1
OSNS1
Full-Scale Command Voltage,
Range Low (0.6V to 2.75V,
Notes 7, 15)
V
Commanded to 2.750V, MFR_PWM_MODEn[1] = 1b
OUTn
2.7
−0.5
2.8
−0.5
V
%
Bits
mV
OUT-RNGL
Set Point Accuracy
Resolution
LSB Step Size
12
0.688
V
Full-Scale Command Voltage,
V
Commanded to 3.6V, MFR_PWM_MODEn[0] = 1b
OUTn
OUT-RNGH
Range High (0.6V to 3.6V, Note 8) Limit Design to 1.5V Operating for Module
Set Point Accuracy
Resolution
LSB Step Size
3.5
3.7
V
Bits
mV
12
1.375
+
+
+
R
R
V
V
Impedance to SGND
0.05V ≤ V
0.05V ≤ V
(Note 8 )
– V ≤ 3.3V
SGND
50
50
50
kΩ
kΩ
ns
VSNS0
VSNS1
OSNS0
OSNS1
VOSNS0
VOSNS1
+
Impedance to SGND
– V
≤ 3.3V
SGND
t
Minimum On-Time
ON(MIN)
R
Resolution
MFR_PWM_CONFIG[4:0] = 0 to 31 (See Figure 1, Note
Section)
5
62
0
Bits
kΩ
kΩ
COMP0,1
m0,1
Compensation Resistor R
Compensation Resistor R
TH(MAX)
TH(MIN)
g
Resolution
COMP0,1 = 1.35V, MFR_PWM_CONFIG[7:5] = 0 to 7
3
Bits
mmho
mmho
mmho
Error Amplifier g
Error Amplifier g
LSB Step Size
5.76
1
m(MAX)
m(MIN)
0.68
Analog OV/UV (Overvoltage/Undervoltage) Output Voltage Supervisor Comparators (VOUT_OV/UV_FAULT_LIMIT and VOUT_OV/UV_WARN_LIMIT Monitors)
N
Resolution, Output Voltage
Supervisors
(Notes 14, 15)
9
Bits
OV/UV_COMP
V
V
V
Output OV Comparator Threshold
Detection Range
(Notes 14, 15)
OV-RNG
High Range Scale, MFR_PWM_MODEn[1] = 0b
Low Range Scale, MFR_PWM_MODEn[1] = 1b
1
3.6
2.7
V
V
0.5
Output OV and UV Comparator
Threshold Programming LSB Step
Size
(Note 15)
OUSTP
High Range Scale, MFR_PWM_MODEn[1] = 0b
Low Range Scale, MFR_PWM_MODEn[1] = 1b
11.2
5.6
mV
mV
Full-Scale Command Voltage,
Range High (0.6V to 3.6V,
Notes 7, 15)
V
Commanded to 3.6V, MFR_PWM_MODEn[0] = 1b
OUTn
3.5
–0.5
3.7
–0.5
V
%
Bits
mV
OUT-RNGH
Set Point Accuracy
Resolution
12
1.375
LSB Step Size
V
Output OV Comparator Threshold
Accuracy Channel 0 and 1
(See Note 14)
OV-ACC-0,1
+
–
l
l
l
1V ≤ V
– V
≤ 2.7V, MFR_PWM_MODE[1] = 1b
1.5
40
1.5
%
mV
%
VOSNSn
VOSNSn
+
–
0.5V ≤ V
2.0V ≤ V
– V
≤ 1V, MFR_PWM_MODE[1] = 1b
VOSNSn
VSNS
VOSNSn
– V
≤ 3.6V, MFR_PWM_MODE[0] = 0b
SNG
Rev 0
6
For more information www.analog.com
LTM4678
ELECTRICAL CHARACTERISTICS The ldenotes the specifications which apply over the specified internal
operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUNn = 3.3V,
EXTVCC = 0, FREQUENCY_SWITCH = 350kHz and VOUTn commanded to 1.000V unless otherwise noted. Configured with factory-default
EEPROM settings and per Test Circuit 1, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
Output UV Comparator Threshold
Detection Range
(Note 15)
UV-RNG
High Range Scale, MFR_PWM_MODEn[1] = 0b
1
0.5
3.6
2.7
V
V
Low Range Scale, MFR_PWM_MODEn[1] = 1b
Output UV Comparator Threshold
Accuracy
(See Note 14)
UV-ACC
+
–
l
l
l
1V ≤V
–V
≤2.7V, MFR_PWM_MODE[1]=1b
1.5
40
1.5
%
mV
%
VOSNSn
VOSNSn
+
–
0.5V ≤V
–V
≤ 1V, MFR_PWM_MODE[1]=1b
VOSNSn
VOSNSn
2.0V ≤ V
– V
≤ 3.6V, MFR_PWM_MODE[0] = 0b
VSNS
SNG
t
t
Output OV Comparator Response
Times
Overdrive to 10% Above Programmed Threshold
100
µs
PROP-OV
PROP-UV
Output UV Comparator Response
Times
Under Drive to 10% Below Programmed Threshold
100
µs
Analog OV/UV SV Input Voltage Supervisor Comparators (Threshold Detectors for VIN_ON and VIN_OFF)
IN
NSVIN-OV/UV-COMP SV OV/UV Comparator Threshold- (Notes 14, 15)
9
Bits
V
IN
Programming Resolution
l
SV
SV
SV
SV OV/UV Comparator Threshold-
4.5
16
IN-OU-RANGE
IN
Programming Range
SV OV/UV Comparator Threshold- (Note 15)
76
mV
IN-OU-STP
IN
Programming LSB Step Size
l
l
SV OV/UV Comparator Threshold 9V < SV ≤ 16V
3.5
315
%
mV
IN-OU-ACC
IN
IN
Accuracy
4.5V ≤ SV ≤ 9V
IN
tPROP-SVIN-HIGH-VIN SV OV/UV Comparator Response Test Circuit 1, and:
IN
l
l
Time, High V Operating
VIN_ON = 9V; SV Driven from 8.775V to 9.225V
100
100
µs
µs
IN
IN
Configuration
VIN_OFF = 9V; SV Driven from 9.225V to 8.775V
IN
tPROP-SVIN-LOW-VIN SV OV/UV Comparator Response Test Circuit 2, and:
IN
l
l
Time, Low V Operating
VIN_ON = 4.5V; SV Driven from 4.225V to 4.725V
100
100
µs
µs
IN
IN
Configuration
VIN_OFF = 4.5V; SV Driven from 4.725V to 4.225V
IN
Channels 0 and 1 Output Voltage Readback (READ_VOUTn)
N
VO-RB
Output Voltage Readback
Resolution and LSB Step Size
(Note 15)
16
244
Bits
µV
V
V
Output Voltage Full-Scale
Digitizable Range
V
= 0V (Note 15)
8
V
O-F/S
RUNn
+
–
l
l
Output Voltage Readback Accuracy Channel 0, 1: 1V ≤ V
– V
≤ 3.6V
Within 0.5%ofReading
Within 5mVofReading
O-RB-ACC
CONVERT-VO-RB
VOSNS
VOSNS
+
–
Channel 0, 1: 0.6V ≤ V
– V
< 1V
VOSNS
VOSNS
t
Output Voltage Readback Update
Rate
MFR_ADC_CONTROL = 0x00 (Notes 9, 15)
MFR_ADC_CONTROL = 0x01 through 0x0C (Notes 9, 15)
MFR_ADC_CONTROL Section
90
8
ms
ms
ms
Input Voltage (SV ) Readback (READ_VIN)
IN
N
Input Voltage Readback Resolution (Notes 10, 15) Limited to Abs Max = 18V for
and LSB Step Size LTM4678 Module
10
15.625
Bits
mV
SVIN-RB
SV
Input Voltage Full-Scale Digitizable (Notes 11, 15)
Range
43
V
IN-F/S
l
SV
Input Voltage Readback Accuracy
READ_VIN, 4.5V ≤ SV ≤ 16V
Within 2% of Reading
IN-RB-ACC
IN
t
Input Voltage Readback Update
Rate
MFR_ADC_CONTROL = 0x00 (Notes 9, 15)
MFR_ADC_CONTROL = 0x01 (Notes 9, 15)
90
8
ms
ms
CONVERT-SVIN-RB
Channels0and1OutputCurrent(READ_IOUTn)
N
IO-RB
Output Current Readback
Resolution and LSB Step Size
(Notes 10, 12)
10
34.1
Bits
mA
Rev 0
7
For more information www.analog.com
LTM4678
ELECTRICAL CHARACTERISTICS The ldenotes the specifications which apply over the specified internal
operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUNn = 3.3V,
EXTVCC = 0, FREQUENCY_SWITCH = 350kHz and VOUTn commanded to 1.000V unless otherwise noted. Configured with factory-default
EEPROM settings and per Test Circuit 1, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I
Output Current Full-Scale
Digitizable Range
(Note 12)
40
A
O-F/S
Utilizing MFR_PWM_MODE[7] = 1, Using IOUT_OC_FAULT_
LIMIT = 34A, Page 90
l
I
I
t
Output Current, Readback Accuracy READ_IOUTn, Channels 0 and 1, 0 ≤ I
≤ 25A, (Note 12)
Within 1.25A of Reading
25
O-RB-ACC
OUTn
Forced-Continuous Mode, MFR_PWM_MODEn[1:0] = 1b
Full Load Output Current Readback
I
= 25A (Note 12). See Histograms in Typical
OUTn
A
O-RB(25A)
Performance Characteristics (Note 12)
Output Current Readback Update
Rate
MFR_ADC_CONTROL = 0x00 (Notes 9, 15)
90
8
ms
ms
CONVERT-IO-RB
MFR_ADC_CONTROL = 0x06 (CH0 I ) or 0x01 (CH1 I
)
OUT
OUT
(Notes 9, 15) See MFR_ADC_CONTROL Section
Input Current Readback
Resolution
N
(Note 10)
10
Bits
+
+
+
–
V
LSB Step Size Full-Scale Range =
Gain = 8, 0V ≤ |V
Gain = 4, 0V ≤ |V
Gain = 2, 0V ≤ |V
– V | ≤ 5mV
15.26
30.52
61
µV
µV
µV
IINSTP
IIN
IIN
IIN
IIN
–
–
16mV
– V | ≤ 20mV
IIN
LSB Step Size Full-Scale Range =
– V | ≤ 50mV
IIN
32mV
LSB Step Size Full-Scale Range =
64mV
+
–
l
l
l
I
Total Unadjusted Error
Gain = 8, 2.5mV ≤ |V
– V
IIN
IIN
|
2
1.3
1.2
%
%
%
IN_TUE
IIN
IIN
+
–
Gain = 4, 4mV ≤ |V
Gain = 2, 6mV ≤ |V
– V
– V
|
|
IIN
IIN
+
–
V
Zero-Code Offset Voltage
Update Rate
(Note 15)
50
µV
OS
t
(Notes 9,15) See MFR_ADC_CONTROL Section for Faster
Update Rates
90
ms
CONVERT
Supply Current Readback
N
Resolution
(Note 10)
10
Bits
µV
V
LSB Step Size Full-Scale Range =
256mV
Onboard 1Ω Resistor
244
ICHIPSTP
I
t
I
Readback
SV Curent
50
90
mA
ms
CHIP-RB
CHIP
IN
Update Rate
(Notes 9,15) See MFR_ADC_CONTROL Section for Faster
Update Rates
CONVERT
Temperature Readback (T0, T1)
Temperature Readback Resolution Channel 0, Channel 1, and Controller (Note 15)
T
0.25
5
°C
RES-RB
T0_TUE
External Temperature Total
Unadjusted Readback Error
Supporting Only ∆V Sensing
BE
°C
°C
l
T1_TUE
Internal TSNS TUE
Update Rate
V
= 0.0, f
= 0kHz (Note 15)
SYNC
1
°C
RUN0,1
t
(Note 9)
MFR_ADC_CONTROL = 0x04 or 0x0C (Notes 9, 15)
90
8
ms
ms
CONVERT
INTV Regulator/EXTV
CC
CC
l
l
V
V
V
V
V
Internal V Voltage No Load
6V ≤ V ≤ 16V
5.25
4.5
5.5
0.5
4.7
290
80
5.75
2
V
%
INTVCC
CC
IN
INTV Load Regulation
I = 0mA to 20mA, 6V ≤ V ≤ 16V
CC IN
LDO_INT
EXTVCC
CC
EXTV Switchover Voltage
V
≥ 7V, EXTV Rising
4.9
V
CC
IN
CC
EXTV Hysteresis
mV
mV
LDO_HYS
LDO_EXT
CC
EXTV Voltage Drop
I
= 20mA, V = 5.5V
EXTVCC
120
CC
CC
Rev 0
8
For more information www.analog.com
LTM4678
ELECTRICAL CHARACTERISTICS The ldenotes the specifications which apply over the specified internal
operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUNn = 3.3V,
EXTVCC = 0, FREQUENCY_SWITCH = 350kHz and VOUTn commanded to 1.000V unless otherwise noted. Configured with factory-default
EEPROM settings and per Test Circuit 1, unless otherwise noted.
SYMBOL
PARAMETER
Threshold to Enable EXTV
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
V
Rising
7
7.4
V
IN_THR
IN
CC
IN
Switchover
V
V
Hysteresis to Disable EXTV
V
Falling
600
mV
IN_THF
IN
CC
IN
Switchover
V
Regulator
DD33
VDD33
LIM
V
Internal V
Voltage
4.5V < V
or 4.8V < V
EXTVCC
3.2
3.3
100
3.5
3.1
3.4
V
mA
V
DD33
INTVCC
I
V
V
V
Current Limit
V
= GND
DD33
DD33
DD33
DD33
V
V
V
V
Overvoltage Threshold
VDD33_OV
VDD33_UV
Undervoltage Threshold
V
Regulator
DD25
VDD25
LIM
Internal V
Voltage
2.5
80
V
DD25
I
V
Current Limit
V
= GND
mA
DD25
DD25
Oscillator and Phase-Locked Loop (PLL)
l
f
f
PLL SYNC Range
Synchronized with Falling Edge of SYNC
300
1075
7.5
kHz
%
RANGE
OSC
Oscillator Frequency Accuracy
SYNC Input Threshold
Frequency Switch = 350.0kHz to 1000.0kHz (Note 15)
V
V
V
Falling
Rising
1
1.5
V
V
TH(SYNC)
SYNC
SYNC
V
SYNC Low Output Voltage
I
= 3mA
0.2
0.4
5
V
OL(SYNC)
LOAD
I
SYNC Leakage Current in Slave
Mode
0V ≤ V ≤ 3.6V
µA
LEAK(SYNC)
PIN
θSYNC-θ0
SYNC to Ch0 Phase Relationship
Based on the Falling Edge of Sync
and Rising Edge of TG0 (Note 15)
MFR_PWM_CONFIG[2:0] = 0,2,3
MFR_PWM_CONFIG[2:0] = 5
MFR_PWM_CONFIG[2:0] = 1
MFR_PWM_CONFIG[2:0]= 4,6
0
Deg
Deg
Deg
Deg
60
90
120
θSYNC-θ1
SYNC to Ch1 Phase Relationship
Based on the Falling Edge of Sync
and Rising Edge of TG1 (Note 15)
MFR_PWM_CONFIG[2:0] = 3
MFR_PWM_CONFIG[2:0] = 0
MFR_PWM_CONFIG[2:0] = 2,4,5
MFR_PWM_CONFIG[2:0] = 1
MFR_PWM_CONFIG[2:0] = 6
120
180
240
270
300
Deg
Deg
Deg
Deg
Deg
EEPROM Characteristics
l
l
Endurance
Retention
(Notes 13 and 17)
0°C ≤ T ≤ 85°C During EEPROM Write Operations
10,000
10
Cycles
Years
ms
J
(Notes 13 and 17)
T < 125°C
J
Mass_Write
Mass Write Operation Time
(Notes 13 and 17)
STORE_USER_ALL, 0°C < T < 85°C
440
4100
J
During EEPROM Write Operation
Leakage Current SDA, SCL, ALERT, RUN
Input Leakage Current
Leakage Current FAULTn, PGOODn
Input Leakage Current
Digital Inputs SCL, SDA, RUNn, GPI0n (Note 15)
l
l
I
OV ≤ V ≤ 5.5V
5
2
µA
µA
OL
PIN
I
OV ≤ V ≤ 3.6V
GL
PIN
l
l
V
V
V
C
Input High Threshold Voltage
Input Low Threshold Voltage
Input Hysteresis
1.35
V
V
IH
0.8
IL
SCL, SDA
0.08
V
HYST
PIN
Input Capacitance
10
pF
Rev 0
9
For more information www.analog.com
LTM4678
ELECTRICAL CHARACTERISTICS The ldenotes the specifications which apply over the specified internal
operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUNn = 3.3V,
EXTVCC = 0, FREQUENCY_SWITCH = 575kHz and VOUTn commanded to 1.000V unless otherwise noted. Configured with factory-default
EEPROM settings and per Test Circuit 1, unless otherwise noted.
SYMBOL
Digital Input WP (Note 15)
Input Pull-Up Current
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I
WP
10
µA
PUWP
Open-Drain Outputs SCL, SDA, FAULTn, ALERT, RUNn, SHARE_CLK, PGOODn (Note 15)
Output Low Voltage = 3mA
Digital Inputs SHARE_CLK, WP (Note 15)
V
I
0.4
1.8
V
OL
SINK
l
l
V
V
Input High Threshold Voltage
Input Low Threshold Voltage
1.5
1
V
V
IH
IL
0.6
Digital Filtering of FAULTn (Note 15)
Input Digital Filtering FAULTn
Digital Filtering of PGOODn (Note 15)
Output Digital Filtering PGOODn
Digital Filtering of RUNn (Note 15)
Input Digital Filtering RUN
PMBus Interface Timing Characteristics (Note 15)
I
3
µs
µs
µs
FLTG
I
60
10
FLTG
I
FLTG
l
l
f
t
Serial Bus Operating Frequency
10
400
kHz
µs
SCL
BUF
Bus Free Time Between Stop and
Start
1.3
l
t
t
Hold Time After Repeated Start
Condition After This Period, the
First Clock is Generated
0.6
µs
HD(STA)
SU(STA)
l
l
Repeated Start Condition Setup
Time
0.6
0.6
10000
0.9
µs
µs
t
t
Stop Condition Setup Time
SU(ST0)
HD(DAT)
Date Hold Time
Receiving Data
Transmitting Data
l
l
0
0.3
µs
µs
t
t
Data Setup Time
Receiving Data
SU(DAT)
0.1
µs
Stuck PMBus Timer Non-Block Reads Measured from the Last PMBus Start Event
Stuck PMBus Timer Block Reads
32
255
ms
TIMEOUT_SMB
l
l
t
t
Serial Clock Low Period
Serial Clock High Period
1.3
0.6
10000
µs
µs
LOW
HIGH
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
the ambient temperature T and the power dissipation PD according the
formula:
A
T = T + (P • θJA
)
J
A
D
Note that the maximum ambient temperature consistent with these
specifications is determined by specific operating conditions in
conjunction with board layout, the rated package thermal resistance and
other environmental factors.
Note 2: The LTM4678 is tested under pulsed-load conditions such that
T ≈ T . The LTM4678E is guaranteed to meet performance specifications
J
A
over the 0°C to 125°C internal operating temperature range. Specifications
over the –40°C to 125°C internal operating temperature range are assured
by design, characterization and correlation with statistical process
controls. The LTM4678I is guaranteed to meet specifications over the full
Note 3: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified
–40°C to 125°C internal operating temperature range. T is calculated from
J
Rev 0
10
For more information www.analog.com
LTM4678
ELECTRICAL CHARACTERISTICS
channel with airflow can be compared with the GUI readback temperature.
Since the inductor and internal temperature sensor are not in the
exact same location. Once this temperature difference is known, then
MFR_TEMP_1_GAIN and the MFR_TEMP_1_OFFSET parameters can be
adjusted to further improve output current readback.
Note 13: EEPROM endurance and retention are guaranteed by wafer-level
testing for data retention. The minimum retention specification applies
for devices whose EEPROM has been cycled less than the minimum
endurance specification, and whose EEPROM data was written to at 0°C
Note 4: The two power inputs—V and V —and their respective power
IN0
IN1
outputs—V
and V —are tested independently in production. A
OUT1
OUT0
shorthand notation is used in this document that allows these parameters
to be referred to by “V ” and “V ”, where n is permitted to take on
INn
OUTn
a value of 0 or 1. This italicized, subscripted “n” notation and convention
is extended to encompass all such pin names, as well as register names
with channel-specific, i.e., paged data. For example, VOUT_COMMANDn
refers to the VOUT_COMMAND command code data located in Pages 0
and 1, which in turn relate to channel 0 (V ) and channel 1 (V
OUT0
).
OUT1
Registers containing non-page-specific data, i.e., whose data is “global” to
the module or applies to both of the module’s channels lack the italicized,
subscripted “n”, e.g., FREQUENCY_SWITCH.
≤ T ≤ 85°C. The RESTORE_USER_ALL or MFR_RESET is valid over
the entire operating temperature range and does not influence EEPROM
characteristics.
J
Note 5: V
(DC) and line and load regulation tests are performed in
Note 14: Channel 0 OV/UV comparator threshold accuracy for
OUTn
+
–
production with digital servo disengaged (MFR_PWM_MODEn[6] = 0b)
and low V range selected MFR_PWM_MODEn[1] = 1b. The digital
MFR_PWM_MODEn[1] = 1b tested in ATE at V
– V
=
VOSNS0
VOSNS0
0.5V and 3.6V. 1V condition tested at IC-Level, only. Channel 1 OV/UV
OUTn
servo control loop is exercised in production (setting MFR_PWM_
MODEn[6] = 1b), but convergence of the output voltage to its final settling
value is not necessarily observed in final test—due to potentially long
time constants involved—and is instead guaranteed by the output voltage
readback accuracy specification. Evaluation in application demonstrates
capability; see the Typical Performance Characteristics section.
comparator threshold accuracy for MFR_PWM_MODEn[1] = 1b tested
in ATE with V
-V
= 0.5V and 3.6V. 1.5V condition tested at
VOSNS1 SGND
IC-level, only. MFR_PWM_MODEn[1] = 1b is the Low Range.
Note 15: Tested at IC-level ATE.
Note 16: The LTM4678 quiescent current (I ) equals the I of V plus
Q
Q
IN
the I of EXTV
.
CC
Q
Note 6: See output current derating curves for different V , V , and T ,
IN OUT
A
Note 17: The LTM4678’s EEPROM temperature range for valid write
commands is 0°C to 85°C. To achieve guaranteed EEPROM data retention,
execution of the “STORE_USER_ALL” command—i.e., uploading RAM
contents to NVM—outside this temperature range is not recommended.
However, as long as the LTM4678’s EEPROM temperature is less than
130°C, the LTM4678 will obey the STORE_USER_ALL command. Only
when EEPROM temperature exceeds 130°C, the LTM4678 will not act
on any STORE_USER_ALL transactions: instead, the LTM4678 NACKs
the serial command and asserts its relevant CML (communications,
memory, logic) fault bits. EEPROM temperature can be queried prior
to commanding STORE_USER_ALL; see the Applications Information
section.
located in the Applications Information section.
Note 7: Even though V and V are specified for 6V absolute
OUT0
OUT1
maximum, the maximum recommended command voltage to regulate
output channels 0 and 1 is: 3.6V with V
the MFR_PWM_MODE[1] = 0b.
range-setting bit is set using
OUT
Note 8: Minimum on-time is tested at wafer sort.
Note 9: The data conversion is done by default in round robin fashion. All
inputs signals are continuously converted for a typical latency of 90ms.
Setting MFR_ADC_CONTRL value to be 0 to 12, LTM4678 can do fast
data conversion with only 8ms to 10ms. See section PMBus Command
for details.
Note 18: The LTM4678 includes overtemperature protection that is
intended to protect the device during momentary overload conditions.
Junction temperature will exceed 125°C when overtemperature protection
is active. Continuous operation above the specified maximum operating
junction temperature may impair device reliability.
Note 10: The following telemetry parameters are formatted in PMBus-
defined “Linear Data Format”, in which each register contains a word
comprised of 5 most significant bits—representing a signed exponent, to
be raised to the power of 2—and 11 least significant bits—representing
a signed mantissa: input voltage (on SV ), accessed via the READ_VIN
IN
command code; output currents (I
command codes; module input current (I
), accessed via the READ_IOUTn
OUTn
+ I
VIN1
+ I ), accessed via
SVIN
ꢀꢁ
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
VIN0
the READ_IIN command code; channel input currents (I
accessed via the MFR_READ_IINn command codes;and duty cycles of
channel 0 and channel 1 switching power stages, accessed via the
+ 1/2 • I
),
SVIN
VINn
READ_DUTY_CYCLE command codes. This data format limits the
n
resolution of telemetry readback data to 10 bits even though the internal
ADC is 16 bits and the LTM4678’s internal calculations use 32-bit words.
Note 11: The absolute maximum rating for the SV pin is 18V. Input
IN
voltage telemetry (READ_VIN) is obtained by digitizing a voltage scaled
down from the SV pin.
IN
Note 12: These typical parameters are based on bench measurements
and are not production tested. Improved output current readback can
be achieved by evaluating the system using the LTM4678. Evaluating
the ambient temperature and the module inductor temperature for each
0
0
ꢀ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ ꢄ0ꢅ
Figure 1. Programmable RCOMP
Rev 0
11
For more information www.analog.com
LTM4678
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C.
Single Output Efficiency,
5VIN, VIN = SVIN = EXTVCC = 5V
CCM Mode
Single Output Efficiency,
8VIN, VIN = SVIN = 8V,
EXTVCC = 5V, CCM Mode
ꢀ00
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀ00
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
0ꢀꢁꢂꢃ ꢄꢅ0ꢆꢇꢈ
0ꢀꢁꢂꢃ ꢄꢅ0ꢆꢇꢈ
ꢉꢀ0ꢂꢃ ꢄꢅ0ꢆꢇꢈ
ꢉꢀꢊꢂꢃ ꢄꢅ0ꢆꢇꢈ
ꢉꢀꢅꢂꢃ ꢅ00ꢆꢇꢈ
ꢉꢀꢋꢂꢃ ꢅꢌꢅꢆꢇꢈ
ꢊꢀꢅꢂꢃ ꢅꢌꢅꢆꢇꢈ
ꢄꢀꢄꢂꢃ ꢅ00ꢆꢇꢈ
ꢉꢀ0ꢂꢃ ꢄꢅ0ꢆꢇꢈ
ꢉꢀꢊꢂꢃ ꢄꢅ0ꢆꢇꢈ
ꢉꢀꢅꢂꢃ ꢅ00ꢆꢇꢈ
ꢉꢀꢋꢂꢃ ꢅꢌꢅꢆꢇꢈ
ꢊꢀꢅꢂꢃ ꢅꢌꢅꢆꢇꢈ
ꢄꢀꢄꢂꢃ ꢌꢅ0ꢆꢇꢈ
0
ꢀ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
0
ꢀ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢃ ꢄ0ꢅ
ꢀꢁꢂꢃ ꢄ0ꢅ
Dual Phase Single Output
Efficiency, 12VIN, VIN = SVIN = 12V,
EXTVCC = 5V, VOUT0 and VOUT1
Paralleled CCM Mode
Single Output Efficiency,
VIN = SVIN = 12V, EXTVCC = 5V
ꢀ00
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀ00
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
0ꢀꢁꢂꢃ ꢄꢅ0ꢆꢇꢈ
ꢉꢀ0ꢂꢃ ꢄꢅ0ꢆꢇꢈ
ꢉꢀꢊꢂꢃ ꢄꢅ0ꢆꢇꢈ
ꢉꢀꢅꢂꢃ ꢅ00ꢆꢇꢈ
ꢉꢀꢋꢂꢃ ꢅꢌꢅꢆꢇꢈ
ꢊꢀꢅꢂꢃ ꢅꢌꢅꢆꢇꢈ
ꢄꢀꢄꢂꢃ ꢌꢅ0ꢆꢇꢈ
ꢀꢁ0ꢀꢀ ꢁꢂ0ꢃꢄꢅ
ꢀꢁꢂꢀꢀ ꢁ00ꢂꢃꢄ
ꢀꢁꢂꢀꢀ ꢁꢂꢃꢄꢅꢆ
ꢀꢁꢀꢀꢀ ꢁꢂ0ꢃꢄꢅ
0
ꢀ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
0
ꢀ
ꢀ0 ꢀꢁ ꢀ0 ꢀꢁ ꢀ0 ꢀꢁ ꢀ0 ꢀꢁ ꢀ0
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢃ ꢄ0ꢅ
ꢀꢁꢂꢃ ꢄ0ꢀ
Rev 0
12
For more information www.analog.com
LTM4678
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.
Single Channel Load Transient
Response 50% to 100% Load Step,
12A/µs 12VIN to 0.9VOUT
Single Channel Load Transient
Response 50% to 100% Load Step,
12A/µs 12VIN to 1.2VOUT
Single Channel Load Transient
Response 50% to 100% Load
Step, 12A/µs 12VIN to 1.5VOUT
50mV/DIV
50mV/DIV
50mV/DIV
LOAD STEP
5A/DIV
LOAD STEP
5A/DIV
LOAD STEP
5A/DIV
4678 G05
4678 G06
4678 G07
50µs/DIV
50µs/DIV
50µs/DIV
FIGURE 46 CIRCUIT, 12V TO 0.9V, FREQ = 350kHz
FIGURE 46 CIRCUIT, 12V TO 1.2V, FREQ = 500kHz
FIGURE 46 CIRCUIT, 12V TO 1.5V, FREQ = 500kHz
C
= 470µF ×2 POSCAP, 100µF ×2 CERAMIC
= 11kΩ, EA-GM = 1ms,
C
= 470µF ×2 POSCAP, 100µF ×2 CERAMIC
= 7kΩ, EA-GM = 1ms,
C
= 470µF ×2 POSCAP, 100µF ×2 CERAMIC
= 7kΩ, EA-GM = 1ms,
OUT
OUT
OUT
R
COMP
R
COMP
R
COMP
COMPna = 1500pF, COMPnb = 150pF
COMPna = 1500pF, COMPnb = 150pF
COMPna = 1500pF, COMPnb = 150pF
Single Channel Load Transient
Response 50% to 100% Load Step,
12A/µs 12VIN to 1.8VOUT
Dual Output Concurrent Rail,
Start-Up/Shut Down
Dual Output Concurrent Rail,
Start-Up/Shut Down, Pre-Bias
ꢀ
ꢅ ꢄꢆꢇꢀ
ꢁꢂꢃꢄ
ꢀ
ꢅ ꢄꢆꢇꢀ
ꢁꢂꢃꢄ
ꢈ00ꢉꢀꢊꢋꢌꢀ
50mV/DIV
ꢈ00ꢉꢀꢊꢋꢌꢀ
ꢀ
ꢅ ꢄꢀ
ꢀ
ꢅ ꢄꢀ
ꢁꢂꢃ0
ꢁꢂꢃ0
ꢈ00ꢉꢀꢊꢋꢌꢀ
ꢈ00ꢉꢀꢊꢋꢌꢀ
LOAD STEP
5A/DIV
ꢌ
ꢅ ꢄꢇꢍ
ꢌ
ꢅ ꢍꢈꢎ
ꢁꢂꢃ0
ꢁꢂꢃ0
ꢈꢍꢊꢋꢌꢀ
ꢄ0ꢎꢊꢋꢌꢀ
Rꢂꢎ0ꢅ Rꢂꢎꢄ
ꢈꢀꢊꢋꢌꢀ
Rꢂꢏ0ꢅ Rꢂꢏꢄ
ꢈꢀꢊꢋꢌꢀ
ꢔꢕꢝꢇ ꢒ0ꢜ
4678 G08
ꢔꢕꢤꢇ ꢒꢄ0
ꢏꢉꢐꢊꢋꢌꢀ
50µs/DIV
ꢍꢉꢐꢊꢋꢌꢀ
ꢑꢌꢒꢂRꢓ ꢔꢕ ꢖꢌRꢖꢂꢌ ꢅ ꢄꢏꢀ ꢅ ꢄꢇꢍ ꢗꢁꢍꢋ ꢀ
ꢅ
FIGURE 46 CIRCUIT, 12V TO 1.8V, FREQ = 575kHz
ꢑꢌꢒꢂRꢓ ꢔꢕ ꢖꢌRꢖꢂꢌ ꢅ ꢄꢍꢀ ꢅ ꢍꢈꢎ ꢗꢁꢎꢋ ꢀ
ꢅ
ꢌꢎ
ꢁꢂꢃ0
ꢌꢏ
ꢁꢂꢃ0
ꢎꢁ ꢗꢁꢍꢋ ꢀ
ꢁꢂꢃꢄ
C
R
= 470µF ×2 POSCAP, 100µF ×2 CERAMIC
= 11kΩ, EA-GM = 1ms,
ꢏꢁ ꢗꢁꢎꢋ ꢀ
ꢅ ꢀ
ꢘRꢓꢙꢚꢌꢎꢛꢓꢋ ꢃꢁ ꢈ00ꢉꢀ
OUT
COMP
ꢁꢂꢃꢄ ꢁꢂꢃꢄ
ꢃꢁꢎꢘRꢌꢙꢓ0 ꢚ ꢛꢉꢐ
ꢃꢁꢎꢘRꢌꢙꢓꢄ ꢚ ꢈꢆꢏꢜꢝꢉꢐ
ꢃꢜRꢁꢂꢒꢜ ꢎ ꢋꢌꢁꢋꢓ ꢝꢘRꢓꢙꢚꢌꢎꢛ ꢋꢌꢛꢖꢁꢏꢏꢓꢖꢃꢓꢋ
ꢎꢃ ꢛꢜꢂꢃꢙꢋꢁꢞꢏꢟ
ꢃꢁꢎꢘꢋꢓꢗꢍꢞ0 ꢚ ꢏꢆꢔꢛꢉꢐ ꢃꢁꢑꢑꢘꢋꢓꢗꢍꢞꢄ ꢚ 0ꢉꢐ
COMPna = 1500pF, COMPnb = 150pF
ꢃꢁꢎꢘꢑꢍꢗꢗ0 ꢚ ꢛꢉꢐ
ꢃꢁꢎꢘꢑꢍꢗꢗꢄ ꢚ ꢈꢆꢛꢏꢇꢉꢐ
ꢃꢁꢏꢠRꢌꢛꢓ0 ꢡ ꢢꢉꢐ
ꢃꢁꢏꢠRꢌꢛꢓꢄ ꢡ ꢈꢆꢍꢣꢤꢉꢐ
ꢁꢎꢘꢁꢑꢑ ꢖꢁꢎꢑꢌꢒꢎ ꢚ 0ꢟꢄꢑ
ꢃꢁꢏꢠꢋꢓꢗꢎꢥ0 ꢡ ꢍꢆꢔꢢꢉꢐ ꢃꢁꢑꢑꢠꢋꢓꢗꢎꢥꢄ ꢡ 0ꢉꢐ
ꢃꢁꢏꢠꢑꢎꢗꢗ0 ꢡ ꢢꢉꢐ
ꢃꢁꢏꢠꢑꢎꢗꢗꢄ ꢡ ꢈꢆꢢꢍꢇꢉꢐ
ꢁꢏꢠꢁꢑꢑ ꢖꢁꢏꢑꢌꢒꢦ ꢡ 0ꢧꢄꢑ
Single Phase Single Output
Short-Circuit Protection, No Load
Dual Output Concurrent Rail,
Start-Up/Shut Down, Pre-Bias
Single Phase Single Output
Short-Circuit Protection, 18A Load
ꢀ
ꢅ ꢄꢆꢇꢀ
ꢁꢂꢃꢄ
ꢀ
ꢀ
ꢈ00ꢉꢀꢊꢋꢌꢀ
ꢁꢂꢃ0
ꢁꢂꢃ0
ꢄ00ꢅꢀꢆꢇꢈꢀ
ꢄ00ꢅꢀꢆꢇꢈꢀ
ꢀ
ꢅ ꢄꢀ
ꢁꢂꢃ0
ꢈ00ꢉꢀꢊꢋꢌꢀ
ꢌ
ꢅ ꢍꢈꢎ
ꢁꢂꢃ0
ꢄ0ꢎꢊꢋꢌꢀ
ꢈ
ꢈ
ꢈꢉ
ꢈꢉ
ꢊꢋꢆꢇꢈꢀ
ꢊꢋꢆꢇꢈꢀ
Rꢂꢏ0ꢅ Rꢂꢏꢄ
ꢈꢀꢊꢋꢌꢀ
ꢔꢕꢤꢇ ꢒꢄꢄ
ꢑꢒꢞꢝ ꢏꢕꢊ
ꢑꢒꢞꢖ ꢏꢕꢟ
ꢍꢉꢐꢊꢋꢌꢀ
ꢊ0ꢌꢍꢆꢇꢈꢀ
ꢊ0ꢌꢍꢆꢇꢈꢀ
ꢑꢌꢒꢂRꢓ ꢔꢕ ꢖꢌRꢖꢂꢌ ꢅ ꢄꢍꢀ ꢅ ꢍꢈꢎ ꢗꢁꢎꢋ ꢀ
ꢁꢂꢃꢄ ꢁꢂꢃꢄ
ꢈ00ꢉꢀ ꢃꢜRꢁꢂꢒꢜ ꢎ ꢋꢌꢁꢋꢓ
ꢝꢘRꢓꢙꢚꢌꢎꢛ ꢋꢌꢛꢖꢁꢏꢏꢓꢖꢃꢓꢋ ꢎꢃ ꢛꢜꢂꢃꢙꢋꢁꢞꢏꢟ
ꢃꢁꢏꢠRꢌꢛꢓ0 ꢡ ꢢꢉꢐ ꢃꢁꢏꢠRꢌꢛꢓ0 ꢡ ꢈꢆꢍꢣꢤꢉꢐ
ꢃꢁꢏꢠꢋꢓꢗꢎꢥ0 ꢡ ꢍꢆꢔꢢꢉꢐ ꢃꢁꢑꢑꢠꢋꢓꢗꢎꢥꢄ ꢡ 0ꢉꢐ
ꢅ
ꢎꢈꢏꢂRꢐ ꢑꢒ ꢓꢈRꢓꢂꢈ ꢔ ꢕꢊꢀ ꢔ ꢉꢁ ꢖꢁꢋꢇ ꢀ
ꢔ
ꢎꢈꢏꢂRꢐ ꢑꢒ ꢓꢈRꢓꢂꢈ ꢔ ꢕꢊꢀ ꢔ ꢕꢖꢋ ꢗꢁꢋꢇ ꢀ
ꢔ
ꢌꢏ
ꢁꢂꢃ0
ꢈꢉ
ꢁꢂꢃ0
ꢈꢉ
ꢁꢂꢃ0
ꢏꢁ ꢗꢁꢎꢋ ꢀ
ꢅ ꢀ
ꢘRꢓꢙꢚꢌꢎꢛꢓꢋ ꢃꢁ
ꢗRꢈꢁR ꢃꢁ ꢋꢗꢗꢖꢈꢓꢋꢃꢈꢁꢉ ꢁꢎ ꢘꢙꢁRꢃꢚꢓꢈRꢓꢂꢈꢃ
ꢂꢘꢐ ꢙꢈꢏꢙ Rꢋꢉꢏꢐ ꢁꢎ ꢈ ꢖꢈꢛꢈꢃ ꢘꢜꢘꢃꢐꢛ
ꢘꢙꢁRꢃꢚꢓꢈRꢓꢂꢈꢃ ꢂꢘꢈꢉꢏ ꢄ0ꢉ0ꢑꢚꢝꢛ
ꢛꢁꢘꢎꢐꢃ ꢋꢓRꢁꢘꢘ ꢁꢂꢃꢗꢂꢃ
ꢘRꢈꢁR ꢃꢁ ꢋꢘꢘꢗꢈꢓꢋꢃꢈꢁꢉ ꢁꢎ ꢙꢚꢁRꢃꢛꢓꢈRꢓꢂꢈꢃ
ꢂꢙꢐ ꢚꢈꢏꢚ Rꢋꢉꢏꢐ ꢁꢎ ꢈ ꢗꢈꢜꢈꢃ ꢙꢝꢙꢃꢐꢜ
ꢙꢚꢁRꢃꢛꢓꢈRꢓꢂꢈꢃ ꢂꢙꢈꢉꢏ ꢄ0ꢉ0ꢑꢛꢖꢜ
ꢜꢁꢙꢎꢐꢃ ꢋꢓRꢁꢙꢙ ꢁꢂꢃꢘꢂꢃ
ꢃꢁꢏꢠꢑꢎꢗꢗ0 ꢡ ꢢꢉꢐ
ꢁꢏꢠꢁꢑꢑ ꢖꢁꢏꢑꢌꢒꢦ ꢡ 0ꢧꢄꢑ
ꢃꢁꢏꢠꢑꢎꢗꢗꢄ ꢡ ꢈꢆꢢꢍꢇꢉꢐ
Rev 0
13
For more information www.analog.com
LTM4678
TA = 25°C, 12VIN to 1VOUT, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current vs Load Current
Comparison, RSENSE = 4mΩ,
12V to 1.0VOUT, 350kHz
Supply Current vs Load Current
Comparison, RSENSE = 4mΩ,
12V to 1.5VOUT,500kHz
Supply Current vs Load Current
Comparison, RSENSE = 4mΩ,
12V to 2.5VOUT, 575kHz
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READ_IOUT of 8 LTM4678 Channels
(DC2570A) 12VIN, 1VOUT
TJ = –40°C, IOUTn = 40A, System
Having Reached Thermally Steady-
State Condition, No Airflow
READ_IOUT of 8 LTM4678 Channels
(DC2570A) 12VIN, 1VOUT
TJ = 25°C, IOUTn = 40A, System
Having Reached Thermally Steady-
State Condition, No Airflow
READ_IOUT of 8 LTM4678 Channels
(DC2570A) 12VIN, 1VOUT
TJ = 125°C, IOUTn = 40A, System
Having Reached Thermally Steady-
State Condition, No Airflow
,
,
,
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0
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Rꢀꢁꢂꢃꢄꢅꢆꢇ ꢈꢉꢁꢊꢊꢀꢋ Rꢀꢁꢂꢌꢁꢈꢍ ꢎꢁꢏ ꢐꢜꢕꢔ ꢝꢓꢔ
Rꢀꢁꢂꢃꢄꢅꢆꢇ ꢈꢉꢁꢊꢊꢀꢋ Rꢀꢁꢂꢌꢁꢈꢍ ꢎꢁꢏ ꢓꢛꢜꢔ ꢝꢗꢑ
Rev 0
14
For more information www.analog.com
LTM4678
PIN FUNCTIONS
PACKAGE ROW AND COLUMN LABELING MAY VARY
SGND (F9-10, G9-10): SGND is the signal ground return
path of the LTM4678. SGND is not internally connected to
GND. Connect SGND to GND local to the LTM4678. See
recommended layout.
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
GND (A3-A6, B1, B3-B6, C1-C6, D2-D6, E5-E6, F5-F7,
G5-G8, H5-H8, J2-J6, K2-6, L1, L3-L6, M3-M6): Power
V
(G1-G4, H1-H4): Positive Power Input to Channel 0
IN0
Ground of the LTM4678. Power return for V
and
OUT0
SwitchingStage.Providesufficientdecouplingcapacitance
in the form of multilayer ceramic capacitors (MLCCs) and
low ESR electrolytic (or equivalent) to handle reflected
input current ripple from the step-down switching stage.
MLCCs should be placed as close to the LTM4678 as
physically possible. See Layout Recommendations in the
Applications Information section.
V
. Return input and output capacitors to this point .
OUT1
V
(K7-K11, L7-L12, M7-M10): Channel 0 Output
OUT0
Voltage. Place recommended output capacitors from this
shape to GND. See recommended layout.
+
V
(M11): Channel 0 Positive Differential Voltage
OSNS0
+
–
Sense Input. Together, V
kelvin-sense the V
and V
serve to
’s point
OSNS0
OSNS0
V
IN1
(E1-E4, F1-F4): Positive Power Input to Channel 1
output voltage at V
OUT0
OUT0
Switching Stage. Provide sufficient decoupling capaci-
tance in the form of MLCCs and low ESR electrolytic (or
equivalent)tohandlereflectedinputcurrentripplefromthe
step-down switching stage. MLCCs should be placed as
close to the LTM4678 as physically possible. See Layout
RecommendationsintheApplicationsInformationsection.
of load (POL) and provide the differential feedback signal
directly to channel 0’s feedback loop. Command V ’s
OUT0
target regulation voltage by serial bus. Its initial command
value at SV power-up is dictated by NVM (non-volatile
IN
memory)contents(factorydefault:1.000V)—or,optionally,
may be set by configuration resistors; see VOUT0_CFG
and the Applications Information section.
SW0 (L2, M1-M2): Switching Node of Channel 0 Step-
Down Converter Stage. Used for test purposes or EMI-
snubbing. May be routed a short distance to a local test
point to monitor switching action of channel 0, if desired,
but do not route near any sensitive signals; otherwise,
leave electrically isolated (open).
–
V
(M12): Channel 0 Negative Differential Voltage
OSNS0
+
Sense Input. See V
.
OSNS0
V
(A7-A10, B7-B12, C7-C9, D7): Channel 1 Output
OUT1
Voltage. Place recommended output capacitors from this
shape to GND See recommended layout.
SW1(A1-A2,B2):SwitchingNodeofChannel1Step-Down
ConverterStage.UsedfortestpurposesorEMI-snubbing.
May be routed a short distance to a local test point to
monitor switching action of channel 1, if desired, but do
notroutenearanysensitivesignals;otherwise,leaveopen.
+
V
(A11): Channel 1 Positive Differential Voltage
OSNS1
+
–
Sense Input. Together, V
kelvin-sense the V
and V
serve to
OSNS1
output voltage at V
OSNS1
’s point
OUT1
OUT1
of load (POL) and provide the differential feedback signal
directly to channel 1’s feedback loop. Command V
’s
OUT1
SV (D1):InputSupplyforLTM4678’sInternalControlIC.
target regulation voltage by serial bus. Its initial command
IN
In most applications, SV connects to V and/or V .
value at SV power-up is dictated by NVM (non-volatile
IN
IN0
IN1
IN
SV can be operated from an auxiliary supply separate
memory)contents(factorydefault:1.000V)—or,optionally,
may be set by configuration resistors; see VOUT1_CFG
and the Applications Information section.
IN
from V /V for powering the V /V from a lower
IN0 IN1
IN0 IN1
supply like 3.3V. The SV pin has an onboard 1Ω and 1µF
IN
decoupling capacitor. The 1Ω resistor is used to measure
theactualcontrolchipcurrent.SeeMFR_READ_ICHIPand
MFR_ADC_CONTROLSection.Whenoperatingfrom4.5V
to 5.75V with no auxiliary bias supply, then the main input
–
V
(A12): Channel 1 Negative Differential Voltage
OSNS1
+
Sense Input. See V
.
OSNS1
Rev 0
15
For more information www.analog.com
LTM4678
PIN FUNCTIONS
supplyshouldconnecttoSV andINTV .SeeTestCircuit
internal pull-up resistors connected to the configuration-
programming pins. No external decoupling is required.
IN
CC
2 for an example. In this configuration, the ICHIP current
will not be relevant since INTV is connected to SV .
CC
IN
ASEL (F12): Serial Bus Address Configuration Pin. On
+
2
I
(J1): Positive Current Sense Amplifier Input. If the
any given I C/SMBus serial bus segment, every device
IN
input current sense amplifier is not used, this pin must be
must have its own unique slave address. If this pin is left
open, the LTM4678 powers up to its default slave address
of 0x4F (hexadecimal), i.e., 1001111b (industry-standard
convention is used throughout this document: 7-bit slave
addressing). The lower four bits of the LTM4678’s slave
addresscanbealteredfromthisdefaultvaluebyconnecting
a resistor from this pin to SGND. Minimize capacitance—
especially when the pin is left open—to assure accurate
detection of the pin state.
–
shorted to the I and SV pin. See Applications section
IN
IN
for detail about the input current sensing.
–
I
(K1): Negative Current Sense Amplifier Input. If the
IN
input current sense amplifier is not used, this pin must be
+
shorted to the I and SV pin. See Applications section
IN
IN
for detail about the input current sensing.
EXTV (F8): External Power Input to an Internal Switch
CC
Connected to INTV . This switch closes and supplies the
CC
FSWPH_CFG (E9): Switching Frequency, Channel Phase-
Interleaving Angle and Phase Relationship to SYNC Con-
figuration Pin. If this pin is left open—or, if the LTM4678
is configured to ignore pin-strap (RCONFIG) resistors,
i.e., MFR_CONFIG_ALL[6] = 1b—then LTM4678’s
switching frequency (FREQUENCY_SWITCH) and chan-
nel phase relationships (with respect to the SYNC clock;
ICpower,bypassingtheinternalregulatorwheneverEXTV
CC
is higher than 4.7V and V is higher than 7V. EXTV also
IN
CC
powers up V
when EXTV is higher than 4.7V and
DD33
CC
INTV is lower than 3.8V. Do not exceed 6V on this pin.
CC
Decouple this pin to PGND with a minimum of 4.7µF low
ESRtantalumorceramiccapacitor. IftheEXTV pinisnot
CC
used to power INTV , the EXTV pin must be tied GND.
CC
CC
MFR_PWM_CONFIG[2:0]) are dictated at SV power-up
IN
INTV (E7) : Internal Regulator, 5.5V Output. When
accordingtotheLTM4678’sNVMcontents.Defaultfactory
values are: 575kHz operation; channel 0 at 0°; and chan-
nel 1 at 180°C (convention throughout this document: a
phase angle of 0° means the channel’s switch node rises
coincident with the falling edge of the SYNC pulse). Con-
necting a resistor from this pin to SGND (and using the
factory-defaultNVMsettingofMFR_CONFIG_ALL[6]=0b)
allows a convenient way to configure multiple LTM4678s
withidenticalNVMcontentsfordifferentswitchingfrequen-
cies of operation and phase interleaving angle settings of
intra- and extra-module-paralleled channels—all, without
GUI intervention or the need to “custom pre-program”
module NVM contents. (See the Applications Information
section.) Minimize capacitance—especially when the pin
is left open—to assure accurate detection of the pin state.
CC
operating the LTM4678 from 5.75V ≤ SV ≤ 16V, an
IN
LDO generates INTV from SV to bias internal control
CC
IN
circuits and the MOSFET drivers of the LTM4678. An
external 2.2µF ceramic decoupling is required. INTV is
CC
regulated regardless of the RUNn pin state. When operat-
ing the LTM4678 with 4.5V ≤ SV < 5.75V, INTV must
IN
CC
be electrically shorted to SV .
IN
V
(E8):InternallyGenerated3.3VPowerSupplyOutput
DD33
Pin.Thispinshouldonlybeusedtoprovideexternalcurrent
forthepull-upresistorsrequiredforFAULTn,SHARE_CLK,
and SYNC, and may be used to provide external current
for pull-up resistors on RUNn, SDA, SCL, ALERT and
PGOODn. No external decoupling is required.
V
(D12):InternallyGenerated2.5VPowerSupplyOut-
DD25
VOUT0_CFG (E11): Output Voltage Select Pin for V
,
OUT0
putPin. Donotloadthispinwithexternalcurrent;itisused
Coarse Setting. If the VOUT0_CFG and VTRIM0_CFG
pins are both left open—or, if the LTM4678 is con-
figured to ignore pin-strap (RCONFIG) resistors, i.e.,
strictly to bias internal logic and provides current for the
Rev 0
16
For more information www.analog.com
LTM4678
PIN FUNCTIONS
MFR_CONFIG_ALL[6] = 1b—then the LTM4678s target
VTRIM1_CFG pins affect the respective settings of V
/
OUT1
channel 1. (See VOUT1_CFG, VTRIM1_CFG and the Ap-
plications Information section.) Minimize capacitance—
especially when the pin is left open—to assure accurate
detection of the pin state. Note that use of RCONFIGs on
V
output voltage setting (VOUT_COMMAND0) and
OUT0
associated power-good and OV/UV warning and fault
thresholds are dictated at SV power-up according to
IN
the LTM4678’s NVM contents. A resistor connected
from this pin to SGND—in combination with resistor pin
settings on VTRIM0_CFG, and using the factory-default
NVM setting of MFR_CONFIG_ALL[6] = 0b—can be used
to configure the LTM4678’s channel 0 output to power-up
to a VOUT_COMMAND value (and associated output volt-
agemonitoringandprotection/fault-detectionthresholds)
different from those of NVM contents. (See the Applica-
tions Information section.) Connecting resistor(s) from
VOUT0_CFG to SGND and/or VTRIM0_CFG to SGND in
this manner allows a convenient way to configure multiple
LTM4678swithidenticalNVMcontentsfordifferentoutput
voltage settings all without GUI intervention or the need
to“custom-preprogram”moduleNVMcontents.Minimize
capacitance especially when the pin is left open to assure
accurate detection of the pin state. Note that use of RCON-
VOUT1_CFG/VTRIM1_CFG can affect the V
range
OUT1
setting (MFR_PWM_MODE1[1]) and loop gain.
VTRIM0_CFG (C12): Output Voltage Select Pin for V
,
OUT0
Fine Setting. Works in combination with VOUT0_CFG to
affect the VOUT_COMMAND (and associated output volt-
agemonitoringandprotection/fault-detectionthresholds)
of channel 0, at SV power-up. (See VOUT0_CFG and the
IN
ApplicationsInformationsection.)Minimizecapacitance—
especially when the pin is left open—to assure accurate
detection of the pin state. Note that use of RCONFIGs on
VOUT0_CFG/ VTRIM0_CFG can affect the V
range
OUT0
setting (MFR_PWM_MODE0[1]) and loop gain.
RUN0, RUN1 (G12, F11 Respectively): Enable Run Input
for Channels 0 and 1, Respectively. Open-drain input and
output. Logic high on these pins enables the respective
outputs of the LTM4678. These open-drain output pins
FIGs on VOUT0_CFG/VTRIM0_CFG can affect the V
range setting (MFR_PWM_MODE0[1]) and loop gain.
OUT0
hold the pin low until the LTM4678 is out of reset and SV
IN
VTRIM1_CFG (E10): Output Voltage Select Pin for V
,
OUT1
is detected to exceed V . A pull-up resistor to 3.3V
IN_ON
Fine Setting. Works in combination with VOUT1_CFG to
affect the VOUT_COMMAND (and associated output volt-
agemonitoringandprotection/fault-detectionthresholds)
is required in the application. The LTM4678 pulls RUN0
and/or RUN1 low, as appropriate, when a global fault and/
or channel-specific fault occurs whose fault response is
of channel 1, at SV power-up. (See VOUT1_CFG and the
IN
configured to latch off and cease regulation; issuing a
Applications Information section.) Minimize capacitance
especially when the pin is left open to assure accurate
detection of the pin state. Note that use of RCONFIGs on
2
CLEAR_FAULTS command via I C or power-cycling SV
IN
is necessary to restart the module, in such cases. Do not
pull RUN logic high with a low impedance source.
VOUT1_CFG/VTRIM1_CFG can affect the V
setting (MFR_PWM_MODE1[1]) and loop gain.
range
OUT1
PGOOD0/PGOOD1(J7/D9):PowerGoodIndicatorOutputs.
Open-drain logic output that is pulled to ground when the
output exceeds the UV and OV regulation window. The
output is deglitch by an internal 100µs filter. A pull-up
resistor to 3.3V is required in the application.
VOUT1_CFG (E12): Output Voltage Select Pin for V
,
OUT1
Coarse Setting. If the VOUT1_CFG and VTRIM1_CFG
pins are both left open or, if the LTM4678 is configured to
ignore pin-strap (R
) resistors, i.e., MFR_CONFIG_
CONFIG
FAULT0/FAULT1 (H12/G11): Digital Programmable FAULT
Inputs and Outputs. Open-drain output. A pull-up resistor
to 3.3V is required in the application.
ALL[6] = 1b then the LTM4678’s target V
output
OUT1
voltage setting (VOUT_COMMAND1) and associated
OV/UV warning and fault thresholds are dictated at SV
IN
power-up according to the LTM4678’s NVM contents,
in precisely the same fashion that the VOUT1_CFG and
Rev 0
17
For more information www.analog.com
LTM4678
PIN FUNCTIONS
COMP0b/COMP1b (H9/C10): Current Control Threshold
andErrorAmplifierCompensationNodes.Eachassociated
channel’scurrentcomparatortrippingthresholdincreases
with its compensation voltage. Each channel has a 22pF
to SGND.
stretching is enabled, SCL becomes a bidirectional, open-
drain output pin on LTM4678.
SDA (H10): Serial Bus Data Open-Drain Input and Output.
A pull-up resistor to 3.3V is required in the application.
ALERT(H11):Open-DrainDigitalOutput.Apull-upresistor
to 3.3V is required in the application only if SMBALERT
interruptdetectionisimplementedinone’sSMBussystem.
COMP0a/COMP1a (J9/D10): Loop Compensation Nodes.
The internal PWM loop compensation resistors R
COMPn
of the LTM4678 can be adjusted using bit[4:0] of the
MFR_PWM_COMP command. The transconductance of
the LTM4678 PWM error amplifier can be adjusted using
bit[7:5] of the MFR_PWM_COMP command. These two
loopcompensationparameterscanbeprogrammedwhen
device is in operation. Refer to the Programmable Loop
Compensation subsection in the Applications Information
section for further details. See Figure 1.
SHARE_CLK(D11):ShareClock,BidirectionalOpen-Drain
ClockSharingPin.Nominally100kHz.Usedforsynchroniz-
ing the time base between multiple LTM4678s (and any
otherAnalogDevicesdeviceswithaSHARE_CLKpin)—to
realize well-defined rail sequencing and rail tracking. Tie
the SHARE_CLK pins of all such devices together; all
devices with a SHARE_CLK pin will synchronize to the
fastest clock. A pull-up resistor to 3.3V is only required
when synchronizing the time base between devices.
SYNC (K12): External Clock Synchronization Input and
Open-Drain Output Pin. If an external clock is present at
this pin, the switching frequency will be synchronized to
the external clock. If clock master mode is enabled, this
pin will pull low at the switching frequency with a 500ns
pulse to ground. A resistor pull-up to 3.3V is required in
the application if the LTM4678 is the master.
TSNS0a, TSNS0b (J11 and J8, Respectively): Channel
0 Temperature Excitation/Measurement and Thermal
Sensor Pins, Respectively. Connect TSNS0a to TSNS0b.
This allows the LTM4678 to monitor the power stage
temperature of channel 0.
TSNS1a, TSNS1b (J10 and D8, Respectively): Channel 1
TemperatureExcitation/MeasurementandThermalSensor
Pins, Respectively. In most applications, connect TSNS1a
toTSNS1b.ThisallowstheLTM4678tomonitorthepower
stage temperature of channel 1. See the Applications sec-
tion for information on how to use TSNS1a to monitor an
external temperature sensor.
SCL (J12): Serial Bus Clock Open-Drain Input (Can Be
an Input and Output, if Clock Stretching is Enabled). A
pull-up resistor to 3.3V is required in the application
for digital communication to the SMBus master(s) that
nominally drive this clock. The LTM4678 will never en-
counter scenarios where it would need to engage clock
stretching unless SCL communication speeds exceed
100kHz—and even then, LTM4678 will not clock stretch
unless clock stretching is enabled by means of setting
MFR_CONFIG_ALL[1] = 1b. The factory-default NVM
configuration setting has MFR_CONFIG_ALL[1] = 0b:
clock stretching disabled. If communication on the bus at
clock speeds above 100kHz is required, the user’s SMBus
master(s) needs to implement clock stretching support
to assure solid serial bus communications, and only then
should MFR_CONFIG_ALL[1] be set to 1b. When clock
WP (C11): Write Protect Pin, Active High. An internal
10µA current source pulls this pin to V
. If WP is
DD33
2
open circuit or logic high, only I C writes to PAGE, OP-
ERATION, CLEAR_FAULTS, MFR_CLEAR_PEAKS and
MFR_EE_UNLOCK are supported. Additionally, Individual
faults can be cleared by writing 1b’s to bits of interest in
2
registers prefixed with “STATUS”. If WP is low, I C writes
are unrestricted.
Rev 0
18
For more information www.analog.com
LTM4678
SIMPLIFIED BLOCK DIAGRAM
R
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ꢀꢁ ꢂꢃꢂꢄꢁꢅ
Rꢆꢂꢇꢈꢂꢉꢊ
ꢀ ꢄꢂRRꢅꢆꢃ ꢇꢅꢆꢇꢅ
ꢁꢂꢃ0
ꢀ
ꢄꢂRRꢅꢆꢃ ꢇꢅꢆꢇꢅ
ꢁꢂꢃ0
ꢀꢁꢂꢁ0ꢃ
ꢀꢁꢂꢁꢃꢄ
ꢀꢁꢂꢃ ꢂꢄꢅ
ꢄ
ꢅ
ꢀ
ꢀ
ꢁꢂꢃꢂ0
ꢁꢂꢃꢂꢄ
Rꢀꢁꢂꢃꢀ ꢄꢀꢅꢄꢀ
ꢀꢁ
ꢀꢁꢂꢃ0
ꢀ
ꢀꢁ
ꢀ
ꢀꢁꢂꢃꢄ
ꢁꢂꢃꢄ0
Rꢀꢁꢂꢃꢀ ꢄꢀꢅꢄꢀ
ꢁꢂꢃꢄꢅ
ꢀꢁꢁ ꢀꢂꢀꢁꢃꢄ
Rꢅꢀꢆꢇꢀꢈꢉ ꢊꢋꢄꢂꢀꢁꢊ
ꢄ
ꢅ
ꢀ
ꢁꢂꢃꢂ0
ꢀ
ꢁꢂꢃꢂꢄ
ꢀRꢁꢂ ꢂꢃ
ꢀRꢁꢂ ꢂꢃ
ꢀ0ꢁꢀ ꢂꢃꢄ
ꢀꢁ0
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂꢃ0ꢄ
ꢀꢀꢁꢂ
ꢀꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅ
ꢀRꢁꢂ R
ꢃꢁꢄꢀ
ꢀRꢁꢂ R
ꢃꢁꢄꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂ
ꢀꢁꢂꢃ0ꢄ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢂꢃ0
ꢀꢁꢂꢂꢃꢄ
ꢀꢁꢀꢂ
ꢀꢁꢂ ꢀꢃꢄꢅꢆ
ꢀꢁꢂꢃ
ꢃꢄꢅꢆRꢇꢈꢃ ꢉꢊꢅꢅꢋꢊꢉ
ꢈꢄꢃ ꢌꢍꢄꢎꢈ
ꢀꢁꢂꢃR ꢄꢁꢅꢆRꢁꢇ ꢈꢉꢊꢉꢆꢋꢇ ꢌꢃꢄꢆꢉꢁꢅ
ꢀ
ꢀꢁꢂ
ꢁꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢀꢂꢃ
ALERT
ꢀꢁꢀꢂꢃꢄꢅꢆꢇRꢈꢉꢄ
ꢊꢋꢆꢆꢃꢋꢊ ꢉꢅꢄ
ꢌꢍꢅꢎꢉ
ꢀꢁꢂ ꢃꢄꢀꢅꢆR
ꢀꢁ
Rꢀꢁ
ꢀꢁꢂꢃ ꢄRꢅꢆꢇR
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄꢅꢆꢀꢇ
Rꢀꢁ0
ꢀꢁꢂꢁꢃꢄꢅ ꢆꢇꢂꢁꢇꢆ
Rꢀꢁ
ꢀꢁꢂꢃꢄ ꢅꢆꢇ
ꢀ
ꢁRꢂꢃ0ꢄꢅꢆꢇ
Rꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅ RꢆꢇꢄꢇꢈꢁRꢇ
ꢈꢁ ꢉꢊꢋꢌ ꢇꢅꢂꢍ ꢂꢁꢈ ꢇꢎꢁꢏꢂ
ꢀ
ꢁRꢂꢃ0ꢄꢅꢆꢇꢈ
FAULT0
ꢀꢀꢁRꢂꢃ
ꢀꢁꢀꢂꢃꢄꢅꢆꢇRꢈꢉꢄ
ꢊꢋꢆꢆꢃꢋꢊ ꢉꢅꢄ
ꢌꢍꢅꢎꢉ
ꢀ
ꢁꢂꢃ0ꢄꢅꢆꢇ
FAULT1
ꢀꢁꢂRꢃꢄꢅꢆꢇ
ꢀ
ꢁꢂꢃꢄꢅꢆꢇꢈ
0
Figure 2. Simplified LTM4678 Block Diagram
TA = 25°C. Using Figure 1 configuration.
CONDITIONS
DECOUPLING REQUIREMENTS
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
C
External High Frequency Input Capacitor Requirement
I
I
= 25A
= 25A
66
66
µF
µF
INH
OUT0
OUT1
(5.75V ≤ V ≤ 16V, V
Commanded to 1.000V)
OUTn
IN
C
External High Frequency Output Capacitor Requirement
(5.75V ≤ V ≤ 16V, V Commanded to 1.000V)
I
I
= 25A
= 25A
400
400
µF
µF
OUTn
OUT0
OUT1
IN
OUTn
Rev 0
19
For more information www.analog.com
LTM4678
FUNCTIONAL DIAGRAM
ꢀꢁꢂꢃ
ꢀꢁꢂ0
ꢀꢁꢂꢃ
ꢀ
ꢁꢂꢃꢄ
ꢁꢂꢃꢄ
ꢁꢂꢃꢄ
ꢁꢂꢃꢄ
ꢀ
ꢀ
ꢀ
ꢀ
ꢁꢂ
ꢀ
ꢁꢂꢀꢃ
ꢀ
ꢀꢁ
Figure 3. Functional LTM4678 Block Diagram
Rev 0
20
For more information www.analog.com
LTM4678
TEST CIRCUITS
Test Circuit 1. LTM4678 ATE High VIN Operating Range Configuration, 5.75V ≤ VIN ≤ 16V
ꢀꢁꢀꢂꢃ
ꢀꢁ0
ꢀ
ꢀꢁꢂꢀꢃ ꢄꢅ ꢆꢇꢃ
ꢀꢁ0ꢂꢃ
ꢁꢂ
ꢂ
ꢀ
ꢀꢁ
ꢀ
ꢁꢂꢃ0
R
ꢀꢁꢂꢀꢁ
ꢀ
ꢁꢂꢃ0
ꢄ
ꢄ ꢅ ꢆꢇꢈꢂꢉꢃꢆꢊꢋꢌ
ꢂ
ꢀ
ꢀ
ꢀꢁ
ꢁꢂꢃꢂ0
ꢂꢍ ꢃꢁ ꢎꢏꢎꢀ ꢆꢃ ꢐꢑꢆ
ꢀ00ꢁꢂ
ꢃꢄ
ꢀꢁꢂꢃ0
ꢀꢀꢁꢂ
ꢃꢄ
ꢄ
ꢀ
ꢁꢂꢃ
ꢀ
ꢁꢂꢃꢂ0
ꢀ
ꢄ ꢅꢂꢆꢇ
ꢁꢂꢃ0
ꢀ
ꢁꢂ0
ꢀꢁꢂ
ꢀꢁ
ꢂꢃ
ꢀ
ꢀꢁ
ꢁꢂꢃꢄ
ꢂꢃ
ꢀ
ꢁꢂꢃꢄ
ꢅ
ꢄ ꢅ ꢆꢇꢈꢂꢉꢃꢆꢊꢋꢌ
ꢂꢍ ꢃꢁ ꢎꢏꢎꢀ ꢆꢃ ꢐꢑꢆ
ꢀ
Rꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅꢆ
ꢁꢂꢃꢂꢄ
ꢀ00ꢁꢂ
ꢃꢄ
ꢀꢁꢂꢀꢃꢃ ꢄꢀꢁꢅRꢀꢆ
ꢀꢁꢂꢃꢄ
Rꢀꢁ0
ꢅ
ꢀ
ꢅ ꢆꢂꢇꢈ
ꢁꢂꢃꢄ
ꢀ
ꢁꢂꢃꢂꢄ
FAULT0
FAULT1
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄ ꢅꢆꢄꢇRRꢂꢈꢄꢉ
ꢀꢁꢂ
ꢀꢁꢂ
ꢁ
ꢀ ꢂꢃꢄꢅꢆꢇꢈ ꢀꢃꢉ ꢊꢀꢋꢌ ꢍꢅꢆꢇꢈ ꢂꢎꢅꢅꢏꢐꢑ ꢄꢒꢋ
ꢀꢁꢂꢃRꢁꢄ ꢅꢆꢄꢅ ꢁR ꢁꢀꢇꢈR ꢉꢁꢊRꢋ
ꢀꢁꢂꢁꢃꢄꢀꢄꢂꢅ ꢆꢇꢂꢅRꢇꢈꢈꢄR
ꢀꢁꢂꢃꢄRꢅꢂꢆꢇꢈꢉꢆꢅꢂ
ꢀꢁꢂꢃꢄꢅꢆꢇꢃ
RꢀꢁꢂꢃꢄꢀR ꢅRꢂꢄꢀ
ꢀRꢁꢂꢃꢄꢂꢅꢁꢆ
ALERT
ꢀꢁꢂRꢃꢄꢅꢆꢇ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁ
ꢅꢆꢇ ꢁ ꢅRꢉ
ꢂꢃꢄꢈ
ꢂꢃꢄ0
ꢂꢊꢄꢋꢂꢆꢅꢌ ꢍꢂR ꢅꢄꢉ ꢄꢉꢎꢄ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢃꢄꢂꢁ RꢅꢆꢇꢆꢈꢉRꢆ ꢉꢊ ꢋꢇꢌꢇꢈꢍꢃ
ꢇꢎꢉ ꢁꢇꢊꢆ ꢊꢉꢈ ꢆꢏꢉꢐꢊꢑ
ꢒꢓꢔꢕ ꢈꢖ0ꢗ
ꢀꢀ00ꢁꢂ
ꢀꢀ00ꢁꢂ
ꢀ00ꢁꢂ
ꢀ00ꢁꢂ
Rev 0
21
For more information www.analog.com
LTM4678
TEST CIRCUITS
Test Circuit 2. LTM4678 ATE Low VIN Operating Range Configuration, 4.5V ≤ VIN ≤ 5.75V
ꢀ
ꢀꢁ
ꢂꢃ
ꢀꢁꢀꢂꢃ
ꢀꢁ0
ꢀ
ꢀꢁꢂꢃ ꢄꢅ ꢂꢁꢆꢂꢃ
ꢀꢁ0ꢂꢃ
ꢁꢂ
ꢂ
ꢀ
ꢀꢁ
ꢀ
ꢁꢂꢃ0
R
ꢀꢁꢂꢀꢁ
ꢀ
ꢁꢂꢃ0
ꢄ
ꢄ ꢅ ꢆꢇꢈꢂꢉꢃꢆꢊꢋꢌ
ꢂ
ꢀ
ꢀ
ꢀꢁ
ꢁꢂꢃꢂ0
ꢂꢍ ꢃꢁ ꢎꢏꢎꢀ ꢆꢃ ꢐꢑꢆ
ꢀ00ꢁꢂ
ꢃꢄ
ꢀꢁꢂꢃ0
ꢀꢀꢁꢂ
ꢃꢄ
ꢄ
ꢀ
ꢁꢂꢃ
ꢀ
ꢁꢂꢃꢂ0
ꢀ
ꢄ ꢅꢂꢆꢇ
ꢁꢂꢃ0
ꢀ
ꢁꢂ0
ꢀꢁꢂ
ꢀꢁ
ꢂꢃ
ꢀ
ꢀꢁ
ꢁꢂꢃꢄ
ꢂꢃ
ꢀ
ꢁꢂꢃꢄ
ꢅ
ꢄ ꢅ ꢆꢇꢈꢂꢉꢃꢆꢊꢋꢌ
ꢂꢍ ꢃꢁ ꢎꢏꢎꢀ ꢆꢃ ꢐꢑꢆ
ꢀ
Rꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅꢆ
ꢁꢂꢃꢂꢄ
ꢀ00ꢁꢂ
ꢃꢄ
ꢀꢁꢂꢀꢃꢃ ꢄꢀꢁꢅRꢀꢆ
ꢀꢁꢂꢃꢄ
Rꢀꢁ0
ꢅ
ꢀ
ꢅ ꢆꢂꢇꢈ
ꢁꢂꢃꢄ
ꢀ
ꢁꢂꢃꢂꢄ
FAULT0
FAULT1
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄ ꢅꢆꢄꢇRRꢂꢈꢄꢉ
ꢀꢁꢂ
ꢀꢁꢂ
ꢁ
ꢀ ꢂꢃꢄꢅꢆꢇꢈ ꢀꢃꢉ ꢊꢀꢋꢌ ꢍꢅꢆꢇꢈ ꢂꢎꢅꢅꢏꢐꢑ ꢄꢒꢋ
ꢀꢁꢂꢃRꢁꢄ ꢅꢆꢄꢅ ꢁR ꢁꢀꢇꢈR ꢉꢁꢊRꢋ
ꢀꢁꢂꢁꢃꢄꢀꢄꢂꢅ ꢆꢇꢂꢅRꢇꢈꢈꢄR
ꢀꢁꢂꢃꢄRꢅꢂꢆꢇꢈꢉꢆꢅꢂ
ꢀꢁꢂꢃꢄꢅꢆꢇꢃ
RꢀꢁꢂꢃꢄꢀR ꢅRꢂꢄꢀ
ꢀRꢁꢂꢃꢄꢂꢅꢁꢆ
ALERT
ꢀꢁꢂRꢃꢄꢅꢆꢇ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁ
ꢅꢆꢇ ꢁ ꢅRꢉ
ꢂꢃꢄꢈ
ꢂꢃꢄ0
ꢂꢊꢄꢋꢂꢆꢅꢌ ꢍꢂR ꢅꢄꢉ ꢄꢉꢎꢄ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢃꢄꢂꢁ RꢅꢆꢇꢆꢈꢉRꢆ ꢉꢊ ꢋꢇꢌꢇꢈꢍꢃ
ꢇꢎꢉ ꢁꢇꢊꢆ ꢊꢉꢈ ꢆꢏꢉꢐꢊꢑ
ꢒꢓꢔꢕ ꢈꢖ0ꢗ
ꢀꢀ00ꢁꢂ
ꢀꢀ00ꢁꢂ
ꢀ00ꢁꢂ
ꢀ00ꢁꢂ
Rev 0
22
For more information www.analog.com
LTM4678
OPERATION
POWER MODULE INTRODUCTION
n
n
Programmable Output Voltage
Programmable Input Voltage On and Off Threshold
Voltage
The LTM4678 is a highly configurable dual 25A output
standalone nonisolated switching mode step-down
DC/DC power supply with built-in EEPROM NVM (non-
volatile memory) with ECC and I C-based PMBus/ SMBus
2-wire serial communication interface capable of 400kHz
SCL bus speed. Two output voltages can be regulated
n
n
n
n
n
n
Programmable Current Limit
2
Programmable Switching Frequency
Programmable OV and UV Threshold voltage
Programmable ON and Off Delay Times
Programmable Output Rise/Fall Times
(V
, V
—collectively, V
) with a few external
OUT0 OUT1
OUTn
inputandoutputcapacitorsandpull-upresistors.Readback
telemetry data of input and output voltages and input and
output currents, and module temperatures are continually
digitizedcyclicallybyanintegrated16-bitADC(analog-to-
digital converter). Many fault thresholds and responses
are customizable. Data can be autonomously saved to
EEPROM when a fault occurs, and the resulting fault log
Phase-Locked Loop for Synchronous PolyPhase
Operation (2, 3, 4 or 6 Phases)
n
n
Nonvolatile Configuration Memory with ECC
Optional External Configuration Resistors for Key
Operating Parameters
2
can be retrieved over I C at a later time, for analysis. See
Figure 2 and Figure 3 for Block Diagrams.
n
Optional Time Base Interconnect for Synchronization
Between Multiple Controllers
POWER MODULE OVERVIEW, MAJOR FEATURES
n
n
WP Pin to Protect Internal Configuration
Major Features Include:
Stand Along Operation After User Factory
Configuration
n
Dedicated Power Good Indicators
n
Direct Input and Chip Current Sensing
n
PMBus, Version 1.2, 400kHz Compliant Interface
n
Programmable Loop Compensation Parameters
The PMBus interface provides access to important power
management data during system operation including:
n
T
Start-Up Time: 30ms
INIT
n
n
n
Internal Controller Temperature
PWM Synchronization Circuit, (See Frequency and
Phasing Section for Details)
n
Internal Power Channel Temperature Average Out-
put Current
MFR_ADC_CONTROL for Fast ADC Sampling of One
Parameter (as Fast as 8ms) (See PMBus Command
for Details)
n
Average Output Voltage
n
Average Input Voltage
n
Fully Differential Output Sensing for Both Channels;
n
Average Input Current
V
/V
Both Programmable Up to 3.6V
OUT0 OUT1
n
Average Chip Input Current from V
n
n
n
n
IN
Power-Up and Program EEPROM with EXTV
Input Voltage Up to 16V
CC
n
Configurable, Latched and Unlatched Individual Fault
and Warning Status
∆V Temperature Sensing
BE
IndividualchannelsareaccessedthroughthePMBususing
the PAGE command, i.e., PAGE 0 or 1.
SYNC Contention Circuit (Refer to Frequency and
Phase Section for Details)
Fault reporting and shutdown behavior are fully configu-
n
Fault Logging
rable.TwoindividualFAULT0,FAULT1outputsareprovided,
both of which can be masked independently.
Rev 0
23
For more information www.analog.com
LTM4678
OPERATION
Three dedicated pins for ALERT, PGOOD0/PGOOD1 func-
tions are provided. The shutdown operation also allows
all faults to be individually masked and can be operated
in either unlatched (hiccup) or latched modes.
The degradation in EEPROM retention for temperatures
>125°C can be approximated by calculating the dimen-
sionless acceleration factor using the following equation:
⎡
⎤
⎥
⎦
⎛
⎞
Ea
k
1
1
⎛
⎞
•
–
⎢
⎜
⎟
⎠
⎜
⎟
AF = e⎣⎝
where:
Individual status commands enable fault reporting over
the serial bus to identify the specific fault event. Fault or
warning detection includes the following:
TUSE+273 TSTRESS+273
⎝
⎠
n
AF = acceleration factor
Output Undervoltage/Overvoltage
Ea = activation energy = 1.4eV
K = 8.617 • 10 eV/°K
n
Input Undervoltage/Overvoltage
–5
n
Input and Output Overcurrent
T
T
= 125°C specified junction temperature
USE
n
Internal Overtemperature
= actual junction temperature in °C
STRESS
n
Communication, Memory or Logic (CML) Fault
Example: Calculate the effect on retention when operating
at a junction temperature of 135°C for 10 hours.
EEPROM WITH ECC
T
T
= 130°C
STRESS
The LTM4678 contains internal EEPROM with ECC (Error
CorrectionCoding)tostoreuserconfigurationsettingsand
fault log information. EEPROM endurance retention and
mass write operation time are specified in the Electrical
Characteristics and Absolute Maximum Ratings sections.
= 125°C,
–5
([(1.4/8.617 • 10 ) • (1/398 – 1/403)] )
USE
AF = e
= 16.6
The equivalent operating time at 125°C = 16.6 hours.
Thus the overall retention of the EEPROM was degraded
by 16.6 hours as a result of operating at a junction tem-
peratureof130°Cfor10hours.Theeffectoftheoverstress
is negligible when compared to the overall EEPROM
retention rating of 87,600 hours at a maximum junction
temperature of 125°C.
Write operations above T = 85°C are possible although
J
the Electrical Characteristics are not guaranteed and the
EEPROM will be degraded. Read operations performed at
temperatures between –40°C and 125°C will not degrade
the EEPROM. Writing to the EEPROM above 85°C will
result in a degradation of retention characteristics. The
faultloggingfunction,whichisusefulindebuggingsystem
problemsthatmayoccurathightemperatures,onlywrites
tofaultlogEEPROMlocations.Ifoccasionalwritestothese
registers occur above 85°C, the slight degradation in the
data retention characteristics of the fault log will not take
away from the usefulness of the function.
TheintegrityoftheentireonboardEEPROMischeckedwith
a CRC calculation each time its data is to be read, such as
after a power-on reset or execution of a RESTORE_USER_
ALL command. If a CRC error occurs, the CML bit is set in
the STATUS_BYTE and STATUS_WORD commands, the
EEPROM CRC Error bit in the STATUS_MFR_SPECIFIC
command is set, and the ALERT and RUN pins pulled
low (PWM channels off). At that point the device will only
respond at special address 0x7C, which is activated only
after an invalid CRC has been detected. The chip will also
respond at the global addresses 0x5A and 0x5B, but use
oftheseaddresseswhenattemptingtorecoverfromaCRC
issueisnotrecommended.Allpowersupplyrailsassociated
with either PWM channel of a device reporting an invalid
CRCshouldremaindisableduntiltheissueisresolved. See
It is recommended that the EEPROM not be written
when the die temperature is greater than 85°C. If the die
temperature exceeds 130°C, the LTM4678 will disable all
EEPROM write operations. All EEPROM write operations
will be re-enabled when the die temperature drops below
125°C. (The controller will also disable all the switching
when the die temperature exceeds the internal overtem-
perature fault limit 160°C with a 10°C hysteresis).
the Applications Information section or contact the factory
Rev 0
24
For more information www.analog.com
LTM4678
OPERATION
for details on efficient in-system EEPROM programming,
includingbulkEEPROMProgramming,whichtheLTM4678
also supports.
able for transient and stability analysis, and experienced
users who prefer to adjust the module’s feedback loop
compensation parameters can use this tool.
TheLTM4678containsdualintegratedconstantfrequency
current mode control buck regulators (channel 0 and
channel 1) whose built-in power MOSFETs are capable of
fast switching speed. The factory NVM-default switching
frequency clocks SYNC at 575kHz, to which the regula-
tors synchronize their switching frequency. The default
phase-interleaving angle between the channels is 180°.
A pin-strapping resistor on FSWPH_CFG configures the
frequencyoftheSYNCclock(switchingfrequency)andthe
channel phase relationship of the channels to each other
and with respect to the falling edge of the SYNC signal.
(Most possible combinations of switching frequency and
phase-angle assignments are settleable by resistor pin
programming; see Table 3. Configure the LTM4678’s
NVM to implement settings not available by resistor-pin
strapping.) When a FSWPH_CFG pin-strap resistor sets
the channel phase relationship of the LTM4678’s chan-
nels, the SYNC clock is not driven by the module; instead,
SYNCbecomesstrictlyahighimpedanceinputandchannel
switchingfrequencyisthensynchronizedtoSYNCprovided
by an externally-generated clock or sibling LTM4678 with
POWER-UP AND INITIALIZATION
The LTM4678 is designed to provide standalone supply
sequencingandcontrolledturn-onandturn-offoperation.
It operates from a single input supply (4.5V to 16V) while
threeon-chiplinearregulatorsgenerateinternal2.5V,3.3V
and 5.5V. If V does not exceed 6V, and the EXTV pin
IN
CC
is not driven by an external supply, the INTV and V
CC
IN
pins must be tied together. The controller configuration is
initialized by an internal threshold based UVLO where V
IN
must be approximately 4V and the 5.5V, 3.3V and 2.5V
linear regulators must be within approximately 20% of
the regulated values. In addition to the power supply, a
PMBus RESTORE_USER_ALL or MFR_RESET command
can initialize the part too.
TheEXTV pinisdrivenbyanexternalregulatortoimprove
CC
efficiency of the circuit and minimize power loss on the
LTM4678 when V is high. The EXTV pin must exceed
IN
CC
approximately 4.7V, and V must exceed approximately
IN
7V before the INTV LDO operates from the EXTV pin.
CC
CC
To minimize application power, the EXTV pin can be
CC
pull-up resistor to V
. Switching frequency and phase
DD33
supplied by a switching regulator.
2
relationship can be altered via the I C interface, but only
when switching action is off, i.e., when the module is not
regulating either output. See the Applications Information
section for details.
During initialization, the external configuration resistors are
identified and/or contents of the NVM are read into the con-
troller’s commands and the power train is held off. The RUNn
and FAULTn and PGOODn are held low. The LTM4678 will
use the contents of Tables 1 thru 5 to determine the resistor
defined parameters. See the RCONFIG (Resistor Configura-
tion) Pins section for more details. The resistor configuration
pins only control some of the preset values of the controller.
The remaining values are programmed in NVM either at the
factory or by the user.
Programmable analog feedback loop compensation for
channel 0 and channel 1 is accomplished with a capacitor
connection from COMP
to SGND, and a capacitor from
0,1a
COMP
to SGND.) The COMP pin is for the high fre-
0,1b
01b
quency gain roll off and is the g amplifier output that has
a programmable range, and the COMP
m
pin has the pro-
0,1a
grammable resistor range along with a capacitor to SGND
thatsetsthefrequencycompensation.SeeProgrammable
Loop Compensation section. The LTM4678 module has
sufficientstabilitymarginsandgoodtransientperformance
with a wide range of output capacitors—even all-ceramic
MLCCs. Table 13 provides guidance on input and output
capacitors recommended for many common operating
conditions along with the programmable compensation
settings. The Analog Devices LTpowerCAD tool is avail-
Iftheconfigurationresistorsarenotinsertedoriftheignore
RCONFIG bit is asserted (bit 6 of the MFR_CONFIG_ALL
configuration command), the LTM4678 will use only the
contents of NVM to determine the DC/DC characteris-
tics. The ASEL value read at power-up or reset is always
respected unless the pin is open. The ASEL will set the
bottom 4LSBs and the MSBs are set by NVM. See the
Applications Information section for more details.
Rev 0
25
For more information www.analog.com
LTM4678
OPERATION
After the part has initialized, an additional comparator
LTM4678PWMalwaysusesdiscontinuousmodeduringthe
TON_RISE operation. In discontinuous mode, the bottom
MOSFETisturnedoffassoonasreversecurrentisdetected
in the inductor. This will allow the regulator to start up into
a pre-biased load. When the TON_MAX_FAULT_LIMIT is
reached, the part transitions to continuous mode, if so
programmed. If TON_MAX_FAULT_LIMIT is set to zero,
there is no time limit and the part transitions to the desired
monitors V . The VIN_ON threshold must be exceeded
IN
before the output power sequencing can begin. After V
IN
is initially applied, the part will typically require 30ms to
initialize and begin the TON_DELAY timer. The readback
of voltages and currents may require an additional 0ms
to 90ms.
conductionmodeafterTON_RISEcompletesandV has
OUT
SOFT-START
exceeded the VOUT_UV_FAULT_LIMIT and IOUT_OC is
not present. However, setting TON_MAX_FAULT_LIMIT
to a value of 0 is not recommended.
The method of start-up sequencing described below is
time-based. The part must enter the run state prior to
soft-start. The run pins are released by the LTM4678
after the part is initialized and V is greater than the
IN
TIME-BASED SEQUENCING
VIN_ON threshold. If multiple LTM4678s are used in an
application, they all hold their respective run pins low until
The default mode for sequencing the outputs on and
off is time-based. Each output is enabled after waiting
TON_DELAY amount of time following either a RUN pin
all devices are initialized and V exceeds the VIN_ON
IN
threshold for every device. The SHARE_CLK pin assures
all the devices connected to the signal use the same time
base. The SHARE_CLK pin is held low until the part has
going high, a PMBus command to turn on or the V rising
IN
aboveapreprogrammedvoltage.Offsequencingishandled
in a similar way. To assure proper sequencing, make sure
allICsconnecttheSHARE_CLKpintogetherandRUNpins
together. If the RUN pins cannot be connected together
for some reasons, set bit 2 of MFR_CHAN_ CONFIG to 1.
ThisbitrequirestheSHARE_CLKpintobeclockingbefore
the power supply output can start. When the RUN pin is
pulledlow, theLTM4678willholdthepinlowfortheMFR_
RESTART_DELAY.TheminimumMFR_RESTART_DELAY
isTOFF_DELAY+TOFF_FALL+136ms.Thisdelayassures
proper sequencing of all rails. The LTM4678 calculates
this delay internally and will not process a shorter delay.
However, a longer commanded MFR_RESTART_DELAY
can be used by the part. The maximum allowed value is
65.52 seconds.
been initialized after V is applied. The LTM4678 can be
IN
set to turn-off (or remain off) if SHARE_CLK is low (set
bit 2 of MFR_CHAN_CONFIG to 1). This allows the user
to assure synchronization across numerous LTC® devices
even if the RUN pins cannot be connected together due
to board constraints. In general, if the user cares about
synchronizationbetweenchipsitisbestnotonlytoconnect
all the respective RUN pins together but also to connect
all the respective SHARE_CLK pins together and pulled up
to V
with a 10k resistor. This assures all chips begin
DD33
sequencing at the same time and use the same time base.
After the RUN pins release and prior to entering a constant
output voltage regulation state, the LTM4678 performs a
monotonic initial ramp or “soft-start”. Soft-start is per-
formedbyactivelyregulatingtheloadvoltagewhiledigitally
rampingthetargetvoltagefrom0Vtothecommandedvolt-
ageset-point. OncetheLTM4678iscommandedtoturnon
(afterpowerupandinitialization),thecontrollerwaitsforthe
user specified turn-on delay (TON_DELAY) prior to initiat-
ing this output voltage ramp. The rise time of the voltage
ramp can be programmed using the TON_RISE command
to minimize inrush currents associated with the start-up
voltage ramp. The soft-start feature is disabled by setting
the value of TON_RISE to any value less than 0.25ms. The
VOLTAGE-BASED SEQUENCING
The sequence can also be voltage-based. As shown
in Figure 4, The PGOOD pin is asserted when the UV
n
threshold is exceeded for each output. It is possible to
feed the PGOOD pin from one LTM4678 into the RUN pin
of the next LTM4678 in the sequence, especially across
multiple LTM4678s. The PGOOD has a 60µs filter. If
n
the V
voltage bounces around the UV threshold for a
OUT
long period of time it is possible for the PGOOD output
n
Rev 0
26
For more information www.analog.com
LTM4678
OPERATION
to toggle more than once. To minimize this problem, set
the TON_RISE time under 100ms.
time is determined by the longer of the MFR_RETRY_
DELAY command or the time required for the regulated
output to decay below 12.5% of the programmed value.
If multiple outputs are controlled by the same FAULTn
pin, the decay time of the faulted output determines the
retry delay. If the natural decay time of the output is too
long, it is possible to remove the voltage requirement of
the MFR_RETRY_DELAY command by asserting bit 0
of MFR_CHAN_CONFIG. Alternatively, latched off mode
means the controller remains latched-off following a fault
and clearing requires user intervention such as toggling
RUNn or commanding the part OFF then ON.
If a fault in the string of rails is detected, only the faulted
rail and downstream rails will fault off. The rails in the
string of devices in front of the faulted rail will remain on
unless commanded off.
SHUTDOWN
The LTM4678 supports two shutdown modes. The first
mode is closed-loop shutdown response, with user de-
fined turn-off delay (TOFF_DELAY) and ramp down rate
Rꢇꢈ0
ꢊꢋꢌꢌꢍ0
ꢎꢁꢏRꢁ
LIGHT-LOAD CURRENT OPERATION
ꢀꢁꢂꢃꢄꢅꢆ
Rꢇꢈꢉ
ꢊꢋꢌꢌꢍꢉ
TheLTM4678hastwomodesofoperation:highefficiency
discontinuous conduction mode or forced continuous
conduction mode. Mode selection is done using the
MFR_PWM _MODE command (discontinuous conduc-
tion is always the start-up mode, forced continuous is the
default running mode).
Rꢇꢈ0
Rꢇꢈꢉ
ꢊꢋꢌꢌꢍ0
ꢊꢋꢌꢌꢍꢉ
ꢀꢁꢂꢃꢄꢅꢆ
ꢃꢄꢅꢆ ꢐ0ꢃ
ꢁꢌ ꢈꢑꢒꢁ ꢓꢔꢏꢈꢈꢑꢀ
ꢕꢈ ꢁꢔꢑ ꢎꢑꢖꢇꢑꢈꢓꢑ
Figure 4. Event (Voltage) Based Sequencing
If a controller is enabled for discontinuous operation, the
inductor current is not allowed to reverse. The reverse
currentcomparator’soutputturnsoffthebottomMOSFET
just before the inductor current reaches zero, preventing
it from reversing and going negative.
(TOFF_FALL). The controller will maintain the mode of
operationforTOFF_FALL.Thesecondmodeisdiscontinu-
ous conduction mode, the controller will not draw current
from the load and the fall time will be set by the output
capacitance and load current, instead of TOFF_FALL.
In forced continuous operation, the inductor current is
allowed to reverse at light loads or under large transient
conditions. Thepeakinductorcurrentisdeterminedsolely
The shutdown occurs in response to a fault condition or
loss of SHARE_CLK (if bit 2 of MFR_CHAN_ CONFIG is set
toa1)orV fallingbelowtheVIN_OFFthresholdorFAULT
by the voltage on the COMP pins. In this mode, the ef-
n
IN
ficiency at light loads is lower than in discontinuous mode
operation.However,continuousmodeexhibitsloweroutput
ripple and less interference with audio circuitry, but may
result in reverse inductor current, which can cause the
input supply to boost. The VIN_OV_FAULT_LIMIT can
detect this and turn off the offending channel. However,
pulled low externally (if the MFR_FAULT_ RESPONSE is
set to inhibit). Under these conditions, the power stage
is disabled in order to stop the transfer of energy to the
load as quickly as possible. The shutdown state can be
entered from the soft-start or active regulation states or
through user intervention.
this fault is based on an ADC read and can take up to t
CON-
There are two ways to respond to faults; which are retry
mode and latched off mode. In retry mode, the controller
respondstoafaultbyshuttingdownandenteringtheinac-
tive state for a programmable delay time (MFR_RETRY_
DELAY).Thisdelayminimizesthedutycycleassociatedwith
autonomous retries if the fault that causes the shutdown
disappears once the output is disabled. The retry delay
to detect. If there is a concern about the input supply
VERT
boosting,keepthepartindiscontinuousconductionmode.
If the part is set to discontinuous mode operation, as the
inductor average current increases, the controller will
automatically modify the operation from discontinuous
mode to continuous mode.
Rev 0
27
For more information www.analog.com
LTM4678
OPERATION
SWITCHING FREQUENCY AND PHASE
PWM LOOP COMPENSATION
The switching frequency of the PWM can be established
with an internal oscillator or an external time base. The
internal phase-locked loop (PLL) synchronizes the PWM
controltothistimingreferencewithproperphaserelation,
whether the clock is provided internally or externally. The
device can also be configured to provide the master clock
to other devices through PMBus command, NVM setting,
or external configuration resistors as outlined in Table 3.
The internal PWM loop compensation resistors R
of the LTM4678 can be adjusted using bit[4:0] of the
MFR_PWM_COMP command.
COMPna
The transconductance (gm) of the LTM4678 PWM error
amplifiercanbeadjustedusingbit[7:5]oftheMFR_PWM_
COMP command. These two loop compensation param-
eters can be programmed when device is in operation.
RefertotheProgrammableLoopCompensationsubsection
in the Applications Information section for further details.
As clock master, the LTM4678 will drive its open-drain
SYNC pin at the selected rate with a pulse width of 500ns.
An external pull-up resistor between SYNC and V
is
DD33
OUTPUT VOLTAGE SENSING
required in this case. Only one device connected to SYNC
should be designated to drive the pin. The LTM4678 will
automatically revert to an external SYNC input, disabling
its own SYNC, as long as the external SYNC frequency is
greater than 80% of the programmed SYNC frequency.
The external SYNC input shall have a duty cycle between
20% and 80%.
Both channels in LTM4678 have differential amplifiers,
which allow the remote sensing of the load voltage be-
+
–
tween V and V pins. The telemetry ADC is also fully
+
differential and makes measurements between V
OSNSn
+
–
and V
-voltages for both channels at the V and V
OSNSn
pins, respectively. The maximum allowed 3.6V, but the
LTM4678 design is limited to 3.3V output.
WhetherconfiguredtodriveSYNCornot,theLTM4678can
continue PWM operation using its own internal oscillator
if an external clock signal is subsequently lost.
INTV /EXTV POWER
CC
CC
PowerfortheinternaltopandbottomMOSFETdriversand
The device can also be programmed to always require an
external oscillator for PWM operation by setting bit 4 of
MFR_CONFIG_ALL. The status of the SYNC driver circuit
is indicated by bit 10 of MFR_PADS.
most other internal circuitry is derived from the INTV
CC
pin. When the EXTV pin is shorted to GND or tied to a
CC
voltage less than 4.7V, an internal 5.5V linear regulator
supplies INTV power from V . If EXTV is taken above
CC
IN
CC
The MFR_PWM_CONFIG command can be used to con-
figure the phase of each channel. Desired phase can also
be set from EEPROM or external configuration resistors
asoutlinedinTable3. Designatedphaseistherelationship
between the falling edge of SYNC and the internal clock
edge that sets the PWM latch to turn on the top power
switch. Additional small propagation delays to the PWM
control pins will also apply. Both channels must be off
beforetheFREQUENCY_SWITCHandMFR_PWM_CONFIG
commands can be written to the LTM4678.
4.7V and V is higher than 7.0V, the 5.5V regulator is
IN
turned off and an internal switch is turned on, connecting
EXTV to INTV . Using the EXTV allows the INTV
CC
CC
CC
CC
power to be derived from a high efficiency external source
such as a switching regulator output. EXTV can provide
CC
power to the internal 3.3V linear regulator even when V
IN
is not present, which allows the LTM4678 to be initialized
and programmed even without main power being applied.
The INTV regulator is powered from the SV pin, the
CC
IN
power through the IC is equal to SV • I
. The gate
IN INTVCC
Thephaserelationshipsandfrequencyoptionsprovidefor
numerousapplicationoptions.MultipleLTM4678modules
can be synchronized to realize a PolyPhase array. In this
case the phases should be separated by 360/n degrees,
where n is the number of phases driving the output volt-
age rail.
charge current is dependent on operating frequency. The
INTV regulator can supply up to 100mA, and the typical
CC
CC
INTV current for the LTM4678 is ~50mA. A 12V input
voltage would equate to a difference of 7V drop across
the internal controller, when multiplied by 50mA equals a
Rev 0
28
For more information www.analog.com
LTM4678
OPERATION
350mWpowerloss. Thislosscanbeeliminatedbyprovid-
ing an external 5V bias on the EXTV pin.
to 5% over temperature. This readback accuracy can be
improved by evaluation the LTM4678 in the end system.
Evaluating the ambient temperature, airflow, and the
difference of the temperature between the GUI and the
inductors on top can provide an offset value that can be
programmedtoimprovetheoutputcurrentreadbackusing
the MFR_TEMP_1_OFFSET command.
CC
Do not tie INTV on the LTM4678 to an external supply
CC
because INTV will attempt to pull the external supply
CC
high and hit current limit, significantly increasing the die
temperature.
For applications where V is 5V, tie the V and INTV
CC
IN
IN
pinstogethertothe5Vinputthrougha1Ωor2.2Ωresistor
INPUT CURRENT SENSING
as shown in Test Circuit 2.
TosensethetotalinputcurrentconsumedbytheLTM4678’s
power stages , a sense resistor is placed between the sup-
ply voltage and the drain of the top N-channel MOSFET.
OUTPUT CURRENT SENSING AND SUB MILLIOHM
DCR CURRENT SENSING
+
–
The I and I pins are connected to the sense resistor.
IN
IN
The LTM4678 use a unique sub-milliohm inductor cur-
rent sensing technique that provides a high level signal
to noise ratio while sensing very low signals in current
mode operation. This enables higher conversion efficien-
cies with the use of the internal sub-milliohm inductors in
heavy load applications. The current limit threshold can
be accurately set with the MFR_PWM_MODE[7] for High
and Low range (see page 90).
The filtered voltage is amplified by the internal high side
current sense amplifier and digitized by the LTM4678’s
telemetryADC.Theinputcurrentsenseamplifierhasthree
gain settings of 2x, 4x, and 8x set by the bit[3:2] of the
MFR_PWM_MODEcommand. The maximuminput sense
voltageforthethreegainsettingsis50mV,20mV,and5mV
respectively.TheLTM4678computestheinputcurrentus-
ing the internal R
value stored in the IIN_CAL_GAIN
SENSE
command. The resulting measured power stage current
is returned by the READ_IIN command.
The internal DCR sensing network, thus current limit are
calculated based on the DCR of the inductor at room tem-
perature. The DCR of the inductor has a large temperature
coefficient, approximately 3900ppm/°C. The temperature
coefficient of the inductor is written to the MFR_IOUT_
CAL_GAIN_TCregister.Theexternaltemperatureissensed
near the inductor and used to modify the internal current
limit circuit to maintain an essentially constant current
limit with temperature. The current sensed is then digitized
by the LTM4678’s telemetry ADC with an input range of
The LTM4678 uses a 1Ω resistor to measure the SV pin
IN
supplycurrentbeingconsumedbytheLTM4678.Thisvalue
is returned by the MFR_READ_ICHIP command. The chip
current is calculated by using the 1Ω value stored in the
MFR_ICHIP_CAL_GAINcommand.Refertothesubsection
titled Input Current Sense Amplifier in the Applications
Information section for further details.
128mV, anoisefloorof7µV
, andapeak-peaknoiseof
RMS
PolyPhase LOAD SHARING
approximately46.5µV.TheLTM4678computestheinductor
currentusingtheDCRvaluestoredintheIOUT_CAL_GAIN
command and the temperature coefficient stored in com-
mand MFR_IOUT_CAL_GAIN_TC. The resulting current
value is returned by the READ_IOUT command.
Multiple LTM4678s can be arrayed in order to provide a
balanced load-share solution by bussing the necessary
pins. Figure 47 illustrates a 4-Phase design sharing con-
nections required for load sharing.
Ifanexternaloscillatorisnotprovided,theSYNCpinshould
only be enabled on one of the LTM4678s. The other(s)
should be programmed to disable SYNC using bit 4 of
MFR_CONFIG_ALL. If an external oscillator is present, the
chip with the SYNC pin enabled will detect the presence
of the external clock and disable its output.
The LTM4678 power inductors for each channel are on
top of the module and the temperature sensors for each
channel are down on the substrate near the power stages
and the inductor clip. They are about a 12°C difference at
maximum load between the inductors and temperature
sensor. This has degraded the output current readback
Rev 0
29
For more information www.analog.com
LTM4678
OPERATION
+
Multiple channels need to tie all the V
pins together,
TheVOUTn_CFGpinsettingsaredescribedinTable1.These
pins set the LTM4678 V and V output voltage
OSNSn
OMPna
andalltheV
–pinstogether,C
andC
pins
OSNSn
OMPnb
OUT0
OUT1
togetheraswell.Donotassertbit[4]ofMFR_CONFIG_ALL
except in a PolyPhase application.
coarse settings. If the pin is open, the VOUT_COMMAND
command is loaded from NVM to determine the output
voltage. The default setting is to have the switcher off
unless the voltage configuration pins are installed. The
VTRIMn_CFG pins in Table 2 are used to set the output
voltage fine adjustment setting. Both combine to offer
several distinct output voltages.
The user must share the SYNC, SHARE_CLK, FAULT, and
ALERT pins of these parts. Be sure to use pull-up resistors
on SYNC, FAULT, SHARE_CLK and ALERT.
EXTERNAL/INTERNAL TEMPERATURE SENSE
Table 1. VOUTn _CFG Pin Strapping Look-Up Table for the
LTM4678’s Output Voltage, Coarse Setting (Not Applicable if
MFR_CONFIG_ALL[6] = 1b)
Temperatureismeasuredusingtheinternaldiode-connect-
ed PNP transistors on either of the TSNS0b or TSNS1b
pinscorrespondingtochannel0or1. TSNSnbpinsshould
be connected to their respective TSNSna pins, and these
returns are directly connected to the LTM4678 SGND pin.
Two different currents are applied to the diode (nominally
2µA and 32µA) and the temperature is calculated from a
R
*
V
(V)
MFR_PWM_
MODEn[1] BIT
VOUTn_CFG
(kΩ)
OUTn
SETTING COARSE
Open
32.4
22.6
18.0
15.4
12.7
10.7
NVM
NVM
3.3
NVM
NVM
0
0
0
0
3.1
∆V measurement made with the internal 16-bit monitor
BE
2.9
ADC (see Figure 2 Block Diagram).
2.7
The LTM4678 will only implement ∆V temperature
BE
2.5
0, if V
1, if V
> 0mV
≤ 0mV
TRIMn
TRIMn
sensing, therefore MFR_PWM_MODE bit[5] is reserved.
9.09
7.68
6.34
5.23
4.22
3.24
2.43
1.65
0.787
0
2.3
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
1
1
1
1
1
1
1
1
1
1
CH0 and CH1 temperatures can be linked to CH0 only for
adjusting the temperature compensated variables, and
internal temperature monitoring. This frees up TSNS1a
for an external/temperature sensing.
RCONFIG (RESISTOR CONFIGURATION) PINS
Therearesixinputpinsutilizing1%resistorsbetweenthese
pins and SGND to select key operating parameters. The
pins are ASEL, FSWPH_CFG, VOUT0_CFG, VOUT1_CFG,
VTRIM0_CFG, VTRIM1_CFG. If pins are floated, the value
stored in the corresponding NVM command is used. If
bit 6 of the MFR_CONFIG_ALL configuration command
is asserted in NVM, the resistor input is ignored upon
power-up except for ASEL which is always respected.
The resistor configuration pins are only measured dur-
ing a power-up reset or after a MFR_RESET or after a
RESTORE_USER_ALL command is executed.
*R
value indicated is nominal. Select R
from a
VOUTn_CFG
VOUTn_CFG
resistor vendor such that its value is always within 3% of the value
indicated in the table. Take into account resistor initial tolerance, T.C.R.
and resistor operating temperatures, soldering heat/IR reflow, and
endurance of the resistor over its lifetime. Thermal shock/cycling,
moisture (humidity) and other effects (depending on one’s specific
application) could also affect R
effects must be taken into account in order for resistor pin strapping to
yield the expected result at every SV power-up and/or every execution
of MFR_RESET or RESTORE_ USER_ALL, over the lifetime of one’s
product.
’s value over time. All such
VOUTn_CFG
IN
Rev 0
30
For more information www.analog.com
LTM4678
OPERATION
Table 2. VTRIMn_CFG Pin Strapping Look-Up Table for the
LTM4678’s Output Voltage, Fine Adjustment Setting (Not
Applicable if MFR_CONFIG_ALL[6] = 1b)
The following parameters are set as a percentage of the
output voltage if the RCONFIG pins are used to determine
the output voltage:
R
*
V
(mV) FINE ADJUSTMENT TO V
SETTING WHEN RESPECTIVE
VTRIMn_CFG
(kΩ)
TRIM
OUTn
n
VOUT_OV_FAULT_LIMIT....................................+10%
n
VOUT_OV_WARN_LIMIT....................................+7.5%
Open
32.4
22.6
18.0
15.4
12.7
10.7
9.09
7.68
6.34
5.23
4.22
3.24
2.43
1.65
0.787
0
0
n
VOUT_MAX.........................................................+7.5%
99
n
VOUT_MARGIN_HIGH........................................+5%
86.625
74.25
n
VOUT_MARGIN_LOW.........................................–5%
n
VOUT_UV_FAULT_LIMIT....................................–7%
61.875
49.5
The FSWPH_CFG pin settings are described in Table 3.
Thispinselectstheswitchingfrequencyandphaseofeach
channel.Thephaserelationshipsbetweenthetwochannels
and SYNC pin are determined in Table 3. To synchronize
to an external clock, the part should be put into external
clock mode (SYNC output disabled but frequency set to
thenominalvalue).Ifnoexternalclockissupplied,thepart
will clock at the programmed frequency. If the application
is multiphase and the SYNC signal between chips is lost,
the parts will not operate at the designed phase even if
theyareprogrammedandtrimmedtothesamefrequency.
37.125
24.75
12.375
–12.375
–24.75
–37.125
–49.5
–61.875
–74.25
–86.625
–99
This may increase the ripple voltage on the output, pos-
sibly produce undesirable operation. If the external SYNC
signal is being generated internally and external SYNC is
not selected, bit 10 of MFR_PADS will be asserted. If no
frequency is selected and the external SYNC frequency is
not present, a PLL_FAULT will occur. If the user does not
wish to see the ALERT from a PLL_FAULT even if there is
not a valid synchronization signal at power-up, the ALERT
mask for PLL_FAULT must be written. See the description
on SMBALERT_MASK for more details. If the SYNC pin is
connectedbetweenmultipleICsonlyoneoftheICsshould
havetheSYNCpinenabledusingtheMFR_CONFIG_ALL[4]
=1,andallotherICsshouldbeconfiguredtohavetheSYNC
pin disabled with MFR_CONFIG_ALL[4] =0.
*R
value indicated is nominal. Select R
from a
VTRIMn_CFG
VTRIMn_CFG
resistor vendor such that its value is always within 3% of the value
indicated in the table. Take into account resistor initial tolerance, T.C.R.
and resistor operating temperatures, soldering heat/IR reflow, and
endurance of the resistor over its lifetime. Thermal shock/cycling,
moisture (humidity) and other effects (depending on one’s specific
application) could also affect R
effects must be taken into account in order for resistor pin strapping to
yield the expected result at every SV power-up and/or every execution
of MFR_RESET, or RESTORE_USER_ALL over the lifetime of one’s
product.
’s value over time. All such
VTRIMn_CFG
IN
The ASEL pin settings are described in Table 4. ASEL
selects slave address for the LTM4678. For more detail,
refer to Table 5.
NOTE: Per the PMBus specification, pin programmed pa-
rameters can be overridden by commands from the digital
interfacewiththeexceptionofASELwhichisalwayshonored.
Do not set any part address to 0x5A or 0x5B because these
are global addresses and all parts will respond to them.
Rev 0
31
For more information www.analog.com
LTM4678
OPERATION
Table 3. FSWPH_CFG Pin Strapping Look-Up Table to Set the LTM4678’s Switching Frequency and Channel Phase-Interleaving Angle
(Not Applicable if MFR_CONFIG_ALL[6] = 1b)
R
*
SWITCHING
FREQUENCY (kHz)
bits [2:0] of MFR_
PWM_CONFIG
bit [4] of MFR_
CONFIG_ALL
FSWPH_CFG
(kΩ)
θSYNC TO
θ
0
θ
SYNC TO 1
θ
NVM; LTM4678
Default = 500
NVM; LTM4678
Default = 0°
NVM; LTM4678
Default = 180°
NVM; LTM4678
Default = 000b
NVM; LTM4678
Default = 0b
Open
32.4
22.6
18.0
15.4
12.7
10.7
7.68
6.34
5.23
4.22
3.24
2.43
1.65
0.787
0
250
350
0°
0°
180°
180°
180°
180°
180°
180°
240°
270°
240°
120°
240°
300°
270°
180°
240°
000b
000b
000b
000b
000b
000b
100b
001b
010b
011b
101b
110b
001b
000b
100b
0b
0b
0b
0b
0b
0b
0b
0b
1b
1b
1b
1b
1b
1b
1b
425
0°
575
0°
650
0°
750
0°
500
120°
90°
0°
500
External**
External**
External**
External**
External**
External**
External**
0°
60°
120°
90°
0°
120°
*R
value indicated is nominal. Select R
from a resistor vendor such that its value is always within 3% of the value indicated in the
FSWPH_CFG
FSWPH_CFG
table. Take into account resistor initial tolerance, T.C.R. and resistor operating temperatures, soldering heat/IR reflow, and endurance of the resistor over
its lifetime. Thermal shock/cycling, moisture (humidity) and other effects (depending on one’s specific application) could also affect R ’s value
FSWPH_CFG
over time. All such effects must be taken into account in order for resistor pin-strapping to yield the expected result at every SV power-up and/or every
IN
execution of MFR_RESET or RESTORE_USER_ALL, over the lifetime of one’s product.
**External setting corresponds to FREQUENCY_SWITCH (Register 0x33) value set to 0x0000; the device synchronizes its switching frequency to that of
the clock provided on the SYNC pin, provided MFR_CONFIG_ALL[4] = 1b.
Rev 0
32
For more information www.analog.com
LTM4678
OPERATION
Table 4. ASEL Pin Strapping Look-Up Table to Set the
LTM4678’s Slave Address (Applicable Regardless of
MFR_CONFIG_ALL[6] Setting)
Table 5. LTM4678 MFR_ADDRESS Command Examples
Expressed in 7- and 8-Bit Addressing
HEX DEVICE
ADDRESS
BIT
R * (kΩ)
ASEL
SLAVE ADDRESS
100_1111_R/W
100_1111_R/W
100_1110_R/W
100_1101_R/W
100_1100_R/W
100_1011_R/W
100_1010_R/W
100_1001_R/W
100_1000_R/W
100_0111_R/W
100_0110_R/W
100_0101_R/W
100_0100_R/W
100_0011_R/W
100_0010_R/W
100_0001_R/W
100_0000_R/W
DESCRIPTION
7-BIT
0x5A
0x5B
0x4F
0x40
0x41
8-BIT
0xB4
0xB6
0x9E
0x80
0x82
7
0
0
0
0
0
1
6
1
1
1
1
1
0
5
0
0
0
0
0
0
4
1
1
0
0
0
0
3
2
0
0
1
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
1
0
R/W
0
Open
4
Rail
1
1
1
0
0
0
32.4
22.6
18.0
15.4
12.7
10.7
9.09
7.68
6.34
5.23
4.22
3.24
2.43
1.65
0.787
0
4
Global
0
Default
0
Example 1
0
Example 2
0
2,3
Disabled
0
Note 1: This table can be applied to the MFR_RAIL_ADDRESSn
commands, but not the MFR_ADDRESS command.
Note 2: A disabled value in one command does not disable the device,
nor does it disable the global address.
Note 3: A disabled value in one command does not inhibit the device
from responding to device addresses specified in other commands.
Note 4: It is not recommended to write the value 0x00, 0x0C (7-bit), 0x5A
(7-bit), 0x5B (7-bit) or 0x7C(7-bit) to the MFR_CHANNEL_ADDRESSn or
the MFR_RAIL_ADDRESSn commands.
FAULT DETECTION AND HANDLING
A variety of fault and warning reporting and handling
mechanisms are available. Fault and warning detection
capabilities include:
Where:
R/W = Read/Write bit in control byte
All PMBus device addresses listed in the specification are 7 bits wide
unless otherwise noted.
Note: The LTM4678 will always respond to slave address 0x5A and 0x5B
n
Input OV FAULT Protection and UV Warning
n
regardless of the NVM or ASEL resistor configuration values.
Average Input OC Warn
*R
CFG
value indicated is nominal. Select R
from a resistor vendor
CFG
n
Output OV/UV Fault and Warn Protection
such that its value is always within 3% of the value indicated in the table.
Take into account resistor initial tolerance, T.C.R. and resistor operating
temperatures, soldering heat/IR reflow, and endurance of the resistor
over its lifetime. Thermal shock cycling, moisture (humidity) and other
effects (depending on one’s specific application) could also affect R ’s
value over time. All such effects must be taken into account in order for
n
Output OC Fault and Warn Protection
n
InternalcontrolDieandInternalModuleOvertempera-
ture Fault and Warn Protection
CFG
resistor pin-strapping to yield the expected result at every SV power-up
and/or every execution of MFR_RESET or RESTORE_USER_ALL, over the
lifetime of one’s product.
IN
n
Internal Undertemperature Fault and Warn Protection
n
CML Fault (Communication, Memory or Logic)
n
External Fault Detection via the Bidirectional FAULTn
Pins
In addition, the LTM4678 can map any combination of
fault indicators to their respective FAULTn pin using the
propagate FAULTn response commands, MFR_FAULT_
PROPAGATE. Typical usage of a FAULTn pin is as a driver
Rev 0
33
For more information www.analog.com
LTM4678
OPERATION
foranexternalcrowbardevice,overtemperaturealert,over-
voltage alert or as an interrupt to cause a microcontroller
to poll the fault commands. Alternatively, the FAULTn pins
canbeusedasinputstodetectexternalfaultsdownstream
of the controller that require an immediate response.
NONE OF THE ABOVE in the STATUS_BYTE indicates that
one or more of the bits in the most-significant nibble of
STATUS_WORD are also set.
In general, any asserted bit in a STATUS_x register also
pulls the ALERT pin low. Once set, ALERT will remain low
until one of the following occurs.
Any fault or warning event will always cause the ALERT
pin to assert low unless the fault or warning is masked by
the SMBALERT_MASK. The pin will remain asserted low
until the CLEAR_FAULTS command is issued, the fault bit
is written to a 1 or bias power is cycled or a MFR_RESET
command is issued, or the RUN pins are toggled OFF/ON
or the part is commanded OFF/ON via PMBus or an ARA
command operation is performed. The MFR_FAULT_
PROPAGATE command determines if the FAULT pins are
pulled low when a fault is detected.
n
ACLEAR_FAULTSorMFR_RESETCommandIsIssued
n
The Related Status Bit Is Written to a One
n
The Faulted Channel Is Properly Commanded Off and
Back On
n
The LTM4678 Successfully Transmits Its Address
During a PMBus ARA
n
Bias Power Is Cycled
Output and input fault event handling is controlled by the
corresponding fault response byte as specified in Table
14 thru 18. Shutdown recovery from these types of faults
can either be autonomous or latched. For autonomous
recovery, the faults are not latched, so if the fault condi-
tions not present after the retry interval has elapsed, a
new soft-start is attempted.
With some exceptions, the SMBALERT_MASK command
can be used to prevent the LTM4678 from asserting
ALERT for bits in these registers on a bit-by-bit basis.
These mask settings are promoted to STATUS_WORD
and STATUS_BYTE in the same fashion as the status bits
themselves. For example, if ALERT is masked for all bits
in channel 0 STATUS_VOUT, then ALERT is effectively
masked for the V
bit in STATUS_WORD for PAGE 0.
OUT
If the fault persists, the controller will continue to retry.
The retry interval is specified by the MFR_RETRY_DELAY
command and prevents damage to the regulator com-
ponents by repetitive power cycling, assuming the fault
condition itself is not immediately destructive. The
MFR_RETRY_DELAY must be greater than 120ms. It can
not exceed 83.88 seconds.
The BUSY bit in STATUS_BYTE also asserts ALERT low
and cannot be masked. This bit can be set as a result of
various internal interactions with PMBus communication.
This fault occurs when a command is received that cannot
be safely executed with one or both channels enabled. As
discussedintheApplicationsInformation,BUSYfaultscan
be avoided by polling MFR_COMMON before executing
some commands.
Status Registers and ALERT Masking
If masked faults occur immediately after power up, ALERT
may still be pulled low because there has not been time
to retrieve all of the programmed masking information
from EEPROM.
Figure 5 summarizes the internal LTM4678 status reg-
isters accessible by PMBus command. These contain
indication of various faults, warnings and other important
operating conditions. As shown, the STATUS_BYTE and
STATUS_WORD commands also summarize contents of
other status registers. Refer to PMBus Command Details
for specific information.
Status information contained in MFR_COMMON and
MFR_PADS can be used to further debug or clarify the
contents of STATUS_BYTE or STATUS_WORD as shown,
but the contents of these registers do not affect the state
of the ALERT pin and may not directly influence bits in
STATUS_BYTE or STATUS_WORD.
Rev 0
34
For more information www.analog.com
LTM4678
OPERATION
STATUS_WORD
STATUS_VOUT*
ꢇꢈ ꢐꢑꢗꢬ
ꢇꢉ ꢛꢑꢗꢬ
ꢇꢊ ꢛꢡꢁꢗꢬ
ꢇꢋ ꢭꢒRꢪꢟꢁꢄꢞꢛꢒꢛꢞ
ꢇꢇ ꢁꢑꢩꢄRꢪꢃꢑꢑꢅꢸ
ꢇ0 ꢀꢘeꢓꢙꢚ 0ꢆ
ꢎ
ꢏ
ꢈ
ꢉ
ꢊ
ꢋ
ꢇ
0
ꢐꢑꢗꢬꢪꢑꢐ ꢒꢓꢔꢕꢖ
ꢐꢑꢗꢬꢪꢑꢐ ꢩꢓꢘꢜꢝꢜꢮ
ꢐꢑꢗꢬꢪꢗꢐ ꢩꢓꢘꢜꢝꢜꢮ
ꢐꢑꢗꢬꢪꢗꢐ ꢒꢓꢔꢕꢖ
ꢐꢑꢗꢬꢪꢭꢂꢵ ꢩꢓꢘꢜꢝꢜꢮ
ꢬꢑꢡꢪꢭꢂꢵ ꢒꢓꢔꢕꢖ
ꢬꢑꢒꢒꢪꢭꢂꢵ ꢩꢓꢘꢜꢝꢜꢮ
ꢀꢘeꢓꢙꢚ 0ꢆ
STATUS_INPUT
ꢐꢛꢡꢪꢑꢐ ꢒꢓꢔꢕꢖ
ꢀꢘeꢓꢙꢚ 0ꢆ
ꢐꢛꢡꢪꢗꢐ ꢩꢓꢘꢜꢝꢜꢮ
ꢀꢘeꢓꢙꢚ 0ꢆ
ꢗꢜꢝꢖ ꢑꢹꢹ ꢹꢢꢘ ꢛꢜꢚꢔꢹꢹꢣꢝeꢜꢖ ꢐꢛꢡ
ꢀꢘeꢓꢙꢚ 0ꢆ
ꢛꢛꢡꢪꢑꢞ ꢩꢓꢘꢜꢝꢜꢮ
ꢀꢘeꢓꢙꢚ 0ꢆ
ꢎ
ꢏ
ꢈ
ꢉ
ꢊ
ꢋ
ꢇ
0
ꢌ
ꢍ
ꢀꢘeꢓꢙꢚ 0ꢆ
ꢀꢘeꢓꢙꢚ 0ꢆ
STATUS_BYTE
ꢀꢁꢂꢃꢄꢅꢆ
ꢎ
ꢏ
ꢈ
ꢉ
ꢊ
ꢋ
ꢇ
0
ꢱꢗꢟꢠ
ꢑꢒꢒ
ꢐꢑꢗꢬꢪꢑꢐ
ꢛꢑꢗꢬꢪꢑꢞ
ꢀꢘeꢓꢙꢚ 0ꢆ
ꢬꢄꢭꢁꢄRꢂꢬꢗRꢄ
ꢞꢭꢫ
ꢡꢑꢡꢄ ꢑꢒ ꢬꢳꢄ ꢂꢱꢑꢐꢄ
STATUS_IOUT
STATUS_MFR_SPECIFIC
ꢎ
ꢏ
ꢈ
ꢉ
ꢊ
ꢋ
ꢇ
0
ꢛꢑꢗꢬꢪꢑꢞ ꢒꢓꢔꢕꢖ
ꢀꢘeꢓꢙꢚ 0ꢆ
ꢛꢑꢗꢬꢪꢑꢞ ꢩꢓꢘꢜꢝꢜꢮ
ꢀꢘeꢓꢙꢚ 0ꢆ
ꢎ
ꢏ
ꢈ
ꢉ
ꢊ
ꢋ
ꢇ
0
ꢛꢜꢖeꢘꢜꢓꢕ ꢬeꢷꢰeꢘꢓꢖꢔꢘe ꢒꢓꢔꢕꢖ
ꢛꢜꢖeꢘꢜꢓꢕ ꢬeꢷꢰeꢘꢓꢖꢔꢘe ꢩꢓꢘꢜꢝꢜꢮ
ꢄꢄꢁRꢑꢭ ꢞRꢞ ꢄꢘꢘꢢꢘ
ꢛꢜꢖeꢘꢜꢓꢕ ꢁꢫꢫ ꢗꢜꢕꢢꢣꢤeꢙ
ꢒꢓꢔꢕꢖ ꢫꢢꢮ ꢁꢘeꢚeꢜꢖ
ꢐꢅꢅꢊꢊ ꢗꢐ ꢢꢘ ꢑꢐ ꢒꢓꢔꢕꢖ
ꢐꢑꢗꢬ ꢟꢨꢢꢘꢖ ꢞꢦꢣꢕeꢙ
FAULT ꢁꢔꢕꢕeꢙ ꢫꢢꢯ ꢱꢦ ꢄꢧꢖeꢘꢜꢓꢕ ꢅevꢝꢣe
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢘeꢓꢙꢚ 0ꢆ
ꢀꢘeꢓꢙꢚ 0ꢆ
ꢀꢘeꢓꢙꢚ 0ꢆ
ꢀꢘeꢓꢙꢚ 0ꢆ
MFR_COMMON
ꢎ
ꢏ
ꢈ
ꢉ
ꢊ
ꢋ
ꢇ
0
ꢞꢨꢝꢰ ꢡꢢꢖ ꢅꢘꢝvꢝꢜꢮ ALERT ꢫꢢꢯ
ꢞꢨꢝꢰ ꢡꢢꢖ ꢱꢔꢚꢦ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃꢄꢅꢆ
ꢛꢜꢖeꢘꢜꢓꢕ ꢞꢓꢕꢣꢔꢕꢓꢖꢝꢢꢜꢚ ꢡꢢꢖ ꢁeꢜꢙꢝꢜꢮ
ꢑꢔꢖꢰꢔꢖ ꢡꢢꢖ ꢛꢜ ꢬꢘꢓꢜꢚꢝꢖꢝꢢꢜ
ꢄꢄꢁRꢑꢭ ꢛꢜꢝꢖꢝꢓꢕꢝꢲeꢙ
ꢀꢘeꢓꢙꢚ 0ꢆ
ꢟꢳꢂRꢄꢪꢞꢫꢴꢪꢫꢑꢩ
ꢩꢁ ꢁꢝꢜ ꢳꢝꢮꢨ
STATUS_TEMPERATURE
MFR_PADS
ꢎ
ꢏ
ꢈ
ꢉ
ꢊ
ꢋ
ꢇ
0
ꢑꢬ ꢒꢓꢔꢕꢖ
ꢇꢈ ꢐꢅꢅꢊꢊ ꢑꢐ ꢒꢓꢔꢕꢖ
ꢇꢉ ꢐꢅꢅꢊꢊ ꢗꢐ ꢒꢓꢔꢕꢖ
ꢇꢊ ꢀꢘeꢓꢙꢚ 0ꢆ
ꢇꢋ ꢀꢘeꢓꢙꢚ 0ꢆ
ꢇꢇ ꢛꢜvꢓꢕꢝꢙ ꢂꢅꢞ Reꢚꢔꢕꢖꢀꢚꢆ
ꢇ0 ꢟꢠꢡꢞ ꢞꢕꢢꢣꢤeꢙ ꢥꢦ ꢄꢧꢖeꢘꢜꢓꢕ ꢟꢢꢔꢘꢣe
ꢑꢬ ꢩꢓꢘꢜꢝꢜꢮ
ꢀꢘeꢓꢙꢚ 0ꢆ
ꢗꢬ ꢒꢓꢔꢕꢖ
ꢀꢘeꢓꢙꢚ 0ꢆ
ꢀꢘeꢓꢙꢚ 0ꢆ
ꢀꢘeꢓꢙꢚ 0ꢆ
ꢀꢘeꢓꢙꢚ 0ꢆ
MFR_INFO
ꢌ
ꢍ
ꢎ
ꢏ
ꢈ
ꢉ
ꢊ
ꢋ
ꢇ
0
ꢞꢨꢓꢜꢜeꢕ ꢇ ꢝꢚ ꢁꢑꢩꢄRꢪꢃꢑꢑꢅ
ꢞꢨꢓꢜꢜeꢕ 0 ꢝꢚ ꢁꢑꢩꢄRꢪꢃꢑꢑꢅ
ꢫꢬꢭꢉꢏꢎꢍ ꢒꢢꢘꢣꢝꢜꢮ Rꢗꢡꢇ ꢫꢢꢯ
ꢫꢬꢭꢉꢏꢎꢍ ꢒꢢꢘꢣꢝꢜꢮ Rꢗꢡ0 ꢫꢢꢯ
Rꢗꢡꢇ ꢁꢝꢜ ꢟꢖꢓꢖe
ꢇꢈ Reꢚeꢘveꢙ
ꢇꢉ Reꢚeꢘveꢙ
ꢇꢊ Reꢚeꢘveꢙ
ꢇꢋ Reꢚeꢘveꢙ
ꢇꢇ Reꢚeꢘveꢙ
ꢇ0 Reꢚeꢘveꢙ
ꢌ
ꢍ
ꢎ
ꢏ
ꢈ
ꢉ
ꢊ
ꢋ
ꢇ
0
ꢀꢁꢂꢃꢄꢅꢆ
STATUS_CML
ꢎ
ꢏ
ꢈ
ꢉ
ꢊ
ꢋ
ꢇ
0
ꢛꢜvꢓꢕꢝꢙꢶꢗꢜꢚꢔꢰꢰꢢꢘꢖeꢙ ꢞꢢꢷꢷꢓꢜꢙ
ꢛꢜvꢓꢕꢝꢙꢶꢗꢜꢚꢔꢰꢰꢢꢘꢖeꢙ ꢅꢓꢖꢓ
ꢁꢓꢣꢤeꢖ ꢄꢘꢘꢢꢘ ꢞꢨeꢣꢤ ꢒꢓꢝꢕeꢙ
ꢭeꢷꢢꢘꢦ ꢒꢓꢔꢕꢖ ꢅeꢖeꢣꢖeꢙ
ꢁꢘꢢꢣeꢚꢚꢢꢘ ꢒꢓꢔꢕꢖ ꢅeꢖeꢣꢖeꢙ
ꢀꢘeꢓꢙꢚ 0ꢆ
Rꢗꢡ0 ꢁꢝꢜ ꢟꢖꢓꢖe
ꢫꢬꢭꢉꢏꢎꢍ ꢒꢢꢘꢣꢝꢜꢮ FAULT1 ꢫꢢꢯ
ꢫꢬꢭꢉꢏꢎꢍ ꢒꢢꢘꢣꢝꢜꢮ FAULT0 ꢫꢢꢯ
FAULT1 ꢁꢝꢜ ꢟꢖꢓꢖe
Reꢚeꢘveꢙ
Reꢚeꢘveꢙ
Reꢚeꢘveꢙ
Reꢚeꢘveꢙ
Reꢚeꢘveꢙ
ꢄꢄꢁRꢑꢭ ꢄꢞꢞ ꢟꢖꢓꢖꢔꢚ
Reꢚeꢘveꢙ
Reꢚeꢘveꢙ
Reꢚeꢘveꢙ
FAULT0 ꢁꢝꢜ ꢟꢖꢓꢖe
ꢉꢏꢎꢍ ꢒ0ꢈ
ꢑꢖꢨeꢘ ꢞꢢꢷꢷꢔꢜꢝꢣꢓꢖꢝꢢꢜ ꢒꢓꢔꢕꢖ
ꢑꢖꢨeꢘ ꢭeꢷꢢꢘꢦ ꢢꢘ ꢫꢢꢮꢝꢣ ꢒꢓꢔꢕꢖ
Reꢚeꢘveꢙ
DESCRIPTION
MASKABLE GENERATES ALERT BIT CLEARABLE
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ꢃeꢜeꢘꢓꢕ ꢡꢢꢜꢺꢭꢓꢚꢤꢓꢥꢕe ꢄveꢜꢖ
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Figure 5. LTM4678 Status Register Summary
Rev 0
35
For more information www.analog.com
LTM4678
OPERATION
Mapping Faults to FAULT Pins
repair can be attempted by writing the desired configura-
tion to the controller and executing a STORE_USER_ALL
command followed by a CLEAR_FAULTS command.
Channel-to-channelfault(includingchannelsfrommultiple
LTM4678s) dependencies can be created by connecting
FAULTn pins together. In the event of an internal fault, one
or more of the channels is configured to pull the bussed
FAULTn pins low. The other channels are then configured
to shut down when the FAULTn pins are pulled low. For
autonomous group retry, the faulted channel is config-
ured to let go of the FAULTn pin(s) after a retry interval,
assuming the original fault has cleared. All the channels
in the group then begin a soft-start sequence. If the fault
responseisLATCH_OFF, theFAULTnpinremainsasserted
low until either the RUN pin is toggled OFF/ON or the part
is commanded OFF/ON. The toggling of the RUN either
by the pin or OFF/ON command will clear faults associ-
ated with the channel. If it is desired to have all faults
cleared when either RUN pin is toggled or, set bit 0 of
MFR_CONFIG_ALL to a 1.
The LTM4678 manufacturing section of the NVM is mir-
rored. If both copies are corrupted, the “NVM CRC Fault”
in the STATUS_MFR_SPECIFIC command is set. If this bit
remainssetafterbeingclearedbyissuingaCLEAR_FAULTS
or writing a 1 to this bit, an irrecoverable internal fault has
occurred. The user is cautioned to disable both output
power supply rails associated with this specific part.
There are no provisions for field repair of NVM faults in
the manufacturing section.
SERIAL INTERFACE
The LTM4678 serial interface is a PMBus compliant slave
device and can operate at any frequency between 10kHz
and 400kHz. The address is configurable using either the
NVM or an external resistor. In addition the LTM4678
always responds to the global broadcast address of 0x5A
(7-bit) or 0x5B (7-bit).
The status of all faults and warnings is summarized in the
STATUS_WORD and STATUS_BYTE commands.
Additional fault detection and handling capabilities are:
The serial interface supports the following protocols de-
fined in the PMBus specifications: 1) send command, 2)
write byte, 3) write word, 4) group, 5) read byte, 6) read
word and 7) read block. 8) write block. All read operations
will return a valid PEC if the PMBus master requests it. If
the PEC_REQUIRED bit is set in the MFR_CONFIG_ALL
command, the PMBus write operations will not be acted
upon until a valid PEC has been received by the LTM4678.
Power Good Pins
The PGOODn pins of the LTM4678 are connected to the
open drains of internal MOSFETs. The MOSFETs turn on
and pull the PGOODn pins low when the channel output
voltageisnotwithinthechannel’sUVandOVvoltagethresh-
olds. During TON_DELAY and TON_RISE sequencing, the
PGOODn pin is held low. The PGOODn pin is also pulled
low when the respective RUNn pin is low. The PGOODn
pin response is deglitched by an internal 60µs digital filter.
The PGOODn pin and PGOOD status may be different at
times due to communication latency of up to 10µs.
Communication Protection
PEC write errors (if PEC_REQUIRED is active), attempts
to access unsupported commands, or writing invalid data
to supported commands will result in a CML fault. The
CML bit is set in the STATUS_BYTE and STATUS_WORD
commands, the appropriate bit is set in the STATUS_CML
command, and the ALERT pin is pulled low.
CRC Protection
The integrity of the NVM memory is checked after a power
on reset. A CRC error will prevent the controller from leav-
ing the inactive state. If a CRC error occurs, the CML bit is
setintheSTATUS_BYTEandSTATUS_WORDcommands,
the appropriate bit is set in the STATUS_MFR_SPECIFIC
command, and the ALERT pin will be pulled low. NVM
DEVICE ADDRESSING
The LTM4678 offers five different types of addressing
overthePMBusinterface,specifically:1)global,2)device,
3) rail addressing and 4) alert response address (ARA).
Rev 0
36
For more information www.analog.com
LTM4678
OPERATION
Global addressing provides a means of the PMBus master
to address all LTM4678 devices on the bus. The LTM4678
global address is fixed 0x5A (7-bit) or 0xB4 (8-bit) and
cannot be disabled. Commands sent to the global address
act the same as if PAGE is set to a value of 0xFF. Com-
mands sent are written to both channels simultaneously.
Globalcommand0x5B(7-bit)or0xB6(8-bit)ispagedand
allows channel specific command of all LTM4678 devices
on the bus. Other ADI device types may respond at one
or both of these global addresses. Reading from global
addresses is strongly discouraged.
The I and I
overcurrent monitors are performed by
IN
OUT
ADC readings and calculations. Thus these values are
based on average currents and can have a time latency
of up to t
. The I
calculation accounts for the
CONVERT
OUT
DCRandtheirtemperaturecoefficient.Theinputcurrentis
equal to the voltage measured across the R resistor
SENSE
divided by the resistors value as set with the MFR_RVIN
command. If this calculated input current exceeds the
IN_OC_WARN_LIMIT the ALERT pin is pulled low and
the IIN_OC_WARN bit is asserted in the STATUS_INPUT
command.
Device addressing provides the standard means of the
PMBus master communicating with a single instance of
an LTM4678. The value of the device address is set by a
combination of the ASEL configuration pin and the MFR_
ADDRESS command. When this addressing means is
used, the PAGE command determines the channel being
acted upon. Device addressing can be disabled by writing
a value of 0x80 to the MFR_ADDRESS.
The digital processor within the LTM4678 provides the
ability to ignore the fault, shut down and latch off or shut
down and retry indefinitely (hiccup). The retry interval
is set in MFR_RETRY_ DELAY and can be from 120ms
to 83.88 seconds in 1ms increments. The shutdown for
OV/UV and OC can be done immediately or after a user
selectable deglitch time.
Output Overvoltage Fault Response
Rail addressing provides a means for the bus master to
simultaneouslycommunicatewithallchannelsconnected
together to produce a single output voltage (PolyPhase).
While similar to global addressing, the rail address can
be dynamically assigned with the paged MFR_RAIL_ AD-
DRESS command, allowing for any logical grouping of
channelsthatmightberequiredforreliablesystemcontrol.
Reading from rail addresses is also strongly discouraged.
A programmable overvoltage comparator (OV) guards
againsttransientovershootsaswellaslong-termovervol-
tagesattheoutput.Insuchcases,thetopMOSFETisturned
off and the bottom MOSFET is turned on. However, the re-
verseoutputcurrentismonitoredwhiledeviceisinOVfault.
When it reaches the limit, both top and bottom MOSFETs
areturnedoff.ThetopandbottomMOSFETswillkeeptheir
stateuntiltheovervoltageconditionisclearedregardlessof
thePMBusVOUT_OV_FAULT_RESPONSEcommandbyte
value. This hardware level fault response delay is typically
2µs from the overvoltage condition to BG asserted high.
Using the VOUT_OV_FAULT_RESPONSE command, the
user can select any of the following behaviors:
All four means of PMBus addressing require the user to
employdisciplinedplanningtoavoidaddressingconflicts.
Communication to LTM4678 devices at global and rail ad-
dresses should be limited to command write operations.
RESPONSES TO V
AND I /I
FAULTS
OUT
IN OUT
n
OV Pull-Down Only (OV Cannot Be Ignored)
V
OVandUVconditionsaremonitoredbycomparators.
OUT
n
Shut Down (Stop Switching) Immediately—Latch Off
The OV and UV limits are set in three ways:
n
Shut Down Immediately—Retry Indefinitely at the
Time Interval Specified in MFR_RETRY_DELAY
n
As a Percentage of the V
Configuration Pins
if Using the Resistor
OUT
Either the Latch Off or Retry fault responses can be de-
glitched in increments of (0-7) • 10µs. See Table 14.
n
n
InNVMifEitherProgrammedattheFactoryorThrough
the GUI
By PMBus Command
Rev 0
37
For more information www.analog.com
LTM4678
OPERATION
Output Undervoltage Response
sequence is started. The resolution of the TON_MAX_
FAULT_LIMIT is 10µs. If the VOUT_UV_FAULT _LIMIT
is not reached within the TON_MAX_FAULT_LIMIT time,
the response of this fault is determined by the value of
the TON_MAX_FAULT_RESPONSE command value. This
response may be one of the following:
The response to an undervoltage comparator output can
be the following:
n
Ignore
n
Shut Down Immediately—Latch Off
n
Ignore
n
Shut Down Immediately—Retry Indefinitely at the
Time Interval Specified in MFR_RETRY_DELAY.
n
n
Shut Down (Stop Switching) Immediately—Latch Off
The UV responses can be deglitched. See Table 15.
Shut Down Immediately—Retry Indefinitely at the
Time Interval Specified in MFR_RETRY_DELAY.
Peak Output Overcurrent Fault Response
This fault response is not deglitched. A value of 0 in
TON_MAX_FAULT_LIMIT means the fault is ignored. The
TON_MAX_FAULT_LIMIT should be set longer than the
TON_RISE time. It is recommended TON_MAX_FAULT_
LIMIT always be set to a non-zero value, otherwise the
output may never come up and no flag will be set to the
user. See Table 18.
Due to the current mode control algorithm, peak output
currentacrosstheinductorisalwayslimitedonacycle-by-
cycle basis. The value of the peak current limit is specified
in Electrical Characteristics table. The current limit circuit
operates by limiting the COMPn maximum voltage. Since
internalDCRsensingisused,theCOMPnmaximumvoltage
has a temperature dependency directly proportional to the
TC of the DCR of the inductor. The LTM4678 automatically
monitors the external temperature sensors and modifies
the maximum allowed COMPn to compensate for this
term. The IOUT_OC_FAULT_LIMIT section provides data
RESPONSES TO V OV FAULTS
IN
V overvoltage is measured with the ADC. The response
IN
is naturally deglitched by the 100ms typical response time
points for I
Limiting on page 90.
of the ADC. The fault responses are:
OUT
n
The overcurrent fault processing circuitry can execute the
following behaviors:
Ignore
n
Shut Down Immediately—Latch Off
n
Current Limit Indefinitely
n
Shut Down Immediately—Retry Indefinitely at the
Time Interval Specified in MFR_RETRY_DELAY. See
Table 18.
n
Shut Down Immediately—Latch Off
n
Shut Down Immediately—Retry Indefinitely at the
Time Interval Specified in MFR_RETRY_DELAY.
RESPONSES TO OT/UT FAULTS
Theovercurrentresponsescanbedeglitchedinincrements
of (0-7) • 16ms. See Table 16.
Internal Overtemperature Fault Response
An internal temperature sensor protects against NVM
damage.Above85°C,nowritestoNVMarerecommended.
Above130°C,theinternalovertemperaturewarnthreshold
isexceededandthepartdisablestheNVManddoesnotre-
enable until the temperature has dropped to 125°C. When
thedietemperatureexceed160°Ctheinternaltemperature
fault response is enabled and the PWM is disabled until
the die temperature drops below 150°C. Temperature is
measured by the ADC. Internal temperature faults cannot
RESPONSES TO TIMING FAULTS
TON_MAX_FAULT_LIMIT is the time allowed for V
to
OUT
rise and settle at start-up. The TON_MAX_FAULT_LIMIT
condition is predicated upon detection of the VOUT_UV_
FAULT_LIMITasthe outputisundergoinga SOFT_START
sequence. The TON_MAX_ FAULT_LIMIT time is started
after TON_DELAY has been reached and a SOFT_START
Rev 0
38
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LTM4678
OPERATION
beignored. Internaltemperaturelimitscannotbeadjusted
by the user. See Table 17.
FAULT LOGGING
The LTM4678 has fault logging capability. Data is logged
into memory in the order shown in Table 19. The data is
stored in a continuously updated buffer in RAM. When a
fault event occurs, the fault log buffer is copied from the
RAM buffer into NVM. Fault logging is allowed at tem-
peratures above 85°C; however, retention of 10 years is
not guaranteed. When the die temperature exceeds 130°C
the fault logging is delayed until the die temperature drops
below 125°C. The fault log data remains in NVM until a
MFR_FAULT _LOG_CLEAR command is issued. Issuing
this command re-enables the fault log feature. Before
re-enabling fault log, be sure no faults are present and a
CLEAR_FAULTS command has been issued.
External Overtemperature and Undertemperature
Fault Response
Two internal temperature sensors are used to sense the
temperature of critical circuit elements like inductors
and power MOSFETs on each channel. The OT_FAULT_
RESPONSE and UT_FAULT_ RESPONSE commands are
usedtodeterminetheappropriateresponsetoanovertem-
perature and under temperature condition, respectively. If
no external sense elements are used (not recommended)
set the UT_FAULT_ RESPONSE to ignore—and set the
UT_FAULT_LIMIT to 275°C. The fault responses are:
n
Ignore
When the LTM4678 powers-up or exits its reset state, it
checks the NVM for a valid fault log. If a valid fault log
exists in NVM, the “Valid Fault Log” bit in the STATUS_
MFR_SPECIFIC command will be set and an ALERT event
will be generated. Also, fault logging will be blocked until
the LTM4678 has received a MFR_FAULT_LOG_CLEAR
command before fault logging will be re-enabled.
n
Shut Down Immediately—Latch Off
n
ShutDownImmediately—RetryIndefinitelyattheTime
Interval Specified in MFR_RETRY_DELAY. See Table 18.
RESPONSES TO INPUT OVERCURRENT AND OUTPUT
UNDERCURRENT FAULTS
Input overcurrent and output undercurrent are measured
with the ADC. The fault responses are:
The information is stored in EEPROM in the event of
any fault that disables the controller on either channel. A
FAULTn being externally pulled low will not trigger a fault
logging event.
n
Ignore
n
Shut Down Immediately—Latch Off
BUS TIMEOUT PROTECTION
n
Shut Down Immediately—Retry Indefinitely at the
The LTM4678 implements a timeout feature to avoid per-
sistent faults on the serial interface. The data packet timer
begins at the first START event before the device address
write byte. Data packet information must be completed
within 30ms or the LTM4678 will three-state the bus and
ignorethegivendatapacket.Ifmoretimeisrequired,assert
bit 3 of MFR_CONFIG_ALL to allow typical bus timeouts
of 255ms. Data packet information includes the device
address byte write, command byte, repeat start event
(if a read operation), device address byte read (if a read
operation), all data bytes and the PEC byte if applicable.
Time Interval Specified in MFR_RETRY_DELAY.
RESPONSES TO EXTERNAL FAULTS
When either FAULTn pin is pulled low, the OTHER bit is
set in the STATUS_WORD command, the appropriate bit
is set in the STATUS_MFR_SPECIFIC command, and the
ALERT pin is pulled low. Responses are not deglitched.
Each channel can be configured to ignore or shut down
then retry in response to its FAULTn pin going low by
modifying the MFR_FAULT_RESPONSE command. To
avoid the ALERT pin asserting low when FAULT is pulled
low, assert bit 1 of MFR_CHAN_CONFIG, or mask the
ALERT using the SMBALERT_MASK command.
TheLTM4678allowslongerPMBustimeoutsforblockread
data packets. This timeout is proportional to the length of
the block read. The additional block read timeout applies
Rev 0
39
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LTM4678
OPERATION
primarilytotheMFR_FAULT_LOGcommand.Thetimeout
period defaults to 32ms.
PMBus SERIAL DIGITAL INTERFACE
TheLTM4678communicateswithahost(master)usingthe
standardPMBusserialbusinterface.TheTimingDiagram,
Figure 6, shows the timing relationship of the signals on
the bus. The two-bus lines, SDA and SCL, must be high
when the bus is not in use. External pull-up resistors or
current sources are required on these lines. The LTM4678
is a slave device. The master can communicate with the
LTM4678 using the following formats:
The user is encouraged to use as high a clock rate as
possibletomaintainefficientdatapackettransferbetween
all devices sharing the serial bus interface. The LTM4678
supports the full PMBus frequency range from 10kHz
to 400kHz.
2
SIMILARITY BETWEEN PMBus, SMBus AND I C
2-WIRE INTERFACE
n
Master Transmitter, Slave Receiver
Master Receiver, Slave Transmitter
The PMBus 2-wire interface is an incremental extension
of the SMBus. SMBus is built upon I C with some minor
n
2
The following PMBus protocols are supported:
differences in timing, DC parameters and protocol. The
PMBus/SMBus protocols are more robust than simple
n
Write Byte, Write Word, Send Byte
2
I C byte commands because PMBus/SMBus provide
n
Read Byte, Read Word, Block Read, Block Write
timeouts to prevent persistent bus errors and optional
packet error checking (PEC) to ensure data integrity. In
n
Alert Response Address
2
general, a master device that can be configured for I C
Figure 7 to Figure 24 illustrate the aforementioned PMBus
protocols. All transactions support PEC and GCP (group
command protocol). The Block Read supports 255 bytes
of returned data. For this reason, the PMBus timeout may
be extended when reading the fault log.
communication can be used for PMBus communication
with little or no change to hardware or firmware. Repeat
2
start (restart) is not supported by all I C controllers but
is required for SMBus/PMBus reads. If a general purpose
2
I C controller is used, check that repeat start is supported.
Figure 7 is a key to the protocol diagrams in this section.
PEC is optional.
TheLTM4678supportsthemaximumSMBusclockspeed
of 100kHz and is compatible with the higher speed PMBus
specification(between100kHzand400kHz)ifMFR_COM-
MON polling or clock stretching is enabled. For robust
communication and operation refer to the Note section
in the PMBus Command Summary. Clock stretching is
enabled by asserting bit 1 of MFR_CONFIG_ALL.
A value shown below a field in the following figures is
mandatory value for that field.
The data formats implemented by PMBus are:
n
Master transmitter transmits to slave receiver. The
transfer direction in this case is not changed.
For a description of the minor extensions and exceptions
PMBus makes to SMBus, refer to PMBus Specification
Part 1 Revision 1.2: Paragraph 5: Transport.
n
Master reads slave immediately after the first byte. At
the moment of the first acknowledgment (provided by
the slave receiver) the master transmitter becomes
a master receiver and the slave receiver becomes a
slave transmitter.
For a description of the differences between SMBus and
2
I C, refer to System Management Bus (SMBus) Speci-
fication Version 2.0: Appendix B—Differences Between
n
Combined format. During a change of direction within
2
SMBus and I C.
a transfer, the master repeats both a start condition
andtheslaveaddressbutwiththeR/Wbitreversed. In
this case, the master receiver terminates the transfer
by generating a NACK on the last byte of the transfer
and a STOP condition.
Rev 0
40
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LTM4678
OPERATION
Refer to Figure 7 for a legend.
Handshaking features are included to ensure robust system communication. Please refer to the PMBus Communication
and Command Processing subsection of the Applications Information section for further details.
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Figure 6. PMBus Timing Diagram
Table 6. Abbreviations of Supported Data Formats
PMBus
SPECIFICATION
REFERENCE
ADI
TERMINOLOGY DEFINITION
TERMINOLOGY
EXAMPLE
N
L11
Linear
Part II ¶7.1
Linear_5s_11s Floating point 16-bit data: value = Y • 2 ,
where N = b[15:11] and Y = b[10:0], both
two’s compliment binary integers
b[15:0] = 0x9807 = 10011_000_0000_0111
–13
value = 7 • 2 = 854E-6
–12
L16
CF
Linear VOUT_
MODE
Part II ¶8.2
Part II ¶7.2
Part II ¶10.3
Linear_16u
Varies
Reg
Floating point 16-bit data: value = Y • 2
where Y = b[15:0], an unsigned integer
,
b[15:0] = 0x4C00 = 0100_1100_0000_0000
–12
value = 19456 • 2 = 4.75
DIRECT
16-bit data with a custom format defined in Often an unsigned or two’s compliment
the detailed PMBus command description integer
Reg
ASC
Register Bits
Per-bit meaning defined in detailed PMBus PMBus STATUS_BYTE command
command description
Text Characters Part II ¶22.2.1
ASCII
ISO/IEC 8859-1 [A05]
ADI (0x4C5443)
Rev 0
41
For more information www.analog.com
LTM4678
OPERATION
Figure 7 to Figure 24 PMBus Protocols
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Figure 7. PMBus Packet Protocol Diagram Element Key
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Figure 8. Quick Command Protocol
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Figure 9. Send Byte Protocol
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Figure 10. Send Byte Protocol with PEC
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ꢂ
ꢏ
ꢓꢔꢐꢑ ꢕꢒꢒ
Figure 11. Write Byte Protocol
ꢕ
ꢒ
ꢕ
ꢕ
ꢓ
ꢕ
ꢓ
ꢕ
ꢓ
ꢕ
ꢕ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢍꢎ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢅꢂꢊꢂ ꢋꢌꢊꢄ
ꢂ
ꢏꢄꢆ
ꢂ
ꢏ
ꢐꢑꢒꢓ ꢔꢕꢖ
Figure 12. Write Byte Protocol with PEC
ꢕ
ꢒ
ꢕ
ꢕ
ꢓ
ꢕ
ꢓ
ꢕ
ꢓ
ꢕ
ꢕ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢍꢎ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢅꢂꢊꢂ ꢋꢌꢊꢄ ꢁꢇꢍ
ꢂ
ꢅꢂꢊꢂ ꢋꢌꢊꢄ ꢗꢘꢙꢗ
ꢂ
ꢏ
ꢐꢑꢒꢓ ꢔꢕꢖ
Figure 13. Write Word Protocol
ꢕ
ꢒ
ꢕ
ꢕ
ꢓ
ꢕ
ꢓ
ꢕ
ꢓ
ꢕ
ꢓ
ꢕ
ꢕ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢍꢎ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢅꢂꢊꢂ ꢋꢌꢊꢄ ꢁꢇꢍ
ꢂ
ꢅꢂꢊꢂ ꢋꢌꢊꢄ ꢖꢗꢘꢖ
ꢂ
ꢏꢄꢆ
ꢂ
ꢏ
ꢐꢑꢒꢓ ꢔꢕꢐ
Figure 14. Write Word Protocol with PEC
Rev 0
42
For more information www.analog.com
LTM4678
OPERATION
ꢒ
ꢏ
ꢒ
ꢒ
ꢐ
ꢒ
ꢒ
ꢏ
ꢒ
ꢒ
ꢐ
ꢒ
ꢒ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢊꢋ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢀꢋ ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ Rꢗ
ꢂ
ꢅꢂꢔꢂ ꢕꢖꢔꢄ
ꢂ
ꢌ
ꢍꢎꢏꢐ ꢑꢒꢓ
Figure 15. Read Byte Protocol
ꢒ
ꢏ
ꢒ
ꢒ
ꢐ
ꢒ
ꢒ
ꢏ
ꢒ
ꢒ
ꢐ
ꢒ
ꢒ
ꢒ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢊꢋ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢀꢋ ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ Rꢖ
ꢂ
ꢅꢂꢓꢂ ꢔꢕꢓꢄ
ꢂ
ꢌꢄꢆ
ꢂ
ꢌ
ꢍꢎꢏꢐ ꢑꢒꢎ
Figure 16. Read Byte Protocol with PEC
ꢒ
ꢏ
ꢒ
ꢒ
ꢐ
ꢒ
ꢒ
ꢏ
ꢒ
ꢒ
ꢐ
ꢒ
ꢐ
ꢒ
ꢒ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢊꢋ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢀꢋ ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ Rꢙ
ꢂ
ꢅꢂꢓꢂ ꢔꢕꢓꢄ ꢁꢇꢊ
ꢂ
ꢅꢂꢓꢂ ꢔꢕꢓꢄ ꢖꢗꢘꢖ
ꢂ
ꢌ
ꢍꢎꢏꢐ ꢑꢒꢏ
Figure 17. Read Word Protocol
ꢒ
ꢏ
ꢒ
ꢒ
ꢐ
ꢒ
ꢒ
ꢏ
ꢒ
ꢒ
ꢐ
ꢒ
ꢐ
ꢒ
ꢐ
ꢒ
ꢒ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢊꢋ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢀꢋ ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ Rꢙ
ꢂ
ꢅꢂꢓꢂ ꢔꢕꢓꢄ ꢁꢇꢊ
ꢂ
ꢅꢂꢓꢂ ꢔꢕꢓꢄ ꢖꢗꢘꢖ
ꢂ
ꢌꢄꢆ
ꢂ
ꢌ
ꢍꢎꢏꢐ ꢑꢒꢐ
Figure 18. Read Word Protocol with PEC
ꢎ
ꢌ
ꢎ
ꢎ
ꢍ
ꢎ
ꢎ
ꢌ
ꢎ
ꢎ
ꢍ
ꢎ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢊꢋ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢀꢋ ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ Rꢔ
ꢂ
ꢏꢐꢑꢄ ꢆꢇꢒꢉꢑ ꢓ ꢉ
ꢂ
ꢕ
ꢍ
ꢎ
ꢍ
ꢎ
ꢕ
ꢕ
ꢍ
ꢎ
ꢎ
ꢅꢂꢑꢂ ꢏꢐꢑꢄ ꢎ
ꢂ
ꢅꢂꢑꢂ ꢏꢐꢑꢄ ꢛ
ꢂ
ꢅꢂꢑꢂ ꢏꢐꢑꢄ ꢉ
ꢂ
ꢖ
ꢗꢘꢌꢍ ꢙꢎꢚ
Figure 19. Block Read Protocol
ꢎ
ꢌ
ꢎ
ꢎ
ꢍ
ꢎ
ꢎ
ꢌ
ꢎ
ꢎ
ꢍ
ꢎ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢊꢋ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢀꢋ ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ Rꢔ
ꢂ
ꢏꢐꢑꢄ ꢆꢇꢒꢉꢑ ꢓ ꢉ
ꢂ
ꢕ
ꢍ
ꢎ
ꢍ
ꢎ
ꢕ
ꢕ
ꢍ
ꢎ
ꢍ
ꢎ
ꢎ
ꢅꢂꢑꢂ ꢏꢐꢑꢄ ꢎ
ꢂ
ꢅꢂꢑꢂ ꢏꢐꢑꢄ ꢖ
ꢂ
ꢅꢂꢑꢂ ꢏꢐꢑꢄ ꢉ
ꢂ
ꢗꢄꢆ
ꢂ
ꢗ
ꢘꢙꢌꢍ ꢚꢖ0
Figure 20. Block Read Protocol with PEC
Rev 0
43
For more information www.analog.com
LTM4678
OPERATION
ꢓ
ꢑ
ꢓ
ꢓ
ꢒ
ꢓ
ꢒ
ꢓ
ꢒ
ꢓ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢏꢐ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢊꢋꢌꢄ ꢆꢇꢍꢉꢌ ꢎ ꢈ
ꢂ
ꢅꢂꢌꢂ ꢊꢋꢌꢄ ꢓ
ꢂ
ꢔ
ꢒ
ꢓ
ꢒ
ꢓ
ꢅꢂꢌꢂ ꢊꢋꢌꢄ ꢕ
ꢂ
ꢔ
ꢅꢂꢌꢂ ꢊꢋꢌꢄ ꢈ
ꢂ
ꢔ
ꢓ
ꢑ
ꢓ
ꢓ
ꢒ
ꢓ
ꢒ
ꢓ
ꢓ
ꢀꢐ ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ Rꢖ
ꢂ
ꢊꢋꢌꢄ ꢆꢇꢍꢉꢌ ꢎ ꢉ
ꢂ
ꢅꢂꢌꢂ ꢊꢋꢌꢄ ꢓ
ꢂ
ꢔ
ꢒ
ꢓ
ꢔ
ꢔ
ꢒ
ꢓ
ꢓ
ꢅꢂꢌꢂ ꢊꢋꢌꢄ ꢕ
ꢂ
ꢅꢂꢌꢂ ꢊꢋꢌꢄ ꢉ
ꢂ
ꢗ
ꢘꢙꢑꢒ ꢚꢕꢓ
Figure 21. Block Write – Block Read Process Call
ꢓ
ꢑ
ꢓ
ꢓ
ꢒ
ꢓ
ꢒ
ꢓ
ꢒ
ꢓ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢏꢐ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢊꢋꢌꢄ ꢆꢇꢍꢉꢌ ꢎ ꢈ
ꢂ
ꢅꢂꢌꢂ ꢊꢋꢌꢄ ꢓ
ꢂ
ꢔ
ꢒ
ꢓ
ꢒ
ꢓ
ꢅꢂꢌꢂ ꢊꢋꢌꢄ ꢕ
ꢂ
ꢔ
ꢅꢂꢌꢂ ꢊꢋꢌꢄ ꢈ
ꢂ
ꢔ
ꢓ
ꢑ
ꢓ
ꢓ
ꢒ
ꢓ
ꢒ
ꢓ
ꢓ
ꢀꢐ ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ Rꢖ
ꢂ
ꢊꢋꢌꢄ ꢆꢇꢍꢉꢌ ꢎ ꢉ
ꢂ
ꢅꢂꢌꢂ ꢊꢋꢌꢄ ꢓ
ꢂ
ꢔ
ꢒ
ꢓ
ꢔ
ꢔ
ꢒ
ꢓ
ꢒ
ꢓ
ꢓ
ꢅꢂꢌꢂ ꢊꢋꢌꢄ ꢕ
ꢂ
ꢅꢂꢌꢂ ꢊꢋꢌꢄ ꢉ
ꢂ
ꢗꢄꢆ
ꢂ
ꢗ
ꢘꢙꢑꢒ ꢚꢕꢕ
Figure 22. Block Write – Block Read Process Call with PEC
ꢑ
ꢌ
ꢑ
ꢑ
ꢍ
ꢑ
ꢑ
ꢀꢁꢂRꢃ Rꢂꢄꢅꢆꢇꢄꢂ
ꢀꢈꢈRꢂꢄꢄ
ꢄ
Rꢉ
ꢀ
ꢈꢂꢒꢓꢔꢂ ꢀꢈꢈRꢂꢄꢄ
ꢀ
ꢅ
ꢊꢋꢌꢍ ꢎꢏꢐ
Figure 23. Alert Response Address Protocol
ꢌ
ꢊ
ꢌ
ꢌ
ꢋ
ꢌ
ꢋ
ꢌ
ꢌ
ꢀꢁꢂRꢃ Rꢂꢄꢅꢆꢇꢄꢂ
ꢀꢈꢈRꢂꢄꢄ
ꢄ
Rꢉ
ꢀ
ꢈꢂꢍꢎꢏꢂ ꢀꢈꢈRꢂꢄꢄ
ꢀ
ꢅꢂꢏ
ꢀ
ꢅ
ꢐꢑꢊꢋ ꢒꢓꢐ
Figure 24. Alert Response Address Protocol with PEC
Rev 0
44
For more information www.analog.com
LTM4678
PMBus COMMAND SUMMARY
PMBus COMMANDS
the manufacturer. Attempting to access non-supported or
reserved commands may result in a CML command fault
event. All output voltage settings and measurements are
Table 7 lists supported PMBus commands and manufac-
turer specific commands. A complete description of these
commandscanbefoundinthe“PMBusPowerSystemMgt
Protocol Specification – Part II – Revision 1.2”. Users are
encouraged to reference this specification. Exceptions or
manufacturer specific implementations are listed in Table
7. Floating point values listed in the “DEFAULT VALUE”
column are either Linear 16-bit Signed (PMBus Section
8.3.1) or Linear_5s_11s (PMBus Section 7.1) format,
whichever is appropriate for the command. All commands
from 0xD0 through 0xFF not listed in Table 7 are implicitly
reserved by the manufacturer. Users should avoid blind
writes within this range of commands to avoid undesired
operation of the part. All commands from 0x00 through
0xCF not listed in Table 7 are implicitly not supported by
based on the VOUT_MODE setting of 0x14. This translates
–12
to an exponent of 2
.
If PMBus commands are received faster than they are be-
ing processed, the part may become too busy to handle
new commands. In these circumstances the part follows
the protocols defined in the PMBus Specification v1.2,
Part II, Section 10.8.7, to communicate that it is busy.
The part includes handshaking features to eliminate busy
errors and simplify error handling software while ensur-
ing robust communication and system behavior. Please
refer to the subsection titled PMBus Communication and
Command Processing in the Applications Information
section for further details.
Table 7. PMBus Commands Summary (Note: The Data Format Abbreviations are Detailed in Table 8)
CMD
DATA
DEFAULT
VALUE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
PAGE
PAGE
0x00 Provides integration with multi-page
PMBus devices.
R/W Byte
N
Y
Y
Reg
Reg
Reg
0x00
0x80
0x1E
NA
77
OPERATION
0x01 Operating mode control. On/off, margin
high and margin low.
R/W Byte
R/W Byte
Y
Y
81
81
ON_OFF_CONFIG
0x02 RUN pin and PMBus bus on/off command
configuration.
CLEAR_FAULTS
0x03 Clear any fault bits that have been set.
Send Byte
W Block
N
N
106
77
PAGE_PLUS_WRITE
0x05 Write a command directly to a
specified page.
PAGE_PLUS_READ
WRITE_PROTECT
0x06 Read a command directly from a
specified page.
Block R/W
R/W Byte
N
N
77
78
0x10 Level of protection provided by the device
against accidental changes.
Reg
Reg
Y
Y
0x00
STORE_USER_ALL
0x15 Store user operating memory to EEPROM. Send Byte
N
N
NA
NA
116
117
RESTORE_USER_ALL
0x16 Restore user operating memory from
EEPROM.
Send Byte
CAPABILITY
0x19 Summary of PMBus optional communication
protocols supported by this device.
R Byte
N
0xB0
105
SMBALERT_MASK
VOUT_MODE
0x1B Mask ALERT activity
Block R/W
R Byte
Y
Y
Reg
Reg
See CMD
106
87
–12
–12
0x20 Output voltage format and exponent (2 ).
2
0x14
VOUT_COMMAND
VOUT_MAX
0x21 Nominal output voltage set point.
R/W Word
R/W Word
Y
Y
L16
L16
V
V
Y
Y
1.0
88
87
0x1000
0x24 Upper limit on the commanded output
voltage including VOUT_MARGIN_HI.
3.6
0xC399
Rev 0
45
For more information www.analog.com
LTM4678
PMBus COMMAND SUMMARY
CMD
DATA
DEFAULT
VALUE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
PAGE
VOUT_MARGIN_HIGH
0x25 Margin high output voltage set point. Must R/W Word
be greater than VOUT_COMMAND.
Y
Y
Y
N
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
L16
L16
L11
L11
L11
L11
L16
Reg
L16
L16
L16
Reg
L11
Reg
L11
L11
Reg
L11
L11
Reg
V
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
1.05
88
0x10CD
VOUT_MARGIN_LOW
VOUT_TRANSITION_ RATE
FREQUENCY_SWITCH
VIN_ON
0x26 Margin low output voltage set point. Must R/W Word
be less than VOUT_COMMAND.
V
0.95
0x0F33
88
94
85
86
86
87
96
87
88
88
97
90
99
91
92
101
92
93
101
0X27 Rate the output changes when V
commanded to a new value.
R/W Word
V/ms
kHz
V
0.001
0x8042
OUT
0x33 Switching frequency of the controller.
R/W Word
350kHz
0xFABC
0x35 Input voltage at which the unit should start R/W Word
power conversion.
4.75
0xD130
VIN_OFF
0x36 Input voltage at which the unit should stop R/W Word
power conversion.
V
4.5
0xD120
VOUT_OV_FAULT_LIMIT
0x40 Output overvoltage fault limit.
R/W Word
R/W Byte
R/W Word
R/W Word
R/W Word
R/W Byte
R/W Word
R/W Byte
R/W Word
R/W Word
R/W Byte
R/W Word
R/W Word
R/W Byte
V
1.1
0x119A
VOUT_OV_FAULT_
RESPONSE
0x41 Action to be taken by the device when an
output overvoltage fault is detected.
0xB8
VOUT_OV_WARN_LIMIT
VOUT_UV_WARN_LIMIT
VOUT_UV_FAULT_LIMIT
0x42 Output overvoltage warning limit.
0x43 Output undervoltage warning limit.
0x44 Output undervoltage fault limit.
V
V
V
1.075
0x1133
0.925
0x0ECD
0.9
0x0E66
VOUT_UV_FAULT_
RESPONSE
0x45 Action to be taken by the device when an
output undervoltage fault is detected.
0xB8
IOUT_OC_FAULT_LIMIT
0x46 Output overcurrent fault limit.
A
40.00
0xE280
IOUT_OC_FAULT_ RESPONSE 0x47 Action to be taken by the device when an
output overcurrent fault is detected.
0x00
IOUT_OC_WARN_LIMIT
0x4A Output overcurrent warning limit.
A
C
30.0
0xDBC0
OT_FAULT_LIMIT
0x4F External overtemperature fault limit.
128.0
0xF200
OT_FAULT_RESPONSE
OT_WARN_LIMIT
0x50 Action to be taken by the device when an
external overtemperature fault is detected,
0xB8
0x51 External overtemperature warning limit.
C
C
125.0
0xEBE8
UT_FAULT_LIMIT
0x53 External undertemperature fault limit.
–45.0
0xE530
UT_FAULT_RESPONSE
0x54 Action to be taken by the device when
an external undertemperature fault is
detected.
0xB8
VIN_OV_FAULT_LIMIT
0x55 Input supply overvoltage fault limit.
R/W Word
R/W Byte
R/W Word
R/W Word
N
Y
N
N
L11
Reg
L11
L11
V
Y
Y
Y
Y
15.5
87
96
86
91
0xD3E0
VIN_OV_FAULT_ RESPONSE 0x56 Action to be taken by the device when an
input overvoltage fault is detected.
0x80
VIN_UV_WARN_LIMIT
0x58 Input supply undervoltage warning limit.
V
A
4.65
0xD12A
IIN_OC_WARN_LIMIT
0x5D Input supply overcurrent warning limit.
10.0
0xD280
Rev 0
46
For more information www.analog.com
LTM4678
PMBus COMMAND SUMMARY
CMD
DATA
PAGED FORMAT UNITS NVM
DEFAULT
VALUE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGE
TON_DELAY
0x60 Time from RUN and/or Operation on to
output rail turn-on.
R/W Word
Y
L11
ms
Y
0.0
0x8000
93
TON_RISE
0x61 Time from when the output starts to rise
R/W Word
R/W Word
R/W Byte
Y
L11
ms
Y
3.0
93
94
until the output voltage reaches the V
commanded value.
0xC300
OUT
TON_MAX_FAULT_LIMIT
0x62 Maximum time from the start of TON_
Y
L11
ms
Y
5.0
0xCA80
RISE for VO to cross the VOUT_UV_
UT
FAULT_LIMIT.
TON_MAX_FAULT_
RESPONSE
0x63 Action to be taken by the device when a
TON_ MAX_FAULT event is detected.
Y
Y
Y
Y
Reg
L11
L11
L11
Y
Y
Y
Y
0xB8
99
94
94
95
TOFF_DELAY
0x64 Time from RUN and/or Operation off to the R/W Word
start of TOFF_FALL ramp.
ms
ms
ms
0.0
0x8000
TOFF_FALL
0x65 Time from when the output starts to fall
until the output reaches zero volts.
R/W Word
3.0
0xC300
TOFF_MAX_WARN_ LIMIT
0x66 Maximum allowed time, after TOFF_FALL
completed, for the unit to decay below
12.5%.
R/W Word
0
0x8000
STATUS_BYTE
STATUS_WORD
0x78 One byte summary of the unit’s fault
condition.
R/W Byte
Y
Y
Reg
Reg
NA
NA
107
108
0x79 Two byte summary of the unit’s fault
condition.
R/W Word
STATUS_VOUT
0x7A Output voltage fault and warning status.
0x7B Output current fault and warning status.
0x7C Input supply fault and warning status.
R/W Byte
R/W Byte
R/W Byte
R/W Byte
Y
Y
N
Y
Reg
Reg
Reg
Reg
NA
NA
NA
NA
108
109
109
110
STATUS_IOUT
STATUS_INPUT
STATUS_TEMPERATURE
0x7D External temperature fault and warning
status for READ_TEMERATURE_1.
STATUS_CML
0x7E Communication and memory fault and
warning status.
R/W Byte
R/W Byte
N
Y
Reg
Reg
NA
NA
110
111
STATUS_MFR_SPECIFIC
0x80 Manufacturer specific fault and state
information.
READ_VIN
0x88 Measured input supply voltage.
0x89 Measured input supply current.
0x8B Measured output voltage.
0x8C Measured output current.
R Word
R Word
R Word
R Word
R Word
N
N
Y
Y
Y
L11
L11
L16
L11
L11
V
A
V
A
C
NA
NA
NA
NA
NA
113
113
113
113
113
READ_IIN
READ_VOUT
READ_IOUT
READ_TEMPERATURE_1
0x8D External temperature sensor temperature.
This is the value used for all temperature
related processing, including IOUT_CAL_
GAIN.
READ_TEMPERATURE_2
0x8E Internal die junction temperature. Does
not affect any other commands.
R Word
N
L11
C
NA
114
READ_FREQUENCY
READ_POUT
0x95 Measured PWM switching frequency.
0x96 Measured output power
R Word
R Word
R Word
R Byte
Y
Y
Y
N
L11
L11
L11
Reg
Hz
W
W
NA
N/A
114
114
114
105
READ_PIN
0x97 Calculated input power
N/A
PMBus_REVISION
0x98 PMBus revision supported by this device.
Current revision is 1.2.
0x22
MFR_ID
0x99 The manufacturer ID of the LTM4678 in
ASCII.
R String
R String
N
N
ASC
ASC
LTC
105
105
MFR_MODEL
0x9A Manufacturer part number in ASCII.
Rev 0
47
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LTM4678
PMBus COMMAND SUMMARY
CMD
DATA
DEFAULT
VALUE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
PAGE
MFR_VOUT_MAX
0xA5 Maximum allowed output voltage
including VOUT_OV_FAULT_LIMIT.
R Word
Y
N
N
L16
%
V
3.6
89
0x0399
MFR_PIN_ACCURACY
USER_DATA_00
0xAC Returns the accuracy of the READ_PIN
command
R Byte
5.0%
NA
114
104
0xB0 OEM RESERVED. Typically used for part
serialization.
R/W Word
Reg
Y
USER_DATA_01
USER_DATA_02
0xB1 Manufacturer reserved for LTpowerPlay.
R/W Word
R/W Word
Y
N
Reg
Reg
Y
Y
NA
NA
104
104
0xB2 OEM RESERVED. Typically used for part
serialization
USER_DATA_03
USER_DATA_04
MFR_EE_UNLOCK
MFR_EE_ERASE
MFR_EE_DATA
0xB3 An NVM word available for the user.
0xB4 An NVM word available for the user.
0xBD Contact factory.
R/W Word
R/W Word
Y
N
Reg
Reg
Y
Y
0x0000
0x0000
104
104
121
121
121
79
0xBE Contact factory.
0xBF Contact factory.
MFR_CHAN_CONFIG
0xD0 Configuration bits that are channel
specific.
R/W Byte
R/W Byte
Y
Reg
Y
0x1D
MFR_CONFIG_ALL
0xD1 General configuration bits.
N
Y
Reg
Reg
Y
Y
0x21
80
MFR_FAULT_ PROPAGATE
0xD2 Configuration that determines which faults R/W Word
0x6993
102
are propagated to the FAULT pin.
MFR_PWM_COMP
0xD3 PWM loop compensation configuration
0xD4 Configuration for the PWM engine.
R/W Byte
R/W Byte
R/W Byte
Y
Y
Y
Reg
Reg
Reg
Y
Y
Y
0x28
0xC7
0xC0
83
82
MFR_PWM_MODE
MFR_FAULT_RESPONSE
0xD5 Action to be taken by the device when the
100
FAULT pin is externally asserted low.
MFR_OT_FAULT_ RESPONSE 0xD6 Action to be taken by the device when an
internal overtemperature fault is detected.
R Byte
N
Y
Reg
L11
0xC0
NA
100
114
MFR_IOUT_PEAK
0xD7 Report the maximum measured value of
READ_ IOUT since last MFR_CLEAR_
PEAKS.
R Word
A
MFR_ADC_CONTROL
MFR_RETRY_DELAY
MFR_RESTART_DELAY
MFR_VOUT_PEAK
MFR_VIN_PEAK
0xD8 ADC telemetry parameter selected for
repeated fast ADC read back
R/W Byte
N
Y
Y
Y
N
Y
Reg
L11
L11
L16
L11
L11
0x00
115
95
0xDB Retry interval during FAULT retry mode.
R/W Word
ms
ms
V
Y
Y
250.0
0xF3E8
0xDC Minimum time the RUN pin is held low by R/W Word
the LTM4678.
150.0
0xF258
95
0xDD Maximum measured value of READ_VOUT
since last MFR_CLEAR_PEAKS.
R Word
R Word
R Word
NA
NA
NA
114
114
115
0xDE Maximum measured value of READ_VIN
since last MFR_CLEAR_PEAKS.
V
MFR_TEMPERATURE_1_ PEAK 0xDF Maximum measured value of external
Temperature (READ_TEMPERATURE_1)
C
since last MFR_CLEAR_PEAKS.
MFR_READ_IIN_PEAK
0xE1 Maximum measured value of READ_IIN
command since last MFR_CLEAR_PEAKS
R Word
N
L11
A
A
NA
115
MFR_CLEAR_PEAKS
MFR_READ_ICHIP
MFR_PADS
0xE3 Clears all peak values.
Send Byte
R Word
N
N
N
NA
NA
NA
107
115
111
0xE4 Measured supply current of the SV pin
L11
Reg
IN
0xE5 Digital status of the I/O pads.
R Word
Rev 0
48
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LTM4678
PMBus COMMAND SUMMARY
CMD
DATA
PAGED FORMAT UNITS NVM
DEFAULT
COMMAND NAME
MFR_ADDRESS
MFR_SPECIAL_ID
CODE DESCRIPTION
TYPE
VALUE
PAGE
79
2
0xE6 Sets the 7-bit I C address byte.
R/W Byte
R Word
N
N
Reg
Reg
Y
0x4F
0xE7 Manufacturer code representing the
LTM4678 and revision
0x4100
105
MFR_IIN_CAL_GAIN
0xE8 The resistance value of the input current
sense element in mΩ.
R/W Word
Send Byte
N
N
L11
mΩ
Y
2.0
91
0xC200
MFR_FAULT_LOG_ STORE
0xEA Command a transfer of the fault log from
RAM to EEPROM.
NA
118
MFR_INFO
0x
0x
Contact factory.
SET AT FACTORY
120
89
MFR_IOUT_CAL_GAIN
MFR_FAULT_LOG_ CLEAR
0xEC Initialize the EEPROM block reserved for
fault logging.
Send Byte
N
NA
121
MFR_FAULT_LOG
MFR_COMMON
0xEE Fault log data bytes.
R Block
R Byte
N
N
Reg
Reg
Y
NA
NA
117
112
0xEF Manufacturer status bits that are common
across multiple ADI chips.
MFR_COMPARE_USER_ ALL
0xF0 Compares current command contents
with NVM.
Send Byte
R Word
N
N
N
Y
N
Y
Y
Y
N
N
NA
NA
117
115
84
MFR_TEMPERATURE_2_ PEAK 0xF4 Peak internal die temperature since last
MFR_ CLEAR_PEAKS.
L11
Reg
CF
C
MFR_PWM_CONFIG
MFR_IOUT_CAL_GAIN_ TC
MFR_ICHIP_CAL_GAIN
MFR_TEMP_1_GAIN
MFR_TEMP_1_OFFSET
MFR_RAIL_ADDRESS
MFR_REAL_TIME
0xF5 Set numerous parameters for the DC/DC
controller including phasing.
R/W Byte
R/W Word
R/W Word
Y
Y
Y
Y
Y
Y
0x10
0xF6 Temperature coefficient of the current
sensing element.
ppm/
˚C
3900
0x0F3C
89
0xF7 The resistance value of the V pin filter
L11
CF
mΩ
1000
0x03E8
86
IN
element in mΩ.
0xF8 Sets the slope of the external temperature R/W Word
sensor.
0.995
0x3FAE
92
0xF9 Sets the offset of the external temperature R/W Word
sensor with respect to –273.1°C
L11
Reg
CF
C
0.0
0x8000
92
0xFA Common address for PolyPhase outputs
to adjust common parameters.
R/W Byte
0x80
79
0xFB 48-bit share-clock counter value.
R Block
NA
105104
81
MFR_RESET
0xFD Commanded reset without requiring a
power down.
Send Byte
NA
Note 1: Commands indicated with Y in the NVM column indicate that these commands are stored and restored using the STORE_USER_ALL and
RESTORE_USER_ALL commands, respectively.
Note 2: Commands with a default value of NA indicate “not applicable”. Commands with a default value of FS indicate “factory set on a per part basis”.
Note 3: The LTM4678 contains additional commands not listed in Table 7. Reading these commands is harmless to the operation of the IC; however, the
contents and meaning of these commands can change without notice.
Note 4: Some of the unpublished commands are read-only and will generate a CML bit 6 fault if written.
Note 5: Writing to commands not published in Table 7 is not permitted.
Note 6: The user should not assume compatibility of commands between different parts based upon command names. Always refer to the manufacturer’s
data sheet for each part for a complete definition of a command’s function. ADI strives to keep command functionality compatible between all ADI
devices. Differences may occur to address specific product requirements.
Rev 0
49
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LTM4678
PMBus COMMAND SUMMARY
Table 8. Data Format Abbreviations
L11
Linear_5s_11s
PMBus data field b[15:0]
N
Value = Y • 2
where N = b[15:11] is a 5-bit two’s complement integer and Y = b[10:0] is an 11-bit two’s complement integer
Example:
For b[15:0] = 0x9807 = ‘b10011_000_0000_0111
–13
–6
Value = 7 • 2 = 854 • 10
From “PMBus Spec Part II: Paragraph 7.1”
L16
Linear_16u
PMBus data field b[15:0]
N
Value = Y • 2
where Y = b[15:0] is an unsigned integer and N = VOUT_MODE_PARAMETER is a 5-bit two’s complement exponent that is
hardwired to –12 decimal
Example:
For b[15:0] = 0x9800 = ‘b1001_1000_0000_0000
–12
Value = 19456 • 2 = 4.75 From “PMBus Spec Part II: Paragraph 8.2”
Reg
L16
Register
PMBus data field b[15:0] or b[7:0].
Bit field meaning is defined in detailed PMBus Command Description.
Integer Word
PMBus data field b[15:0]
Value = Y
where Y = b[15:0] is a 16-bit unsigned integer
Example:
For b[15:0] = 0x9807 = ‘b1001_1000_0000_0111
Value = 38919 (decimal)
CF
Custom Format
ASCII Format
Value is defined in detailed PMBus Command Description.
This is often an unsigned or two’s complement integer scaled by an MFR specific constant.
ASC
A variable length string of text characters conforming to ISO/IEC 8859-1 standard.
Rev 0
50
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LTM4678
APPLICATIONS INFORMATION
V TO V
STEP-DOWN RATIOS
OUTPUT CAPACITORS
IN
OUT
There are restrictions in the maximum V and V
step-
The LTM4678 is designed for low output voltage ripple
noise and good transient response. The bulk output
IN
OUT
down ratio that can be achieved for a given input voltage.
Each output of the LTM4678 is capable of 95% duty cycle
capacitors defined as C
are chosen with low enough
OUT
at 500kHz, but the V to V
minimum dropout is still
effective series resistance (ESR) to meet the output volt-
age ripple and transient requirements. C can be a low
IN
OUT
a function of its load current and will limit output current
OUT
capability related to high duty cycle on the topside switch.
ESR tantalum capacitor, a low ESR polymer capacitor or
ceramic capacitor. The typical output capacitance range
for each output is from 400µF to 1000µF. Additional
output filtering may be required by the system designer,
if further reduction of output ripple or dynamic transient
spikes is required. Table 13 shows a matrix of different
output voltages and output capacitors to minimize the
voltage droop and overshoot during a 0A to 12.5A step,
12A/µs transient each channel. Table 13 optimizes total
equivalent ESR and total bulk capacitance to optimize the
transient performance. Stability criteria are considered
in the Table 13 matrix, and the LTPowerCAD Design Tool
will be provided for stability analysis. Multiphase opera-
tion reduces effective output ripple as a function of the
number of phases. Application Note 77 discusses this
noise reduction versus output ripple current cancella-
tion, but the output capacitance should be considered
carefully as a function of stability and transient response.
The LTPowerCAD Design Tool can calculate the output
ripple reduction as the number of implemented phases
Minimum on-time t
is another consideration in
ON(MIN)
operating at a specified duty cycle while operating at a
certain frequency due to the fact that t < D/f
,
SW
ON(MIN)
where D is duty cycle and f is the switching frequency.
SW
t
is specified in the electrical parameters as 50ns.
ON(MIN)
See Note 6 in the Electrical Characteristics section for
output current guideline.
INPUT CAPACITORS
The LTM4678 module should be connected to a low AC
impedance DC source. For the regulator input, four 22µF
input ceramic capacitors are used to handle the RMS
ripple current. A 47µF to 150µF surface mount aluminum
electrolytic bulk capacitor can be used for more input bulk
capacitance. This bulk input capacitor is only needed if
the input source impedance is compromised by long in-
ductive leads, traces or not enough source capacitance.
If low impedance power planes are used, then this bulk
capacitor is not needed.
increases by N times. A small value 10Ω resistor can be
+
placed in series from V
to the V
pin to allow
OUTn
OSNS0
For a buck converter, the switching duty-cycle can be
estimated as:
for a bode plot analyzer to inject a signal into the control
loop and validate the regulator stability. The LTM4678’s
stability compensation can be adjusted using two external
capacitors, and the MFR_PWM_COMP commands.
VOUTn
Dn =
V
INn
Without considering the inductor current ripple, for each
output, the RMS current of the input capacitor can be
estimated as:
LIGHT LOAD CURRENT OPERATION
The LTM4678 has two modes of operation including high
efficiency, discontinuous conduction mode or forced
continuous conduction mode. The mode of operation is
configured by bit 0 of the MFR_PWM_MODEn command
(discontinuous conduction is always the start-up mode,
forced continuous is the default running mode).
IOUTn(MAX)
ICIN (RMS)
=
• D • 1−D
n n
(
)
n
η%
Intheaboveequation, %istheestimatedefficiencyofthe
η
power module. The bulk capacitor can be a switcher-rated
electrolytic aluminum capacitor, or a polymer capacitor.
If a channel is enabled for discontinuous mode opera-
tion, the inductor current is not allowed to reverse. The
Rev 0
51
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LTM4678
APPLICATIONS INFORMATION
reverse current comparator, I , turns off the bottom
tor pin-strap settings on the FSWPH_CFG pin (see Table
3). Using MFR_CONFIG_ALL[4] = 1b, the LTM4678s
SYNC pin becomes a high impedance input, only—i.e.,
it does not drive SYNC low. The module synchronizes its
frequency to that of the clock applied to its SYNC pin.
The only shortcoming of this approach is: in the absence
of an externally applied clock, the switching frequency of
the module will default to the low end of its frequency-
synchronization capture range (~225kHz).
REV
MOSFET (MBn) just before the inductor current reaches
zero, preventing it from reversing and going negative.
Thus, the controller can operate in discontinuous (pulse-
skipping) operation. In forced continuous operation, the
inductor current is allowed to reverse at light loads or
under large transient conditions. The peak inductor cur-
rent is determined solely by the voltage on the COMPnb
pin. In this mode, the efficiency at light loads is lower than
in discontinuous mode operation. However, continuous
mode exhibits lower output ripple and less interference
with audio circuitry. Forced continuous conduction mode
may result in reverse inductor current, which can cause
the input supply to boost. The VIN_OV_FAULT_LIMIT can
If fault-tolerance to the loss of an externally applied SYNC
clock is desired, the FREQUENCY_SWITCH command of
a “sync slave” can be left at the nominal target switching
frequency of the application, and not 0x0000. However,
it is then still necessary to configure MFR_CONFIG_
ALL[4] = 1b. With this combination of configurations, the
LTM4678’s SYNC pin becomes a high impedance input
and the module synchronizes its frequency to that of the
externallyappliedclock, providedthatthefrequencyofthe
externallyappliedclockexceeds~½ofthetargetfrequency
(FREQUENCY_SWITCH). If the SYNC clock is absent, the
module responds by operating at its target frequency,
indefinitely. If and when the SYNC clock is restored, the
module automatically phase-locks to the SYNC clock as
normal. The only shortcoming of this approach is: the
EEPROMmustbeconfiguredperaboveguidance;resistor
pin-strappingoptionsontheFSWPH_CFGpinalonecannot
provide fault-tolerance to the absence of the SYNC clock.
detect this (if SV is connected to V and/or V ) and
IN
IN0
IN1
turn off the offending channel. However, this fault is based
on an ADC read and can nominally take up to 100ms to
detect. If there is a concern about the input supply boost-
ing, keep the part in discontinuous conduction operation.
SWITCHING FREQUENCY AND PHASE
The switching frequency of the LTM4678’s channels is
established by its analog phase-locked-loop (PLL) lock-
ing on to the clock present at the module’s SYNC pin. The
clock waveform on the SYNC pin can be generated by the
LTM4678’sinternalcircuitrywhenanexternalpull-upresis-
tor to 3.3V (e.g., V
) is provided, in combination with
DD33
2
theLTM4678controlIC’sFREQUENCY_SWITCHcommand
beingsettooneofthefollowingsupportedvalues:250kHz,
350kHz,425kHz,500kHz,575kHz,650kHz,750kHz.Inthis
configuration,themoduleiscalleda“syncmaster”:(using
thefactory-defaultsettingofMFR_CONFIG_ALL[4]=0b),
SYNC becomes a bidirectional open-drain pin, and the
LTM4678 pulls SYNC logic low for nominally 500ns at a
time, at the prescribed clock rate. The SYNC signal can be
bused to other LTM4678 modules (configured as “sync
slaves”),forpurposesofsynchronizingswitchingfrequen-
cies of multiple modules within a system—but only one
LTM4678 should be configured as a “sync master”; the
other LTM4678(s) should be configured as “sync slaves”.
The FREQUENCY_SWITCH register can be altered via I C
commands,butonlywhenswitchingactionisdisengaged,
i.e.,themodule’soutputsareturnedoff.TheFREQUENCY_
SWITCH command takes on the value stored in NVM at
SV power-up, but is overridden according to a resis-
IN
tor pin-strap applied between the FSWPH_CFG pin and
SGND only if the module is configured to respect resistor
pin-strap settings (MFR_CONFIG_ALL[6] = 0b). Table 3
highlights available resistor pin-strap and corresponding
FREQUENCY_SWITCH settings.
The relative phasing of all active channels in a PolyPhase
rail should be optimally phased. The relative phasing of
each rail is 360°/n, where n is the number of phases in the
rail. MFR_PWM_CONFIG[2:0]configureschannelrelative
phasing with respect to the SYNC pin. Phase relationship
The most straightforward way is to set its FREQUENCY_
SWITCH command to 0x0000 and MFR_CONFIG_
ALL[4] = 1b. This can be easily implemented with resis-
Rev 0
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LTM4678
APPLICATIONS INFORMATION
values are indicated with 0° corresponding to the falling
edge of SYNC being coincident with the turn-on of the top
MOSFETs, (MTn).
Table 9. Recommended Switching Frequency for Various VIN-
to-VOUT Step-Down Scenarios
5V
IN
8V
IN
12V
IN
0.9V
1.0V
1.2V
1.5V
1.8V
2.5V
3.3V
OUT
OUT
OUT
OUT
OUT
OUT
OUT
The MFR_PWM_CONFIG command can be altered via
350kHz to 400kHz
2
I C commands, but only when switching action is dis-
engaged, i.e., the module’s outputs are turned off. The
MFR_PWM_CONFIG command takes on the value stored
450kHz to 550kHz
650kHz to 750kHz
in NVM at SV power-up, but is overridden according to a
IN
resistorpin-strapappliedbetweentheFSWPH_CFGpinand
SGND only if the module is configured to respect resistor
pin-strap settings (MFR_CONFIG_ALL[6] = 0b). Table 3
highlights available resistor pin-strap and corresponding
MFR_PWM_CONFIG[2:0] settings.
OUTPUT CURRENT LIMIT PROGRAMMING
Thecycle-by-cyclecurrentlimitthresholdvoltage,V limit
IL
is proportional to V
, which can be programmed
Some combinations of FREQUENCY_SWITCH and
MFR_PWM_CONFIG[2:0] are not available by resistor
pin-strapping the FSWPH_CFG pin. All combinations
of supported values for FREQUENCY_SWITCH and
MFR_PWM_CONFIG[2:0] can be configured by NVM pro-
COMPnb
from1.45Vto2.2VusingthePMBuscommandIOUT_OC_
FAULT_LIMIT. The LTM4678 uses only the sub-milliohm
sensing to detect current levels. See page 90. The
LTM4678 has two ranges of current limit programming.
The value of MFR_PWM_MODE[2] is reserved and the
MFR_PWM_MODE[7], and IOUT_OC_FAULT_LIMIT are
usedtosetthecurrentlimitlevel,seethesectionofthePM-
Buscommands,thedevicecanregulateoutputvoltagewith
thepeakcurrentunderthevalueofIOUT_OC_FAULT_LIMIT
in normal operation. In case of output current exceeding
that current limit, an OC fault will be issued. Each of the
IOUT_OC_FAULT_LIMIT ranges will effects the loop gain,
and subsequently effects the loop stability, so setting the
range of current limiting is a part of loop design.
2
gramming—or,I Ctransactions,providedswitchingaction
is disengaged, i.e., the module’s outputs are turned off.
Care must be taken to minimize capacitance on SYNC
to assure that the pull-up resistor versus the capacitor
load has a low enough time constant for the application
to form a “clean” clock. (See “Open-Drain Pins”, later in
this section.)
When a LTM4678 is configured as a sync slave, it is per-
missible for external circuitry to drive the SYNC pin from
a current-limited source (less than 10mA), rather than
using a pull-up resistor. Any external circuitry must not
The LTPowerCAD Design Tool can be used to look at the
loop stability changes if current limit is adjusted. The
LTM4678 will automatically update the current limit as the
inductor temperature changes. Keep in mind this opera-
tion is on a cycle-by-cycle basis and is only a function of
the peak inductor current. The average inductor current is
monitored by the ADC converter and can provide a warn-
ing if too much average output current is detected. The
overcurrent fault is detected when the COMPnb voltage
hits the maximum value. The digital processor within the
LTM4678 provides the ability to either ignore the fault,
shut down and latch off or shut down and retry indefinitely
(hiccup). Refer to the overcurrent portion of the Operation
section for more detail. The Read_POUT can be used to
readback calculated output power.
drive high with arbitrarily low impedance at SV power-
IN
up, because the SYNC output can be low impedance until
NVM contents have been downloaded to RAM.
Recommended LTM4678 switching frequencies of op-
eration for many common V -to-V
applications are
IN
OUT
indicated below. When the two channels of an LTM4678
are stepping input voltage(s) down to output voltages
whose recommended switching frequencies below are
significantly different, operation at the higher of the two
recommended switching frequencies is preferable, but
minimum on-time must be considered. (See Minimum
On-Time Considerations section.)
Rev 0
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LTM4678
APPLICATIONS INFORMATION
MINIMUM ON-TIME CONSIDERATIONS
Soft-start is performed by actively regulating the load
voltage while digitally ramping the target voltage from 0V
to the commanded voltage set point. The rise time of the
voltage ramp can be programmed using the TON_RISEn
commandtominimizeinrushcurrentsassociatedwiththe
start-up voltage ramp. The soft-start feature is disabled
by setting TON_RISEn to any value less than 0.250ms.
The LTM4678 performs the necessary math internally
to assure the voltage ramp is controlled to the desired
slope. However, the voltage slope can not be any faster
Minimum on-time, t , is the smallest time duration
ON(MIN)
thattheLTM4678iscapableofturningonthetopMOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
VOUTn
INn •fOSC
tON(MIN)
<
V
than the V
fundamental limits of the power stage. The
OUTn
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
number of t
steps in the ramp is proportional to
ON(MIN)
TON_RISE/0.1ms.Therefore, the shorter the TON_RISEn
time setting, the more discrete steps in the soft-start
ramp appear.
The minimum on-time for the LTM4678 is 50ns.
The LTM4678 PWM always operates in discontinuous
mode during the TON_RISEn operation. In discontinuous
mode, the bottom MOSFET (MBn) is turned off as soon
as reverse current is detected in the inductor. This allows
the regulator to start up into a pre-biased load.
VARIABLE DELAY TIME, SOFT-START AND OUTPUT
VOLTAGE RAMPING
The LTM4678 must enter its run state prior to soft-start.
There is no analog tracking feature in the LTM4678; how-
ever, two outputs can be given the same TON_RISEn and
TON_DELAYn times to achieve ratiometric rail tracking.
Because the RUNn pins are released at the same time and
both units use the same time base (SHARE_CLK), the
outputs track very closely. If the circuit is in a PolyPhase
configuration, all timing parameters must be the same.
The RUNn pins are released after the part initializes and
SV is greater than the VIN_ON threshold. If multiple
IN
LTM4678s are used in an application, they should be
configured to share the same RUNn pins. They all hold
their respective RUNn pins low until all devices initialize
and SV exceeds the VIN_ON threshold for all devices.
IN
The SHARE_CLK pin assures all the devices connected to
the signal use the same time base.
DIGITAL SERVO MODE
After the RUNn pin releases, the controller waits for the
user-specified turn-on delay (TON_DELAYn) prior to ini-
tiating an output voltage ramp. Multiple LTM4678s and
other ADI parts can be configured to start with variable
delay times. To work correctly, all devices use the same
timing clock (SHARE_CLK) and all devices must share
the RUNn pin.
For maximum accuracy in the regulated output voltage,
enable the digital servo loop by asserting bit 6 of the
MFR_PWM_MODE command. In digital servo mode, the
LTM4678 will adjust the regulated output voltage based
on the ADC voltage reading. Every 90ms the digital servo
loop will step the LSB of the DAC (nominally 1.375mV or
0.688mV depending on the voltage range bit) until the
outputisatthecorrectADCreading.Atpower-upthismode
engages after TON_MAX_FAULT_LIMIT unless the limit
is set to 0 (infinite). If the TON_MAX_FAULT_LIMIT is set
to0(infinite),theservobeginsafterTON_RISEiscomplete
This allows the relative delay of all parts to be synchro-
nized. The actual variation in the delay will be dependent
on the highest clock rate of the devices connected to the
SHARE_CLK pin (all Analog Devices ICs are configured
to allow the fastest SHARE_CLK signal to control the tim-
ing of all devices). The SHARE_CLK signal can be 10%
in frequency, thus the actual time delays will have some
variance.
and V
has exceeded the VOUT_UV_FAULT_LIMIT.
OUT
This same point in time is when the output changes from
Rev 0
54
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LTM4678
APPLICATIONS INFORMATION
discontinuous to the programmed mode as indicated in
SOFT OFF (SEQUENCED OFF)
MFR_PWM_MODE bit 0. Refer to Figure 25 for details on
Inadditiontoacontrolledstart-up, theLTM4678alsosup-
portscontrolledturn-off.TheTOFF_DELAYandTOFF_FALL
functionsareshowninFigure26.TOFF_FALLisprocessed
when the RUN pin goes low or if the part is commanded
off. If the part faults off or FAULTn is pulled low externally
and the part is programmed to respond to this, the output
will three-state rather than exhibiting a controlled ramp.
The output will decay as a function of the load. The output
voltage will operate as shown in Figure 26 as long as the
part is in forced continuous mode and the TOFF_FALL
time is sufficiently slow that the power stage can achieve
the desired slope. The TOFF_FALL time can only be met if
the power stage and controller can sink sufficient current
to assure the output is at zero volts by the end of the fall
time interval. If the TOFF_FALL time is set shorter than
the time required to discharge the load capacitance, the
output will not reach the desired zero volt state. At the end
of TOFF_FALL, the controller will cease to sink current and
the V
waveform under time-based sequencing. If the
OUT
TON_MAX_FAULT_LIMIT is set to a value greater than 0
and the TON_MAX_FAULT_RESPONSE is set to ignore
0x00, the servo begins:
1. After the TON_RISE sequence is complete
2. After the TON_MAX_FAULT_LIMIT time is reached;
and
3. After the VOUT_UV_FAULT_LIMIT has been exceed
or the IOUT_OC_FAULT_LIMIT is no longer active.
If the TON_MAX_FAULT_LIMIT is set to a value greater
than 0 and the TON_MAX_FAULT_RESPONSE is not set
to ignore 0x00, the servo begins:
1. After the TON_RISE sequence is complete
2. After the TON_MAX_FAULT_LIMIT time has expired
and both VOUT_UV_FAULT and IOUT_OC_FAULT are
not present.
V
will decay at the natural rate determined by the load
OUT
impedance. If the controller is in discontinuous mode, the
controller will not pull negative current and the output
will be pulled low by the load, not the power stage. The
maximum fall time is limited to 1.3 seconds. The shorter
TOFF_FALL time is set, the larger the discrete steps in the
TOFF_FALL ramp will appear. The number of steps in the
ramp is equal to TOFF_FALL/0.1ms.
The maximum rise time is limited to 1.3 seconds.
In a PolyPhase configuration it is recommended only one
of the control loops have the digital servo mode enabled.
Thiswillassurethevariousloopsdonotworkagainsteach
other due to slight differences in the reference circuits.
ꢀꢍꢇꢍꢆꢁꢅ ꢋꢈRꢃꢄ
ꢎꢄꢀꢈ ꢈꢊꢁꢖꢅꢈꢀ
ꢐꢍꢊꢁꢅ ꢄꢗꢆꢘꢗꢆ
ꢃꢄꢅꢆꢁꢇꢈ Rꢈꢁꢂꢙꢈꢀ
ꢆꢄꢊꢚꢎꢁꢛꢚꢐꢁꢗꢅꢆꢚꢅꢍꢎꢍꢆ
ꢆꢍꢎꢈ ꢀꢈꢅꢁꢏ ꢄꢐ
ꢑ00ꢒꢓ00ꢔꢕ
ꢀꢁꢂ ꢃꢄꢅꢆꢁꢇꢈ
ꢈRRꢄR ꢉꢊꢄꢆ
ꢆꢄ ꢋꢂꢁꢅꢈꢌ
ꢃ
ꢄꢗꢆ
ꢐ
ꢁꢑꢀ
ꢋꢌꢍꢎ ꢂꢏꢌ
ꢀꢉꢊꢇ
ꢓꢜꢝꢞ ꢐꢑꢟ
ꢆꢍꢎꢈ
ꢀꢁꢂꢂꢃꢆꢇꢅꢄꢈ
ꢀꢁꢂꢂꢃꢂꢄꢅꢅ
ꢆꢄꢊꢚRꢍꢋꢈ
ꢆꢄꢊꢚꢀꢈꢅꢁꢏ
Figure 25. Timing Controlled VOUT Rise
Figure 26. TOFF_DELAY and TOFF_FALL
Rev 0
55
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LTM4678
APPLICATIONS INFORMATION
UNDERVOLTAGE LOCKOUT
can be pulled low by external sources indicating a fault in
some other portion of the system. The fault response is
configurable and allows the following options:
The LTM4678 is initialized by an internal threshold-based
UVLO where VIN must be approximately 4V and INTVCC,
VDD33, and VDD25 must be within approximately 20% of
their regulated values. In addition, VDD33 must be within
approximately 7% of the targeted value before the RUN
pin is released. After the part has initialized, an additional
comparatormonitorsVIN. TheVIN_ONthresholdmustbe
exceeded before the power sequencing can begin. When
VIN drops below the VIN_OFF threshold, the SHARE_CLK
pin will be pulled low and VIN must increase above the
VIN_ON threshold before the controller will restart. The
normalstart-upsequencewillbeallowedaftertheVIN_ON
threshold is crossed. If FAULTn is held low when VIN is
applied, ALERT will be asserted low even if the part is
programmed to not assert ALERT when FAULTn is held
low. If I2C communication occurs before the LTM4678 is
out of reset and only a portion of the command is seen by
the part, this can be interpreted as a CML fault. If a CML
fault is detected, ALERT is asserted low.
n
Ignore
n
Shut Down Immediately—Latch Off
n
Shut Down Immediately—Retry Indefinitely at the
Time Interval Specified in MFR_RETRY_DELAY
Refer to the PMBus section of the data sheet and the
PMBus specification for more details.
The OV response is automatic. If an OV condition is de-
tected, TGn goes low and BGn is asserted.
Fault logging is available on the LTM4678. The fault log-
ging is configurable to automatically store data when a
fault occurs that causes the unit to fault off. The header
portion of the fault logging table contains peak values. It
is possible to read these values at any time. This data will
be useful while troubleshooting the fault.
If the LTM4678 internal temperature is in excess of 85°C,
writes into the NVM (other than fault logging) are not
recommended. The data will still be held in RAM, unless
the 3.3V supply UVLO threshold is reached. If the die
temperature exceeds 130°C all NVM communication is
disabled until the die temperature drops below 120°C.
It is possible to program the contents of the NVM in the
applicationiftheVDD33supplyisexternallydrivendirectly
to VDD33 or through EXTVCC. This will activate the digital
portion of the LTM4678 without engaging the high volt-
age sections. PMBus communications are valid in this
supply configuration. If VIN has not been applied to the
LTM4678, bit 3 (NVM Not Initialized) in MFR_COMMON
will be asserted low. If this condition is detected, the part
will only respond to addresses 5A and 5B. To initialize
the part issue the following set of commands: global ad-
dress 0x5B command 0xBD data 0x2B followed by global
address 5B command 0xBD and data 0xC4. The part will
now respond to the correct address. Configure the part
as desired then issue a STORE_USER_ALL. When VIN
is applied a MFR_RESET command must be issued to
allow the PWM to be enabled and valid ADC conversions
to be read.
OPEN-DRAIN PINS
The LTM4678 has the following open-drain pins:
3.3V Pins
1. FAULTn
2. SYNC
3. SHARE_CLK
4. PGOODn
5V Pins (5V pins operate correctly when pulled to 3.3V.)
1. RUNn
2. ALERT
3. SCL
4. SDA
Rev 0
FAULT DETECTION AND HANDLING
The LTM4678 FAULT pins are configurable to indicate a
variety of faults including OV, UV, OC, OT, timing faults,
and peak over current faults. In addition, the FAULT pins
56
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LTM4678
APPLICATIONS INFORMATION
All the above pins have on-chip pull-down transistors that
can sink 3mA at 0.4V. The low threshold on the pins is
0.8V; thus, there is plenty of margin on the digital signals
with 3mA of current. For 3.3V pins, 3mA of current is
a 1.1k resistor. Unless there are transient speed issues
associated with the RC time constant of the resistor pull-
up and parasitic capacitance to ground, a 10k resistor or
larger is generally recommended.
PHASE-LOCKED LOOP AND FREQUENCY
SYNCHRONIZATION
The LTM4678 has a phase-locked loop (PLL) comprised
of an internal voltage-controlled oscillator (VCO) and a
phase detector. The PLL is locked to the falling edge of
the SYNC pin. The phase relationship between the PWM
controller and the falling edge of SYNC is controlled by
the lower 3 bits of the MFR_PWM_ CONFIG command.
For PolyPhase applications, it is recommended that all
the phases be spaced evenly. Thus for a 2-phase system
the signals should be 180° out of phase and a 4-phase
system should be spaced 90°.
For high speed signals such as the SDA, SCL and SYNC,
a lower value resistor may be required. The RC time con-
stant should be set to 1/3 to 1/5 the required rise time
to avoid timing issues. For a 100pF load and a 400kHz
PMBus communication rate, the rise time must be less
than 300ns. The resistor pull-up on the SDA and SCL pins
with the time constant set to 1/3 the rise time is:
The phase detector is an edge-sensitive digital type that
provides a known phase shift between the external and
internal oscillators. This type of phase detector does not
exhibit false lock to harmonics of the external clock.
tRISE
3•100pF
RPULLUP
=
=1k
The output of the phase detector is a pair of complemen-
tary current sources that charge or discharge the internal
filter network. The PLL lock range is guaranteed between
200kHzand1MHz.Nominalpartswillhavearangebeyond
this; however, operation to a wider frequency range is not
guaranteed.
The closest 1% resistor value is 1k. Be careful to minimize
parasitic capacitance on the SDA and SCL pins to avoid
communicationproblems. Toestimatetheloadingcapaci-
tance, monitor the signal in question and measure how
long it takes for the desired signal to reach approximately
63% of the output value. This is a one time constant. The
SYNC pin has an on-chip pull-down transistor with the
output held low for nominally 500ns. If the internal oscil-
lator is set for 500kHz and the load is 100pF and a 3x time
constant is required, the resistor calculation is as follows:
The PLL has a lock detection circuit. If the PLL should lose
lockduringoperation,bit4oftheSTATUS_MFR_SPECIFIC
command is asserted and the ALERT pin is pulled low. The
fault can be cleared by writing a 1 to the bit. If the user
does not wish to see the ALERT pin assert if a PLL_FAULT
occurs, the SMBALERT_MASK command can be used to
prevent the alert.
2µs–500ns
3•100pF
RPULLUP
=
= 5k
If the SYNC signal is not clocking in the application, the
nominal programmed frequency will control the PWM
circuitry. However, if multiple parts share the SYNC pins
and the signal is not clocking, the parts will not be syn-
chronized and excess voltage ripple on the output may be
present. Bit 10 of MFR_PADS will be asserted low if this
condition exists.
The closest 1% resistor is 4.99k.
If timing errors are occurring or if the SYNC frequency is
notasfastasdesired,monitorthewaveformanddetermine
if the RC time constant is too long for the application. If
possible reduce the parasitic capacitance. If not, reduce
the pull-up resistor sufficiently to assure proper timing.
The SHARE_CLK pull-up resistor has a similar equation
with a period of 10µs and a pull-down time of 1µs. The
RC time constant should be approximately 3µs or faster.
If the PWM signal appears to be running at too high a
frequency, monitor the SYNC pin. Extra transitions on
the falling edge will result in the PLL trying to lock on to
noise versus the intended signal. Review routing of digital
control signals and minimize crosstalk to the SYNC signal
Rev 0
57
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LTM4678
APPLICATIONS INFORMATION
to avoid this problem. Multiple LTM4678s are required
to share one SYNC pin in PolyPhase configurations.
For other configurations, connecting the SYNC pins to
form a single SYNC signal is optional. If the SYNC pin
is shared between LTM4678s, only one LTM4678 can
be programmed with a frequency output. All the other
LTM4678s should be programmed to disable the SYNC
output. However their frequency should be programmed
to the nominal desired value.
5.73mmho, and the compensationresistorR
varies
COMPn
from 0kΩ to 62kΩ inside the controller. Two compensa-
tion capacitors, COMPna and COMPnb, are required in the
designandthetypicalratiobetweenCOMPnaandCOMPnb
is 10. Also see Figure 2 Block Diagram and Figure 27.
By adjusting the g and R
only, the LTM4678 can
m
COMPn
provideaflexibleTypeIIcompensationnetworktooptimize
the loop over a wide range of output capacitors. Adjusting
the g will change the gain of the compensation over the
m
whole frequency range without moving the pole and zero
INPUT CURRENT SENSE AMPLIFIER
location, as shown in Figure 28.
The LTM4678 input current sense amplifier can sense the
supply current into the V and V power stages pins
AdjustingtheR
willchangethepoleandzerolocation,
COMP
as shown in Figure 29. It is recommended that the user
IN0
IN1
using an external sense resistor as shown in the Figure
determines the appropriate value for the g and R
using the LTPowerCAD tool.
m
COMPn
2 Block Diagram. The R value can be programmed
SENSE
using the MFR_IIN_CAL_GAIN command. Kelvin sensing
is recommended across the R resistor to eliminate
SENSE
errors.TheMFR_PWM_CONFIG[6:5]setstheinputcurrent
sense amplifier gain. See the MFR_PWM_CONFIG sec-
tion. The IIN_OC_WARN_LIMIT command sets the value
of the input current measured by the ADC, in amperes,
that causes a warning indicating the input current is high.
The READ_IIN value will be used to determine if this limit
has been exceeded. The READ_IIN command returns the
input current, in Amperes, as measured across the input
current sense resistor.
ꢂ
ꢁ
Rꢃꢄ
ꢐ
ꢑ
ꢄꢅ
ꢀ
ꢊꢊꢏꢄ
ꢋꢌꢍꢎnb
R
ꢋꢌꢍꢎn
ꢋꢌꢍꢎna
ꢆꢇꢈꢉ ꢄꢊꢈ
ꢋ
ꢋ
ꢋꢌꢍꢎH
ꢋꢌꢍꢎL
Figure 27. Programmable Loop Compensation
There is an IR voltage drop from the supply to the SV pin
IN
duetothecurrentflowingintotheSV pin.Tocompensate
IN
for this voltage drop, the MFR_RVIN will be automatically
set to the 1Ω internal sense resistor in the Figure 2 Block
Diagram.TheLTM4678willmultiplytheMFR_READ_ICHIP
measurement value by this 1Ω resistor and add this volt-
ꢒꢋꢓꢃ ꢀꢀ ꢂꢔꢕꢓꢃꢁꢅꢄꢒꢀꢔꢁ
ꢑꢄꢀꢁ
age to the measured voltage at the SV pin. Therefore,
IN
READ_VIN = VSVIN_PIN + (MFR_READ_ICHIP • 1Ω)
The MFR_READ_ICHIP command is used to measure the
internalcontrollercurrent.UsingtheREAD_PINcommand
allows for reading calculated input power.
ꢀꢁꢂRꢃꢄꢅꢃ ꢆ
ꢇ
ꢈRꢃꢉꢊꢃꢁꢂꢋ
ꢌꢍꢎꢏ ꢈꢐꢏ
PROGRAMMABLE LOOP COMPENSATION
Figure 28. Error Amp gm Adjust
The LTM4678 offers programmable loop compensation
to optimize the transient response without any hardware
change.Theerroramplifiergaing variesfrom1.0mmhoto
m
Rev 0
58
For more information www.analog.com
LTM4678
APPLICATIONS INFORMATION
ꢔꢌꢈꢃ ꢀꢀ ꢂꢆꢇꢈꢃꢁꢅꢄꢔꢀꢆꢁ
The COMPna series internal R
and external C
COMPna
COMPn
ꢓꢄꢀꢁ
filter sets the dominant pole-zero loop compensation. The
internal R value can be modified (from 0Ω to 62kΩ)
COMPn
usingbits[4:0]oftheMFR_PWM_COMPcommand.Adjust
the value of R to optimize transient response once
COMPn
the final PCB layout is done and the particular C
COMPbn
filter capacitor and output capacitor type and value have
beendetermined.Theoutputcapacitorsneedtobeselected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 80%
of full-load current having a rise time of 1µs to 10µs will
produceoutputvoltageandCOMPpinwaveformsthatwill
give a sense of the overall loop stability without break-
ing the feedback loop. Placing a power MOSFET with a
resistor to ground directly across the output capacitor
and driving the gate with an appropriate signal generator
is a practical way to produce to a load step. The MOSFET
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ꢂꢆꢇꢈn
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Figure 29. RTH Adjust
CHECKING TRANSIENT RESPONSE
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
+ R
will produce output currents approximately
SERIES
equal to V /R
load current. When a load step occurs, V
shifts by an
OUT
. R
values from 0.1Ω to 2Ω
OUT SERIES SERIES
amount equal to ∆I
, where ESR is the effective
LOAD(ESR)
are valid depending on the current limit settings and the
programmedoutputvoltage.Theinitialoutputvoltagestep
resulting from the step change in output current may not
bewithinthebandwidthofthefeedbackloop,sothissignal
cannot be used to determine phase margin. This is why
it is better to look at the COMP pin signal which is in the
feedback loop and is the filtered and compensated control
loop response. The gain of the loop will be increased by
series resistance of C . ∆I
also begins to charge or
generating the feedback error signal that
OUT
LOAD
discharge C
OUT
forces the regulator to adapt to the current change and
return V to its steady-state value. During this recovery
OUT
OUT
time V
can be monitored for excessive overshoot or
ringing, which would indicate a stability problem. The
availabilityoftheCOMPpinnotonlyallowsoptimizationof
control loop behavior but also provides a DC-coupled and
AC-filtered closed-loop response test point. The DC step,
rise time and settling at this test point truly reflects the
closed-loop response. Assuming a predominantly second
order system, phasemarginand/or dampingfactorcan be
estimated using the percentage of overshoot seen at this
pin.Thebandwidthcanalsobeestimatedbyexaminingthe
risetimeatthepin. TheCOMPnaexternalcapacitorshown
in the Typical Application circuit will provide an adequate
starting point for most applications. The programmable
parametersthataffectloopgainarethevoltagerange,bit[1]
of the MFR_PWM_CONFIG command, the current range
increasing R
and the bandwidth of the loop will be
COMP
increased by decreasing C
. If R
is increased
COMPna
COMP
by the same factor that C is decreased, the zero fre-
TH
quency will be kept the same, thereby keeping the phase
shift the same in the most critical frequency range of the
feedback loop. The gain of the loop will be proportional
to the transconductance of the error amplifier which is
set using bits[7:5] of the MFR_PWM_COMP command.
The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance. A second, more
severe transient is caused by switching in loads with large
(>1µF) supply bypass capacitors. The discharged bypass
bit[7] of the MFR_PWM_MODE command, the g of the
m
PWM channel amplifier bits [7:5] of MFR_PWM_COMP,
capacitorsareeffectivelyputinparallelwithC , causing
OUT
and the internal R
compensation resistor, bits[4:0]
COMP
a rapid drop in V . No regulator can alter its delivery of
OUT
of MFR_PWM_COMP. Be sure to establish these settings
prior to compensation calculation.
currentquicklyenoughtopreventthissuddenstepchange
Rev 0
59
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LTM4678
APPLICATIONS INFORMATION
2
in output voltage if the load switch resistance is low and
CONNECTING THE USB TO I C/SMBUS/PMBUS
it is driven quickly. If the ratio of C
to C
is greater
CONTROLLER TO THE LTM4678 IN SYSTEM
LOAD
OUT
than1:50, theswitchrisetimeshouldbecontrolledsothat
the load rise time is limited to approximately 25 • C
Thus a 10µF capacitor would require a 250µs rise time,
limiting the charging current to about 200mA.
2
The ADI USB-to-I C/SMBus/PMBus adapter (DC1613A or
.
LOAD
equivalent)canbeinterfacedtotheLTM4678ontheuser’s
board for programming, telemetry and system debug.
The adapter, when used in conjunction with LTpowerPlay,
providesapowerfulwaytodebuganentirepowersystem.
Faults are quickly diagnosed using telemetry, fault status
commands and the fault log. The final configuration can
be quickly developed and stored to the LTM4678 EE-
PROM. Figure 30 illustrates the application schematic for
powering, programming and communication with one or
more LTM4678s via the ADI I C/SMBus/PMBus adapter
regardless of whether or not system power is present. If
system power is not present, the dongle will power the
LTM4678throughtheV
when V is not applied and the V
global address 0x5B command 0xBD data 0x2B followed
byaddress0x5Bcommand0xBDdata0xC4.TheLTM4678
cannowcommunicatewiththeinternalEEPROMandread
the project file utilizing Figure 30. Controller Connection
can be updated. To write the updated project file to the
PolyPhase Configuration
WhenconfiguringaPolyPhaserailwithmultipleLTM4678s,
theusermustsharetheSYNC,COMP,SHARE_CLK,FAULT,
andALERTpinsoftheseparts.Besuretousepull-upresis-
tors on FAULT, SHARE_CLK and ALERT. One of the part’s
SYNCpinsmustbesettothedesiredswitchingfrequency,
and all other FREQUENCY_SWITCH commands must be
set to External Clock. If an external oscillator is provided,
settheFREQUENCY_SWITCHcommandtoExternalClock
forallparts. Therelativephasingofallthechannelsshould
be spaced equally. The MFR_RAIL_ ADDRESS of all the
devices should be set to the same value.
2
supplypin.Toinitializethepart
DD33
pin is powered, use
IN
DD33
+
Multiple channels need to tie all the V
pins to-
SENSEn
–
gether, and all the V
pins together, COMPna and
SENSEn
COMP pins together as well. Do not assert bit[4] of
nb
NVM issue a STORE_USER _ALL command. When V is
applied, a MFR_RESET must be issued to allow the PWM
POWER to be enabled and valid ADCs to be read.
IN
MFR_CONFIG_ALL except in a PolyPhase application.
See application example Figure 47.
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ꢑꢒꢈꢃꢒR
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ꢉ00ꢛ
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ꢅ
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ꢘꢏꢂꢐRꢏꢜꢜꢒR
ꢀ
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ꢀ
ꢀ
ꢃꢃꢅꢆ
ꢃꢃꢄꢄ
ꢐꢓ0ꢉ0ꢉꢔ
ꢉꢊꢋ
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ꢇꢃꢈ
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ꢁꢂ
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ꢙꢗꢚꢕ ꢋꢄ0
Figure 30. Controller Connection
Rev 0
60
For more information www.analog.com
LTM4678
APPLICATIONS INFORMATION
Because of the adapter’s limited current sourcing capabil-
target system. The software also provides an automatic
update feature to keep the revisions current with the latest
set of device drivers and documentation.
ity, only the LTM4678s, their associated pull-up resistors
2
and the I C pull-up resistors should be powered from the
2
V
3.3V supply. In addition any device sharing the I C
DD33
A great deal of context sensitive help is available with
LTpower Play along with several tutorial demos. Complete
information is available at:
bus connections with the LTM4678 should not have body
diodesbetweentheSDA/SCLpinsandtheirrespectiveV
DD
nodebecausethiswillinterferewithbuscommunicationin
theabsenceofsystempower.IfV isapplied,theDC1613A
http://www.linear.com/ltpowerplay
IN
will not supply the power to the LTM4678s on the board. It
is recommended the RUNn pins be held low or no voltage
configuration resistors inserted to avoid providing power
to the load until the part is fully configured.
PMBus COMMUNICATION AND COMMAND
PROCESSING
The LTM4678 has a one deep buffer to hold the last data
written for each supported command prior to processing
as shown in Figure 32, Write Command Data Processing.
Whenthepartreceivesanewcommandfromthebus,itcop-
ies the data into the Write Command Data Buffer, indicates
to the internal processor that this command data needs
to be fetched, and converts the command to its internal
formatsothatitcanbeexecuted.Twodistinctparallelblocks
manage command buffering and command processing
(fetch,convert,andexecute)toensurethelastdatawritten
to any command is never lost. Command data buffering
handles incoming PMBus writes by storing the command
datatotheWriteCommandDataBufferandmarkingthese
commands for future processing. The internal processor
runs in parallel and handles the sometimes slower task of
fetching, convertingandexecutingcommandsmarkedfor
processing. Some computationally intensive commands
(e.g., timing parameters, temperatures, voltages and
currents) have internal processor execution times that
may be long relative to PMBus timing. If the part is busy
processing a command, and new command(s) arrive,
executionmaybedelayedorprocessedinadifferentorder
thanreceived.Thepartindicateswheninternalcalculations
are in process via bit 5 of MFR_COMMON (“calculations
not pending”). When the part is busy calculating, bit 5 is
cleared. When this bit is set, the part is ready for another
command. An example polling loop is provided in Figure
33 which ensures that commands are processed in order
while simplifying error handling routines.
TheLTM4678isfullyisolatedfromthehostPC’sgroundby
theDC1613A.The3.3VfromtheadapterandtheLTM4678
V
pinmustbedriventoeachLTM4678withaseparate
DD33
PFET. If both V and EXTV are not applied, the V
IN
CC
DD33
pins can be in parallel because the on-chip LDO is off. The
controller 3.3V current limit is 100mA but typical V
DD33
currents are under 15mA. The V
does back drive the
DD33
INTV /EXTV pin. Normally this is not an issue if V
CC
CC
IN
is open.
LTpowerPlay: AN INTERACTIVE GUI FOR DIGITAL
POWER
LTpowerPlay (Figure 31) is a powerful Windows-based
development environment that supports Analog De-
vices digital power system management ICs including
the LTM4678. The software supports a variety of differ-
ent tasks. LTpowerPlay can be used to evaluate Analog
Devices ICs by connecting to a demo board or the user
application. LTpowerPlay can also be used in an offline
mode(withnohardwarepresent)inordertobuildmultiple
IC configuration files that can be saved and reloaded at a
latertime.LTpowerPlayprovidesunprecedenteddiagnostic
and debug features. It becomes a valuable diagnostic tool
during board bring-up to program or tweak the power
system or to diagnose power issues when bring up rails.
2
LTpowerPlay utilizes Analog Devices’ USB-to-I C/SMBus/
PMBus adapter to communication with one of the many
potential targets including the DC2165A demo board, the
DC2298A socketed programming board, or a customer
Rev 0
61
For more information www.analog.com
LTM4678
APPLICATIONS INFORMATION
Figure 31. LTpowerPlay Screen Shot
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Figure 32. Write Command Data Processing
Rev 0
62
For more information www.analog.com
LTM4678
APPLICATIONS INFORMATION
When the part receives a new command while it is busy,
it will communicate this condition using standard PMBus
protocol. Depending on part configuration it may either
NACK the command or return all ones (0xFF) for reads. It
may also generate a BUSY fault and ALERT notification,
or stretch the SCL clock low. For more information refer
to PMBus Specification v1.1, Part II, Section 10.8.7 and
SMBusv2.0section4.3.3.Clockstretchingcanbeenabled
by asserting bit 1 of MFR_CONFIG_ ALL. Clock stretch-
ing will only occur if enabled and the bus communication
speed exceeds 100kHz.
An example of a robust command write algorithm for the
VOUT_COMMAND register is provided in Figure 33.
It is recommended that all command writes (write byte,
write word, etc.) be preceded with a polling loop to avoid
the extra complexity of dealing with busy behavior and
unwantedALERTnotification. Asimplewaytoachievethis
is to create a SAFE_WRITE_BYTE() and SAFE_WRITE_
WORD()subroutine.Theabovepollingmechanismallows
your software to remain clean and simple while robustly
communicating with the part. For a detailed discussion
of these topics and other special cases please refer to the
application note section located at:
// wait until chip is not busy
do
{
www.linear.com/designtools/app_notes
mfrCommonValue=PMBUS_READ_BYTE(0xEF);
partReady = (mfrCommonValue & 0x68) ==
0x68;
When communicating using bus speeds at or below
100kHz, the polling mechanism shown here provides a
simplesolutionthatensuresrobustcommunicationwithout
clock stretching. At bus speeds in excess of 100kHz, it is
strongly recommended that the part be configured to en-
able clock stretching. This requires a PMBus master that
supports clock stretching. System software that detects
and properly recovers from the standard PMBus NACK/
BUSY faults as described in the PMBus Specification
v1.1, Par II, Section 10.8.7 is required to communicate
The LTM4678 is not recommended in applications with
bus speeds in excess of 400kHz.
}while(!partReady)
// now the part is ready to receive the
next command
PMBUS_WRITE_WORD(0x21,0x2000);//write
VOUT_COMMAND to 2V
Figure 33. Example of a Command Write of VOUT_COMMAND
PMBus busy protocols are well accepted standards, but
can make writing system level software somewhat com-
plex. The part provides three ‘hand shaking’ status bits
which reduce complexity while enabling robust system
level communication.
The three hand shaking status bits are in the MFR_ COM-
MON register. When the part is busy executing an internal
operation, it will clear bit 6 of MFR_COMMON (‘chip not
busy’). When the part is busy specifically because it is
THERMAL CONSIDERATIONS AND OUTPUT
CURRENT DERATING
The thermal resistances reported in the Pin Configura-
tion section of this data sheet are consistent with those
parameters defined by JESD51-12 and are intended for
use with finite element analysis (FEA) software modeling
tools that leverage the outcome of thermal modeling,
simulation, and correlation to hardware evaluation per-
formed on a µModule package mounted to a hardware
test board defined by JESD51-9 (“Test Boards for Area
Array Surface Mount Package Thermal Measurements”).
The motivation for providing these thermal coefficients is
found in JESD51-12 (“Guidelines for Reporting and Using
Electronic Package Thermal Information”).
in a transitional V
state (margining hi/lo, power off/
OUT
on, moving to a new output voltage set point, etc.) it will
clear bit 4 of MFR_COMMON (‘output not in transition’).
When internal calculations are in process, the part will
clear bit 5 of MFR_COMMON (‘calculations not pending’).
These three status bits can be polled with a PMBus read
byte of the MFR_COMMON register until all three bits are
set. A command immediately following the status bits
being set will be accepted without NACKing or generat-
ing a BUSY fault/ALERT notification. The part can NACK
commands for other reasons, however, as required by the
PMBus spec (for instance, an invalid command or data).
Rev 0
63
For more information www.analog.com
LTM4678
APPLICATIONS INFORMATION
Many designers may opt to use laboratory equipment
and a test vehicle such as the demo board to predict the
µModule regulator’s thermal performance in their appli-
cation at various electrical and environmental operating
conditions to compliment any FEA activities. Without FEA
software, the thermal resistances reported in the Pin Con-
figuration section are in-and-of themselves not relevant
to providing guidance of thermal performance; instead,
the derating curves provided later in this data sheet can
be used in a manner that yields insight and guidance per-
taining to one’s application-usage, and can be adapted to
correlate thermal performance to one’s own application.
of the package, but there is always heat flow out into
the ambient environment. As a result, this thermal
resistance value may be useful for comparing pack-
ages but the test conditions don’t generally match the
user’s application.
3. θJCtop, the thermal resistance from junction to top of
the product case, is determined with nearly all of the
componentpowerdissipationflowingthroughthetop
of the package. As the electrical connections of the
typical µModule regulator are on the bottom of the
package, it is rare for an application to operate such
that most of the heat flows from the junction to the
top of the part. As in the case of θJCbottom, this value
may be useful for comparing packages but the test
conditionsdon’tgenerallymatchtheuser’sapplication.
The Pin Configuration section gives four thermal coeffi-
cients explicitly defined in JESD51-12; these coefficients
are quoted or paraphrased below:
1. θJA, the thermal resistance from junction to ambi-
ent, is the natural convection junction-to-ambient
air thermal resistance measured in a one cubic foot
sealed enclosure. This environment is sometimes
referred to as “still air” although natural convection
causes the air to move. This value is determined with
the part mounted to a JESD51-9 defined test board,
which does not reflect an actual application or viable
operating condition.
4
θJB,thethermalresistancefromjunctiontotheprinted
circuit board, is the junction-to-board thermal resis-
tance where almost all of the heat flows through the
bottom of the µModule regulator and into the board,
and is really the sum of the θJCbottom and the thermal
resistance of the bottom of the part through the solder
joints and through a portion of the board. The board
temperature is measured a specified distance from
the package, using a two sided, two layer board. This
board is described in JESD51-9.
2. θJCbottom, the thermal resistance from junction to the
bottom of the product case, is determined with all of
the component power dissipation flowing through
the bottom of the package. In the typical µModule
regulator, the bulk of the heat flows out the bottom
A graphical representation of the aforementioned thermal
resistances is given in Figure 34; blue resistances are
contained within the µModule regulator, whereas green
resistances are external to the µModule package.
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Rꢍꢘꢏꢘꢔꢗꢓꢐꢍ
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Figure 34. Graphical Representation of JESD51-12 Thermal Coefficients
Rev 0
64
For more information www.analog.com
LTM4678
APPLICATIONS INFORMATION
As a practical matter, it should be clear to the reader that
no individual or sub-group of the four thermal resistance
parameters defined by JESD51-12 or provided in the
Pin Configuration section replicates or conveys normal
operating conditions of a µModule regulator. For example,
in normal board-mounted applications, never does 100%
of the device’s total power loss (heat) thermally conduct
exclusively through the top or exclusively through bot-
tom of the µModule package—as the standard defines
for θJCtop and θJCbottom, respectively. In practice, power
loss is thermally dissipated in both directions away from
the package—granted, in the absence of a heat sink and
airflow, a majority of the heat flow is into the board.
processandduediligenceyieldsthesetofderatingcurves
provided in later sections of this data sheet, along with
well-correlated JESD51-12-defined
θ values provided in
the Pin Configuration section of this data sheet.
The 5V, 8V and 12V power loss curves in Figures 35,
36 and 37 respectively can be used in coordination with
the load current derating curves in Figures 38 to 43 for
calculating an approximate θJA thermal resistance for
the LTM4678 with airflow conditions. These thermal
resistances represent demonstrated performance of the
LTM4678 on hardware; a 6-layer FR4 PCB measuring
99mm × 130mm × 1.6mm using 2oz copper on all layers.
Thepowerlosscurvesaretakenatroomtemperature, and
are increased with multiplicative factors of 1.35 when the
junction temperature reaches 125°C. The derating curves
are plotted with the LTM4678’s paralleled outputs initially
sourcing up to 50A and the ambient temperature at 25°C.
The output voltages are 0.9V and 1.8V. These are chosen
to include the lower and higher output voltage ranges for
correlating the thermal resistance. Thermal models are
derivedfromseveraltemperaturemeasurementsinacon-
trolledtemperaturechamberalongwiththermalmodeling
analysis. The junction temperatures are monitored while
ambienttemperatureisincreasedwithandwithoutairflow.
Within the LTM4678, be aware there are multiple power
devices and components dissipating power, with a con-
sequence that the thermal resistances relative to different
junctions of components or die are not exactly linear with
respect to total package power loss. To reconcile this
complicationwithoutsacrificingmodelingsimplicity—but
also,notignoringpracticalrealities—anapproachhasbeen
taken using FEA software modeling along with laboratory
testinginacontrolled-environmentchambertoreasonably
defineandcorrelatethethermalresistancevaluessupplied
in this data sheet: (1) Initially, FEA software is used to ac-
curately build the mechanical geometry of the LTM4678
and the specified PCB with all of the correct material
coefficients along with accurate power loss source defini-
tions; (2) this model simulates a software-defined JEDEC
environment consistent with JESD51-9 and JESD51-12
to predict power loss heat flow and temperature readings
at different interfaces that enable the calculation of the
JEDEC-defined thermal resistance values; (3) the model
and FEA software is used to evaluate the LTM4678 with
heat sink and airflow; (4) having solved for and analyzed
these thermal resistance values and simulated various
operating conditions in the software model, a thorough
laboratory evaluation replicates the simulated conditions
with thermocouples within a controlled environment
chamber while operating the device at the same power
loss as that which was simulated. The outcome of this
Thepowerlossincreasewithambienttemperaturechange
is factored into the derating curves. The junctions are
maintained at 125°C maximum while lowering output
current or power while increasing ambient temperature.
The decreased output current decreases the internal
module loss as ambient temperature is increased. The
monitored junction temperature of 125°C minus the am-
bient operating temperature specifies how much module
temperature rise can be allowed. As an example in Figure
40, the load current is derated to ~35A at ~73°C ambient
with no air or heat sink and the room temperature (25°C)
power loss for this 12V to 0.9V
at 35A
condition
IN
OUT
OUT
is ~4W. A 5.4W loss is calculated by multiplying the ~4W
room temperature loss from the 12V to 0.9V power
IN
OUT
loss curve at 35A (Figure 35), with the 1.35 multiplying
factor. If the 73°C ambient temperature is subtracted
Rev 0
65
For more information www.analog.com
LTM4678
APPLICATIONS INFORMATION
from the 125°C junction temperature, then the difference
of 52°C divided by 5.4W yields a thermal resistance, θJA
of 9.6°C/W—in good agreement with Table 10. Tables 10
and 11 provide equivalent thermal resistances for 0.9V
and 1.8V outputs with and without airflow. The derived
thermal resistances in Tables 10 and 11 for the various
conditions can be multiplied by the calculated power loss
asafunctionofambienttemperaturetoderivetemperature
rise above ambient, thus maximum junction temperature.
Room temperature power loss can be derived from the ef-
ficiencycurvesintheTypicalPerformanceCharacteristics
section and adjusted with the above ambient temperature
multiplicative factors.
,
TABLES 10 THRU 11: OUTPUT CURRENT DERATING
Table 10. 0.9V Output
DERATING CURVE
Figures 38, 39, 40
Figures 38, 39, 40
Figures 38, 39, 40
V
(V)
POWER LOSS CURVE
Figures 35, 36, 37
Figures 35, 36, 37
Figures 35, 36, 37
AIRFLOW (LFM)
HEAT SINK
None
θJA (°C/W)
IN
5, 8, 12
5, 8, 12
5, 8, 12
0
9
200
400
None
8
None
6.5
Table 11. 1.8V Output
DERATING CURVE
Figures 41, 42, 43
Figures 41, 42, 43
Figures 41, 42, 43
V
(V)
POWER LOSS CURVE
Figures 35, 36, 37
Figures 35, 36, 37
Figures 35, 36, 37
AIRFLOW (LFM)
HEAT SINK
None
θJA (°C/W)
IN
5, 8, 12
5, 8, 12
5, 8, 12
0
9
200
400
None
8
None
6.5
Rev 0
66
For more information www.analog.com
LTM4678
APPLICATIONS INFORMATION
Table 12. Channel Output Voltage vs Component Selection, 0A to 12.5A/μs Load Step
Output Capacitor-GRM32ER60G337ME05L, 330μF, 4V, X5R, Murata
LOAD
STEP
(A)
PK-PK
DEVIATION
(mV)
RECOVERY
TIME
V
V
C
C
B
C
A
EA-GM
(mS)
F
SW
IN
(V)
OUT
OUT
COMP
COMP
(V)
0.9
0.9
0.9
0.9
0.9
0.9
1
(CER CAP)
330μFx5
330μFx5
330μFx5
330μFx7
330μFx7
330μFx7
330μFx5
330μFx5
330μFx5
330μFx7
330μFx7
330μFx7
330μFx5
330μFx5
330μFx5
330μFx5
330μFx5
330μFx5
330μFx5
330μFx5
330μFx5
330μFx5
330μFx5
330μFx5
330μFx5
330μFx5
330μFx5
(pF)
(nF)
R_ITH (kΩ)
(kHz)
350
350
350
350
350
350
350
350
350
350
350
350
350
350
350
500
500
500
575
575
575
575
575
575
750
750
750
(μS)
5
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
1.5
1.5
1.5
1.5
1.5
1.5
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
5
5
5
5
5
5
2.35
2.35
2.35
2.35
2.35
2.35
2.35
2.35
2.35
2.35
2.35
2.35
2.35
2.35
2.35
2.35
2.35
2.35
2.35
2.35
2.35
1.68
1.68
1.68
1.68
1.68
1.68
0-12.5
0-12.5
0-12.5
0-12.5
0-12.5
0-12.5
0-12.5
0-12.5
0-12.5
0-12.5
0-12.5
0-12.5
0-12.5
0-12.5
0-12.5
0-12.5
0-12.5
0-12.5
0-12.5
0-12.5
0-12.5
0-12.5
0-12.5
0-12.5
0-12.5
0-12.5
0-12.5
100
100
100
85
20
20
20
30
30
30
20
20
20
30
30
30
20
20
20
25
25
25
25
25
25
20
20
20
25
20
20
12
16
5
12
16
5
85
85
100
100
100
85
12
16
5
1
1
1
12
16
5
1
85
1
85
1.2
1.2
1.2
1.5
1.5
1.5
1.8
1.8
1.8
2.5
2.5
2.5
3.3
3.3
3.3
120
100
100
100
100
100
120
100
100
200
150
150
220
160
160
12
16
5
12
16
5
12
16
6
12
16
8
12
16
Rev 0
67
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LTM4678
APPLICATIONS INFORMATION
Table 13. Channel Output Voltage vs Component Selection, 0A to 12.5A/μs Load Step
Murata
Panasonic
POSCAP
PK-PK
DEVIATION
(mV)
V
C
C
C
B
C
A
EA-GM
(ms)
LOAD STEP
(A)
RECOVERY
TIME (μs)
OUT
OUT
OUT
COMP
(pF)
COMP
(nF)
V
(V)
(V)
0.9
1
(CER CAP)
*100μFx3
*100μFx3
*100μFx2
*100μFx2
*100μFx2
*100μFx2
*100μFx2
*100μFx2
*100μFx2
*100μFx2
*100μFx2
*100μFx2
*100μFx2
*100μFx2
*100μFx2
*100μFx2
*100μFx2
*100μFx2
*100μFx2
*100μFx2
*100μFx2
*100μFx2
*100μFx2
*100μFx2
*100μFx2
*100μFx2
*100μFx2
*100μFx2
*100μFx2
*100μFx2
*100μFx2
*100μFx2
*100μFx2
(BULK CAP)
**470μFx2
**470μFx2
**470μFx2
**470μFx2
**470μFx2
**470μFx2
**470μFx2
**470μFx2
**470μFx2
**470μFx2
**470μFx2
**470μFx2
**470μFx2
**470μFx2
**470μFx2
**470μFx2
**470μFx2
**470μFx2
***470μFx2
***470μFx2
***470μFx2
***470μFx2
***470μFx2
***470μFx2
***470μFx2
***470μFx1
***470μFx1
***470μFx1
***470μFx1
***470μFx2
***470μFx2
***470μFx2
***470μFx2
R
(kΩ)
F
SW
(kHz)
IN
COMPn
12
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
11
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
350
0-12.5
0-12.5
0-12.5
0-12.5
0-12.5
0-12.5
0-12.5
0-12.5
0-12.5
0-12.5
0-12.5
0-12.5
0-12.5
0-12.5
0-12.5
0-12.5
0-12.5
0-12.5
0-12.5
0-12.5
0-12.5
0-10
90
20
20
20
20
20
20
20
20
25
25
25
25
25
25
20
20
20
20
40
40
40
20
20
20
20
40
40
40
40
40
40
40
40
12
5
11
11
11
11
11
11
11
7
350
350
350
350
350
350
350
350
350
350
500
500
500
575
575
575
575
575
575
575
575
575
575
575
750
750
750
750
750
750
750
750
90
0.9
0.9
0.9
1
100
100
100
100
100
100
120
120
120
100
100
100
120
90
12
16
5
12
16
5
1
1
1.2
1.2
1.2
1.5
1.5
1.5
1.8
1.8
1.8
1.8
2.5
2.5
2.5
2.5
2.5
2.5
2.5
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
12
16
5
7
7
7
12
16
5
7
7
11
11
11
11
11
11
11
15
15
15
15
11
11
11
11
15
15
15
15
6
12
16
6
90
90
180
150
150
110
120
100
100
180
180
150
150
120
110
100
100
12
16
5
6
0-12.5
0-12.5
0-12.5
0-10
12
16
6
8
0-12.5
0-12.5
0-12.5
0-10
12
16
6
8
0-12.5
0-12.5
0-12.5
12
16
Dual Phase Single Output Voltage vs Component Selection, 25A to 50A/μs Load Step
5.5
12
16
6
1
*100μFx6
*100μFx6
*100μFx6
*100μFx6
*100μFx6
*100μFx6
*100μFx6
*100μFx6
*100μFx6
**470μFx2
**470μFx2
**470μFx2
**470μFx2
**470μFx2
**470μFx2
**470μFx2
**470μFx2
**470μFx2
150
150
150
150
150
150
150
150
150
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
2.5
2.5
2.5
5
1
500
500
500
500
500
500
575
575
575
25-50
25-50
25-50
25-50
25-50
25-50
25-50
25-50
25-50
90
90
15
15
15
15
15
15
15
15
15
1
1
1
1
90
1.5
1.5
1.5
1.8
1.8
1.8
1.68
1.68
1.68
1.68
1.68
1.68
100
100
100
110
100
100
12
16
6
5
5
5
12
16
5
5
Rev 0
68
For more information www.analog.com
LTM4678
APPLICATIONS INFORMATION-DERATING CURVES
ꢀꢁ
ꢀ0
ꢀ
ꢀꢁ
ꢀ0
ꢀ
ꢀꢁ
ꢀ0
ꢀ
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0
0
0
0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀꢁꢂꢃꢁꢂ ꢄꢁRRꢅꢆꢂ ꢇꢈꢉ
ꢀꢁꢂꢃꢁꢂ ꢄꢁRRꢅꢆꢂ ꢇꢈꢉ
ꢀꢁꢂꢃꢁꢂ ꢄꢁRRꢅꢆꢂ ꢇꢈꢉ
ꢀꢁꢂꢃ ꢄꢅꢆ
ꢀꢁꢂꢃ ꢄꢅꢁ
ꢀꢁꢂꢃ ꢄꢅꢂ
Figure 35. 5VIN Power Loss Curve
Figure 36. 8VIN Power Loss Curve
Figure 37. 12VIN Power Loss Curve
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
0
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ00
ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ00
ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ00
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉꢊꢋꢌ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉꢊꢋꢌ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉꢊꢋꢌ
ꢀꢁꢂꢃ ꢄꢅꢃ
ꢀꢁꢂꢃ ꢄꢅꢆ
ꢀꢁꢂꢃ ꢄꢀ0
Figure 38. 5V to 0.9V Derating
Curve, No Heat Sink
Figure 39. 8V to 0.9V Derating
Curve, No Heat Sink
Figure 40. 12V to 0.9V Derating
Curve, No Heat Sink
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
0
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
0ꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀ00ꢁꢂꢃ
0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ00
ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ00
ꢀꢁꢂ
0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ00
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉꢊꢋꢌ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉꢊꢋꢌ
ꢀꢁꢂꢃꢄꢅꢆ ꢆꢄꢁꢇꢄRꢀꢆꢈRꢄ ꢉꢊꢋꢌ
ꢀꢁꢂꢃ ꢄꢀꢅ
ꢀꢁꢂꢃ ꢄꢀꢅ
ꢀꢁꢂꢃ ꢄꢀꢅ
Figure 43. 12V to 1.8V Derating
Curve, No Heat Sink
Figure 41. 5V to 1.8V Derating
Curve, BGA No Heat Sink
Figure 42. 8V to 1.8V Derating
Curve, No Heat Sink
Rev 0
69
For more information www.analog.com
LTM4678
APPLICATIONS INFORMATION
EMI PERFORMANCE
SAFETY CONSIDERATIONS
The LTM4678 modules do not provide galvanic isolation
from V to V . There is no internal fuse. If required,
The SWn pin provides access to the midpoint of the power
MOSFETs in LTM4678’s power stages.
IN
OUT
a slow blow fuse with a rating twice the maximum input
current needs to be provided to protect each unit from
catastrophic failure.
Connecting an optional series RC network from SWn to
GND can dampen high frequency (~30MHz+) switch node
ringing caused by parasitic inductances and capacitances
in the switched-current paths. The RC network is called
a snubber circuit because it dampens (or “snubs”) the
resonanceoftheparasitics,attheexpenseofhigherpower
loss. To use a snubber, choose first how much power to
allocate to the task and how much PCB real estate is avail-
able to implement the snubber. For example, if PCB space
allows a low inductance 0.5W resistor to be used then the
capacitor in the snubber network (CSW) is computed by:
The fuse or circuit breaker should be selected to limit the
current to the regulator during overvoltage in case of an
internaltopMOSFETfault. IftheinternaltopMOSFETfails,
then turning it off will not resolve the overvoltage, thus
the internal bottomMOSFET willturn on indefinitely trying
to protect the load. Under this fault condition, the input
voltage will source very large currents to ground through
the failed internal top MOSFET and enabled internal bot-
tom MOSFET. This can cause excessive heat and board
damage depending on how much power the input voltage
can deliver to this system. A fuse or circuit breaker can be
used as a secondary fault protector in this situation. The
device does support over current and overtemperature
protection.
PSNUB
CSW
=
V
2 • fSW
INn(MAX)
where V
is the maximum input voltage that the
INn(MAX)
input to the power stage (V ) will see in the application,
INn
and f
is the DC/DC converter’s switching frequency
SW
of operation. C should be NPO, C0G or X7R-type (or
SW
LAYOUT CHECKLIST/EXAMPLE
better) material.
The high integration of LTM4678 makes the PCB board
layoutverysimpleandeasy.However,tooptimizeitselectri-
cal and thermal performance, some layout considerations
are still necessary.
The snubber resistor (R ) value is then given by:
SW
5nH
CSW
RSW
=
n
Use large PCB copper areas for high current paths,
The snubber resistor should be low ESL and capable of
withstanding the pulsed currents present in snubber cir-
cuits. A value between 0.7Ω and 4.2Ω is normal.
including V , GND and V
. It helps to minimize
INn
OUTn
the PCB conduction loss and thermal stress.
n
Placehighfrequencyceramicinputandoutputcapaci-
A 2.2nF snubber capacitor is a good value to start with in
series with the snubber resistor to ground. The no load
input quiescent current can be monitored while selecting
differentRCseriessnubbercomponentstogetaincreased
power loss versus switch node ringing attenuation.
tors next to the V , GND and V
pins to minimize
INn
OUTn
high frequency noise.
n
n
Place a dedicated power ground layer underneath the
module.
Tominimizetheviaconductionlossandreducemodule
thermal stress, use multiple vias for interconnection
between top layer and other power layers.
Rev 0
70
For more information www.analog.com
LTM4678
APPLICATIONS INFORMATION
+
n
Donotputviasdirectlyonpads,unlesstheyarecapped
For parallel modules, tie the V
, V
/V
OSNSn
OUTn
OSNSn
or plated over.
voltage-sense differential pair lines, RUNn, COMPna,
COMP pin together.
n
nb
Use a separate SGND copper plane for components
connected to signal pins. Connect SGND to GND local
to the LTM4678.
n
The user must share the SYNC, SHARE_CLK, FAULT,
and ALERT pins of these parts. Be sure to use pull-up
resistors on FAULT, SHARE_CLK and ALERT.
n
UseKelvinsenseconnectionsacrosstheinputR
resistor if input current monitoring is used.
SENSE
n
Bringouttestpointsonthesignalpinsformonitoring.
Figure 44givesagoodexampleoftherecommendedlayout.
ꢌꢈꢍ
ꢆꢂꢇ
ꢆꢂꢇ
ꢀ
ꢃꢄꢅꢈ
ꢆ
ꢉꢊꢋꢎ
ꢆ
ꢉꢊꢋ0
ꢀ
ꢃꢄꢅ0
ꢆꢂꢇ
ꢆꢂꢇ
ꢌꢈꢍ
ꢌꢈꢍ
ꢌꢈꢍ
ꢌꢈꢍ
ꢆ
ꢇꢈ
ꢃꢉꢅꢁꢃꢂꢊꢋ ꢁꢂꢉꢄꢅ
ꢌꢄRRꢍꢂꢅ ꢎꢍꢂꢎꢍ
ꢀ
ꢁꢂ
ꢆꢂꢇ
ꢆꢂꢇ
ꢓꢔꢕꢖ ꢗꢓꢓꢐ
ꢀꢁꢂꢃ ꢄꢀꢀꢅ
ꢏꢅꢐ ꢑꢉꢋꢋꢉꢒ ꢓꢔꢕꢖR
ꢏꢐꢑ ꢅꢃꢉ ꢋꢊꢒꢍR
Figure 44. Recommended PCB Layout Package Top View
Rev 0
71
For more information www.analog.com
LTM4678
TYPICAL APPLICATIONS
ꢀ0ꢁ
ꢀꢁꢀꢂꢃ
ꢀꢁꢂꢂꢃ
ꢀ
ꢁꢁꢂꢂ
ꢀꢁꢂꢀꢃ ꢄꢅ ꢆꢇꢃ
ꢀ
ꢁꢂ
ꢂ
ꢀ
ꢀꢁ
ꢀꢁ0
ꢀ
ꢀꢁ0ꢂꢃ
1mΩ
ꢁꢂꢃ0
ꢀ00ꢁꢂ
ꢀꢁ
ꢂ
ꢀ
ꢀꢁ
ꢄ
0ꢀꢁꢂ ꢃꢄ ꢅ0ꢃ
ꢀ
ꢀ
ꢁꢂꢃ
ꢁꢂꢃꢂ0
ꢀꢀꢁꢂ
ꢀꢁ
ꢄ
ꢀ
ꢁꢂ0
ꢀ
ꢁꢂꢃꢂ0
ꢀꢁ
ꢀꢁꢂ
ꢀ
ꢂꢃ
ꢁꢁꢂꢂ
ꢀ0ꢁ ꢀꢁꢂꢂꢃ ꢀ0ꢁ ꢀ0ꢁ
ꢀ
ꢁꢂꢃꢄ
ꢀ00ꢁꢂ
ꢀꢁ
ꢀꢁꢂꢃꢄꢅꢆ
ꢅ
ꢄ
ꢄ
Rꢀꢁꢂ
ꢀ
ꢁꢂꢃꢂꢄ
ꢀ
ꢀ
ꢅꢃꢆ
ꢅꢈ
ꢁꢂꢃꢂ0
ꢁꢂꢃꢂꢇ
ꢀꢁꢀꢁꢂꢂꢃꢁꢄꢂꢅꢆ
ꢅ
ꢀꢁꢂꢃ
Rꢀꢁ0
ꢀ
ꢁꢂꢃꢂꢄ
Rꢉꢊꢁꢈꢉ ꢋꢃꢆ
ꢌꢁꢍꢃꢈ
ꢀꢁꢂꢃꢄ ꢅꢆꢄꢇRRꢂꢈꢄꢉ
FAULT0
ꢀꢁꢂ
ꢀꢁꢂ
FAULT1
ALERT
ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀ0ꢁ ꢀ0ꢁ
ꢀ0ꢁ
ꢀꢁꢂRꢃꢄꢅꢆꢇ
ꢀꢁꢂꢃ
ꢀ
ꢁꢁꢂꢂ
ꢀꢁ
ꢁ
ꢀ ꢂꢃꢄꢅꢆꢇꢈ ꢀꢉꢊꢋRꢌꢍꢂꢋ ꢎꢀꢊꢏ ꢐꢅꢆꢇꢈ ꢂꢑꢅꢅꢍꢉꢒ ꢄꢋꢊ
ꢀꢁꢂꢃRꢁꢄ ꢅꢆꢄꢅ ꢁR ꢁꢀꢇꢈR ꢉꢁꢊRꢋ
ꢀꢁꢂꢁꢃꢄꢀꢄꢂꢅ ꢆꢇꢂꢅRꢇꢈꢈꢄR
ꢀꢁꢂꢃ ꢄꢀꢅ
ꢀꢀꢁꢂꢃ ꢀꢀꢁꢂꢃ
825Ω
ꢀꢁꢂꢃꢄꢅ RꢆꢇꢄꢇꢈꢁRꢇ ꢉRꢆ
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ0ꢈꢈꢉ
ꢀ00ꢁꢂ
ꢀꢀ00ꢁꢂ
ꢀ ꢁꢂꢃꢄꢅ ꢃꢆꢆRꢅꢁꢁ ꢇ ꢈ00ꢈꢈꢈ0ꢉRꢊꢋ ꢌ0ꢍꢎꢅꢏ
ꢀ ꢐꢑ0ꢒꢓꢔ ꢁꢋꢕꢖꢗꢓꢕꢘꢙ ꢚRꢅꢛꢜꢅꢘꢗꢝ
ꢀ ꢘꢞ ꢙꢜꢕ ꢗꢞꢘꢚꢕꢙꢜRꢃꢖꢕꢞꢘ ꢃꢘꢆ ꢘꢞ ꢟꢃRꢖꢠꢁꢟꢅꢗꢕꢚꢕꢗ ꢟRꢞꢙRꢃꢡꢡꢕꢘꢙ RꢅꢛꢜꢕRꢅꢆ
ꢀ ꢕꢘ ꢡꢜꢂꢖꢕꢠꢡꢞꢆꢜꢂꢅ ꢁꢝꢁꢖꢅꢡꢁꢢ ꢗꢞꢘꢚꢕꢙꢜRꢕꢘꢙ RꢃꢕꢂꢉꢃꢆꢆRꢅꢁꢁ ꢕꢁ Rꢅꢗꢞꢡꢡꢅꢘꢆꢅꢆ
Figure 45. 50A, 0.9V Output DC/DC µModule Regulator with I2C/SMBus/PMBus Serial Interface
Rev 0
72
For more information www.analog.com
LTM4678
TYPICAL APPLICATIONS
ꢀ0ꢁ
ꢀꢁꢀꢂꢃ
ꢀꢁꢂꢂꢃ0
ꢀꢁꢂꢂꢃꢄ
ꢀ0ꢁ
ꢀ
ꢁꢁꢂꢂ
Rꢀꢁꢂꢃ0
ꢀꢁꢂꢀꢃ ꢄꢅ ꢆꢇꢃ
ꢀ
ꢁꢂ
ꢂ
ꢀ
ꢀꢁ
ꢀꢁ0
ꢀꢁꢂꢃꢄ0
ꢀꢁ0ꢂꢃ
1mΩ
ꢂ
ꢀ
ꢀ
ꢁꢂꢃ0
ꢀꢁ
ꢀ
ꢄ ꢅ ꢆꢇꢈ
ꢁꢂꢃ0
ꢄ
ꢀ
ꢀ
ꢁꢂꢃꢂ0
ꢁꢂꢃ
ꢀꢀꢁꢂ
ꢀꢁ
ꢀ00ꢁꢂ
ꢀꢁ
ꢀꢁ0ꢂꢃ
ꢀꢁꢂꢃ0
ꢀ
ꢁꢂ0
ꢀꢁ
ꢄ
ꢀ
ꢁꢂꢃꢂ0
ꢀꢁ
ꢂꢃ
Rꢀꢁꢂꢃꢄ
ꢀ
ꢁꢁꢂꢂ
ꢀ0ꢁ ꢀꢁꢂꢂꢃ ꢀ0ꢁ ꢀ0ꢁ ꢀ0ꢁ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅ
ꢀ
ꢀ0ꢁ
ꢁꢂꢃꢄ
ꢀ
ꢄꢅꢆ ꢇ ꢈꢆꢉ
ꢁꢂꢃꢄ
ꢅ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀ
ꢁꢂꢃꢂꢄ
Rꢀꢁꢂ
ꢀ00ꢁꢂ
ꢀꢁ
ꢀꢁ0ꢂꢃ
ꢀꢁ
ꢀꢁꢂꢃꢄ
ꢀꢁꢀꢁꢂꢂꢃꢁꢄꢂꢅꢆ
ꢅ
Rꢀꢁ0
ꢀ
ꢁꢂꢃꢂꢄ
ꢀꢁꢂꢃꢄ ꢅꢆꢄꢇRRꢂꢈꢄꢉ
FAULT0
ꢀꢁꢂ
ꢀꢁꢂ
FAULT1
ALERT
ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀ0ꢁ ꢀ0ꢁ
ꢀ0ꢁ
ꢀꢁꢂRꢃꢄꢅꢆꢇ
ꢀꢁꢂꢃ
ꢀ
ꢁꢁꢂꢂ
ꢀꢁ
ꢁ
ꢀ ꢂꢃꢄꢅꢆꢇꢈ ꢀꢉꢊꢋRꢌꢍꢂꢋ ꢎꢀꢊꢏ ꢐꢅꢆꢇꢈ ꢂꢑꢅꢅꢍꢉꢒ
ꢀꢁꢂꢃRꢁꢄ ꢅꢆꢄꢅ ꢁR ꢁꢀꢇꢈR ꢉꢁꢊRꢋ
ꢀꢁꢂꢁꢃꢄꢀꢄꢂꢅ ꢆꢇꢂꢅRꢇꢈꢈꢄR
ꢀ00ꢁꢂ
ꢀꢀ00ꢁꢂ
ꢀꢁꢂꢃꢄ ꢀꢁꢂꢂꢃ ꢀꢁꢂ ꢀꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄꢅ RꢆꢇꢄꢇꢈꢁRꢇ ꢉRꢆ
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ0ꢈꢈꢉ
ꢀꢀ00ꢁꢂ
ꢀ00ꢁꢂ
ꢀ ꢁꢂꢃꢄꢅ ꢃꢆꢆRꢅꢁꢁ ꢇ ꢈ00ꢈꢈꢈ0ꢉRꢊꢋ ꢌ0ꢍꢎꢅꢏ
ꢀ ꢎꢐꢑꢒꢓꢔ ꢁꢋꢕꢖꢗꢓꢕꢘꢙ ꢚRꢅꢛꢜꢅꢘꢗꢝ
ꢀ ꢘꢞ ꢙꢜꢕ ꢗꢞꢘꢚꢕꢙꢜRꢃꢖꢕꢞꢘ ꢃꢘꢆ ꢘꢞ ꢟꢃRꢖꢠꢁꢟꢅꢗꢕꢚꢕꢗ ꢟRꢞꢙRꢃꢡꢡꢕꢘꢙ RꢅꢛꢜꢕRꢅꢆ
ꢀ ꢕꢘ ꢡꢜꢂꢖꢕꢠꢡꢞꢆꢜꢂꢅ ꢁꢝꢁꢖꢅꢡꢁꢢ ꢗꢞꢘꢚꢕꢙꢜRꢕꢘꢙ RꢃꢕꢂꢉꢃꢆꢆRꢅꢁꢁ ꢕꢁ Rꢅꢗꢞꢡꢡꢅꢘꢆꢅꢆ
Figure 46. 1.0V and 1.5V Outputs at 25A With Providing I2C/SMBus/PMBus Serial Interface
Rev 0
73
For more information www.analog.com
LTM4678
TYPICAL APPLICATIONS
ꢀꢁꢀꢂꢃ
ꢀꢁꢂꢂꢃ
ꢀꢁꢂꢂꢃ
ꢀ
ꢃꢄ
ꢁꢁꢂꢂ
ꢀꢁ
ꢀꢁ0
ꢀ
ꢀꢁꢂꢀꢃ ꢄꢅ ꢆꢇꢃ
ꢁꢂ
ꢂ
ꢀ
ꢀꢁ
ꢀ
ꢀꢁ0ꢂꢃ
ꢁꢂꢃ0
ꢀ00ꢁꢂ
ꢀꢁ
ꢄ
ꢂ
ꢀꢁ0ꢂꢃ
ꢀꢁ
ꢀ
ꢀ
ꢁꢂꢃꢂ0
ꢀꢁ
ꢄ
ꢀ
ꢁꢂꢃꢂ0
ꢀ
ꢁꢂꢃ
ꢀꢀꢁꢂ
ꢀꢁ
ꢀꢁꢂ
ꢀ
ꢃꢄ
ꢀ
ꢁꢁꢂꢂ
ꢁꢂ0
ꢀ
ꢁꢂꢃꢄ
ꢀꢁ
ꢂꢃ
ꢀ0ꢁ ꢀꢁꢂꢂꢃ ꢀ0ꢁ ꢀ0ꢁ
ꢀ00ꢁꢂ
ꢀꢁ
ꢅ
ꢀ
ꢁꢂꢃꢂꢄ
ꢀꢁ0ꢂꢃ
ꢀꢁ
ꢀꢁꢂꢃꢄꢅꢆ
Rꢀꢁꢂ
ꢅ
ꢀ
ꢁꢂꢃꢂꢄ
ꢀꢁꢂꢀꢃꢃ ꢄꢀꢁꢅRꢀꢆ
Rꢀꢁ0
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄ ꢅꢆꢄꢇRRꢂꢈꢄꢉ
FAULT0
FAULT1
ꢀꢁꢂꢃ
ꢀꢁꢂ
ALERT
ALERT
ꢀꢁꢂꢃ ꢃꢄꢅꢃꢆ
ꢀꢁꢂRꢃ ꢄꢅꢆꢄꢇ
ꢀ0ꢁ ꢀ0ꢁ ꢀ0ꢁ
ꢀꢁꢂ
ꢀꢁꢂRꢃꢄꢅꢆꢇ
ꢀꢁꢂꢃ
ꢀꢁ
ꢀ
ꢃꢄ
ꢁꢁꢂꢂ
ꢀꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢀꢃ
ꢀꢁꢂꢃꢄꢅ RꢆꢇꢄꢇꢈꢁRꢇ ꢉRꢆ
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ0ꢈꢈꢉ
ꢀꢁ0ꢂꢃ
ꢀꢁꢂꢃꢄ
ꢀꢁ00ꢂꢃ
ꢁ
ꢀ ꢂꢃꢄꢅꢆꢇꢈ ꢀꢃꢉ ꢊꢀꢋꢌ ꢍꢅꢆꢇꢈ ꢂꢎꢅꢅꢏꢐꢑ
ꢀꢁꢂꢂꢃ
ꢀꢁꢀꢂꢃ
ꢄꢒꢋ
ꢀꢁꢂꢃRꢁꢄ ꢅꢆꢄꢅ ꢁR ꢁꢀꢇꢈR ꢉꢁꢊRꢋ
ꢀꢁꢂꢁꢃꢄꢀꢄꢂꢅ ꢆꢇꢂꢅRꢇꢈꢈꢄR
ꢀ
ꢃꢄ
ꢁꢁꢂꢂ
ꢀꢁ
ꢀ
ꢁꢂ
ꢀꢁ0
ꢂ
ꢀ
ꢀꢁ
ꢀ
ꢁꢂꢃ0
ꢀ00ꢁꢂ
ꢄ
ꢂ
ꢀꢁ0ꢂꢃ
ꢀꢁ
ꢀ
ꢁꢂꢃꢂ0
ꢀ
ꢀꢁ
ꢀꢁ
ꢄ
ꢀ
ꢁꢂꢃꢂ0
ꢀ
ꢁꢂꢃ
ꢀꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ
ꢀ
ꢁꢂ0
ꢀ
ꢁꢂꢃꢄ
ꢀꢁ
ꢂꢃ
ꢀ00ꢁꢂ
ꢅ
ꢀꢁ0ꢂꢃ
ꢀ
ꢁꢂꢃꢂꢄ
ꢀꢁ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁ
Rꢀꢁꢂ
ꢅ
ꢀ
ꢁꢂꢃꢂꢄ
Rꢀꢁ0
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
FAULT0
FAULT1
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁ ꢂꢃ ꢀ00ꢂ
ALERT
ALERT
ꢀꢁꢂꢃꢄ
ꢀꢁꢂ
ꢀꢁꢂRꢃꢄꢅꢆꢇ
ꢀꢁꢂꢃ
ꢀꢁ
ꢀꢁꢂꢃꢄꢅ RꢆꢇꢄꢇꢈꢁRꢇ ꢉRꢆ
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ0ꢈꢈꢉ
4678 F47
ꢀ ꢁꢂꢃ ꢄꢅꢆꢇꢈ ꢆꢉꢉRꢈꢄꢄ ꢊ ꢂ000000ꢋRꢌꢍ ꢎ0ꢏꢐ0ꢑ
ꢀ ꢁꢒꢃ ꢄꢅꢆꢇꢈ ꢆꢉꢉRꢈꢄꢄ ꢊ ꢂ00000ꢂꢋRꢌꢍ ꢎ0ꢏꢐꢂꢑ
ꢀ ꢓꢔ0ꢕꢖꢗ ꢄꢍꢘꢙꢚꢖꢘꢛꢜ ꢝRꢈꢞꢁꢈꢛꢚꢟ ꢍꢘꢙꢖ ꢘꢛꢙꢈRꢅꢈꢆꢇꢘꢛꢜ
ꢀ ꢛꢠ ꢜꢁꢘ ꢚꢠꢛꢝꢘꢜꢁRꢆꢙꢘꢠꢛ ꢆꢛꢉ ꢛꢠ ꢡꢆRꢙꢢ
ꢄꢡꢈꢚꢘꢝꢘꢚ ꢡRꢠꢜRꢆꢣꢣꢘꢛꢜ RꢈꢞꢁꢘRꢈꢉ
787Ω
ꢀꢀꢁꢂꢃ
*OPTIONAL 5V BIAS ≥ 100mA TOTAL
FOR EFFICIENCY AND THERMAL
IMPROVEMENT
ꢀꢁꢂꢀꢃ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀ ꢘꢛ ꢣꢁꢅꢙꢘꢢꢣꢠꢉꢁꢅꢈ ꢄꢟꢄꢙꢈꢣꢄꢤ ꢚꢠꢛꢝꢘꢜꢁRꢘꢛꢜ
RꢆꢘꢅꢋꢆꢉꢉRꢈꢄꢄ ꢘꢄ Rꢈꢚꢠꢣꢣꢈꢛꢉꢈꢉ
Figure 47. Two Paralleled LTM4678 Producing 1VOUT at 100A. Integrated Power System Management Features Accessible
Over 2-Wire I2C/SMBus/PMBus Serial Interface, No Input Current Readback
Rev 0
74
For more information www.analog.com
LTM4678
TYPICAL APPLICATIONS
ꢀꢁ ꢂꢃꢄꢅ
ꢀ0ꢆꢄ
ꢀ0ꢁ
ꢀꢁꢀꢂꢃ
ꢀꢁꢂꢂꢃ
ꢀ
ꢁꢁꢂꢂ
ꢀꢁꢀꢂ
ꢀ
ꢁꢂ
ꢂ
ꢀ
ꢀꢁ0
ꢀꢁ
ꢀꢀꢁꢂ
ꢀꢁ
ꢂ
ꢀ
ꢀꢀ0ꢁꢂ
ꢁꢂꢃ0
ꢀ
ꢀꢁ
ꢀ00ꢁꢂ
ꢀꢁ
ꢀ
ꢁꢂꢃ
ꢄ
ꢀꢁ ꢂꢃ ꢄꢅꢂ
ꢀ
ꢁꢂꢃꢂ0
ꢀ
ꢁꢂ0
ꢀꢁꢂꢃꢄ0ꢅꢆꢇ
ꢀꢁ ꢂꢃꢄꢅ
ꢀꢁꢂꢃ
ꢀꢀ0ꢁꢂ
ꢄ
ꢀ
ꢁꢂꢃꢂ0
ꢀꢁ ꢂꢃꢄꢅ
ꢀ
ꢁꢁꢂꢂ
ꢀꢁ
ꢀꢁꢂ
ꢂꢃ
ꢀ
ꢁꢂꢃꢄ
ꢀ00ꢁꢂ
ꢀ0ꢁ ꢀꢁꢂꢂꢃ ꢀ0ꢁ ꢀ0ꢁ
ꢀꢁ
ꢀꢁꢂꢃꢄꢅꢆ
Rꢀꢁꢂ
Rꢀꢁ0
FAULT0
ꢀꢁꢂꢃ ꢄꢅ ꢂꢆꢄ
ꢅ
ꢀ
ꢁꢂꢃꢂꢄ
ꢀꢁꢀꢁꢂꢂꢃꢁꢄꢂꢅꢆ
ꢀꢁꢂꢃ
ꢀꢀ0ꢁꢂ
ꢅ
ꢀ
ꢁꢂꢃꢂꢄ
ꢀꢁꢂꢃꢄ ꢅꢆꢄꢇRRꢂꢈꢄꢉ
ꢀꢁꢂ
ꢀꢁꢂ
FAULT1
ꢀꢁꢂꢃ
ALERT
ꢀꢁꢂ
ꢀ0ꢁ
ꢀ0ꢁ
ꢀ0ꢁ
ꢀꢁꢂRꢃꢄꢅꢆꢇ
ꢀꢁ
ꢀ
ꢁꢁꢂꢂ
ꢀꢁꢂꢃ
ꢁ
ꢀ ꢂꢃꢄꢅꢆꢇꢈ ꢀꢃꢉ ꢊꢀꢋꢌ ꢍꢅꢆꢇꢈ ꢂꢎꢅꢅꢏꢐꢑ ꢄꢒꢋ
ꢀꢁꢂꢃRꢁꢄ ꢅꢆꢄꢅ ꢁR ꢁꢀꢇꢈR ꢉꢁꢊRꢋ
ꢀꢁꢂꢁꢃꢄꢀꢄꢂꢅ ꢆꢇꢂꢅRꢇꢈꢈꢄR
ꢀꢁꢂꢃꢄ ꢀꢁꢂꢃꢄ ꢀꢀꢁꢂꢃ ꢀꢀꢁꢂꢃ
ꢀ00ꢁꢂ
ꢀꢀ00ꢁꢂ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀꢆꢇ00 ꢀꢀꢀ0Rꢀꢁ
ꢀ00ꢁꢂ
ꢀꢀ00ꢁꢂ
ꢀꢁꢂꢃꢄꢅ RꢆꢇꢄꢇꢈꢁRꢇ ꢉRꢆ
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ0ꢈꢈꢉ
ꢀꢁ0ꢂꢃꢄ
Figure 48. 1V and 1.2V Outputs Generated from 3.3V Power Input and Providing I2C/SMBus/PMBus Serial Interface
Rev 0
75
For more information www.analog.com
LTM4678
TYPICAL APPLICATIONS
ꢀꢁꢀꢂꢃ
ꢀꢁꢂꢂꢃ
ꢀꢁꢂꢂꢃ
ꢀꢁꢀꢂꢃ
ꢀꢁꢂꢂꢃ
ꢀ
ꢃꢄ
ꢀ
ꢃꢂ
ꢁꢁꢂꢂ
ꢁꢁꢂꢂ
ꢀꢁ
ꢀꢁ0
ꢀꢁ
ꢀ
ꢀ
ꢀꢁꢂꢀꢃ ꢄꢅ ꢆꢇꢃ
ꢁꢂ
ꢀꢁ0
ꢁꢂ
ꢂ
ꢂ
ꢀ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀ
ꢁꢂꢃ0
ꢁꢂꢃ0
ꢀꢀꢁꢂ
ꢀꢁ
ꢀꢁ0ꢂꢃ
ꢀꢀꢁꢂ
ꢀꢁ
ꢄ
ꢄ
ꢂ
ꢂ
ꢀꢁ0ꢂꢃ
ꢀꢁ
ꢀ
ꢀ
ꢁꢂꢃꢂ0
ꢀ
ꢀꢁ
ꢀ00ꢁꢂ
ꢀꢁ
ꢀ
ꢁꢂꢃꢂ0
ꢀꢁ
ꢄ
ꢄ
ꢀ
ꢀ
ꢁꢂꢃꢂ0
ꢁꢂꢃꢂ0
ꢀ
ꢀ
ꢁꢂꢃ
ꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ
ꢃꢄ
ꢁꢁꢂꢂ
ꢀ
ꢀ
ꢁꢂ0
ꢁꢂ0
ꢀ
ꢀ
ꢁꢂꢃꢄ
ꢁꢂꢃꢄ
ꢀꢁ
ꢀꢁ
ꢂꢃ
ꢂꢃ
ꢀ0ꢁ ꢀꢁꢂꢂꢃ ꢀ0ꢁ ꢀ0ꢁ
ꢀꢁꢂꢀꢃꢃ
ꢅ
ꢀ00ꢁꢂ
ꢅ
ꢀꢁ0ꢂꢃ
ꢀ
ꢀ
ꢁꢂꢃꢂꢄ
ꢁꢂꢃꢂꢄ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁ
ꢀꢁ
Rꢀꢁꢂ
Rꢀꢁꢂ
ꢀꢁꢂꢀꢃꢃ
ꢅ
ꢅ
ꢀ
ꢀ
ꢁꢂꢃꢂꢄ
ꢁꢂꢃꢂꢄ
Rꢀꢁ0
Rꢀꢁ0
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅ
FAULT0
FAULT0
FAULT1
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂ
ALERT
ALERT
FAULT1
ꢀꢁꢂꢃꢄꢅ
ALERT
ALERT
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀ0ꢁ ꢀ0ꢁ ꢀ0ꢁ
ꢀꢁꢂ
ꢀꢁꢂRꢃ ꢄꢅꢆ
ꢀꢁꢂ
ꢀꢁꢂRꢃꢄꢅꢆꢇ
ꢀꢁꢂRꢃꢄꢅꢆꢇ
ꢀꢁꢂRꢃꢀꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁ
ꢀꢁ
ꢀ
ꢃꢄ
ꢁꢁꢂꢂ
ꢀꢀꢁꢂꢃ ꢀꢁꢂꢃꢄ
787Ω ꢀꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢀꢃ
ꢀꢁꢂꢀꢃ
ꢀꢁꢂꢃꢄꢅ RꢆꢇꢄꢇꢈꢁRꢇ ꢉRꢆ
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ0ꢈꢈꢉ
ꢀꢀ0ꢁꢂ
ꢀꢁꢂꢃꢄ
ꢀꢁ00ꢂꢃ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢁ
ꢀ ꢂꢃꢄꢅꢆꢇꢈ ꢀꢃꢉ ꢊꢀꢋꢌ ꢍꢅꢆꢇꢈ ꢂꢎꢅꢅꢏꢐꢑ
ꢄꢒꢋ
ꢀꢁꢂꢃRꢁꢄ ꢅꢆꢄꢅ ꢁR ꢁꢀꢇꢈR ꢉꢁꢊRꢋ
ꢀꢁꢀꢂꢃ
ꢀꢁꢂꢂꢃ
ꢀꢁꢀꢂꢃ
ꢀꢁꢂꢂꢃ
ꢀꢁꢂꢁꢃꢄꢀꢄꢂꢅ ꢆꢇꢂꢅRꢇꢈꢈꢄR
ꢀ
ꢃꢄ
ꢀ
ꢃꢄ
ꢁꢁꢂꢂ
ꢁꢁꢂꢂ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀ
ꢁꢂ
ꢀꢁ0
ꢁꢂ
ꢀꢁ0
ꢂ
ꢂ
ꢀ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀ
ꢁꢂꢃ0
ꢀ
ꢀꢀꢁꢂ
ꢀꢁ
ꢁꢂꢃ0
ꢀꢀꢁꢂ
ꢀꢁ
ꢄ
ꢄ
ꢂ
ꢂ
ꢀ
ꢀꢁ0ꢂꢃ
ꢀꢁ
ꢀ
ꢀ00ꢁꢂ
ꢀ
ꢀꢁ
ꢁꢂꢃꢂ0
ꢁꢂꢃꢂ0
ꢀ
ꢀꢁ
ꢀꢁ
ꢄ
ꢄ
ꢀ
ꢀ
ꢁꢂꢃꢂ0
ꢁꢂꢃꢂ0
ꢀ
ꢀ
ꢁꢂꢃ
ꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ
ꢀ
ꢁꢂ0
ꢁꢂ0
ꢀ
ꢀ
ꢁꢂꢃꢄ
ꢁꢂꢃꢄ
ꢀꢁ
ꢂꢃ
ꢀꢁ
ꢂꢃ
ꢅ
ꢅ
ꢀ00ꢁꢂ
ꢀꢁ
ꢀ
ꢀꢁ0ꢂꢃ
ꢀ
ꢁꢂꢃꢂꢄ
ꢁꢂꢃꢂꢄ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁ
Rꢀꢁꢂ
Rꢀꢁꢂ
OFF ON
ꢅ
ꢀ
ꢅ
ꢁꢂꢃꢂꢄ
ꢀꢁꢂꢀꢃꢃ
ꢀ
ꢁꢂꢃꢂꢄ
Rꢀꢁ0
Rꢀꢁ0
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ ꢂꢃ
ꢄ00ꢂ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂ
ꢀꢁꢂ
FAULT0
FAULT0
FAULT1
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ALERT
FAULT1
ꢀꢁꢂꢃꢄꢅ
ALERT
ALERT
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ALERT
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂRꢃꢄꢅꢆꢇ
ꢀꢁꢂRꢃꢄꢅꢆꢇ
ꢀꢁꢂ
ꢀꢁꢂRꢃꢄꢅꢆꢇ
ꢀꢁꢂRꢃꢄꢅꢆꢇ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁ
ꢀꢁ
4678 F49
ꢀꢁꢂꢃꢄꢅ RꢆꢇꢄꢇꢈꢁRꢇ ꢉRꢆ
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ0ꢈꢈꢉ
*OPTIONAL 5V BIAS ≥ 200mA TOTAL
FOR EFFICIENCY AND THERMAL
IMPROVEMENT
ꢀꢁꢂꢃꢄ ꢀꢀꢁꢂꢃ
ꢀꢀꢁꢂꢃ
ꢀꢁꢂꢀꢃ
ꢀꢁꢂꢀꢃ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
Figure 49. 8-Phase Operation with Four LTM4678 Producing 1V at 200A. Power System Management Features Accessible Through
the LTM4678 2-Wire I2C/SMBus/PMBus Serial Interface
Rev 0
76
For more information www.analog.com
LTM4678
PMBus COMMAND DETAILS
ADDRESSING AND WRITE PROTECT
CMD
DATA
DEFAULT
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM VALUE
PAGE
0x00 Provides integration with multi-page PMBus devices.
R/W Byte
N
N
N
Reg
0x00
PAGE_PLUS_WRITE
PAGE_PLUS_READ
0x05 Write a supported command directly to a PWM channel. W Block
0x06 Read a supported command directly from a PWM
channel.
Block
R/W
WRITE_PROTECT
0x10 Level of protection provided by the device against
accidental changes.
R/W Byte
N
Reg
Y
0x00
2
MFR_ADDRESS
0xE6 Sets the 7-bit I C address byte.
R/W Byte
R/W Byte
N
Y
Reg
Reg
Y
Y
0x4F
0x80
MFR_RAIL_ADDRESS
0xFA Common address for PolyPhase outputs to adjust
common parameters.
PAGE
The PAGE command provides the ability to configure, control and monitor both PWM channels through only one physi-
cal address, either the MFR_ADDRESS or GLOBAL device address. Each PAGE contains the operating commands for
one PWM channel.
Pages 0x00 and 0x01 correspond to Channel 0 and Channel 1, respectively, in this device.
Setting PAGE to 0xFF applies any following paged commands to both outputs. With PAGE set to 0xFF the LTM4678
will respond to read commands as if PAGE were set to 0x00 (Channel 0 results).
This command has one data byte.
PAGE_PLUS_WRITE
The PAGE_PLUS_WRITE command provides a way to set the page within a device, send a command, and then send
the data for the command, all in one communication packet. Commands allowed by the present write protection level
may be sent with PAGE_PLUS_WRITE.
The value stored in the PAGE command is not affected by PAGE_PLUS_WRITE. If PAGE_PLUS_WRITE is used to send
a non-paged command, the Page Number byte is ignored.
This command uses Write Block protocol. An example of the PAGE_PLUS_WRITE command with PEC sending a com-
mand that has two data bytes is shown in Figure 50.
ꢘ
ꢖ
ꢘ
ꢘ
ꢗ
ꢘ
ꢗ
ꢘ
ꢗ
ꢘ
ꢗ
ꢘ
ꢀꢁꢂꢃꢄ
ꢂꢅꢅRꢄꢀꢀ
ꢆꢂꢇꢄꢈꢆꢁꢉꢀ
ꢊꢋꢌꢌꢂꢍꢅ ꢊꢋꢅꢄ
ꢎꢁꢋꢊꢏ ꢊꢋꢉꢍꢐ
ꢑꢒ ꢓꢔ
ꢆꢂꢇꢄ
ꢍꢉꢌꢎꢄR
ꢊꢋꢌꢌꢂꢍꢅ
ꢊꢋꢅꢄ
ꢀ
ꢕ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢙ
ꢗ
ꢘ
ꢗ
ꢘ
ꢗ
ꢘ
ꢘ
ꢁꢋꢕꢄR ꢅꢂꢐꢂ
ꢎꢚꢐꢄ
ꢉꢆꢆꢄR ꢅꢂꢐꢂ
ꢎꢚꢐꢄ
ꢂ
ꢂ
ꢆꢄꢊ ꢎꢚꢐꢄ
ꢂ
ꢆ
ꢓꢛꢖꢗ ꢜꢝ0
Figure 50. Example of PAGE_PLUS_WRITE
PAGE_PLUS_READ
The PAGE_PLUS_READ command provides the ability to set the page within a device, send a command, and then read
the data returned by the command, all in one communication packet .
Rev 0
77
For more information www.analog.com
LTM4678
PMBus COMMAND DETAILS
The value stored in the PAGE command is not affected by PAGE_PLUS_READ. If PAGE_PLUS_READ is used to access
data from a non-paged command, the Page Number byte is ignored.
This command uses the Process Call protocol. An example of the PAGE_PLUS_READ command with PEC is shown
in Figure 51.
ꢁ
ꢗ
ꢁ
ꢁ
ꢘ
ꢁ
ꢘ
ꢁ
ꢘ
ꢁ
ꢘ
ꢁ
ꢂꢃꢄꢅꢆ
ꢄꢇꢇRꢆꢂꢂ
ꢀꢄꢈꢆꢉꢀꢃꢊꢂ
ꢋꢌꢍꢍꢄꢎꢇ ꢋꢌꢇꢆ
ꢏꢃꢌꢋꢐ ꢋꢌꢊꢎꢑ
ꢒꢓ ꢔꢕ
ꢀꢄꢈꢆ
ꢎꢊꢍꢏꢆR
ꢋꢌꢍꢍꢄꢎꢇ
ꢋꢌꢇꢆ
ꢂ
ꢖ
ꢄ
ꢄ
ꢄ
ꢄ
ꢄ
ꢙ
ꢁ
ꢗ
ꢁ
ꢁ
ꢘ
ꢁ
ꢘ
ꢁ
ꢘ
ꢁ
ꢘ
ꢁ
ꢁ
ꢂꢃꢄꢅꢆ
ꢄꢇꢇRꢆꢂꢂ
ꢏꢃꢌꢋꢐ ꢋꢌꢊꢎꢑ
ꢃꢌꢖꢆR ꢇꢄꢑꢄ
ꢏꢚꢑꢆ
ꢊꢀꢀꢆR ꢇꢄꢑꢄ
ꢏꢚꢑꢆ
ꢂꢛ
R
ꢄ
ꢄ
ꢄ
ꢄ
ꢀꢆꢋ ꢏꢚꢑꢆ
ꢎꢄ
ꢀ
ꢒꢓ ꢔꢕ
ꢜꢝꢗꢘ ꢞꢟꢁ
Figure 51. Example of PAGE_PLUS_READ
Note: PAGE_PLUS commands cannot be nested. A PAGE_PLUS command cannot be used to read or write another
PAGE_PLUS command. If this is attempted, the LTM4678 will NACK the entire PAGE_PLUS packet and issue a CML
fault for Invalid/Unsupported Data.
WRITE_PROTECT
The WRITE_PROTECT command is used to control writing to the LTM4678 device. This command does not indicate
the status of the WP pin which is defined in the MFR_COMMON command. The WP pin takes precedence over the
value of this command.
BYTE MEANING
0x80 Disable all writes except to the WRITE_PROTECT, PAGE, MFR_
EE_UNLOCK, and STORE_USER_ALL commands.
0x40 Disable all writes except to the WRITE_PROTECT, PAGE,
MFR_EE_UNLOCK, MFR_CLEAR_PEAKS, STORE_USER_ALL,
OPERATION and CLEAR_FAULTS command. Individual fault
bits can be cleared by writing a 1 to the respective bits in the
STATUS commands.
0x20 Disable all writes except to the WRITE_PROTECT, OPERATION,
MFR_EE_UNLOCK, MFR_CLEAR_PEAKS, CLEAR_FAULTS,
PAGE, ON_OFF_CONFIG, VOUT_COMMAND and STORE_USER_
ALL. Individual fault bits can be cleared by writing a 1 to the
respective bits in the STATUS commands.
0x10 Reserved, must be 0
0x08 Reserved, must be 0
0x04 Reserved, must be 0
0x02 Reserved, must be 0
0x01 Reserved, must be 0
Enable writes to all commands when WRITE_PROTECT is set to 0x00.
IfWPpinishigh,PAGE,OPERATION,MFR_CLEAR_PEAKS,MFR_EE_UNLOCK,WRITE_PROTECTandCLEAR_FAULTS
commands are supported. Individual fault bits can be cleared by writing a 1 to the respective bits in the STATUS
commands.
Rev 0
78
For more information www.analog.com
LTM4678
PMBus COMMAND DETAILS
MFR_ADDRESS
The MFR_ADDRESS command byte sets the 7 bits of the PMBus slave address for this device.
Setting this command to a value of 0x80 disables device addressing. The GLOBAL device address, 0x5A and 0x5B,
cannot be deactivated. If RCONFIG is set to ignore, the ASEL pin is still used to determine the LSB of the channel ad-
dress. If the ASEL pin is open, the LTM4678 will use the lower 4 bits of the MFR_ADDRESS value stored in NVM to
construct the effective address of the part.
This command has one data byte.
MFR_RAIL_ADDRESS
The MFR_RAIL_ADDRESS command enables direct device address access to the PAGE activated channel. The value
of this command should be common to all devices attached to a single power supply rail.
The user should only perform command writes to this address. If a read is performed from this address and the rail
devices do not respond with EXACTLY the same value, the LTM4678 will detect bus contention and may set a CML
communications fault.
Setting this command to a value of 0x80 disables rail device addressing for the channel.
This command has one data byte.
GENERAL CONFIGURATION COMMANDS
DATA
DEFAULT
VALUE
COMMAND NAME
MFR_CHAN_CONFIG
MFR_CONFIG_ALL
CMD CODE DESCRIPTION
TYPE
Configuration bits that are channel specific. R/W Byte
General configuration bits. R/W Byte
PAGED FORMAT UNITS NVM
0xD0
0xD1
Y
N
Reg
Reg
Y
Y
0x1D
0x21
MFR_CHAN_CONFIG
General purpose configuration command common to multiple ADI products.
BIT MEANING
7
6
5
4
3
2
1
Reserved
Reserved
Reserved
Disable RUN Low. When asserted the RUN pin is not pulsed low if commanded OFF.
Enable Short Cycle recognition if this bit is set to a 1.
SHARE_CLOCK control. If SHARE_CLOCK is held low, the output is disabled.
No FAULT ALERT, ALERT is not pulled low if FAULT is pulled low externally. Assert this bit if either POWER_GOOD or VOUT_UVUF are
propagated on FAULT.
0
Disables the V
decay value requirement for MFR_RETRY_TIME and t
processing. When this bit is set to a 0, the output must decay to
OUT
OFF(MIN)
less than 12.5% of the programmed value for any action that turns off the rail including a fault, an OFF/ON command, or a toggle of RUN from
high to low to high.
This command has one data byte.
Rev 0
79
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LTM4678
PMBus COMMAND DETAILS
A ShortCycle event occurs whenever the PWM channel is commanded back ON, or reactivated, after the part has been
commanded OFF and is processing either the TOFF_DELAY or the TOFF_FALL states. The PWM channel can be turned
ON and OFF through either the RUN pin and or the PMBus OPERATION command.
If the PWM channel is reactivated during the TOFF_DELAY, the part will perform the following:
1. Immediately tri-state the PWM channel output;
2. Start the retry delay timer as specified by the t
.
OFF(MIN)
3. After the t
value has expired, the PWM channel will proceed to the TON_DELAY state and the STATUS_
OFF(MIN)
MFR_SPECIFIC bit #1 will assert.
If the PWM channel is reactivated during the TOFF_FALL, the part will perform the following:
1. Stop ramping down the PWM channel output;
2. Immediately tri-state the PWM channel output;
3. Start the retry delay timer as specified by the t
.
OFF(MIN)
4. After the t
value has expired, the PWM channel will proceed to the TON_DELAY state and the STATUS_
OFF(MIN)
MFR_SPEFIFIC bit #1 will assert.
If the ShortCycle event occurs and the ShortCycle MFR_CHAN_CONFIG bit is not set, the PWM channel state machine
will complete its TOFF_DELAY and TOFF_FALL operations as previously commanded by the user.
MFR_CONFIG_ALL
General purpose configuration command common to multiple ADI products.
BIT MEANING
7
6
5
4
3
2
Enable Fault Logging
Ignore Resistor Configuration Pins
Mask PMBus, Part II, Section 10.9.1 Violations
Disable SYNC output
Enable 255ms PMBus timeout
A valid PEC required for PMBus writes to be accepted. If this bit is not
set, the part will accept commands with invalid PEC.
1
0
Enable the use of PMBus clock stretching
Execute CLEAR_FAULTS on rising edge of either RUN pin.
This command has one data byte.
ON/OFF/MARGIN
CMD
DATA
DEFAULT
VALUE
COMMAND NAME
ON_OFF_CONFIG
OPERATION
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
0x02 RUN pin and PMBus bus on/off command configuration. R/W Byte
Y
Y
Reg
Reg
Y
Y
0x1E
0x80
0x01 Operating mode control. On/off, margin high and margin R/W Byte
low.
MFR_RESET
0xFD Commanded reset without requiring a power-down.
Send Byte
N
NA
Rev 0
80
For more information www.analog.com
LTM4678
PMBus COMMAND DETAILS
ON_OFF_CONFIG
The ON_OFF_CONFIG command specifies the combination of RUNn pin input state and PMBus commands needed to
turn the PWM channel on and off.
Supported Values:
VALUE
MEANING
0x1F
OPERATION value and RUNn pin must both command the device to start/run. Device executes immediate off when commanded off.
OPERATION value and RUNn pin must both command the device to start/run. Device uses TOFF_ command values when commanded off.
RUNn pin control with immediate off when commanded off. OPERATION on/off control ignored.
RUNn pin control using TOFF_ command values when commanded off. OPERATION on/off control ignored.
0x1E
0x17
0x16
Programming an unsupported ON_OFF_CONFIG value will generate a CML fault and the command will be ignored.
This command has one data byte.
OPERATION
The OPERATION command is used to turn the unit on and off in conjunction with the input from the RUNn pins. It
is also used to cause the unit to set the output voltage to the upper or lower MARGIN VOLTAGEs. The unit stays in
the commanded operating mode until a subsequent OPERATION command or change in the state of the RUNn pin
instructs the device to change to another mode. If the part is stored in the MARGIN_LOW/HIGH state, the next RESET
or POWER_ON cycle will ramp to that state. If the OPERATION command is modified, for example ON is changed
to MARGIN_LOW, the output will move at a fixed slope set by the VOUT_TRANSITION_RATE. The default operation
command is sequence off. If V is applied to a part with factory default programming and the VOUT_CONFIG resistor
IN
configuration pins are not installed, the outputs will be commanded off.
The part defaults to the Sequence Off state.
This command has one data byte.
Supported Values:
VALUE
MEANING
0xA8
Margin high.
Margin low.
0x98
0x80
On (V
back to nominal even if bit 3 of ON_OFF_CONFIG is not set).
OUT
0x40*
0x00*
Soft off (with sequencing).
Immediate off (no sequencing).
*Device does not respond to these commands if bit 3 of ON_OFF_CONFIG is not set.
Programming an unsupported OPERATION value will generate a CML fault and the command will be ignored.
This command has one data byte.
MFR_RESET
This command provides a means to reset the LTM4678 from the serial bus. This forces the LTM4678 to turn off both
PWM channels, load the operating memory from internal EEPROM, clear all faults and then perform a soft-start of
both PWM channels, if enabled.
This write-only command has no data bytes.
Rev 0
81
For more information www.analog.com
LTM4678
PMBus COMMAND DETAILS
PWM CONFIGURATION
DATA
DEFAULT
COMMAND NAME
MFR_PWM_COMP
MFR_PWM_MODE
MFR_PWM_CONFIG
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM VALUE
0xD3
0xD4
0xF5
PWM loop compensation configuration
R/W Byte
R/W Byte
R/W Byte
Y
Y
N
Reg
Reg
Reg
Y
Y
Y
0x28
0xC7
0x10
Configuration for the PWM engine.
Set numerous parameters for the DC/DC controller
including phasing.
FREQUENCY_SWITCH
0x33
Switching frequency of the controller.
R/W
Word
N
L11
kHz
Y
350
0xFABC
MFR_PWM_MODE
The MFR_PWM_MODE command sets important PWM controls for each channel.
The MFR_PWM_MODE command allows the user to program the PWM controller to use discontinuous (pulse-skipping
mode), or forced continuous conduction mode.
BIT
7
0b
1b
6
MEANING
Use High Range of I
Low Current Range
High Current Range
Enable Servo Mode
LIMIT
5
External temperature sense:
0: ∆V measurement.
BE
Now reserved, ∆V only supported.
BE
4
Page 0 Only: Use of TSNS -Sensed Temperature Telemetry
1a
0 - Temperature sensed via TSNS is used to temperature-correct the current-sense information digitized by Channel 1’s current sense input,
1a
ISNS +/ISNS –.
1a
1a
1 - Temperature sensed via TSNS is used to temperature-correct the current-sense information digitized by Channel 1’s current sense input,
0a
ISNS +/ISNS –. Telemetry obtained from the thermal sensor connected to TSNS can be external to the module, if desired.
1a
1a
1a
3
Reserved
2
1
Reserved, always low DCR current sense
Range
V
OUT
1b
0b
The maximum output voltage is 2.75V
The maximum output voltage is 3.6V
Bit[0] Mode
0b
1b
Discontinuous
Forced Continuous
Bit [7] of this command determines if the part is in high range or low range of the IOUT_OC_FAULT_LIMIT command.
Changing this bit value changes the PWM loop gain and compensation. This bit value should not be changed when the
channel output is active. Writing this bit when the channel is active will generate a CML fault.
Bit [6] The LTM4678 will not servo while the part is OFF, ramping on or ramping off. When set to a one, the output servo
is enabled. The output set point DAC will be slowly adjusted to minimize the difference between the READ_VOUT_ADC
and the VOUT_COMMAND (or the appropriate margined value).
The LTM4678 computes temperature in °C from ∆V measured by the ADC at the TSNSn pin as
BE
T = (G • ∆V • q/(K • ln(16))) – 273.15 + O
BE
Rev 0
82
For more information www.analog.com
LTM4678
PMBus COMMAND DETAILS
For both equations,
–14
G = MFR_TEMP_1_GAIN • 2 , and
O = MFR_TEMP_1_OFFSET
Bit[2] is now reserved, and Ultra Low DCR mode is default.
Bit[1] of this command determines if the part is in high range or low voltage range. Changing this bit value changes
the PWM loop gain and compensation. This bit value should not be changed when the channel output is active. Writing
this bit when the channel is active will generate a CML fault.
B
it[0] determines if the PWM mode of operation is discontinuous (pulse-skipping mode), or forced continuous con-
duction mode. Whenever the channel is ramping on, the PWM mode will be discontinuous, regardless of the value of
this bit. This command has one data byte.
MFR_PWM_COMP
The MFR_PWM_COMP command sets the g of the PWM channel error amplifiers and the value of the internal R
m
ITHn
compensation resistors. This command affects the loop gain of the PWM output which may require modifications to
the external compensation network.
BIT
MEANING
BIT [7:5]
000b
Error Amplifier GM Adjust (mS)
1.00
1.68
2.35
3.02
3.69
4.36
5.04
5.73
001b
010b
011b
100b
101b
110b
111b
BIT [4:0]
00000b
00001b
00010b
00011b
00100b
00101b
00110b
00111b
01000b
01001b
01010b
01011b
01100b
01101b
01110b
01111b
R
ITH
(kΩ)
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
2.5
3
3.5
4
4.5
5
5.5
Rev 0
83
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LTM4678
PMBus COMMAND DETAILS
10000b
10001b
10010b
10011b
10100b
10101b
10110b
10111b
11000b
11001b
11010b
11011b
11100b
11101b
11110b
11111b
6
7
8
9
11
13
15
17
20
24
28
32
38
46
54
62
This command has one data byte.
MFR_PWM_CONFIG
The MFR_PWM_CONFIG command sets the switching frequency phase offset with respect to the falling edge of the
SYNC signal. The part must be in the OFF state to process this command. Either the RUN pins must be low or the
channels must be commanded off. If either channel is in the RUN state and this command is written, the command
will be NACK’d and a BUSY fault will be asserted.
BIT
MEANING
7
Reserved
[6:5]
00b
01b
10b
11b
Input current sense gain.
2x gain. 0mV to 50mV range.
4x gain. 0mV to 20mV range.
8x gain. 0mV to 5mV range.
Reserved
4
Share Clock Enable : If this bit is 1, the
SHARE_CLK pin will not be released until
IN
V
> VIN_ON. The SHARE_CLK pin will be
pulled low when V < VIN_OFF. If this bit is 0, the SHARE_
IN
CLK pin will not be pulled low when VIN < VIN_OFF except
for the initial application of VIN.
3
BIT [2:0]
000b
001b
010b
011b
100b
101b
110b
Reserved
CHANNEL 0 (DEGREES)
CHANNEL 1 (DEGREES)
0
90
0
180
270
240
120
240
240
300
0
120
60
120
Rev 0
84
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LTM4678
PMBus COMMAND DETAILS
FREQUENCY_SWITCH
The FREQUENCY_SWITCH command sets the switching frequency, in kHz, of the LTM4678.
Supported Frequencies:
VALUE [15:0]
0x0000
0xF3E8
RESULTING FREQUENCY (TYP)
External Oscillator
250kHz
0xFABC
0xFB52
0xFBE8
0x023F
350kHz
425kHz
500kHz
575kHz
0x028A
0x02EE
0x03E8
650kHz
750kHz
1000kHz
The part must be in the OFF state to process this command. The RUN pin must be low or both channels must be
commanded off. If the part is in the RUN state and this command is written, the command will be NACK'd and a BUSY
fault will be asserted. When the part is commanded off and the frequency is changed, a PLL_UNLOCK status may be
detected as the PLL locks onto the new frequency.
This command has two data bytes and is formatted in Linear_5s_11s format.
VOLTAGE
Input Voltage and Limits
DATA
PAGED FORMAT
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
UNITS
NVM
VIN_OV_FAULT_LIMIT
0x55
0x58
0x35
0x36
0xF7
Input supply overvoltage fault limit.
R/W
N
N
N
N
N
L11
L11
L11
L11
L11
V
Y
15.5
Word
0xD3E0
VIN_UV_WARN_LIMIT
VIN_ON
Input supply undervoltage warning limit.
R/W
Word
V
V
Y
Y
Y
Y
4.65
D12A
Input voltage at which the unit should start
power conversion.
R/W
Word
4.75
D130
VIN_OFF
Input voltage at which the unit should stop
power conversion.
R/W
Word
V
4.5
D120
MFR_ICHIP_CAL_GAIN
The resistance value of the V pin filter
R/W
Word
mΩ
1000
0x03E8
IN
element in milliohms
VIN_OV_FAULT_LIMIT
The VIN_OV_FAULT_LIMIT command sets the value of the input voltage measured by the ADC, in volts, that causes
an input overvoltage fault.
This command has two data bytes in Linear_5s_11s format.
Rev 0
85
For more information www.analog.com
LTM4678
PMBus COMMAND DETAILS
VIN_UV_WARN_LIMIT
The VIN_UV_WARN_LIMIT command sets the value of input voltage measured by the ADC that causes an input under-
voltage warning. This warning is disabled until the input exceeds the input startup threshold value set by the VIN_ON
command and the unit has been enabled. If the V Voltage drops below the VIN_OV_WARN_LIMIT the device:
IN
•
•
•
Sets the INPUT Bit Is the STATUS_WORD
Sets the V Undervoltage Warning Bit in the STATUS_INPUT Command
IN
Notifies the Host by Asserting ALERT, unless Masked
VIN_ON
The VIN_ON command sets the input voltage, in Volts, at which the unit starts power conversion.
This command has two data bytes and is formatted in Linear_5s_11s format.
VIN_OFF
The VIN_OFF command sets the input voltage, in Volts, at which the unit stops power conversion.
This command has two data bytes and is formatted in Linear_5s_11s format.
MFR_ICHIP_CAL_GAIN
The MFR_ICHIP_CAL_GAIN command is used to set the resistance value of the V pin filter element in milliohms.
IN
(See also READ_VIN). Set MFR_RVIN equal to 0 if no filter element is used.
This command has two data bytes and is formatted in Linear_5s_11s format.
Output Voltage and Limits
DATA
DEFAULT
VALUE
2
0x14
3.6
0xC399
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
R Byte
PAGED FORMAT
Y
UNITS
NVM
–12
VOUT_MODE
0x20
Output voltage format and exponent
Reg
L16
–12
(2 ).
VOUT_MAX
0x24
Upper limit on the output voltage
the unit can command regardless of
any other commands.
R/W
Word
Y
V
Y
VOUT_OV_FAULT_ LIMIT
VOUT_OV_WARN_ LIMIT
VOUT_MARGIN_HIGH
0x40
0x42
0x25
Output overvoltage fault limit.
R/W
Y
Y
Y
L16
L16
L16
V
V
V
Y
Y
Y
1.1
Word
0x119A
Output overvoltage warning limit.
R/W
Word
R/W
Word
1.075
0x1133
1.05
0x10CD
Margin high output voltage set
point. Must be greater than VOUT_
COMMAND.
VOUT_COMMAND
0x21
0x26
Nominal output voltage set point.
R/W
Y
Y
L16
L16
V
V
Y
Y
1.0
Word
0x1000
VOUT_MARGIN_LOW
Margin low output voltage set
point. Must be less than VOUT_
COMMAND.
R/W
Word
0.95
0x0F33
VOUT_UV_WARN_ LIMIT
VOUT_UV_FAULT_ LIMIT
MFR_VOUT_MAX
0x43
0x44
0xA5
Output undervoltage warning limit.
Output undervoltage fault limit.
Maximum allowed output voltage.
R/W
Y
Y
Y
L16
L16
L16
V
V
V
Y
Y
0.925
Word
0x0ECD
R/W
Word
R Word
0.9
0x0E66
3.6
0x0399
Rev 0
86
For more information www.analog.com
LTM4678
PMBus COMMAND DETAILS
VOUT_MODE
The data byte for VOUT_MODE command, used for commanding and reading output voltage, consists of a 3-bit mode
(only linear format is supported) and a 5-bit parameter representing the exponent used in output voltage Read/Write
commands.
This read-only command has one data byte.
VOUT_MAX
The VOUT_MAX command sets an upper limit on any voltage, including VOUT_MARGIN_HIGH, the unit can com-
mand regardless of any other commands or combinations. The maximum allowed value of this command is 3.6V.
The maximum output voltage the LTM4678 can produce is 3.3V including VOUT_MARGIN_HIGH. However, the
VOUT_OV_FAULT_LIMIT can be commanded as high as 3.6V.
This command has two data bytes and is formatted in Linear_16u format.
VOUT_OV_FAULT_LIMIT
The VOUT_OV_FAULT_LIMIT command sets the value of the output voltage measured by the OV supervisor compara-
tor at the sense pins, in volts, which causes an output overvoltage fault.
If the VOUT_OV_FAULT_LIMIT is modified and the part is in the RUN state, allow 10ms after the command is modi-
fied to assure the new value is being honored. The part indicates if it is busy making a calculation. Monitor bits 5 and
6 of MFR_COMMON. Either bit is low if the part is busy. If this wait time is not honored and the VOUT_COMMAND
is modified above the old overvoltage limit, an OV condition might temporarily be detected resulting in undesirable
behavior and possible damage to the switcher.
If VOUT_OV_FAULT_RESPONSE is set to OV_PULLDOWN or 0x00, the FAULT pin will not assert if VOUT_OV_FAULT is
propagated. The LTM4678 will pull the TG low and assert the BG bit as soon as the overvoltage condition is detected.
This command has two data bytes and is formatted in Linear_16u format.
VOUT_OV_WARN_LIMIT
The VOUT_OV_WARN_LIMIT command sets the value of the output voltage measured by the ADC at the sense pins,
in volts, which causes an output voltage high warning. The MFR_VOUT_PEAK value can be used to determine if this
limit has been exceeded.
In response to the VOUT_OV_WARN_LIMIT being exceeded, the device:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the VOUT Overvoltage Warning bit in the STATUS_VOUT command
• Notifies the host by asserting ALERT pin, unless masked
This condition is detected by the ADC so the response time may be up to t
This command has two data bytes and is formatted in Linear_16u format.
.
CONVERT
Rev 0
87
For more information www.analog.com
LTM4678
PMBus COMMAND DETAILS
VOUT_MARGIN_HIGH
The VOUT_MARGIN_HIGH command loads the unit with the voltage to which the output is to be changed, in Volts,
when the OPERATION command is set to “Margin High”. The value should be greater than VOUT_COMMAND. The
maximum guaranteed value on VOUT_MARGIN_HIGH is 3.7V.
ThiscommandwillnotbeactedonduringTON_RISEandTOFF_FALLoutputsequencing.TheVOUT_TRANSITION_RATE
will be used if this command is modified while the output is active and in a steady-state condition.
This command has two data bytes and is formatted in Linear_16u format.
VOUT_COMMAND
The VOUT_COMMAND consists of two bytes and is used to set the output voltage, in volts. The maximum guaranteed
value on VOUT is 3.6V.
ThiscommandwillnotbeactedonduringTON_RISEandTOFF_FALLoutputsequencing.TheVOUT_TRANSITION_RATE
will be used if this command is modified while the output is active and in a steady-state condition.
This command has two data bytes and is formatted in Linear_16u format.
VOUT_MARGIN_LOW
The VOUT_MARGIN_LOW command loads the unit with the voltage to which the output is to be changed, in volts,
when the OPERATION command is set to “Margin Low”. The value must be less than VOUT_COMMAND.
ThiscommandwillnotbeactedonduringTON_RISEandTOFF_FALLoutputsequencing.TheVOUT_TRANSITION_RATE
will be used if this command is modified while the output is active and in a steady-state condition.
This command has two data bytes and is formatted in Linear_16u format.
VOUT_UV_WARN_LIMIT
The VOUT_UV_ WARN_LIMIT command reads the value of the output voltage measured by the ADC at the sense pins,
in volts, which causes an output voltage low warning.
In response to the VOUT_UV_WARN_LIMIT being exceeded, the device:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the VOUT Undervoltage Warning bit in the STATUS_VOUT command
• Notifies the host by asserting ALERT pin, unless masked
This command has two data bytes and is formatted in Linear_16u format.
VOUT_UV_FAULT_LIMIT
The VOUT_UV_FAULT_LIMIT command reads the value of the output voltage measured by the UV supervisor com-
parator at the sense pins, in volts, which causes an output undervoltage fault.
This command has two data bytes and is formatted in Linear_16u format.
Rev 0
88
For more information www.analog.com
LTM4678
PMBus COMMAND DETAILS
MFR_VOUT_MAX
The MFR_VOUT_MAX command is the maximum output voltage in volts for each channel, including VOUT_OV_FAULT_
LIMIT. If the output voltages are set to high range (Bit 6 of MFR_PWM_CONFIG set to a 0) MFR_VOUT_MAX is 3.6V. If
the output voltage is set to low range (Bit 6 of MFR_PWM_CONFIG set to a 1) the MFR_VOUT_MAX is 2.75V. Entering
a VOUT_COMMAND value greater than this will result in a CML fault and the output voltage setting will be clamped
to the maximum level. This will also result in Bit 3 VOUT_MAX_Warning in the STATUS_VOUT command being set.
This read only command has 2 data bytes and is formatted in Linear_16u format.
OUTPUT CURRENT AND LIMITS
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS
NVM
MFR_IOUT_CAL_GAIN
0xDA
The ratio of the voltage at the current
R Word
Y
L11
mΩ
Factory 0.85 Typical
sense pins to the sensed current. For
devices using a fixed current sense
resistor, it is the resistance value in
mΩ.
Only
NVM
0xB365
MFR_IOUT_CAL_GAIN_TC
IOUT_OC_FAULT_LIMIT
IOUT_OC_WARN_LIMIT
0xF6
0x46
0x4A
Temperature coefficient of the current R/W Word
sensing element.
Y
Y
Y
CF
Y
Y
Y
3900
0x0F3C
Output overcurrent fault limit.
R/W Word
L11
L11
A
A
40.0
0xE280
Output overcurrent warning limit.
R/W Word
30.0
0xDBC0
MFR_IOUT_CAL_GAIN
The MFR_IOUT_CAL_GAIN command is used to set the resistance value of the current sense resistor in milliohms.
(see also MFR_IOUT_CAL_GAIN_TC).
This command has two data bytes and is formatted in Linear_5s_11s format.
MFR_IOUT_CAL_GAIN_TC
The MFR_IOUT_CAL_GAIN_TC command allows the user to program the temperature coefficient of the MFR_IOUT_
CAL_GAIN sense resistor or inductor DCR in ppm/°C.
This command has two data bytes and is formatted in 16-bit 2’s complement integer ppm. N = –32768 to 32767 •
–6
10 . Nominal temperature is 27°C. The MFR_IOUT_CAL_GAIN is multiplied by:
[1.0 + MFR_IOUT_CAL_GAIN_TC • (READ_TEMPERATURE_1-27)].
DCR sensing will have a typical value of 3900.
The MFR_IOUT_CAL_GAIN and MFR_IOUT_CAL_GAIN_TC impact all current parameters including: READ_IOUT,
MFR_IOUT_PEAK, IOUT_OC_FAULT_LIMIT and IOUT_OC_WARN_LIMIT.
Rev 0
89
For more information www.analog.com
LTM4678
PMBus COMMAND DETAILS
IOUT_OC_FAULT_LIMIT
The IOUT_OC_FAULT_LIMIT command sets the value of the peak output current limit, in Amperes. When the control-
ler is in current limit, the overcurrent detector will indicate an overcurrent fault condition. The following table lists the
+
–
progammable peak output current limit value in mV between I
and I
. The actual value of current limit is
SENSE
SENSE
+
–
(I
– I
)/MFR_IOUT_CAL_GAIN in Amperes.
SENSE
SENSE
BASED ON INDUCTOR CURRENT = 50% OF MAX LOAD OF 25A FOR WORSE CASE, THESE ARE APPROXIMATES, SO USE GUARDBAND AND CHECK
MFR_PWM_MODE[7] = 1
High Current Range (mV)
MFR_PWM_MODE[7] = 0
Low Current Range (mV)
~ILPeak (A)
18.28
19.63
20.98
22.32
24.17
25.02
26.36
27.70
29.05
30.39
31.74
33.08
34.42
35.78
37.11
38.46
~IOUT (A)
12
~ ILPeak (A)
10.17
10.9
~ IOUT (A)
4.88
15.45
16.59
17.73
18.86
20.42
21.14
22.27
23.41
24.55
25.68
26.82
27.95
29.50
30.23
31.36
32.50
8.59
9.22
14.35
15.70
17.04
18.88
19.74
21.07
22.42
23.77
25.11
26.46
27.80
29.14
30.49
31.83
33.18
5.63
9.85
11.66
12.40
13.42
13.89
14.64
15.40
16.14
16.89
17.63
18.38
19.12
19.87
20.62
21.37
6.38
10.48
11.34
11.74
12.37
13.01
13.64
14.27
14.90
15.53
16.5
7.12
8.14
8.61
9.36
10.12
10.86
11.61
12.35
13.10
13.84
14.59
15.33
16.09
16.79
17.42
18.06
Note: This is the peak of the current waveform. The READ_IOUT command returns the average current. The peak output
current limits are adjusted with temperature based on the MFR_IOUT_CAL_GAIN_TC using the equation:
Peak Current Limit = MFR_IOUT_CAL_GAIN • (1 + MFR_IOUT_CAL_GAIN_TC • (READ_TEMPERTURE_1-27.0)).
MFR_IOUT_CAL_GAIN is Set at Production Test.
The LTM4678 automatically convert currents to the appropriate internal bit value.
The I
range is set with bit 7 of the MFR_PWM_MODE command.
OUT
The IOUT_OC_FAULT_LIMIT is ignored during TON_RISE and TOFF_FALL.
If the IOUT_OC_FAULT_LIMIT is exceeded, the device:
• Sets the IOUT bit in the STATUS word
• Sets the IOUT Overcurrent fault bit in the STATUS_IOUT
• Notifies the host by asserting ALERT, unless masked
Rev 0
90
For more information www.analog.com
LTM4678
PMBus COMMAND DETAILS
This command has two data bytes and is formatted in Linear_5s_11s format.
IOUT_OC_WARN_LIMIT
This command sets the value of the output current measured by the ADC that causes an output overcurrent warning
in Amperes. The READ_IOUT value will be used to determine if this limit has been exceeded.
In response to the IOUT_OC_WARN_LIMIT being exceeded, the device:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the IOUT bit in the STATUS_WORD
• Sets the IOUT Overcurrent Warning bit in the STATUS_IOUT command, and
• Notifies the host by asserting ALERT pin, unless masked
The IOUT_OC_FAULT_LIMIT is ignored during TON_RISE and TOFF_FALL.
This command has two data bytes and is formatted in Linear_5s_11s format
Input Current and Limits
CMD
DATA
FORMAT
DEFAULT
VALUE
COMMAND NAME
CODE DESCRIPTION
TYPE
UNITS
NVM
MFR_IIN_CAL_GAIN
0xE8 The resistance value of the input current sense
element in mΩ.
R/W Word
L11
mΩ
Y
2.000
0xC200
MFR_IIN_CAL_GAIN
The MFR_IIN_CAL_GAIN command is used to set the resistance value of the input current sense resistor in milliohms.
(see also READ_IIN).
This command has two data bytes and is formatted in Linear_5s_11s format.
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
0x5D Input overcurrent warning
limit.
TYPE
PAGED
FORMAT
UNITS
NVM
IIN_OC_WARN_LIMIT
R/W Word
N
L11
A
Y
10.0
0xD280
IIN_OC_WARN_LIMIT
The IIN_OC_WARN_LIMIT command sets the value of the input current measured by the ADC, in amperes, that causes
a warning indicating the input current is high. The READ_IIN value will be used to determine if this limit has been
exceeded.
In response to the IIN_OC_WARN_LIMIT being exceeded, the device:
• Sets the OTHER bit in the STATUS_BYTE
• Sets the INPUT bit in the upper byte of the STATUS_WORD
• Sets the IIN Overcurrent Warning bit[1] in the STATUS_INPUT command, and
• Notifies the host by asserting ALERT pin
This command has two data bytes and is formatted in Linear_5s_11s format.
Rev 0
91
For more information www.analog.com
LTM4678
PMBus COMMAND DETAILS
TEMPERATURE
Power Stage DCR Temperature Calibration
DATA
DEFAULT
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM VALUE
MFR_TEMP_1_GAIN
0xF8
Sets the slope of the external temperature
sensor.
R/W Word
Y
Y
CF
Y
Y
0.995
0x3FAE
MFR_TEMP_1_OFFSET
0xF9
Sets the offset of the external temperature R/W Word
sensor.
L11
C
0.0
0x8000
MFR_TEMP_1_GAIN
The MFR_TEMP_1_GAIN command will modify the slope of the power stage sensor to account for non-idealities in
the element and errors associated with the remote sensing of the temperature in the inductor.
This command has two data bytes and is formatted in 16-bit 2’s complement integer. The effective gain adjustment is
–14
N • 2 . The nominal value is 1. N = 8192 to 32767
MFR_TEMP_1_OFFSET
The MFR_TEMP_1_OFFSET command will modify the offset of the power stage temperature sensor to account for
non-idealities in the element and errors associated with the remote sensing of the temperature in the inductor due to
location.
This command has two data bytes and is formatted in Linear_5s_11s format. The part starts the calibration with a
–273.15 so the default adjustment is zero.
Power Stage Temperature Limits
DATA
FORMAT
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED
UNITS
NVM
OT_FAULT_LIMIT
0x4F
0x51
0x53
Power stage overtemperature fault
R/W Word
Y
L11
L11
L11
C
Y
128.0
limit.
0xF200
OT_WARN_LIMIT
UT_FAULT_LIMIT
Power stage overtemperature
warning limit.
R/W Word
R/W Word
Y
Y
C
C
Y
Y
125.0
0xEBE8
Power stage undertemperature fault
limit.
–45.0
0xE530
OT_FAULT_LIMIT
The OT_FAULT_LIMIT command sets the value of the power stage temperature measured by the ADC, in degrees
Celsius, which causes an overtemperature fault. The READ_TEMPERATURE_1 value will be used to determine if this
limit has been exceeded.
This command has two data bytes and is formatted in Linear_5s_11s format.
OT_WARN_LIMIT
The OT_WARN_LIMIT command sets the value of the power stage temperature measured by the ADC, in degrees
Celsius, which causes an overtemperature warning. The READ_TEMPERATURE_1 value will be used to determine if
this limit has been exceeded.
Rev 0
92
For more information www.analog.com
LTM4678
PMBus COMMAND DETAILS
In response to the OT_WARN_LIMIT being exceeded, the device:
• Sets the TEMPERATURE bit in the STATUS_BYTE
• Sets the Overtemperature Warning bit in the STATUS_TEMPERATURE command, and
• Notifies the host by asserting ALERT pin, unless masked
This command has two data bytes and is formatted in Linear_5s_11s format.
UT_FAULT_LIMIT
TheUT_FAULT_LIMITcommandsetsthevalueofthepowerstagetemperaturemeasuredbytheADC,indegreesCelsius,
whichcausesanundertemperaturefault.TheREAD_TEMPERATURE_1valuewillbeusedtodetermineifthislimithasbeen
exceeded.
Note: If the temp sensors are not installed, the UT_FAULT_LIMIT can be set to –275°C and UT_FAULT_LIMIT response
set to ignore to avoid ALERT being asserted.
This command has two data bytes and is formatted in Linear_5s_11s format.
TIMING
Timing—On Sequence/Ramp
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS
NVM
TON_DELAY
0x60
Time from RUN and/or Operation on to
R/W Word
Y
L11
L11
ms
Y
0.0
output rail turn-on.
0x8000
TON_RISE
0x61
Time from when the output starts to
rise until the output voltage reaches the
VOUT commanded value.
Maximum time from the start of TON_
RISE for VOUT to cross the VOUT_UV_
FAULT_LIMIT.
R/W Word
R/W Word
R/W Word
Y
ms
Y
Y
Y
3.0
0xC300
TON_MAX_FAULT_LIMIT
VOUT_TRANSITION_RATE
TON_DELAY
0x62
0x27
Y
Y
L11
L11
ms
5.0
0xCA80
Rate the output changes when VOUT
commanded to a new value.
V/ms
0.001
0x8042
The TON_DELAY command sets the time, in milliseconds, from when a start condition is received until the output
voltage starts to rise. Values from 0ms to 83 seconds are valid. The resulting turn-on delay will have a typical delay of
270µs for TON_DELAY = 0 and an uncertainty of 50µs for all values of TON_DELAY.
This command has two data bytes and is formatted in Linear_5s_11s format.
TON_RISE
The TON_RISE command sets the time, in milliseconds, from the time the output starts to rise to the time the output
enters the regulation band. Values from 0 to 1.3 seconds are valid. The part will be in discontinuous mode during
TON_RISE events. If TON_RISE is less than 0.25ms, the LTM4678 digital slope will be bypassed and the output voltage
transition will only be controlled by the analog performance of the PWM switcher. The number of steps in TON_RISE
is equal to TON_RISE (in ms)/0.1ms with an uncertainty of 0.1ms.
This command has two data bytes and is formatted in Linear_5s_11s format.
Rev 0
93
For more information www.analog.com
LTM4678
PMBus COMMAND DETAILS
TON_MAX_FAULT_LIMIT
The TON_MAX_FAULT_LIMIT command sets the value, in milliseconds, on how long the unit can attempt to power
up the output without reaching the output undervoltage fault limit.
A data value of 0ms means that there is no limit and that the unit can attempt to bring up the output voltage indefinitely.
The maximum limit is 83 seconds.
This command has two data bytes and is formatted in Linear_5s_11s format.
VOUT_TRANSITION_RATE
When a PMBus device receives either a VOUT_COMMAND or OPERATION (Margin High, Margin Low) that causes the
output voltage to change this command set the rate in V/ms at which the output voltage changes. The commanded
rate of change does not apply when the unit is commanded on or off. The maximum allowed slope is 4V/ms.
This command has two data bytes and is formatted in Linear_5s_11s format.
Timing—Off Sequence/Ramp
DATA
FORMAT UNITS
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED
NVM
TOFF_DELAY
0x64
0x65
0x66
Time from RUN and/or Operation off to
the start of TOFF_FALL ramp.
Time from when the output starts to fall R/W Word
until the output reaches zero volts.
Maximum allowed time, after TOFF_FALL R/W Word
completed, for the unit to decay below
12.5%.
R/W Word
Y
L11
L11
L11
ms
ms
ms
Y
0.0
0x8000
TOFF_FALL
Y
Y
Y
Y
3.0
0xC300
TOFF_MAX_WARN_LIMIT
0
0x8000
TOFF_DELAY
The TOFF_DELAY command sets the time, in milliseconds, from when a stop condition is received until the output
voltage starts to fall. Values from 0 to 83 seconds are valid. The resulting turn off delay will have a typical delay of
270µs for TOFF_DELAY = 0 and an uncertainty of 50µs for all values of TOFF_DELAY. TOFF_DELAY is not applied
when a fault event occurs
This command has two data bytes and is formatted in Linear_5s_11s format.
TOFF_FALL
The TOFF_FALL command sets the time, in milliseconds, from the end of the turn-off delay time until the output volt-
age is commanded to zero. It is the ramp time of the V
set to high impedance state.
DAC. When the V
DAC is zero, the PWM output will be
OUT
OUT
The part will maintain the mode of operation programmed. For defined TOFF_FALL times, the user should set the part
to continuous conduction mode. Loading the max value indicates the part will ramp down at the slowest possible rate.
The minimum supported fall time is 0.25ms. A value less than 0.25ms will result in a 0.25ms ramp. The maximum
fall time is 1.3 seconds. The number of steps in TOFF_FALL is equal to TOFF_FALL (in ms)/0.1ms with an uncertainty
of 0.1ms.
In discontinuous conduction mode, the controller will not draw current from the load and the fall time will be set by
the output capacitance and load current.
This command has two data bytes and is formatted in Linear_5s_11s format.
Rev 0
94
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LTM4678
PMBus COMMAND DETAILS
TOFF_MAX_WARN_LIMIT
The TOFF_MAX_WARN_LIMIT command sets the value, in milliseconds, on how long the output voltage exceeds
12.5% of the programmed voltage before a warning is asserted. The output is considered off when the V
voltage
OUT
is less than 12.5% of the programmed VOUT_COMMAND value. The calculation begins after TOFF_FALL is complete.
A data value of 0ms means that there is no limit and that the output voltage exceeds 12.5% of the programmed voltage
indefinitely. Other than 0, values from 120ms to 524 seconds are valid.
This command has two data bytes and is formatted in Linear_5s_11s format.
Precondition for Restart
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
0xDC Minimum time the RUN pin is held
low by the LTM4678.
TYPE
PAGED
FORMAT
UNITS
NVM
MFR_RESTART_ DELAY
R/W Word
Y
L11
ms
Y
150
0xF258
MFR_RESTART_DELAY
This command specifies the minimum RUN off time in milliseconds. This device will pull the RUN pin low for this length
of time once a falling edge of RUN has been detected. The minimum recommended value is 136ms.
Note: The restart delay is different than the retry delay. The restart delay pulls RUN low for the specified time, after
which a standard start-up sequence is initiated. The minimum restart delay should be equal to TOFF_DELAY + TOFF_
FALL + 136ms. Valid values are from 136ms to 65.52 seconds in 16ms increments. To assure a minimum off time,
set the MFR_RESTART_DELAY 16ms longer than the desired time. The output rail can be off longer than the MFR_
RESTART_DELAY after the RUN pin is pulled high if the output decay bit 0 is enabled in MFR_CHAN_CONFIG and the
output takes a long time to decay below 12.5% of the programmed value.
This command has two data bytes and is formatted in Linear_5s_11s format.
FAULT RESPONSE
Fault Responses All Faults
DATA
FORMAT
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED
UNITS
NVM
MFR_RETRY_ DELAY
0xDB
Retry interval during FAULT retry R/W Word
mode.
Y
L11
ms
Y
250
0xF3E8
MFR_RETRY_DELAY
This command sets the time in milliseconds between retries if the fault response is to retry the controller at specified
intervals. This command value is used for all fault responses that require retry. The retry time starts once the fault has
been detected by the offending channel. Valid values are from 120ms to 83.88 seconds in 10µs increments.
Note: The retry delay time is determined by the longer of the MFR_RETRY_DELAY command or the time required
for the regulated output to decay below 12.5% of the programmed value. If the natural decay time of the output is
too long, it is possible to remove the voltage requirement of the MFR_RETRY_DELAY command by asserting bit 0 of
MFR_CHAN_CONFIG.
This command has two data bytes and is formatted in Linear_5s_11s format.
Rev 0
95
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LTM4678
PMBus COMMAND DETAILS
Fault Responses Input Voltage
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS
NVM
VIN_OV_FAULT_RESPONSE
0x56
Action to be taken by the device when an R/W Byte
input supply overvoltage fault is detected.
Y
Reg
Y
0x80
VIN_OV_FAULT_RESPONSE
The VIN_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an input over-
voltage fault. The data byte is in the format given in Table 18.
The device also:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Set the INPUT bit in the upper byte of the STATUS_WORD
• Sets the VIN Overvoltage Fault bit in the STATUS_INPUT command, and
• Notifies the host by asserting ALERT pin, unless masked
This command has one data byte.
Fault Responses Output Voltage
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS
NVM
VOUT_OV_FAULT_RESPONSE
0x41
0x45
0x63
Action to be taken by the device when an R/W Byte
output overvoltage fault is detected.
Y
Y
Y
Reg
Reg
Reg
Y
0xB8
0xB8
0xB8
VOUT_UV_FAULT_RESPONSE
Action to be taken by the device when an R/W Byte
output undervoltage fault is detected.
Y
Y
TON_MAX_FAULT_
RESPONSE
Action to be taken by the device when a
TON_MAX_FAULT event is detected.
R/W Byte
VOUT_OV_FAULT_RESPONSE
The VOUT_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an output
overvoltage fault. The data byte is in the format given in Table 14.
The device also:
• Sets the VOUT_OV bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the VOUT Overvoltage Fault bit in the STATUS_VOUT command
• Notifies the host by asserting ALERT pin, unless masked
The only values recognized for this command are:
0x00–Part performs OV pull down only, or OV_PULLDOWN.
0x80–The device shuts down (disables the output) and the unit does not attempt to retry. (PMBus, Part II, Section 10.7).
Rev 0
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LTM4678
PMBus COMMAND DETAILS
0xB8–The device shuts down (disables the output) and device attempts to retry continuously, without limitation, until
it is commanded OFF (by the RUN pin or OPERATION command or both), bias power is removed, or another fault
condition causes the unit to shut down.
0x4n The device shuts down and the unit does not attempt to retry. The output remains disabled until the part is com-
manded OFF then ON or the RUN pin is asserted low then high or RESET through the command or removal of VIN.
The OV fault must remain active for a period of n • 10µs, where n is a value from 0 to 7.
0x78+n The device shuts down and the unit attempts to retry continuously until either the fault condition is cleared
or the part is commanded OFF then ON or the RUN pin is asserted low then high or RESET through the command or
removal of VIN. The OV fault must remain active for a period of n • 10µs, where n is a value from 0 to 7.
Any other value will result in a CML fault and the write will be ignored.
This command has one data byte.
Table 14. VOUT_OV_FAULT_RESPONSE Data Byte Contents
BITS DESCRIPTION
VALUE MEANING
7:6
Response
00
Part performs OV pull down only or OV_PULLDOWN
(i.e., turns off the top MOSFET and turns on lower MOSFET
while V is > VOUT_OV_FAULT).
For all values of bits [7:6], the LTM4678:
• Sets the corresponding fault bit in the status commands and
• Notifies the host by asserting ALERT pin, unless masked.
OUT
01
The PMBus device continues operation for the delay time
specified by bits [2:0] and the delay time unit specified for that
particular fault. If the fault condition is still present at the end of
the delay time, the unit responds as programmed in the Retry
Setting (bits [5:3]).
The fault bit, once set, is cleared only when one or more of the
following events occurs:
• The device receives a CLEAR_FAULTS command.
10
11
The device shuts down immediately (disables the output) and
responds according to the retry setting in bits [5:3].
• The output is commanded through the RUN pin, the OPERATION
command, or the combined action of the RUN pin and
OPERATION command, to turn off and then to turn back on, or
Not supported. Writing this value will generate a CML fault.
• Bias power is removed and reapplied to the LTM4678.
Retry Setting
5:3
2:0
000
111
The unit does not attempt to restart. The output remains
disabled until the fault is cleared until the device is commanded
OFF bias power is removed.
The PMBus device attempts to restart continuously, without
limitation, until it is commanded OFF (by the RUN pin or
OPERATION command or both), bias power is removed, or
another fault condition causes the unit to shut down without
retry. Note: The retry interval is set by the MFR_RETRY_DELAY
command.
Delay Time
000-111 The delay time in 10µs increments. This delay time determines
how long the controller continues operating after a fault is
detected. Only valid for deglitched off state.
VOUT_UV_FAULT_RESPONSE
The VOUT_UV_FAULT_RESPONSE command instructs the device on what action to take in response to an output
undervoltage fault. The data byte is in the format given in Table 8.
The device also:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the VOUT undervoltage fault bit in the STATUS_VOUT command
• Notifies the host by asserting ALERT pin, unless masked
Rev 0
97
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LTM4678
PMBus COMMAND DETAILS
The UV fault and warn are masked until the following criteria are achieved:
1) The TON_MAX_FAULT_LIMIT has been reached
2) The TON_DELAY sequence has completed
3) The TON_RISE sequence has completed
4) The VOUT_UV_FAULT_LIMIT threshold has been reached
5) The IOUT_OC_FAULT_LIMIT is not present
The UV fault and warn are masked whenever the channel is not active.
The UV fault and warn are masked during TON_RISE and TOFF_FALL sequencing.
This command has one data byte.
Table 15. VOUT_UV_FAULT_RESPONSE Data Byte Contents
BITS DESCRIPTION
VALUE MEANING
7:6
Response
00
The PMBus device continues operation without interruption.
(Ignores the fault functionally)
For all values of bits [7:6], the LTM4678:
• Sets the corresponding fault bit in the status commands and
• Notifies the host by asserting ALERT pin, unless masked.
01
The PMBus device continues operation for the delay time
specified by bits [2:0] and the delay time unit specified for
that particular fault. If the fault condition is still present at the
end of the delay time, the unit responds as programmed in the
Retry Setting (bits [5:3]).
The fault bit, once set, is cleared only when one or more of the
following events occurs:
• The device receives a CLEAR_FAULTS command.
10
11
The device shuts down (disables the output) and responds
according to the retry setting in bits [5:3].
• The output is commanded through the RUN pin, the OPERATION
command, or the combined action of the RUN pin and
OPERATION command, to turn off and then to turn back on, or
Not supported. Writing this value will generate a CML fault.
• The device receives a RESTORE_USER_ALL command.
• The device receives a MFR_RESET command.
• The device supply power is cycled.
Retry Setting
5:3
2:0
000
111
The unit does not attempt to restart. The output remains
disabled until the fault is cleared until the device is commanded
OFF bias power is removed.
The PMBus device attempts to restart continuously, without
limitation, until it is commanded OFF (by the RUN pin or
OPERATION command or both), bias power is removed, or
another fault condition causes the unit to shut down without
retry. Note: The retry interval is set by the MFR_RETRY_DELAY
command.
Delay Time
000-111 The delay time in 10µs increments. This delay time determines
how long the controller continues operating after a fault is
detected. Only valid for deglitched off state.
Rev 0
98
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LTM4678
PMBus COMMAND DETAILS
TON_MAX_FAULT_RESPONSE
The TON_MAX_FAULT_RESPONSE command instructs the device on what action to take in response to a TON_MAX
fault. The data byte is in the format given in Table 13.
The device also:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the TON_MAX_FAULT bit in the STATUS_VOUT command, and
• Notifies the host by asserting ALERT pin, unless masked
A value of 0 disables the TON_MAX_FAULT_RESPONSE. It is not recommended to use 0.
Note: The PWM channel remains in discontinues mode until the TON_MAX_FAULT_LIMIT has been exceeded.
This command has one data byte.
Fault Responses Output Current
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
IOUT_OC_FAULT_RESPONSE
0x47
Action to be taken by the device when an R/W Byte
output overcurrent fault is detected.
Y
Reg
Y
0x00
IOUT_OC_FAULT_RESPONSE
The IOUT_OC_FAULT_RESPONSE command instructs the device on what action to take in response to an output
overcurrent fault. The data byte is in the format given in Table 9.
The device also:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the IOUT_OC bit in the STATUS_BYTE
• Sets the IOUT bit in the STATUS_WORD
• Sets the IOUT Overcurrent Fault bit in the STATUS_IOUT command, and
• Notifies the host by asserting ALERT pin, unless masked
This command has one data byte.
Rev 0
99
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LTM4678
PMBus COMMAND DETAILS
Table 16. OUT_OC_FAULT_RESPONSE Data Byte Contents
BITS DESCRIPTION
VALUE MEANING
7:6
Response
00
The LTM4678 continues to operate indefinitely while
maintaining the output current at the value set by
IOUT_OC_FAULT_LIMIT without regard to the output
voltage (known as constant-current or brick-wall limiting).
For all values of bits [7:6], the LTM4678:
• Sets the corresponding fault bit in the status commands and
• Notifies the host by asserting ALERT pin, unless masked.
01
10
Not supported.
The fault bit, once set, is cleared only when one or more of the
following events occurs:
The LTM4678 continues to operate, maintaining the output
current at the value set by IOUT_OC_FAULT_LIMIT without
regard to the output voltage, for the delay time set by bits [2:0].
If the device is still operating in current limit at the end of the
delay time, the device responds as programmed by the Retry
Setting in bits [5:3].
• The device receives a CLEAR_FAULTS command.
• The output is commanded through the RUN pin, the OPERATION
command, or the combined action of the RUN pin and
OPERATION command, to turn off and then to turn back on, or
11
The LTM4678 shuts down immediately and responds as
programmed by the Retry Setting in bits [5:3].
• The device receives a RESTORE_USER_ALL command.
• The device receives a MFR_RESET command.
• The device supply power is cycled.
Retry Setting
5:3
2:0
000
111
The unit does not attempt to restart. The output remains
disabled until the fault is cleared by cycling the RUN pin or
removing bias power.
The device attempts to restart continuously, without limitation,
until it is commanded OFF (by the RUN pin or OPERATION
command or both), bias power is removed, or another fault
condition causes the unit to shut down. Note: The retry interval
is set by the MFR_RETRY_DELAY command.
Delay Time
000-111 The number of delay time units in 16ms increments. This
delay time is used to determine the amount of time a unit is
to continue operating after a fault is detected before shutting
down. Only valid for deglitched off response.
Fault Responses IC Temperature
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS
NVM
MFR_OT_FAULT_
RESPONSE
0xD6
Action to be taken by the device when an
internal overtemperature fault is detected.
R Byte
N
Reg
0xC0
MFR_OT_FAULT_RESPONSE
The MFR_OT_FAULT_RESPONSE command byte instructs the device on what action to take in response to an internal
overtemperature fault. The data byte is in the format given in Table 12.
The LTM4678 also:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the MFR bit in the STATUS_WORD, and
• Sets the Overtemperature Fault bit in the STATUS_MFR_SPECIFIC command
• Notifies the host by asserting ALERT pin, unless masked
This command has one data byte.
Rev 0
100
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LTM4678
PMBus COMMAND DETAILS
Table 17. Data Byte Contents MFR_OT_FAULT_RESPONSE
BITS DESCRIPTION
VALUE MEANING
7:6
Response
00
01
10
Not supported. Writing this value will generate a CML fault.
Not supported. Writing this value will generate a CML fault
For all values of bits [7:6], the LTM4678:
• Sets the corresponding fault bit in the status commands and
• Notifies the host by asserting ALERT pin, unless masked.
The device shuts down immediately (disables the output) and
responds according to the retry setting in bits [5:3].
11
The device’s output is disabled while the fault is present.
Operation resumes and the output is enabled when the fault
condition no longer exists.
The fault bit, once set, is cleared only when one or more of the
following events occurs:
• The device receives a CLEAR_FAULTS command.
• The output is commanded through the RUN pin, the OPERATION
command, or the combined action of the RUN pin and
OPERATION command, to turn off and then to turn back on, or
• Bias power is removed and reapplied to the LTM4678.
Retry Setting
5:3
2:0
000
The unit does not attempt to restart. The output remains
disabled until the fault is cleared.
001-111 Not supported. Writing this value will generate CML fault.
Delay Time
XXX
Not supported. Value ignored
Fault Responses External Temperature
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS
NVM
OT_FAULT_ RESPONSE
0x50
Action to be taken by the device when an
external overtemperature fault is detected,
R/W Byte
Y
Reg
Reg
Y
0xB8
UT_FAULT_ RESPONSE
0x54
Action to be taken by the device when an
external undertemperature fault is detected.
R/W Byte
Y
Y
0xB8
OT_FAULT_RESPONSE
The OT_FAULT_RESPONSE command instructs the device on what action to take in response to an external overtem-
perature fault on the external temp sensors. The data byte is in the format given in Table 13.
The device also:
• Sets the TEMPERATURE bit in the STATUS_BYTE
• Sets the Overtemperature Fault bit in the STATUS_TEMPERATURE command, and
• Notifies the host by asserting ALERT pin, unless masked
This command has one data byte.
UT_FAULT_RESPONSE
The UT_FAULT_RESPONSE command instructs the device on what action to take in response to an external under-
temperature fault on the external temp sensors. The data byte is in the format given in Table 13.
The device also:
• Sets the TEMPERATURE bit in the STATUS_BYTE
• Sets the Undertemperature Fault bit in the STATUS_TEMPERATURE command, and
• Notifies the host by asserting ALERT pin, unless masked
Rev 0
101
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LTM4678
PMBus COMMAND DETAILS
This condition is detected by the ADC so the response time may be up to t
.
CONVERT
This command has one data byte.
Table 18. Data Byte Contents: TON_MAX_FAULT_RESPONSE, VIN_OV_FAULT_RESPONSE,
OT_FAULT_RESPONSE, UT_FAULT_RESPONSE
BITS DESCRIPTION
VALUE MEANING
7:6
Response
00
01
10
The PMBus device continues operation without interruption.
Not supported. Writing this value will generate a CML fault.
For all values of bits [7:6], the LTM4678:
• Sets the corresponding fault bit in the status commands, and
• Notifies the host by asserting ALERT pin, unless masked.
The device shuts down immediately (disables the output) and
responds according to the retry setting in bits [5:3].
11
Not supported. Writing this value will generate a CML fault.
The fault bit, once set, is cleared only when one or more of the
following events occurs:
• The device receives a CLEAR_FAULTS command.
• The output is commanded through the RUN pin, the OPERATION
command, or the combined action of the RUN pin and
OPERATION command, to turn off and then to turn back on, or
• The device receives a RESTORE_USER_ALL command.
• The device receives a MFR_RESET command.
• The device supply power is cycled.
Retry Setting
5:3
2:0
000
111
The unit does not attempt to restart. The output remains
disabled until the fault is cleared until the device is commanded
OFF bias power is removed.
The PMBus device attempts to restart continuously, without
limitation, until it is commanded OFF (by the RUN pin or
OPERATION command or both), bias power is removed, or
another fault condition causes the unit to shut down without
retry. Note: The retry interval is set by the MFR_RETRY_DELAY
command.
Delay Time
XXX
Not supported. Values ignored
FAULT SHARING
Fault Sharing Propagation
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
0xD2 Configuration that determines which faults
are propagated to the FAULT pins.
TYPE
PAGED FORMAT UNITS
NVM
MFR_FAULT_
PROPAGATE
R/W Word
Y
Reg
Y
0x6993
MFR_FAULT_PROPAGATE
The MFR_FAULT_PROPAGATE command enables the faults that can cause the FAULTn pin to assert low. The com-
mand is formatted as shown in Table 19. Faults can only be propagated to the FAULTn pin if they are programmed to
respond to faults.
This command has two data bytes.
Rev 0
102
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LTM4678
PMBus COMMAND DETAILS
Table 19. FAULTn Propagate Fault Configuration
The FAULT0 and FAULT1 pins are designed to provide electrical notification of selected events to the user. Some of these events are common to both output
channels. Others are specific to an output channel. They can also be used to share faults between channels.
BIT(S)
SYMBOL
OPERATION
B[15]
VOUT disabled while not decayed.
This is used in a PolyPhase configuration when bit 0 of the MFR_CHAN_CONFIG_LTM4678 is a
zero. If the channel is turned off, by toggling the RUN pin or commanding the part OFF, and then
the RUN is reasserted or the part is commanded back on before the output has decayed, VOUT
will not restart until the 12.5% decay is honored. The FAULT pin is asserted during this condition
if bit 15 is asserted.
B[14]
b[13]
Mfr_fault_propagate_short_CMD_cycle 0: No action
1: Asserts low if commanded off then on before the output has sequenced off. Re-asserts high
after sequence off.
t
OFF(MIN)
Mfr_fault_propagate_ton_max_fault
0: No action if a TON_MAX_FAULT fault is asserted
1: Associated output will be asserted low if a TON_MAX_FAULT fault is asserted
FAULT0 is associated with page 0 TON_MAX_FAULT faults
FAULT1 is associated with page 1 TON_MAX_FAULT faults
b[12]
b[11]
Reserved
Mfr_fault0_propagate_int_ot,
Mfr_fault1_propagate_int_ot
Reserved
0: No action if the MFR_OT_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the MFR_OT_FAULT_LIMIT fault is asserted
b[10]
b[9]
Reserved
b[8]
Mfr_fault0_propagate_ut,
Mfr_fault1_propagate_ut
0: No action if the UT_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the UT_FAULT_LIMIT fault is asserted
FAULT0 is associated with page 0 UT faults
FAULT1 is associated with page 1 UT faults
b[7]
Mfr_fault0_propagate_ot,
Mfr_fault1_propagate_ot
0: No action if the OT_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the OT_FAULT_LIMIT fault is asserted
FAULT0 is associated with page 0 OT faults
FAULT1 is associated with page 1 OT faults
b[6]
b[5]
b[4]
Reserved
Reserved
Mfr_fault0_propagate_input_ov,
Mfr_fault1_propagate_input_ov
Reserved
0: No action if the VIN_OV_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the VIN_OV_FAULT_LIMIT fault is asserted
b[3]
b[2]
Mfr_fault0_propagate_iout_oc,
Mfr_fault1_propagate_iout_oc
0: No action if the IOUT_OC_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the IOUT_OC_FAULT_LIMIT fault is asserted
FAULT0 is associated with page 0 OC faults
FAULT1 is associated with page 1 OC faults
b[1]
b[0]
Mfr_fault0_propagate_vout_uv,
Mfr_fault1_propagate_vout_uv
0: No action if the VOUT_UV_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the VOUT_UV_FAULT_LIMIT fault is asserted
FAULT0 is associated with page 0 UV faults
FAULT1 is associated with page 1 UV faults
Mfr_fault0_propagate_vout_ov,
Mfr_fault1_propagate_vout_ov
0: No action if the VOUT_OV_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the VOUT_OV_FAULT_LIMIT fault is asserted
FAULT0 is associated with page 0 OV faults
FAULT1 is associated with page 1 OV faults
Rev 0
103
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LTM4678
PMBus COMMAND DETAILS
Fault Sharing Response
DATA
DEFAULT
VALUE
0xC0
COMMAND NAME
CMD CODE DESCRIPTION
0xD5 Action to be taken by the device when the
FAULT pin is asserted low.
TYPE
R/W Byte
PAGED FORMAT UNITS
Y
NVM
Y
MFR_FAULT_RESPONSE
Reg
MFR_FAULT_RESPONSE
The MFR_FAULT_RESPONSE command instructs the device on what action to take in response to the FAULTn pin
being pulled low by an external source.
Supported Values:
VALUE
MEANING
0xC0
FAULT_INHIBIT The LTM4678 will three-state the output in response to the FAULT pin pulled low.
FAULT_IGNORE The LTM4678 continues operation without interruption.
0x00
The device also:
•
•
•
Sets the MFR Bit in the STATUS_WORD.
Sets Bit 0 in the STATUS_MFR_SPECIFIC Command to Indicate FAULTn Is Being Pulled Low
Notifies the Host by Asserting ALERT, Unless Masked
This command has one data byte.
SCRATCHPAD
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS
NVM
USER_DATA_00
0xB0
OEM reserved. Typically used for part
serialization.
R/W Word
N
Reg
Y
NA
USER_DATA_01
USER_DATA_02
0xB1
0xB2
Manufacturer reserved for LTpowerPlay.
R/W Word
R/W Word
Y
N
Reg
Reg
Y
Y
NA
NA
OEM reserved. Typically used for part
serialization.
USER_DATA_03
USER_DATA_04
0xB3
0xB4
A NVM word available for the user.
A NVM word available for the user.
R/W Word
R/W Word
Y
N
Reg
Reg
Y
Y
0x0000
0x0000
USER_DATA_00 through USER_DATA_04
These commands are non-volatile memory locations for customer storage. The customer has the option to write any
value to the USER_DATA_nn at any time. However, the LTpowerPlay software and contract manufacturers use some of
these commands for inventory control. Modifying the reserved USER_DATA_nn commands may lead to undesirable
inventory control and incompatibility with these products.
These commands have 2 data bytes and are in register format.
Rev 0
104
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LTM4678
PMBus COMMAND DETAILS
IDENTIFICATION
DATA
FORMAT UNITS
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED
NVM
PMBus_REVISION
0x98
PMBus revision supported by this device.
R Byte
N
Reg
Reg
FS
0x22
Current revision is 1.2.
CAPABILITY
0x19
Summary of PMBus optional communication
protocols supported by this device.
R Byte
N
0xB0
MFR_ID
0x99
0x9A
0xE7
The manufacturer ID of the LTM4678 in ASCII.
Manufacturer part number in ASCII.
R String
R String
R Word
N
N
N
ASC
ASC
Reg
LTC
MFR_MODEL
MFR_SPECIAL_ID
LTM4678
0x410x
Manufacturer code representing the LTM4678.
PMBus_REVISION
The PMBUS_REVISION command indicates the revision of the PMBus to which the device is compliant. The LTM4678
is PMBus Version 1.2 compliant in both Part I and Part II.
This read-only command has one data byte.
CAPABILITY
This command provides a way for a host system to determine some key capabilities of a PMBus device.
The LTM4678 supports packet error checking, 400kHz bus speeds, and ALERT pin.
This read-only command has one data byte.
MFR_ID
The MFR_ID command indicates the manufacturer ID of the LTM4678 using ASCII characters.
This read-only command is in block format.
MFR_MODEL
The MFR_MODEL command indicates the manufacturer’s part number of the LTM4678 using ASCII characters.
This read-only command is in block format.
MFR_SPECIAL_ID
The 16-bit word representing the part name and revision. 0x41 denotes the part is an LTM4678, XX is adjustable by
the manufacturer.
This read-only command has two data bytes.
Rev 0
105
For more information www.analog.com
LTM4678
PMBus COMMAND DETAILS
FAULT WARNING AND STATUS
DEFAULT
VALUE
NA
See CMD
Details
COMMAND NAME
CLEAR_FAULTS
SMBALERT_MASK
CMD CODE DESCRIPTION
TYPE
PAGED
N
Y
FORMAT UNITS
NVM
0x03
0x1B
Clear any fault bits that have been set. Send Byte
Mask activity.
Block R/W
Reg
Y
MFR_CLEAR_PEAKS
STATUS_BYTE
0xE3
0x78
Clears all peak values.
One byte summary of the unit’s fault
condition.
Two byte summary of the unit’s fault
condition.
Output voltage fault and warning
status.
Output current fault and warning
status.
Input supply fault and warning status.
External temperature fault and warning R/W Byte
status for READ_TEMERATURE_1.
Send Byte
R/W Byte
Y
Y
NA
NA
Reg
Reg
Reg
Reg
STATUS_WORD
STATUS_VOUT
STATUS_IOUT
0x79
0x7A
0x7B
R/W Word
R/W Byte
R/W Byte
R/W Byte
Y
Y
Y
NA
NA
NA
STATUS_INPUT
STATUS_ TEMPERATURE
0x7C
0x7D
N
Y
Reg
Reg
NA
NA
STATUS_CML
0x7E
0x80
Communication and memory fault and R/W Byte
warning status.
N
Y
Reg
Reg
NA
NA
STATUS_MFR_ SPECIFIC
Manufacturer specific fault and state
information.
R/W Byte
MFR_PADS
MFR_COMMON
0xE5
0xEF
Digital status of the I/O pads.
Manufacturer status bits that are
common across multiple ADI chips.
R Word
R Byte
N
N
Reg
Reg
NA
NA
CLEAR_FAULTS
The CLEAR_FAULTS command is used to clear any fault bits that have been set. This command clears all bits in all
status commands simultaneously. At the same time, the device negates (clears, releases) its ALERT pin signal output
if the device is asserting the ALERT pin signal. If the fault is still present when the bit is cleared, the fault bit will remain
set and the host notified by asserting the ALERT pin low. CLEAR_FAULTS can take up to 10µs to process. If a fault
occurs within that time frame it may be cleared before the status register is set.
This write-only command has no data bytes.
The CLEAR_FAULTS does not cause a unit that has latched off for a fault condition to restart. Units that have shut
down for a fault condition are restarted when:
• The output is commanded through the RUN pin, the OPERATION command, or the combined action of the RUN pin
and OPERATION command, to turn off and then to turn back on, or
• MFR_RESET command is issued.
• Bias power is removed and reapplied to the integrated circuit
SMBALERT_MASK
The SMBALERT_MASK command can be used to prevent a particular status bit or bits from asserting ALERT as they
are asserted.
Figure 33 shows an example of the Write Word format used to set an ALERT mask, in this case without PEC. The bits in
themaskbytealignwithbitsinthespecifiedstatusregister. Forexample, ifthe STATUS_TEMPERATUREcommandcode
is sent in the first data byte, and the mask byte contains 0x40, then a subsequent External Overtemperature Warning
Rev 0
106
For more information www.analog.com
LTM4678
PMBus COMMAND DETAILS
would still set bit 6 of STATUS_TEMPERATURE but not assert ALERT. All other supported STATUS_TEMPERATURE
bits would continue to assert ALERT if set.
Figure 50 shows an example of the Block Write – Block Read Process Call protocol used to read back the present state
of any supported status register, again without PEC.
SMBALERT_MASK cannot be applied to STATUS_BYTE, STATUS_WORD, MFR_COMMON or MFR_PADS_LTM4678.
Factory default masking for applicable status registers is shown below. Providing an unsupported command code to
SMBALERT_MASK will generate a CML for Invalid/Unsupported Data.
SMBALERT_MASK Default Setting: (Refer Also to Figure 2)
STATUS RESISTER
ALERT Mask Value MASKED BITS
STATUS_VOUT
0x00
0x00
0x00
0x00
0x00
0x11
None
STATUS_IOUT
None
STATUS_TEMPERATURE
STATUS_CML
None
None
STATUS_INPUT
None
STATUS_MFR_SPECIFIC
Bit 4 (internal PLL unlocked), bit 0 (FAULT pulled low by external device)
ꢁ
ꢓ
ꢁ
ꢁ
ꢔ
ꢁ
ꢔ
ꢁ
ꢔ
ꢁ
ꢁ
ꢂꢃꢄꢅꢆ
ꢄꢇꢇRꢆꢂꢂ
ꢂꢈꢉꢄꢃꢆRꢊꢋꢈꢄꢂꢌ
ꢍꢎꢈꢈꢄꢏꢇ ꢍꢎꢇꢆ
ꢂꢊꢄꢊꢐꢂꢋꢑ
ꢍꢎꢈꢈꢄꢏꢇ ꢍꢎꢇꢆ
ꢂ
ꢒ
ꢄ
ꢄ
ꢄ
ꢈꢄꢂꢌ ꢉꢕꢊꢆ
ꢄ
ꢀ
ꢖꢗꢓꢔ ꢘꢙꢚ
Figure 52. Example of Writing SMBALERT_MASK
ꢑ
ꢔ
ꢑ
ꢑ
ꢕ
ꢑ
ꢕ
ꢑ
ꢕ
ꢑ
ꢀꢁꢂꢃꢄ
ꢂꢅꢅRꢄꢀꢀ
ꢀꢆꢇꢂꢁꢄRꢈꢉꢆꢂꢀꢊ
ꢋꢌꢆꢆꢂꢍꢅ ꢋꢌꢅꢄ
ꢇꢁꢌꢋꢊ ꢋꢌꢎꢍꢈ
ꢏꢐ ꢑꢒ
ꢀꢈꢂꢈꢎꢀꢉꢖ
ꢋꢌꢆꢆꢂꢍꢅ ꢋꢌꢅꢄ
ꢀ
ꢓ
ꢂ
ꢂ
ꢂ
ꢂ
ꢗ
ꢑ
ꢔ
ꢑ
ꢑ
ꢕ
ꢑ
ꢕ
ꢑ
ꢑ
ꢀꢁꢂꢃꢄ
ꢂꢅꢅRꢄꢀꢀ
ꢇꢁꢌꢋꢊ ꢋꢌꢎꢍꢈ
ꢏꢐ ꢑꢒ
ꢀꢘ
R
ꢂ
ꢂ
ꢆꢂꢀꢊ ꢇꢟꢈꢄ
ꢍꢂ
ꢙ
ꢚꢛꢔꢕ ꢜꢝꢞ
Figure 53. Example of Reading SMBALERT_MASK
MFR_CLEAR_PEAKS
The MFR_CLEAR_PEAKS command clears the MFR_*_PEAK data values. A MFR_RESET command will also clear the
MFR_*_PEAK data values.
This write-only command has no data bytes.
STATUS_BYTE
The STATUS_BYTE command returns one byte of information with a summary of the most critical faults. This is the
lower byte of the status word.
Rev 0
107
For more information www.analog.com
LTM4678
PMBus COMMAND DETAILS
STATUS_BYTE Message Contents:
BIT
7*
6
STATUS BIT NAME MEANING
BUSY
OFF
A fault was declared because the LTM4678 was unable to respond.
This bit is set if the channel is not providing power to its output, regardless of the reason, including simply not being enabled.
An output overvoltage fault has occurred.
5
VOUT_OV
IOUT_OC
VIN_UV
4
An output overcurrent fault has occurred.
3
Not supported (LTM4678 returns 0).
2
TEMPERATURE
CML
A temperature fault or warning has occurred.
1
A communications, memory or logic fault has occurred.
0*
NONE OF THE ABOVE A fault Not listed in bits[7:1] has occurred.
*ALERT can be asserted if either of these bits is set. They may be cleared by writing a 1 to their bit position in the STATUS_BYTE, in lieu of a CLEAR_
FAULTS command.
This command has one data byte.
STATUS_WORD
The STATUS_WORD command returns a two-byte summary of the channel's fault condition. The low byte of the
STATUS_WORD is the same as the STATUS_BYTE command.
STATUS_WORD High Byte Message Contents:
BIT
15
14
13
12
11
10
9
STATUS BIT NAME
MEANING
V
An output voltage fault or warning has occurred.
An output current fault or warning has occurred.
An input voltage fault or warning has occurred.
A fault or warning specific to the LTM4678 has occurred.
The POWER_GOOD state is false if this bit is set.
Not supported (LTM4678 returns 0).
OUT
OUT
I
INPUT
MFR_SPECIFIC
POWER_GOOD#
FANS
OTHER
Not supported (LTM4678 returns 0).
8
UNKNOWN
Not supported (LTM4678 returns 0).
If any of the bits in the upper byte are set, NONE_OF_THE_ABOVE is asserted.
This command has two data bytes.
STATUS_VOUT
The STATUS_VOUT command returns one byte of V
status information.
OUT
STATUS_VOUT Message Contents:
BIT
MEANING
7
V
V
V
V
V
overvoltage fault.
overvoltage warning.
undervoltage warning.
undervoltage fault.
max warning.
OUT
OUT
OUT
OUT
OUT
6
5
4
3
2
TON max fault.
1
TOFF max fault.
0
Not supported (LTM4678 returns 0).
Rev 0
108
For more information www.analog.com
LTM4678
PMBus COMMAND DETAILS
The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear
status by means other than using the CLEAR_FAULTS command.
Any supported fault bit in this command will initiate an ALERT event.
This command has one data byte.
STATUS_IOUT
The STATUS_IOUT command returns one byte of I
status information.
OUT
STATUS_IOUT Message Contents:
BIT
MEANING
7
I
overcurrent fault.
OUT
6
Not supported (LTM4678 returns 0).
I overcurrent warning.
OUT
5
4:0
Not supported (LTM4678 returns 0).
The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear
status by means other than using the CLEAR_FAULTS command.
Any supported fault bit in this command will initiate an ALERT event. This command has one data byte.
STATUS_INPUT
The STATUS_INPUT command returns one byte of V (VINSNS) status information.
IN
STATUS_INPUT Message Contents:
BIT
MEANING
7
V
overvoltage fault.
IN
6
Not supported (LTM4678 returns 0).
V undervoltage warning.
IN
5
4
Not supported (LTM4678 returns 0).
3
Unit off for insufficient V .
IN
2
Not supported (LTM4678 returns 0).
1
I overcurrent warning.
IN
0
Not supported (LTM4678 returns 0).
The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear
status by means other than using the CLEAR_FAULTS command.
Any supported fault bit in this command will initiate an ALERT event. Bit 3 of this command is not latched and will not
generate an ALERT even if it is set. This command has one data byte.
Rev 0
109
For more information www.analog.com
LTM4678
PMBus COMMAND DETAILS
STATUS_TEMPERATURE
The STATUS_TEMPERATURE commands returns one byte with status information on temperature. This is a paged
command and is related to the respective READ_TEMPERATURE_1 value.
STATUS_TEMPERATURE Message Contents:
BIT
MEANING
7
External overtemperature fault.
External overtemperature warning.
Not supported (LTM4678 returns 0).
External undertemperature fault.
Not supported (LTM4678 returns 0).
6
5
4
3:0
.
The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear
status by means other than using the CLEAR_FAULTS command.
This command has one data byte.
STATUS_CML
The STATUS_CML command returns one byte of status information on received commands, internal memory and logic.
STATUS_CML Message Contents:
BIT
MEANING
7
Invalid or unsupported command received.
Invalid or unsupported data received.
Packet error check failed.
6
5
4
Memory fault detected.
3
Processor fault detected.
2
Reserved (LTM4678 returns 0).
Other communication fault.
Other memory or logic fault.
1
0
If either bit 3 or bit 4 of this command is set, a serious and significant internal error has been detected. Continued
operation of the part is not recommended if these bits are continuously set.
The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear
status by means other than using the CLEAR_FAULTS command.
Any supported fault bit in this command will initiate an ALERT event.
This command has one data byte.
Rev 0
110
For more information www.analog.com
LTM4678
PMBus COMMAND DETAILS
STATUS_MFR_SPECIFIC
The STATUS_MFR_SPECIFIC commands returns one byte with the manufacturer specific status information.
The format for this byte is:
BIT MEANING
7
6
5
4
3
2
1
0
Internal Temperature Fault Limit Exceeded.
Internal Temperature Warn Limit Exceeded.
Factory Trim Area NVM CRC Fault.
PLL is Unlocked
Fault Log Present
V
UV or OV Fault
DD33
ShortCycle Event Detected
FAULT Pin Asserted Low by External Device
If any of these bits are set, the MFR bit in the STATUS_WORD will be set, and ALERT may be asserted.
The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear
status by means other than using the CLEAR_FAULTS command. However, the fault log present bit can only be cleared
by issuing the MFR_FAULT_LOG_CLEAR command.
Any supported fault bit in this command will initiate an ALERT event.
This command has one data byte.
MFR_PADS
This command provides the user a means of directly reading the digital status of the I/O pins of the device. The bit
assignments of this command are as follows:
BIT ASSIGNED DIGITAL PIN
15
14
V
V
OV Fault
UV Fault
DD33
DD33
13 Reserved
12 Reserved
11 ADC Values Invalid, Occurs During Start-Up. May Occur Briefly on Current Measurement Channels During Normal Operation
10 SYNC clocked by external device (when LTM4678 configured to drive SYNC pin)
9
8
7
6
5
4
3
2
1
0
Channel 1 Power Good
Channel 0 Power Good
LTM4678 Driving RUN1 Low
LTM4678 Driving RUN0 Low
RUN1 Pin State
RUN0 Pin State
LTM4678 Driving FAULT1 Low
LTM4678 Driving FAULT0 Low
FAULT1 Pin State
FAULT0 Pin State
A 1 indicates the condition is true.
This read-only command has two data bytes.
Rev 0
111
For more information www.analog.com
LTM4678
PMBus COMMAND DETAILS
MFR_COMMON
The MFR_COMMON command contains bits that are common to all ADI digital power and telemetry products.
BIT
7
MEANING
Module Not Driving ALERT Low
LTM4678 Not Busy
Calculations Not Pending
LTM4678 Outputs Not in Transition
NVM Initialized
6
5
4
3
2
Reserved
1
SHARE_CLK Timeout
WP Pin Status
0
This read-only command has one data byte.
MFR_INFO
The MFR_INFO command contains additional status bits that are LTC3884-specific and may be common to multiple
ADI PSM products.
MFR_INFO Data Contents:
BIT
15:5
4
MEANING
Reserved.
EEPROM ECC status.
0: Corrections made in the EEPROM user space.
1: No corrections made in the EEPROM user space.
3:0
Reserved
EEPROM ECC status is updated after each RESTORE_USER_ALL or RESET command, a power-on reset or an EEPROM
bulk read operation. This read-only command has two data bytes.
TELEMETRY
CMD
DEFAULT
VALUE
COMMAND NAME
READ_VIN
READ_IIN
READ_VOUT
READ_IOUT
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS
NVM
0x88 Measured input supply voltage.
0x89 Measured input supply current.
0x8B Measured output voltage.
0x8C Measured output current.
0x8D Power stage temperature sensor. This is
the value used for all temperature related
processing, including MFR_IOUT_CAL_GAIN.
R Word
R Word
R Word
R Word
R Word
N
N
Y
Y
Y
L11
L11
L16
L11
L11
V
A
V
A
C
NA
NA
NA
NA
NA
READ_TEMPERATURE_1
READ_TEMPERATURE_2
0x8E Internal junction temperature. Does not affect
any other controller commands.
R Word
N
L11
C
NA
READ_FREQUENCY
READ_POUT
READ_PIN
0x95 Measured PWM switching frequency.
0x96 Calculated output power.
0x97 Calculated input power.
R Word
R Word
R Word
Y
Y
N
N
L11
L11
L11
Hz
W
W
%
NA
NA
NA
MFR_PIN_ACCURACY
0xAC Returns the accuracy of the READ_PIN command R Byte
5.0%
Rev 0
112
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LTM4678
PMBus COMMAND DETAILS
MFR_IOUT_PEAK
MFR_VOUT_PEAK
MFR_VIN_PEAK
0xD7 Report the maximum measured value of
R Word
R Word
R Word
R Word
Y
Y
N
Y
L11
L16
L11
L11
A
V
V
C
NA
NA
NA
NA
READ_IOUT since last MFR_CLEAR_PEAKS.
0xDD Maximum measured value of READ_VOUT
since last MFR_CLEAR_PEAKS.
0xDE Maximum measured value of READ_VIN since
last MFR_CLEAR_PEAKS.
MFR_TEMPERATURE_1_PEAK 0xDF Maximum measured value of external
Temperature (READ_TEMPERATURE_1) since
last MFR_CLEAR_PEAKS.
MFR_READ_IIN_PEAK
0xE1 Maximum measured value of READ_IIN
command since last MFR_CLEAR_PEAKS.
R Word
N
L11
A
NA
MFR_READ_ICHIP
0xE4 Measured current used by the LTM4678.
R Word
R Word
N
N
L11
L11
A
C
NA
NA
MFR_TEMPERATURE_2_PEAK 0xF4 Peak internal die temperature since last
MFR_CLEAR_PEAKS.
MFR_ADC_CONTROL
0xD8 ADC telemetry parameter selected for repeated R/W Byte
fast ADC read back.
N
N
Reg
NA
READ_VIN
The READ_VIN command returns the measured V pin voltage, in volts added to READ_ICHIP • MFR_RVIN. This
IN
compensates for the IR voltage drop across the V filter element due to the supply current of the LTM4678.
IN
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
READ_VOUT
The READ_VOUT command returns the measured output voltage by the VOUT_MODE command.
This read-only command has two data bytes and is formatted in Linear_16u format.
READ_IIN
The READ_IIN command returns the input current, in Amperes, as measured across the input current sense resistor
(see also MFR_IIN_CAL_GAIN).
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
READ_IOUT
The READ_IOUT command returns the average output current in amperes. The IOUT value is a function of:
a) the differential voltage measured across the I
b) the IOUT_CAL_GAIN value
pins
SENSE
c) the MFR_IOUT_CAL_GAIN_TC value, and
d) READ_TEMPERATURE_1 value
e) The MFR_TEMP_1_GAIN and the MFR_TEMP_1_OFFSET
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
READ_TEMPERATURE_1
The READ_TEMPERATURE_1 command returns the temperature, in degrees Celsius, of the power stage sense element.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
Rev 0
113
For more information www.analog.com
LTM4678
PMBus COMMAND DETAILS
READ_TEMPERATURE_2
The READ_TEMPERATURE_2 command returns the LTM4678’s die temperature, in degrees Celsius, of the internal
sense element.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
READ_FREQUENCY
The READ_FREQUENCY command is a reading of the PWM switching frequency in kHz.
This read-only command has 2 data bytes and is formatted in Linear_5s_11s format.
READ_POUT
The READ_POUT command is a reading of the DC/DC converter output power in Watts. POUT is calculated based on
the most recent correlated output voltage and current reading.
This read-only command has 2 data bytes and is formatted in Linear_5s_11s format.
READ_PIN
The READ_PIN command is a reading of the DC/DC converter input power in Watts. PIN is calculated based on the
most recent input voltage and current reading.
This read-only command has 2 data bytes and is formatted in Linear_5s_11s format.
MFR_PIN_ACCURACY
TheMFR_PIN_ACCURACYcommandreturnstheaccuracy,inpercent,ofthevaluereturnedbytheREAD_PINcommand.
There is one data byte. The value is 0.1% per bit which gives a range of 0.0% to 25.5%.
This read-only command has one data byte and is formatted as an unsigned integer.
MFR_IOUT_PEAK
The MFR_IOUT_PEAK command reports the highest current, in amperes, reported by the READ_IOUT measurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
MFR_VOUT_PEAK
The MFR_VOUT_PEAK command reports the highest voltage, in volts, reported by the READ_VOUT measurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_16u format.
MFR_VIN_PEAK
The MFR_VIN_PEAK command reports the highest voltage, in volts, reported by the READ_VIN measurement.
Rev 0
114
For more information www.analog.com
LTM4678
PMBus COMMAND DETAILS
This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
MFR_TEMPERATURE_1_PEAK
The MFR_TEMPERATURE_1_PEAK command reports the highest temperature, in degrees Celsius, reported by the
READ_TEMPERATURE_1 measurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
MFR_READ_IIN_PEAK
TheMFR_READ_IIN_PEAKcommandreportsthehighestcurrent, inAmperes, reportedbytheREAD_IINmeasurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This command has two data bytes and is formatted in Linear_5s_11s format.
MFR_READ_ICHIP
The MFR_READ_ICHIP command returns the measured input current, in Amperes, used by the LTM4678.
This command has two data bytes and is formatted in Linear_5s_11s format.
MFR_TEMPERATURE_2_PEAK
The MFR_TEMPERATURE_2_PEAK command reports the highest temperature, in degrees Celsius, reported by the
READ_TEMPERATURE_2 measurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
MFR_ADC_CONTROL
The MFR_ADC_CONTROL command determines the ADC read back selection. A default value of 0 in the command runs
the standard telemetry loop with all parameters updated in a round robin fashion with a typical latency of t
.
CONVERT
The user can command a non-zero value to monitored a single parameter with an approximate update rate of 8ms.
This command has a latency of up to 2 ADC conversions or approximately 16ms (external temperature conversions
may have a latency of up to 3 ADC conversion or approximately 24ms). It is recommended the part remain in standard
telemetry mode except for special cases where fast ADC updates of a single parameter is required. The part should be
commanded to monitor the desired parameter for a limited period of time (less then 1 second) then set the command
back to standard round robin mode. If this command is set to any value except standard round robin telemetry (0) all
warnings and faults associated with telemetry other than the selected parameter are effectively disabled and voltage
servoing is disabled. When round robin is reasserted, all warnings and faults and servo mode are re-enabled.
Rev 0
115
For more information www.analog.com
LTM4678
PMBus COMMAND DETAILS
COMMANDED VALUE
TELEMETRY COMMAND NAME
DESCRIPTION
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
Reserved
Reserved
Reserved
Channel 1 external temperature
Reserved
Channel 1 measured output current
Channel 1 measured output voltage
Channel 0 external temperature
Reserved
Channel 0 measured output current
Channel 0 measured output voltage
Internal junction temperature
Measured input supply current
READ_TEMPERATURE_1
READ_IOUT
READ_VOUT
READ_TEMPERATURE_1
READ_IOUT
READ_VOUT
READ_TEMPERATURE_2
READ_IIN
MFR_READ_ICHIP
Measured supply current of the
LTM4678
0x01
0x00
READ_VIN
Measured input supply voltage
Standard ADC Round Robin Telemetry
If a reserved command value is entered, the telemetry will default to Internal IC Temperature and issue a CML fault. CML
faults will continue to be issued by the LTM4678 until a valid command value is entered. The accuracy of the measured
input supply voltage is only guaranteed if the MFR_ADC_CONTROL command is set to standard round robin telemetry.
This write-only command has 1 data byte and is formatted in register format.
NVM MEMORY COMMANDS
Store/Restore
CMD
DEFAULT
VALUE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED
FORMAT
UNITS
NVM
STORE_USER_ALL
0x15
0x16
0xF0
Store user operating memory to
EEPROM.
Send Byte
N
NA
NA
NA
RESTORE_USER_ALL
Restore user operating memory from Send Byte
EEPROM.
N
N
MFR_COMPARE_USER_ALL
Compares current command contents Send Byte
with NVM.
STORE_USER_ALL
The STORE_USER_ALL command instructs the PMBus device to copy the non-volatile user contents of the Operating
Memory to the matching locations in the non-volatile User NVM memory.
Executing this command if the die temperature exceeds 85°C or is below 0°C is not recommended and the data reten-
tion of 10 years cannot be guaranteed. If the die temperature exceeds 130°C, the STORE_USER_ALL command is
disabled. The command is re-enabled when the IC temperature drops below 125°C.
Communication with the LTM4678 and programming of the NVM can be initiated when EXTV or VDD33 is available
CC
and VIN is not applied. To enable the part in this state, using global address 0x5B write MFR_EE_UNLOCK to 0x2B
followed by 0xC4. The LTM4678 will now communicate normally, and the project file can be updated. To write the
Rev 0
116
For more information www.analog.com
LTM4678
PMBus COMMAND DETAILS
updated project file to the NVM issue a STORE_USER_ALL command. When VIN is applied, a MFR_RESET must be
issued to allow the PWM to be enabled and valid ADCs to be read.
This write-only command has no data bytes.
RESTORE_USER_ALL
The RESTORE_USER_ALL command instructs the LTM4678 to copy the contents of the non-volatile User memory
to the matching locations in the Operating Memory. The values in the Operating Memory are overwritten by the value
retrieved from the User commands. The LTM4678 ensures both channels are off, loads the operating memory from
the internal EEPROM, clears all faults, reads the resistor configuration pins, and then performs a soft-start of both
PWM channels if applicable.
STORE_USER_ALL, MFR_COMPARE_USER_ALLandRESTORE_USER_ALLcommandsaredisabledifthedieexceeds
130°C and are not re-enabled until the die temperature drops below 125°C.
This write-only command has no data bytes.
MFR_COMPARE_USER_ALL
The MFR_COMPARE_USER_ALL command instructs the PMBus device to compare current command contents with
what is stored in non-volatile memory. If the compare operation detects differences, a CML bit 0 fault will be generated.
This write-only command has no data bytes.
Fault Logging
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
MFR_FAULT_LOG
0xEE
0xEA
Fault log data bytes.
R Block
N
N
CF
Y
NA
NA
MFR_FAULT_LOG_ STORE
Command a transfer of the fault log from RAM Send Byte
to EEPROM.
MFR_FAULT_LOG_CLEAR
0xEC
Initialize the EEPROM block reserved for fault
logging.
Send Byte
N
NA
MFR_FAULT_LOG
The MFR_FAULT_LOG command allows the user to read the contents of the FAULT_LOG after the first fault occur-
rence since the last MFR_FAULT_LOG_CLEAR command was written. The contents of this command are stored in
non-volatile memory, and are cleared by the MFR_FAULT_LOG_CLEAR command. The length and content of this
command are listed in Table 15. If the user accesses the MFR_FAULT_LOG command and no fault log is present, the
command will return a data length of 0. If a fault log is present, the MFR_FAULT_LOG will return a block of data 147
bytes long. If a fault occurs within the first second of applying power, some of the earlier pages in the fault log may
not contain valid data.
NOTE: The approximate transfer time for this command is 3.4ms using a 400kHz clock.
This read-only command is in block format.
Rev 0
117
For more information www.analog.com
LTM4678
PMBus COMMAND DETAILS
MFR_FAULT_LOG_STORE
The MFR_FAULT_LOG_STORE command forces the fault log operation to be written to NVM just as if a fault event
occurred. This command will set bit 3 of the STATUS_MFR_SPECIFIC fault if bit 7 “Enable Fault Logging” is set in
the MFR_CONFIG_ALL command.
If the die temperature exceeds 130°C, the MFR_FAULT_LOG_STORE command is disabled until the IC temperature
drops below 125°C.
This write-only command has no data bytes.
Table 20. Fault Logging
This table outlines the format of the block data from a read block data of the MFR_FAULT_LOG command.
Data Format Definitions
LIN 11 = PMBus = Rev 1.2, Part 2, section 7.1
LIN 16 = PMBus Rev 1.2, Part 2, section 8. Mantissa portion only
BYTE = 8 bits interpreted per definition of this command
DATA
FORMAT BYTE NUM BLOCK READ COMMAND
DATA
BITS
Block Length
BYTE
147
The MFR_FAULT_LOG command is a fixed length of 147 bytes
The block length will be zero if a data log event has not been captured
HEADER INFORMATION
Fault Log Preface
[7:0]
[7:0]
[15:8]
[7:0]
ASC
Reg
0
1
2
Returns LTxx beginning at byte 0 if a partial or complete fault log exists.
Word xx is a factory identifier that may vary part to part.
3
Fault Source
MFR_REAL_TIME
[7:0]
[7:0]
Reg
Reg
4
5
Refer to Table 16.
48 bit share-clock counter value when fault occurred (200µs resolution).
[15:8]
[23:16]
[31:24]
[39:32]
[47:40]
[15:8]
6
7
8
9
10
11
MFR_VOUT_PEAK (PAGE 0)
MFR_VOUT_PEAK (PAGE 1)
MFR_IOUT_PEAK (PAGE 0)
MFR_IOUT_PEAK (PAGE 1)
L16
L16
L11
L11
Peak READ_VOUT on Channel 0 since last power-on or CLEAR_PEAKS
command.
[7:0]
[15:8]
12
13
Peak READ_VOUT on Channel 1 since last power-on or CLEAR_PEAKS
command.
[7:0]
[15:8]
14
15
Peak READ_IOUT on Channel 0 since last power-on or CLEAR_PEAKS
command.
[7:0]
[15:8]
16
17
Peak READ_IOUT on Channel 1 since last power-on or CLEAR_PEAKS
command.
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
18
19
20
21
22
23
24
25
26
MFR_VIN_PEAK
L11
L11
L11
L11
Peak READ_VIN since last power-on or CLEAR_PEAKS command.
Power stage temperature sensor 0 during last event.
Power stage temperature sensor 1 during last event.
LTM4678 die temperature sensor during last event.
READ_TEMPERATURE1 (PAGE 0)
READ_TEMPERATURE1 (PAGE 1)
READ_TEMPERATURE2
Rev 0
118
For more information www.analog.com
LTM4678
PMBus COMMAND DETAILS
CYCLICAL DATA
EVENT n
Event “n” represents one complete cycle of ADC reads through the MUX
at time of fault. Example: If the fault occurs when the ADC is processing
step 15, it will continue to take readings through step 25 and then store
the header and all 6 event pages to EEPROM
(Data at Which Fault Occurred; Most Recent Data)
READ_VOUT (PAGE 0)
READ_VOUT (PAGE 1)
READ_IOUT (PAGE 0)
READ_IOUT (PAGE 1)
READ_VIN
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
LIN 16
LIN 16
LIN 16
LIN 16
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
BYTE
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
READ_IIN
STATUS_VOUT (PAGE 0)
STATUS_VOUT (PAGE 1)
STATUS_WORD (PAGE 0)
BYTE
[15:8]
[7:0]
[15:8]
[7:0]
WORD
WORD
WORD
WORD
BYTE
STATUS_WORD (PAGE 1)
STATUS_MFR_SPECIFIC (PAGE 0)
STATUS_MFR_SPECIFIC (PAGE 1)
BYTE
EVENT n-1
(data measured before fault was detected)
READ_VOUT (PAGE 0)
READ_VOUT (PAGE 1)
READ_IOUT (PAGE 0)
READ_IOUT (PAGE 1)
READ_VIN
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
LIN 16
LIN 16
LIN 16
LIN 16
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
BYTE
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
READ_IIN
STATUS_VOUT (PAGE 0)
STATUS_VOUT (PAGE 1)
STATUS_WORD (PAGE 0)
BYTE
[15:8]
[7:0]
[15:8]
[7:0]
WORD
WORD
WORD
WORD
BYTE
STATUS_WORD (PAGE 1)
STATUS_MFR_SPECIFIC (PAGE 0)
STATUS_MFR_SPECIFIC (PAGE 1)
BYTE
Rev 0
119
For more information www.analog.com
LTM4678
PMBus COMMAND DETAILS
EVENT n-5
(Oldest Recorded Data)
READ_VOUT (PAGE 0)
READ_VOUT (PAGE 1)
READ_IOUT (PAGE 0)
READ_IOUT (PAGE 1)
READ_VIN
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
LIN 16
LIN 16
LIN 16
LIN 16
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
BYTE
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
READ_IIN
STATUS_VOUT (PAGE 0)
STATUS_VOUT (PAGE 1)
STATUS_WORD (PAGE 0)
BYTE
[15:8]
[7:0]
[15:8]
[7:0]
WORD
WORD
WORD
WORD
BYTE
STATUS_WORD (PAGE 1)
STATUS_MFR_SPECIFIC (PAGE 0)
STATUS_MFR_SPECIFIC (PAGE 1)
BYTE
Table 21. Explanation of Position_Fault Values
POSITION_FAULT VALUE
SOURCE OF FAULT LOG
MFR_FAULT_LOG_STORE
TON_MAX_FAULT
VOUT_OV_FAULT
0xFF
0x00
0x01
0x02
0x03
0x05
0x06
0x07
0x0A
VOUT_UV_FAULT
IOUT_OC_FAULT
TEMP_OT_FAULT
TEMP_UT_FAULT
VIN_OV_FAULT
MFR_TEMP_2_OT_FAULT
MFR_INFO
Contact the factory for details.
MFR_IOUT_CAL_GAIN
Contact the factory for details.
Rev 0
120
For more information www.analog.com
LTM4678
PMBus COMMAND DETAILS
MFR_FAULT_LOG_CLEAR
The MFR_FAULT_LOG_CLEAR command will erase the fault log file stored values. It will also clear bit 3 in the
STATUS_MFR_SPECIFIC command. After a clear is issued, the status can take up to 8ms to clear.
This write-only command is send bytes.
Block Memory Write/Read
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS NVM
MFR_EE_UNLOCK
0xBD
0xBE
0xBF
Unlock user EEPROM for access by MFR_EE_ERASE
R/W Byte
N
N
N
Reg
Reg
Reg
NA
NA
NA
and MFR_EE_DATA commands.
MFR_EE_ERASE
MFR_EE_DATA
Initialize user EEPROM for bulk programming by
MFR_EE_DATA.
R/W Byte
Data transferred to and from EEPROM using
sequential PMBus word reads or writes. Supports bulk
programming.
R/W
Word
All the NVM commands are disabled if the die temperature exceeds 130°C. NVM commands are re-enabled when the
die temperature drops below 125°C.
MFR_EE_xxxx
The MFR_EE_xxxx commands facilitate bulk programming of the LTM4678 internal EEPROM. Contact the factory for
details.
Rev 0
121
For more information www.analog.com
LTM4678
PACKAGE DESCRIPTION
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
Table 22. LTM4678 BGA Pinout
PIN ID FUNCTION PIN ID
FUNCTION
GND
PIN ID
C1
FUNCTION
GND
PIN ID
D1
FUNCTION
SV
PIN ID
E1
FUNCTION
PIN ID FUNCTION
A1
A2
SW1
SW1
GND
GND
GND
GND
B1
B2
V
V
V
V
F1
F2
V
V
V
V
IN
IN1
IN1
IN1
IN1
IN1
IN1
IN1
IN1
SW1
C2
GND
D2
GND
GND
GND
GND
GND
E2
A3
B3
GND
C3
GND
D3
E3
F3
A4
B4
GND
C4
GND
D4
E4
F4
A5
B5
GND
C5
GND
D5
E5
GND
GND
F5
GND
GND
GND
A6
B6
GND
C6
GND
D6
E6
F6
A7
V
B7
V
V
V
V
V
V
C7
V
OUT1
V
OUT1
V
OUT1
D7
V
OUT1
E7
INTV
F7
OUT1
OUT1
OUT1
OUT1
OUT1
OUT1
OUT1
OUT1
OUT1
OUT1
CC
DD33
A8
V
V
V
B8
C8
D8
TSNS1b
E8
V
F8
EXTV
CC
A9
B9
C9
D9
PGOOD1
COMP1a
E9
FSWPH_CFG
VTRIM1_CFG
VOUT0_CFG
VOUT1_CFG
F9
SGND
SGND
RUN1
ASEL
A10
A11
A12
B10
B11
B12
C10
C11
C12
COMP1b
WP
D10
D11
D12
E10
E11
E12
F10
F11
F12
+
–
V
V
SHARE_CLK
OSNS1
OSNS1
VTRIM0_CFG
V
DD25
PIN ID FUNCTION PIN ID
FUNCTION
PIN ID
J1
FUNCTION
PIN ID
K1
FUNCTION
PIN ID
L1
FUNCTION
GND
PIN ID FUNCTION
+
G1
G2
V
V
V
V
H1
H2
V
V
V
V
I
I
IN
M1
M2
SW0
SW0
GND
GND
GND
GND
IN0
IN0
IN0
IN0
IN0
IN0
IN0
IN0
IN
J2
GND
GND
K2
GND
GND
GND
GND
GND
L2
SW0
G3
H3
J3
K3
L3
GND
M3
G4
H4
J4
GND
K4
L4
GND
M4
G5
GND
GND
H5
GND
GND
J5
GND
K5
L5
GND
M5
G6
H6
J6
GND
K6
L6
GND
M6
G7
GND
H7
GND
J7
PGOOD0
TSNS0b
COMP0a
TSNS1a
TSNS0a
SCL
K7
V
L7
V
OUT0
V
OUT0
V
OUT0
V
OUT0
V
OUT0
V
OUT0
M7
V
OUT0
OUT0
OUT0
OUT0
OUT0
OUT0
OUT0
OUT0
OUT0
G8
GND
H8
GND
J8
K8
V
V
V
V
L8
M8
V
V
V
G9
SGND
SGND
FAULT1
RUN0
H9
COMP0b
SDA
J9
K9
L9
M9
G10
G11
G12
H10
H11
H12
J10
J11
J12
K10
K11
K12
L10
L11
L12
M10
M11
M12
+
–
ALERT
FAULT0
V
V
OSNS0
OSNS0
SYNC
Rev 0
122
For more information www.analog.com
LTM4678
PACKAGE DESCRIPTION
ꢜ
ꢜ
ꢜ
ꢝ ꢝ ꢞ ꢞ ꢞ
ꢜ
ꢢꢢꢢ
ꢜ
ꢥ ꢤ ꢦ ꢗ ꢕ 0
ꢕ ꢤ ꢧ ꢘ ꢕ 0
ꢙ ꢤ ꢙ ꢙ ꢕ 0
ꢠ ꢤ ꢘ ꢧ ꢕ 0
ꢘ ꢤ ꢦ 0 ꢕ 0
0 ꢤ ꢥ ꢠ ꢕ 0
0 ꢤ 0 0 0 0
0 ꢤ ꢥ ꢠ ꢕ 0
ꢘ ꢤ ꢦ 0 ꢕ 0
ꢠ ꢤ ꢘ ꢧ ꢕ 0
ꢙ ꢤ ꢙ ꢙ ꢕ 0
ꢕ ꢤ ꢧ ꢘ ꢕ 0
ꢥ ꢤ ꢦ ꢗ ꢕ 0
Rev 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
123
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
LTM4678
PACKAGE PHOTOGRAPH
DESIGN RESOURCES
SUBJECT
DESCRIPTION
Design:
• Selector Guides
µModule Design and Manufacturing Resources
Manufacturing:
• Quick Start Guide
• PCB Design, Assembly and Manufacturing Guidelines
• Package and Board Level Reliability
• Demo Boards and Gerber Files
• Free Simulation Tools
µModule Regulator Products Search
1. Sort table of products by parameters and download the result as a spread sheet.
2. Search using the Quick Power Search parametric table.
TechClip Videos
Quick videos detailing how to bench test electrical and thermal performance of µModule products.
Digital Power System Management
Analog Devices’ family of digital power supply management ICs are highly integrated solutions that
offer essential functions, including power supply monitoring, supervision, margining and sequencing,
and feature EEPROM for storing user configurations and fault logging.
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PART NUMBER
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DESCRIPTION
COMMENTS
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Dual 13A or Single 26A
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Same Power as the LTM4677 but without Digital Power
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LTM4620/LTM4620A
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10A, 10A, 10A
IN
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IN
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Dual 9A or Single 18A, 11.9mm × 16mm × 3.5mm
Dual 25A or Single 50A
LTM4650/LTM4650-1 More Current Up to 50A µModule Regulator
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Dual 18A or Single 36A with PSM
4.5V ≤ V ≤ 16V, 0.5V ≤ V
≤ 1.8V
OUT
IN
Rev 0
D16884-0-5/18(0)
www.analog.com
124
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