LTC7802HUFDM [ADI]
40V Low IQ, 3MHz Dual, 2-Phase Synchronous Step-Down Controller with Spread Spectrum;
| 型号： | LTC7802HUFDM |
| 厂家： | 
ADI |
| 描述： | 40V Low IQ, 3MHz Dual, 2-Phase Synchronous Step-Down Controller with Spread Spectrum |
| 文件： | 总34页 (文件大小：2990K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC7802
40V Low I , 3MHz Dual, 2-Phase Synchronous
Q
Step-Down Controller with Spread Spectrum
FEATURES
DESCRIPTION
The LTC®7802 is a high performance dual step-down
synchronous DC/DC switching regulator controller that
drives all N-channel power MOSFET stages. Constant fre-
quency current mode architecture allows a phase-lockable
switching frequency of up to 3MHz. The LTC7802 oper-
ates from a wide 4.5V to 40V input supply range. Power
loss and supply noise are minimized by operating the two
controller output stages out-of-phase.
n
Wide Input Voltage Range: 4.5V to 40V
n
n
n
n
n
Wide Output Voltage Range: 0.8V to 99% • V
IN
Low Operating I : 14μA (14V to 3.3V, Channel 1 On)
Q
Spread Spectrum Operation
R
SENSE
or DCR Current Sensing
Out-of-Phase Controllers Reduce Required Input
Capacitance and Power Supply Induced Noise
Programmable Fixed Frequency (100kHz to 3MHz)
Phase-Lockable Frequency (100kHz to 3MHz)
Selectable Continuous, Pulse-Skipping, or Low
Ripple, Burst Mode® Operation at Light Loads
Very Low Dropout Operation: 99% Duty Cycle
Power Good Output Voltage Monitors
n
n
n
The very low no-load quiescent current extends oper-
ating runtime in battery powered systems. OPTI-LOOP
compensation allows the transient response to be opti-
mized over a wide range of output capacitance and ESR
values. The LTC7802 features a precision 0.8V reference
and power good output indicators. The MODE pin selects
among Burst Mode operation, pulse-skipping mode, or
continuous inductor current mode at light loads.
n
n
n
n
n
n
Output Overvoltage Protection
Internal LDO Powers Gate Drive from V or EXTV
Low Shutdown I : 1.5μA
Small 28-Lead 4mm × 5mm QFN Package
IN
CC
Q
The LTC7802 additionally features spread spectrum oper
-
ation which significantly reduces the peak radiated and
conducted noise on both the input and output supplies,
making it easier to comply with electromagnetic interfer-
ence (EMI) standards.
APPLICATIONS
n
Automotive and Transportation
n
Industrial
All registered trademarks and trademarks are the property of their respective owners.
n
Military/Avionics
TYPICAL APPLICATION
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Rev. 0
1
Document Feedback
For more information www.analog.com
LTC7802
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
Input Supply Voltage (V )......................... –0.3V to 40V
IN
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BOOST1, BOOST2...................................... –0.3V to 46V
Switch Voltage (SW1, SW2).......................... –5V to 40V
RUN1, RUN2 Voltages................................ –0.3V to 40V
EXTV Voltage ......................................... –0.3V to 30V
CC
ꢏꢐ ꢏꢨ ꢏꢥ ꢏꢖ ꢏꢔ ꢏꢡ
ꢦ
INTV Voltage ............................................ –0.3V to 6V
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CC
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(BOOST1–SW1), (BOOST2–SW2)................ –0.3V to 6V
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+
+
–
–
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Rꢇꢚꢞ
Rꢇꢚꢏ
SENSE1 , SENSE1 Voltages...................... –0.3V to 40V
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SENSE2 , SENSE2 Voltages ..................... –0.3V to 40V
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TRACK/SS1, V Voltages .......................... –0.3V to 6V
FB1
FB2
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TRACK/SS2, V Voltages.......................... –0.3V to 6V
ꢧ
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MODE, PGOOD1, PGOOD2 Voltages ............ –0.3V to 6V
PLLIN/SPREAD, FREQ Voltages................... –0.3V to 6V
ITH1, ITH2 Voltages ..................................... –0.3V to 2V
BG1, BG2, TG1, TG2...........................................(Note 9)
Operating Junction Temperature Range (Notes 2, 8)
LTC7802E, LTC7802I ......................... –40°C to 125°C
LTC7802J, LTC7802H........................ –40°C to 150°C
Storage Temperature Range .................. –65°C to 150°C
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ꢞ0 ꢞꢞ ꢞꢏ ꢞꢡ ꢞꢔ
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ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC7802EUFDM#PBF
AUTOMOTIVE PRODUCTS**
LTC7802IUFDM#WPBF
LTC7802JUFDM#WPBF
LTC7802HUFDM#WPBF
LTC7802EUFDM#TRPBF
7802
28-Lead (4mm × 5mm) Plastic QFN
−40°C to 125°C
LTC7802IUFDM#WTRPBF 7802
LTC7802JUFDM#WTRPBF 7802
LTC7802HUFDM#WTRPBF 7802
28-Lead (4mm × 5mm) Plastic QFN
28-Lead (4mm × 5mm) Plastic QFN
28-Lead (4mm × 5mm) Plastic QFN
−40°C to 125°C
−40°C to 150°C
−40°C to 150°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These
models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your
local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for
these models.
Rev. 0
2
For more information www.analog.com
LTC7802
ELECTRICAL CHARACTERISTICS The ldenotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VIN = 12V, RUN1,2 > 1.25V, EXTVCC = 0V, unless otherwise noted. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Input Supply (V )
IN
V
Input Supply Operating Range
Current in Regulation
4.5
40
V
IN
I
V
Front Page Circuit, 14V to 3.3V,
No Load, RUN2 = 0V
14
µA
VIN
IN
Controller Operation
V
V
Output Voltage Operating Range
Regulated Feedback Voltage
0.8
40
V
OUT1,2
FB1,2
(Note 4) V = 4.5V to 40V,
IN
l
ITH1,2 Voltage = 0.6V to 1.2V
0°C to 85°C, All Grades
0.788
0.792
0.800
0.800
0.812
0.808
V
V
Feedback Current
5
50
13
nA
%
Feedback Overvoltage Protection Threshold
Measured at V
Relative to
7
10
FB1,2
FB1,2
Regulated V
g
Transconductance Amplifier g
(Note 4) ITH1,2 = 1.2V, Sink/Source = 5μA
1.8
50
0
mmho
mV
m1,2
m
–
l
V
Maximum Current Sense Threshold
V
V
V
V
= 0.7V, V
= 3.3V
45
55
3.5
1
SENSE(MAX)
FB1,2
SENSE1,2
–
Matching Between Channels
= 3.3V
–3.5
mV
SENSE1,2
SENSE1,2
+
+
+
I
I
SENSE1, 2 Pin Current
= 3.3V
µA
SENSE1,2
–
–
–
SENSE1 Pin Current
≤ 2.8V
1
µA
µA
µA
SENSE1
SENSE1
–
3.2V ≤ V
< INTV – 0.5V
50
SENSE1
CC
–
V
> INTV + 0.5V
700
SENSE1
CC
–
–
–
–
I
SENSE2 Pin Current
V
V
= 3.3V
2
µA
µA
SENSE2
SENSE2
SENSE2
> INTV + 0.5V
650
12.5
1.20
100
CC
Soft-Start Charge Current
RUN Pin ON Threshold
RUN Pin Hysteresis
V
V
= 0V
10
15
µA
V
TRACK/SS1,2
l
Rising
1.15
1.25
RUN1,2
mV
DC Supply Current (Note 5)
V
V
Shutdown Current
Sleep Mode Current
RUN1,2 = 0V
1.5
µA
IN
IN
–
V
< 3.2V, EXTV = 0V
CC
SENSE1
One Channel On
15
18
24
30
µA
µA
Both Channels On
–
Sleep Mode Current (Note 3)
Only Channel 1 On
V
V
V
≥ 3.2V
SENSE1
IN
IN
Current, EXTV = 0V
5
1
9
4
10
18
µA
µA
µA
µA
CC
CC
Current, EXTV ≥ 4.8V
EXTV Current, EXTV ≥ 4.8V
5
CC
CC
–
SENSE1 Current
10
–
Sleep Mode Current (Note 3)
Both Channels On
V
V
≥ 3.2V, EXTV ≥ 4.8V
SENSE1
IN
CC
Current
1
7
12
4
14
22
µA
µA
µA
EXTV Current
CC
–
SENSE1 Current
Pulse-Skipping or Forced Continuous Mode
One Channel On
Both Channels On
2
3
mA
mA
V
or EXTV Current (Note 3)
IN
CC
Rev. 0
3
For more information www.analog.com
LTC7802
ELECTRICAL CHARACTERISTICS The ldenotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VIN = 12V, RUN1,2 > 1.25V, EXTVCC = 0V, unless otherwise noted. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Gate Drivers
TG or BG On-Resistance
Pull-Up
Pull-Down
2.0
1.0
Ω
Ω
TG or BG Transition Time
Rise Time
Fall Time
(Note 6)
LOAD
LOAD
C
C
= 3300pF
= 3300pF
25
15
ns
ns
TG Off to BG On Delay
Synchronous Switch-On Delay Time
C
LOAD
= 3300pF Each Driver
15
ns
BG Off to TG On Delay
Top Switch-On Delay Time
C
LOAD
= 3300pF Each Driver
15
ns
t
TG Minimum On-Time
(Note 7)
40
99
ns
%
ON(MIN)1,2
Maximum Duty Factor for TG
f
= 350kHz
98
OSC
INTV Low Dropout (LDO) Linear Regulator
CC
INTV Regulation Point
4.9
5.1
5.3
V
CC
INTV Load Regulation
I
I
= 0mA to 100mA, V ≥ 6V
1.2
1.2
2
2
%
%
CC
CC
CC
IN
= 0mA to 100mA, V
≥ 6V
EXTVCC
EXTV LDO Switchover Voltage
EXTV Rising
4.5
4.7
4.8
V
CC
CC
EXTV Switchover Hysteresis
250
mV
CC
l
l
UVLO
Undervoltage Lockout
INTV Rising
4.10
3.75
4.20
3.85
4.35
4.00
V
V
CC
INTV Falling
CC
Spread Spectrum Oscillator and Phase-Locked Loop
f
Low Fixed Frequency
High Fixed Frequency
Programmable Frequency
V
V
= 0V, PLLIN/SPREAD = 0V
320
2.0
350
380
2.5
kHz
OSC
FREQ
FREQ
l
= INTV , PLLIN/SPREAD = 0V
2.25
MHz
CC
R
R
R
= 374kΩ, PLLIN/SPREAD = 0V
= 75kΩ, PLLIN/SPREAD = 0V
= 12.1kΩ, PLLIN/SPREAD = 0V
100
500
3
kHz
kHz
MHz
FREQ
FREQ
FREQ
450
550
3
l
Synchronizable Frequency Range
PLLIN/SPREAD = External Clock
0.1
2.2
MHz
l
l
PLLIN Input High Level
PLLIN Input Low Level
V
V
0.5
Spread Spectrum Frequency Range
PLLIN/SPREAD = INTV
Minimum Frequency
Maximum Frequency
CC
(Relative to f
)
–12
15
%
%
OSC
PGOOD1 and PGOOD2 Outputs
PGOOD Voltage Low
PGOOD Leakage Current
PGOOD Trip Level
I
= 2mA
= 5V
0.2
0.4
1
V
PGOOD1,2
V
µA
PGOOD1,2
V
Rising
7
10
2.5
13
%
%
FB
V
Relative to Set Regulation Point
Hysteresis
FB
V
Falling
–13
–10
2.5
–7
%
%
FB
Hysteresis
PGOOD Delay for Reporting a Fault
25
µs
Rev. 0
4
For more information www.analog.com
LTC7802
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
lowest output voltage greater than 3.2V and connect EXTV to the lowest
output voltage greater than 4.8V
CC
Note 4: The LTC7802 is tested in a feedback loop that servos V
to a
ITH1,2
specified voltage and measures the resultant V . The specification at
FB1,2
Note 2: The LTC7802 is tested under pulsed load conditions such that T ≈
85°C is not tested in production and is assured by design, characterization
and correlation to production testing at other temperatures (125°C for the
LTC7802E/LTC7802I, 150°C for the LTC7802J/LTC7802H).
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.
Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 7: The minimum on-time condition is specified for an inductor
J
T . The LTC7802E is guaranteed to meet specifications from 0°C to 85°C
A
junction temperature. Specifications over the –40°C to 125°C operating
junction temperature range are assured by design, characterization and
correlation with statistical process controls. The LTC7802I is guaranteed
over the –40°C to 125°C operating junction temperature range, and the
LTC7802J/LTC7802H are guaranteed over the –40°C to 150°C operating
junction temperature range. High junction temperatures degrade operating
lifetimes; operating lifetime is derated for junction temperatures greater
than 125°C. Note that the maximum ambient temperature consistent
with these specifications is determined by specific operating conditions
in conjunction with board layout, the rated package thermal impedance
peak-to-peak ripple current >40% of I
(See Minimum On-Time
L(MAX)
Considerations in the Applications Information section).
Note 8: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. The maximum
rated junction temperature will be exceeded when this protection is active.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability or permanently damage
the device.
Note 9: Do not apply a voltage or current source to these pins. They must
be connected to capacitive loads only, otherwise permanent damage
may occur.
and other environmental factors. The junction temperature (T , in °C) is
J
calculated from the ambient temperature (T , in °C) and power dissipation
A
(P , in Watts) according to the formula: T = T + (P • θ ), where θ (in
D
J
A
D
JA
JA
°C/W) is the package thermal impedance.
–
Note 3: When SENSE1 ≥ 3.2V or EXTV ≥ 4.8V, V supply current
CC
IN
is transferred to these pins to reduce the total input supply quiescent
–
current. SENSE1 bias current is reflected to the channel 1 input supply by
the formula I
= I
– • V
/(V • η), where η is the efficiency.
OUT1 IN1
VIN1
SENSE1
EXTV bias current is similarly reflected to the input supply when biased
CC
by an output. To minimize input supply current, select channel 1 to be the
Rev. 0
5
For more information www.analog.com
LTC7802
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency and Power Loss
vs Load Current
Efficiency vs Load Current
Efficiency vs Input Voltage
ꢀ00
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
0
ꢀ00
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ꢀ0
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ꢀꢁꢂꢃRꢄ ꢅ ꢆꢁRꢆꢃꢁꢇ
ꢀ
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ꢀ ꢁꢂ
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0.ꢀ
0.0ꢀ
0.00ꢀ
ꢀꢁRꢂꢃ
ꢀꢁꢂꢂ
ꢀꢁꢂꢃꢄꢅꢃꢆꢇꢀꢀꢇꢈꢉ
ꢀꢁꢂꢂ
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ꢀ
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ꢀ ꢁꢂꢃ
ꢀ ꢁꢂꢃ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀ ꢁꢂꢃ
ꢀ ꢁꢂ
ꢀꢁ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂꢃRꢄ ꢅ ꢆꢁRꢆꢃꢁꢇ
ꢀꢁꢂꢃꢄ ꢅꢆꢇe ꢈꢉꢊRꢋꢌꢍꢈꢎ
ꢀꢁꢂꢃRꢄ ꢅ ꢆꢁRꢆꢃꢁꢇ
0.000ꢀ 0.00ꢀ
0.0ꢀ
0.ꢀ ꢀ0
ꢀ
0
ꢀ
ꢀ0 ꢀꢁ ꢀ0 ꢀꢁ ꢀ0 ꢀꢁ ꢀ0
0.000ꢀ 0.00ꢀ
0.0ꢀ
0.ꢀ
ꢀ
ꢀ0
ꢀꢁꢂꢃꢁꢂ ꢄꢁRRꢅꢆꢂ ꢇꢈꢉ
ꢀꢁꢂꢃꢄ ꢅꢆꢇꢄꢈꢉꢊ ꢋꢅꢌ
ꢀꢁꢂꢃꢁꢂ ꢄꢁRRꢅꢆꢂ ꢇꢈꢉ
ꢀꢁ0ꢂ ꢃ0ꢄ
ꢀꢁ0ꢂ ꢃ0ꢄ
ꢀꢁ0ꢂ ꢃ0ꢂ
Load Step Forced
Continuous Mode
Load Step Burst Mode Operation
Load Step Pulse-Skipping Mode
ꢀ
ꢀ
ꢁꢂꢃ
ꢁꢂꢃ
ꢀ
ꢁꢂꢃ
ꢄ00ꢅꢀꢆꢇꢈꢀ
ꢄ00ꢅꢀꢆꢇꢈꢀ
ꢄ00ꢅꢀꢆꢇꢈꢀ
ꢀꢁꢂꢃꢄꢅꢆR
ꢄꢃRRꢇꢁꢅ
ꢈꢉꢊꢂꢀꢋ
ꢀꢁꢂꢃꢄꢅꢆR
ꢄꢃRRꢇꢁꢅ
ꢈꢉꢊꢂꢀꢋ
ꢀꢁꢂꢃꢄꢅꢆR
ꢄꢃRRꢇꢁꢅ
ꢈꢉꢊꢂꢀꢋ
ꢀꢁꢂꢃ
ꢄꢅRRꢆꢇꢈ
ꢉꢂꢊꢃꢋꢌ
ꢀꢁꢂꢃ
ꢄꢅRRꢆꢇꢈ
ꢉꢂꢊꢃꢋꢌ
ꢀꢁꢂꢃ
ꢄꢅRRꢆꢇꢈ
ꢉꢂꢊꢃꢋꢌ
ꢀꢁ0ꢂ ꢃ0ꢄ
ꢀꢁ0ꢂ ꢃ0ꢄ
ꢀꢁ0ꢂ ꢃ0ꢄ
ꢀ0ꢁꢂꢃꢄꢅꢆ
ꢀ0ꢁꢂꢃꢄꢅꢆ
ꢀ0ꢁꢂꢃꢄꢅꢆ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢁꢂ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀ ꢁꢂ
ꢀ
ꢀ ꢁꢂ
ꢀ
ꢀ ꢁꢂ
ꢀ00ꢁꢂ ꢃꢄ ꢅꢂ ꢆꢄꢂꢇ ꢈꢃꢉꢊ
ꢀ00ꢁꢂ ꢃꢄ ꢅꢂ ꢆꢄꢂꢇ ꢈꢃꢉꢊ
ꢀ00ꢁꢂ ꢃꢄ ꢅꢂ ꢆꢄꢂꢇ ꢈꢃꢉꢊ
ꢀꢁꢂꢃRꢄ ꢅ ꢆꢁRꢆꢃꢁꢇ
ꢀꢁꢂꢃRꢄ ꢅ ꢆꢁRꢆꢃꢁꢇ
ꢀꢁꢂꢃRꢄ ꢅ ꢆꢁRꢆꢃꢁꢇ
Regulated Feedback Voltage
vs Temperature
Inductor Current at Light Load
Soft Start-Up
ꢀ0ꢀ
ꢀ0ꢁ
ꢀ0ꢁ
ꢀ0ꢁ
ꢀ00
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁRꢂꢃꢄ
ꢂꢁꢅꢆꢇꢅꢈꢁꢈꢉ
ꢊꢁꢄꢃ
Rꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄꢁ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄꢁ
ꢀꢁꢂꢃꢄ ꢅꢆꢇe
ꢈꢉꢊRꢋꢌꢍꢈꢎ
ꢏꢋꢐꢑꢍꢒ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄꢁ
ꢀꢁꢂꢃꢄ
ꢃꢅꢆꢀꢀꢆꢇꢈ
ꢉꢊꢋꢄ
ꢀꢁ0ꢂ ꢃ0ꢀ
ꢀꢁ0ꢂ ꢃ0ꢁ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀ
ꢀ ꢁ0ꢂ
ꢀꢁꢂ
ꢀꢁ
ꢀ
ꢀ ꢁ0ꢂ
ꢀꢁ
ꢀ
ꢀ ꢁꢂ
ꢀꢁꢂꢃRꢄ ꢅ ꢆꢁRꢆꢃꢁꢇ
ꢀꢁ ꢂꢁꢃꢄ
ꢀꢁꢁ ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ ꢀꢁꢂ ꢀꢁꢁ
ꢀꢁꢂꢃRꢄ ꢅ ꢆꢁRꢆꢃꢁꢇ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢀꢀꢁ
ꢀꢁ0ꢂ ꢃ0ꢄ
Rev. 0
6
For more information www.analog.com
LTC7802
TYPICAL PERFORMANCE CHARACTERISTICS
Current Sense Threshold
vs ITH Voltage
SENSE1,2– Input Current
vs VSENSE Voltage
SENSE1,2+ Input Current
vs VSENSE Voltage
ꢀ0
ꢀ0
ꢀ00
ꢀ00
ꢀ00
ꢀ00
ꢀ00
ꢀ00
ꢀ00
ꢀ00
ꢀ00
0
ꢀ.0
0.ꢀ
ꢀꢁꢂꢃꢄꢅꢃꢆꢇꢀꢀꢇꢈꢉ
ꢀꢁꢂꢃꢄ ꢅꢆꢇe ꢈꢉꢊRꢋꢌꢍꢈꢎ
ꢀꢁRꢂꢃꢄ ꢂꢁꢅꢆꢇꢅꢈꢁꢈꢉ
ꢀꢁꢂꢃ ꢄ ꢅꢆꢇꢈ
ꢀꢁꢂꢃ ꢄ ꢅꢆꢇꢈ
ꢀꢀ
ꢀꢀ
ꢀ
ꢀꢁꢂꢀꢁꢃ ꢀꢁRRꢂꢃꢄ
0.ꢀ
ꢀ0
0.ꢀ
ꢀ
ꢀꢁꢂꢀꢁꢃ ꢀꢁRRꢂꢃꢄ
ꢀ0
0.ꢀ
ꢀ0
0.0
0
ꢀ0.ꢁ
ꢀ0.ꢁ
ꢀ0.ꢁ
ꢀ0.ꢁ
ꢀꢁ.0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
0
0.ꢀ 0.ꢀ 0.ꢀ 0.ꢀ ꢀ.0 ꢀ.ꢁ ꢀ.ꢁ
0
ꢀ
ꢀ0 ꢀꢁ ꢀ0 ꢀꢁ ꢀ0 ꢀꢁ ꢀ0
0
ꢀ
ꢀ0 ꢀꢁ ꢀ0 ꢀꢁ ꢀ0 ꢀꢁ ꢀ0
ꢀꢁꢂ ꢃꢄꢅꢁꢆꢇꢈ ꢉꢃꢊ
ꢀ
ꢀ
ꢀꢁ0ꢂ ꢃꢄ0
ꢀꢁꢂꢀꢁ ꢀꢁꢂꢃꢄꢅꢆ ꢇꢀꢈ
ꢀꢁ0ꢂ ꢃꢄꢄ
ꢀꢁꢂꢀꢁ ꢀꢁꢂꢃꢄꢅꢆ ꢇꢀꢈ
ꢀꢁ0ꢂ ꢃꢄꢂ
SENSE1,2– Input Current
vs Temperature
SENSE1,2+ Input Current
vs Temperature
Foldback Current Limit
ꢀ00
ꢀ00
ꢀ00
ꢀ00
ꢀ00
ꢀ00
ꢀ00
ꢀ00
ꢀ00
0
ꢀ.0
0.ꢀ
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
0
ꢀꢁꢂꢃ ꢄ ꢅꢆꢇꢈ
ꢀꢁꢂꢃ ꢄ ꢅꢆꢇꢈ
ꢀꢀ
ꢀꢀ
ꢀ
ꢀꢁꢂꢀꢁꢃꢄꢅ ꢀ ꢁꢂꢃꢄ ꢀ0.ꢁꢂ
ꢀꢀ
0.ꢀ
ꢀ
ꢀꢁꢂꢀꢁ ꢀ ꢁꢂꢃ
0.ꢀ
0.ꢀ
ꢀ
ꢀꢁꢂꢀꢁ ꢀ ꢁ.ꢁꢂ
0.0
ꢀ
ꢀꢁꢂꢀꢁ ꢀ ꢁꢂ
ꢀ0.ꢁ
ꢀ0.ꢁ
ꢀ0.ꢁ
ꢀ0.ꢁ
ꢀꢁ.0
ꢀ
ꢀꢁꢂꢀꢁ ꢀ 0ꢁ
ꢀ
ꢀꢁꢂꢀꢁꢃ ꢀ ꢁꢂꢃꢄ ꢀ0.ꢁꢂ
ꢀꢀ
ꢀ
ꢀꢁꢂꢀꢁꢃ ꢀ ꢁꢂꢃꢄ ꢀ0.ꢁꢂ
ꢀꢀ
ꢀꢁ00
ꢀꢁꢁ ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ ꢀꢁꢂ ꢀꢁꢁ
ꢀꢁꢁ ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ ꢀꢁꢂ ꢀꢁꢁ
0
ꢀ00 ꢀ00 ꢀ00 ꢀ00 ꢀ00 ꢀ00 ꢀ00 ꢀ00
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢀꢀꢁ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢀꢀꢁ
ꢀꢁꢁꢂꢃꢄꢅꢆ ꢇꢈꢉꢊꢄꢋꢁ ꢌꢍꢇꢎ
ꢀꢁ0ꢂ ꢃꢄꢅ
ꢀꢁ0ꢂ ꢃꢄꢅ
ꢀꢁ0ꢂ ꢃꢄꢅ
Maximum Current Sense
Oscillator Frequency
vs Temperature
RUN Pin Thresholds vs
Temperature
Threshold vs SENSE– Voltage
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
0
ꢀ.ꢁꢂ
ꢀ.ꢁꢂ
ꢀ.ꢁꢁ
ꢀ.ꢁ0
ꢀ.ꢀꢁ
ꢀ.ꢀꢁ
ꢀ.ꢀꢁ
ꢀ.ꢀꢁ
ꢀ.ꢀ0
ꢀ.0ꢁ
ꢀ.0ꢁ
ꢀ0
ꢀ
R
R
R
ꢀ ꢁꢂꢃꢄ ꢅꢆ00ꢄꢇꢈꢉ
ꢀ ꢁꢂꢃ ꢄꢂ00ꢃꢅꢆꢇ
ꢀ ꢁꢂ.ꢃꢄ ꢅꢆꢇꢈꢉꢊ
ꢀRꢁꢂ
ꢀRꢁꢂ
ꢀRꢁꢂ
ꢀRꢁꢂ ꢃ ꢄꢅꢆ ꢇꢈꢉ0ꢊꢋꢌꢍ
ꢀRꢁꢂ ꢃꢄꢅꢆꢇ ꢀꢁ.ꢁꢂꢃꢄꢅꢆ
Rꢀꢁꢀꢂꢃ
ꢀ
ꢀꢀ
ꢀ
ꢀ
0
ꢀꢁꢂꢂꢃꢄꢅ
ꢀꢁ
ꢀꢁ
ꢀꢁ
0
ꢀ
ꢀ0 ꢀꢁ ꢀ0 ꢀꢁ ꢀ0 ꢀꢁ ꢀ0
ꢀꢁꢁ ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ ꢀꢁꢂ ꢀꢁꢁ
ꢀꢁꢁ ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ ꢀꢁꢂ ꢀꢁꢁ
ꢀ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢀꢀꢁ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢀꢀꢁ
ꢀꢁꢂꢀꢁ ꢀꢁꢂꢃꢄꢅꢆ ꢇꢀꢈ
ꢀꢁ0ꢂ ꢃꢄꢅ
ꢀꢁ0ꢂ ꢃꢄꢁ
ꢀꢁ0ꢂ ꢃꢄꢀ
Rev. 0
7
For more information www.analog.com
LTC7802
TYPICAL PERFORMANCE CHARACTERISTICS
EXTVCC Switchover and INTVCC
Voltage vs Temperature
INTVCC Undervoltage Lockout
Thresholds vs Temperature
INTVCC Load Regulation
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.0
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢀ
ꢀ.ꢁ
ꢀ.0
ꢀ.ꢀ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.0
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.0
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢀ
ꢀ.ꢁ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢁ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢁ
ꢀꢁꢂꢃ ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃ ꢀ ꢁꢂ
ꢀꢀ
ꢀꢀ
Rꢀꢁꢀꢂꢃ
ꢀꢁꢂꢃ ꢀ 0ꢁ
ꢀꢀ
ꢀꢁꢂꢃ ꢀ ꢁꢂ
ꢀꢀ
ꢀꢁꢂꢃ Rꢀꢁꢀꢂꢃ
ꢀꢀ
ꢀꢁꢂꢂꢃꢄꢅ
ꢀꢁꢂꢃ ꢀꢁꢂꢂꢃꢄꢅ
ꢀꢀ
0
ꢀ0
ꢀ00
ꢀꢁ0
ꢀ00
ꢀꢁ0
ꢀ00
ꢀꢁꢁ ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ ꢀꢁꢂ ꢀꢁꢁ
ꢀꢁꢁ ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ ꢀꢁꢂ ꢀꢁꢁ
ꢀꢁꢂꢃ ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢊꢂꢋ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢀꢀꢁ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢀꢀꢁ
ꢀꢀ
ꢀꢁ0ꢂ ꢃꢄꢅ
ꢀꢁ0ꢂ ꢃꢂꢄ
ꢀꢁ0ꢂ ꢃꢂ0
Quiescent Current
vs Temperature
TRACK/SS Pull-Up Current
vs Temperature
Shutdown Current vs VIN Voltage
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀ
ꢀ.0
ꢀ.0
ꢀ.0
ꢀ.0
ꢀ.0
ꢀ.0
ꢀ.0
ꢀ.0
0
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢀ
ꢀ0
ꢀ
ꢀꢁꢂꢃ ꢄꢅꢆꢁꢁꢇꢂ ꢈ ꢀꢁ
ꢀꢁꢂꢂꢃ ꢄꢅꢆꢂ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢁ
ꢀꢁꢁꢀꢀ
ꢀꢁꢂꢀꢀ
ꢀꢁꢂꢃ ꢀ 0ꢁ
ꢀꢀ
ꢀ
ꢀꢁꢂꢀꢁꢃ ꢀ 0ꢁ
ꢀꢁꢂꢃ ꢀ 0ꢁ
ꢀꢀ
ꢀ
ꢀꢁꢂꢀꢁꢃ ꢀ ꢁ.ꢁꢂ
ꢀꢁꢂꢃ ꢀ ꢁꢂ
ꢀꢁꢂꢀꢁꢃ ꢀ ꢁ.ꢁꢂ
ꢀꢀ
ꢀ
ꢀꢁꢀꢀ
ꢀꢁꢁꢀꢀ
0
ꢀꢁꢁ ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁ ꢀꢁ ꢀꢁꢂ ꢀꢁꢁ
0
ꢀ
ꢀ0 ꢀꢁ ꢀ0 ꢀꢁ ꢀ0 ꢀꢁ ꢀ0
ꢀꢁꢂꢃꢄꢅꢆ ꢇꢀꢈ
ꢀꢁꢁ ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ ꢀꢁꢂ ꢀꢁꢁ
ꢀ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢀꢀꢁ
ꢀ
ꢀꢁ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆ ꢀꢁ
ꢀꢁ0ꢂ ꢃꢂꢂ
ꢀꢁ0ꢂ ꢃꢂꢄ
ꢀꢁ0ꢂ ꢃꢂꢄ
PIN FUNCTIONS
SENSE1+, SENSE2+ (Pins 1,8): The Positive (+) Input
FREQ (Pin 3): Frequency Control Pin for the Internal
to the Differential Current Comparators. The ITH pin
Oscillator. Connect to ground to set the switching fre-
–
voltage and controlled offsets between the SENSE and
quency to 350kHz. Connect to INTV to set the switching
CC
+
SENSE pins in conjunction with R
trip threshold.
set the current
frequency to 2.25MHz. Frequencies between 100kHz and
3MHz can be programmed using a resistor between the
FREQ pin and ground. Minimize the capacitance on this pin.
SENSE
–
–
SENSE1 , SENSE2 (Pins 2,7): The Negative (–) Input to
the Differential Current Comparators. The SENSE– pins
MODE (Pin 4): Mode Select Input. This input, which acts
on both channels, determines how the LTC7802 operates
at light loads. Pulling this pin to ground selects Burst
Mode operation. An internal 100k resistor to ground also
invokes Burst Mode operation when the pin is floating.
supply current to the current comparators when they are
–
greater than INTV . When SENSE1 is 3.2V or greater,
CC
it also supplies the majority of the sleep mode quiescent
current instead of V , further reducing the input-referred
IN
quiescent current.
Rev. 0
8
For more information www.analog.com
LTC7802
PIN FUNCTIONS
INTV pins and the BOOST2 and INTV pins. Voltage
Tying this pin to INTV forces continuous inductor cur-
CC
CC
CC
swing at the BOOST pins is from INTV to (V + INTV ).
rent operation. Tying this pin to INTV through a 100k
CC
IN
CC
CC
resistor selects pulse-skipping operation.
SW1, SW2 (Pins 22,14): Switch Node Connections to
Inductors.
RUN1, RUN2 (Pins 5,6): Run Control Inputs for Each
Controller. Forcing either of these pins below 1.1V disables
switching of the corresponding controller. Forcing both of
these pins below 0.7V shuts down the entire LTC7802,
reducing quiescent current to approximately 1.5µA. These
TG1, TG2 (Pins 23,13): High Current Gate Drives for Top
N Channel MOSFETs. These are the outputs of floating
drivers with a voltage swing of INTV superimposed on
CC
the switch node voltage SW.
pins can be tied to V for always-on operation. Do not
IN
PGOOD1, PGOOD2 (Pins 24,12): Open-Drain Power
float the RUN pins.
Good Outputs. The V
pins are monitored to ensure
FB1,2
INTV (Pin 17): Output of the Internal 5.1V Low Dropout
CC
that V
are in regulation. When V
is not within
OUT1,2
OUT
Regulator. The driver and control circuits are powered by
this supply. Must be decoupled to ground with a minimum
of 4.7μF ceramic or tantalum capacitor.
10% of its regulation point, the corresponding PGOOD
pin is pulled low.
TRACK/SS1, TRACK/SS2 (Pins 26,11): External Tracking
and Soft-Start Input. The LTC7802 regulates the VFB1,2
voltage to the lesser of 0.8V or the voltage on the TRACK/
SS1,2 pin. Internal 12.5µA pull-up current sources are
connected to these pins. A capacitor to ground sets the
start-up ramp time to the final regulated output voltage.
The ramp time is equal to 0.65ms for every 10nF of capac-
itance. Alternatively, a resistor divider on another voltage
supply connected to the TRACK/SS pins allows the
LTC7802 output to track the other supply during start-up.
EXTVCC (Pin 18): External Power Input to an Internal LDO
Connected to INTV . This LDO supplies INTV power,
CC
CC
bypassing the internal LDO powered from V whenever
IN
EXTVCC is higher than 4.7V. See INTVCC Regulators in the
Applications Information section. Do not exceed 30V on
this pin. Connect this pin to ground if the EXTV LDO
CC
is not used.
VIN (Pin 19): Main Bias Input Supply Pin. A bypass capac-
itor should be tied between this pin and GND.
ITH1, ITH2 (Pins 27,10): Error Amplifier Outputs and
Switching Regulator Compensation Points. Each asso-
ciated channel’s current comparator trip point increases
with this control voltage. Place compensation compo-
nents between the ITH pins and ground.
PLLIN/SPREAD (Pin 25): External Synchronization Input
and Spread Spectrum Selection. When an external clock
is applied to this pin, the phase-locked loop will force the
rising TG1 signal to be synchronized with the rising edge
of the external clock. When an external clock is present, the
regulators operate in pulse-skipping mode if it is selected
by the MODE pin, or in forced continuous mode otherwise.
When not synchronizing to an external clock, tie this input
to INTVCC to enable spread spectrum dithering of the oscil-
lator or to ground to disable spread spectrum.
VFB1, VFB2 (Pins 28,9): Controller Feedback Inputs.
Connect an external resistor divider between the output
voltage and the VFB pin to set the regulated output voltage.
Tie VFB2 to INTVCC to configure the channels for a 2-phase
single output application, in which both channels share
V
, ITH1, and TRACK/SS1.
FB1
BG1, BG2 (Pins 20,16): High Current Gate Drives for
Bottom (Synchronous) N-Channel MOSFETs. Voltage
GND (Exposed Pad Pin 29): Ground. Connects to the
sources of the bottom N-Channel MOSFETs and the (–)
terminal(s) of decoupling capacitors. The exposed pad
must be soldered to PCB ground for rated electrical and
thermal performance.
swing at these pins is from ground to INTV .
CC
BOOST1, BOOST2 (Pins 21,15): Bootstrapped Supplies to
the Top Side Floating Drivers. Connect capacitors between
the corresponding BOOST and SW pins for each channel.
Also connect Schottky diodes between the BOOST1 and
Rev. 0
9
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LTC7802
FUNCTIONAL DIAGRAM
ꢄꢐꢖꢋꢇꢉꢗꢈꢓ ꢝꢌR ꢅꢓꢉꢌꢎꢄ ꢉꢌꢎꢈRꢌꢋꢋꢓR ꢉꢊꢗꢎꢎꢓꢋ
Rꢐꢎ
ꢇꢎꢈꢏ
ꢉꢉ
ꢄ
ꢏ
ꢃ
ꢇꢎ
ꢃꢌꢌꢅꢈ
ꢈꢍ
ꢔ
ꢕ
ꢗꢋꢋꢌꢝꢝ
ꢑ.ꢂꢏ
ꢉ
ꢃ
ꢈꢌꢖ
ꢃꢌꢈ
ꢉ
ꢇꢎ
ꢝRꢓꢙ
ꢅꢖRꢓꢗꢄ
ꢅꢖꢓꢉꢈRꢐꢘ
ꢌꢅꢉꢇꢋꢋꢗꢈꢌR
ꢗꢎꢄ ꢖꢋꢋ
ꢉꢋꢟꢂ
ꢉꢋꢟꢑ
ꢄRꢌꢖꢌꢐꢈ
ꢄꢓꢈꢓꢉꢈ
ꢅꢆꢇꢈꢉꢊ
ꢋꢌꢍꢇꢉ
ꢖꢋꢋꢇꢎꢠꢅꢖRꢓꢗꢄ
ꢅ
R
ꢈꢌꢖ ꢌꢎ
ꢅꢆ
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ꢇꢎꢈꢏ
ꢉꢉ
ꢃꢍ
ꢕ
ꢔ
0.ꢛꢂꢚꢏ
ꢅꢋꢓꢓꢖ
ꢍꢎꢄ
ꢘꢌꢄꢓ
ꢑ00ꢢ
ꢇꢉꢘꢖ
ꢇR
ꢔ
ꢕ
ꢕ
ꢔ
ꢕ ꢔ
R
ꢅꢓꢎꢅꢓ
ꢋ
ꢔꢕ
ꢏ
ꢌꢐꢈꢑꢒꢂ
ꢕ
ꢂꢞꢏ
ꢅꢓꢎꢅꢓ
ꢉ
ꢌꢐꢈ
ꢔ
ꢅꢓꢎꢅꢓ
ꢅꢋꢌꢖꢓ ꢉꢌꢘꢖ
R
ꢏ
ꢝꢑ
ꢝꢃ
ꢔ
ꢕ
ꢕ
ꢓꢗ
0.ꢁꢏ
R
ꢝꢂ
ꢉ
R
ꢉ
ꢇꢈꢊ
ꢏ
ꢇꢎ
ꢇꢈꢊ
ꢉꢋꢗꢘꢖ
ꢑ.ꢛꢏ
ꢉ
ꢉꢑ
ꢓꢜꢈꢏ
ꢉꢂ
ꢉꢉ
ꢑꢂ.ꢚꢡꢗ
ꢈRꢗꢉꢟꢠꢅꢅ
ꢖꢍꢌꢌꢄ
ꢕ
ꢔ
ꢔ
ꢕ
0.ꢁꢁꢏ
0.ꢀꢂꢏ
0ꢏ
ꢉ
ꢅꢅ
ꢗꢋꢋꢌꢝꢝ
ꢛ.ꢀꢏ
ꢔ
ꢕ
ꢓꢎ
ꢔ
ꢕ
ꢓꢎ
ꢚ.ꢑꢏ
ꢚ.ꢑꢏ
ꢔ
ꢕ
ꢓꢜꢈꢏ ꢋꢄꢌ
ꢉꢉ
ꢏ
ꢋꢄꢌ
ꢃꢇꢗꢅ
ꢇꢎꢈꢏ
ꢉꢉ
ꢀꢁ0ꢂ ꢃꢄ
Rev. 0
10
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LTC7802
OPERATION (Refer to Functional Diagram)
Main Control Loop
Each top MOSFET driver is biased from the floating boot-
strap capacitor C , which normally recharges during each
cycle through anBexternal diode when the switch voltage
goes low.
The LTC7802 is a dual synchronous step-down (buck)
controller utilizing a constant frequency, peak current
mode architecture. The two controller channels oper-
ate 180° out of phase which reduces the required input
capacitance and power supply induced noise. During nor-
mal operation, the external top MOSFET is turned on when
the clock for that channel sets the SR latch, causing the
inductor current to increase. The main switch is turned off
when the main current comparator, ICMP, resets the SR
latch. After the top MOSFET is turned off each cycle, the
bottom MOSFET is turned on which causes the inductor
current to decrease until either the inductor current starts
to reverse, as indicated by the current comparator IR, or
the beginning of the next clock cycle.
If the input voltage decreases to a voltage close to its
output, the loop may enter dropout and attempt to turn
on the top MOSFET continuously. The dropout detector
detects this and forces the top MOSFET off for a short
time every tenth cycle to allow C to recharge, resulting in
a 99% duty cycle at 350kHz opeBration and approximately
98% duty cycle at 2MHz operation.
Start-Up and Shutdown (RUN and TRACK/SS Pins)
The two channels of the LTC7802 can be independently
shut down using the RUN1 and RUN2 pins. Pulling a RUN
pin below 1.1V shuts down the main control loop for that
channel. Pulling both RUN pins below 0.7V disables
both controllers and most internal circuits, including the
INTV LDOs. In this shutdown state, the LTC7802 draws
only C1C.5μA of quiescent current.
The peak inductor current at which ICMP trips and resets
the latch is controlled by the voltage on the ITH pin, which
is the output of the error amplifier EA. The error amplifier
compares the output voltage feedback signal at the V
FB
pin, (which is generated with an external resistor divider
connected across the output voltage, V , to ground) to
OUT
The RUN pins may be externally pulled up or driven
directly by logic. Each pin can tolerate up to 40V (abso-
the internal 0.8V reference voltage. When the load current
increases, it causes a slight decrease in V relative to the
FB
lute maximum), so it can be conveniently tied to V in
IN
reference,which causes the EA to increase the I voltage
until the average inductor current matches theTnHew load
current.
always-on applications where one or both controllers are
enabled continuously and never shut down. Additionally,
a resistive divider from V to a RUN pin can be used to
IN
set a precise input undervoltage lockout so that the power
supply does not operate below a user adjustable level.
Power and Bias Supplies (V , EXTV , and INTV )
IN
CC
CC
The INTVCC pin supplies power for the top and bottom
MOSFET drivers and most of the internal circuitry. LDOs
(low dropout linear regulators) are available from both the
The start-up of each channel’s output voltage V
is con-
OUT
trolled by the voltage on the corresponding TRACK/SS
pin. When the voltage on the TRACK/SS pin is less than
the 0.8V internal reference voltage, the LTC7802 regulates
V and EXTV pins to provide power to INTV , which
IN
CC
CC
has a regulation point of 5.1V. When the EXTV pin is
CC
the V voltage to the TRACK/SS pin voltage instead of
FB
left open or tied to a voltage less than 4.7V, the V LDO
IN
the 0.8V reference voltage. This allows the TRACK/SS pin
to be used as a soft-start which smoothly ramps the out-
put voltage on start-up, thereby limiting the input supply
inrush current. An external capacitor from the TRACK/
SS pin to GND is charged by an internal 12.5μA pull-up
current, creating a voltage ramp on the TRACK/SS pin. As
supplies power to INTV . If EXTV is taken above 4.7V,
CC
CC
the V LDO is turned off and the EXTV LDO is turned
IN
CC
on. Once enabled, the EXTVCC LDO supplies power to
INTV . Using the EXTV pin allows the INTV power
CC
CC
CC
to be derived from a high efficiency external source such
as one of the LTC7802 switching regulator outputs.
Rev. 0
11
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LTC7802
OPERATION
the TRACK/SS voltage rises linearly from 0V to 0.8V (and
beyond), the output voltage VOUT rises smoothly from
zero to its final value.
–
supplied by the SENSE1 pin, which further reduces the
input-referred quiescent current by the ratio of V /V
multiplied by the efficiency.
IN OUT
Alternatively, the TRACK/SS pins can be used to make the
start-up of VOUT track that of another supply. Typically
this requires connecting to the TRACK/SS pin through an
external resistor divider from the other supply to ground
(see the Applications Information section).
In sleep mode, the load current is supplied by the output
capacitor. As the output voltage decreases, the EA’s out-
put begins to rise. When the output voltage drops enough,
the ITH pin is reconnected to the output of the EA, the
sleep signal goes low, and the controller resumes normal
operation by turning on the top MOSFET on the next cycle
of the internal oscillator.
Light Load Operation: Burst Mode Operation, Pulse-
Skipping, or Forced Continuous Mode (MODE Pin)
When a controller is enabled for Burst Mode operation,
the inductor current is not allowed to reverse. The reverse
current comparator (IR) turns off the bottom MOSFET
just before the inductor current reaches zero, preventing
it from reversing and going negative. Thus, the controller
operates in discontinuous operation.
The LTC7802 can be set to enter high efficiency Burst
Mode operation, constant frequency pulse-skipping
mode or forced continuous conduction mode at low load
currents.
To select Burst Mode operation, tie the MODE pin to
ground. To select forced continuous operation, tie the
In forced continuous operation the inductor current is
allowed to reverse at light loads or under large transient
conditions. The peak inductor current is determined by
the voltage on the ITH pin, just as in normal operation.
In this mode, the efficiency at light loads is lower than
in Burst Mode operation. However, continuous operation
has the advantage of lower output voltage ripple and less
interference to audio circuitry. In forced continuous mode,
the output ripple is independent of load current.
MODE pin to INTV . To select pulse-skipping mode, tie
CC
the MODE pin to a DC voltage greater than 1.2V and less
than INTV – 1.3V. An internal 100k resistor to ground
invokes BCuCrst Mode operation when the MODE pin is
floating and pulse-skipping mode when the MODE pin is
tied to INTV through an external 100k resistor.
CC
When the controllers are enabled for Burst Mode opera-
tion, the minimum peak current in the inductor is set to
approximately 25% of its maximum value even though
the voltage on the ITH pin might indicate a lower value.
If the average inductor current is higher than the load
current, the error amplifier EA will decrease the voltage
on the ITH pin. When the ITH voltage drops below 0.425V,
the internal sleep signal goes high (enabling sleep mode)
and both external MOSFETs are turned off. The ITH pin is
then disconnected from the output of the EA and parked
at 0.45V.
When the MODE pin is connected for pulse-skipping
mode, the LTC7802 operates in PWM pulse-skipping
mode at light loads. In this mode, constant frequency
operation is maintained down to approximately 1% of
designed maximum output current. At very light loads, the
current comparator ICMP may remain tripped for several
cycles and force the top MOSFET to stay off for the same
number of cycles (i.e., skipping pulses). The inductor cur-
rent is not allowed to reverse (discontinuous operation).
This mode, like forced continuous operation, exhibits low
output ripple as well as low audio noise and reduced RF
interference as compared to Burst Mode operation. It pro-
vides higher low current efficiency than forced continuous
mode, but not nearly as high as Burst Mode operation.
In sleep mode, much of the internal circuitry is turned off,
reducing the quiescent current that the LTC7802 draws. If
one channel is in sleep mode and the other channel is shut
down, the LTC7802 draws only 15μA of quiescent current.
If both channels are in sleep mode, the LTC7802 draws
only 18μA of quiescent current. When V
on channel 1
OUT
Unlike forced continuous mode and pulse-skipping mode,
Burst Mode cannot be synchronized to an external clock.
is 3.2V or higher, the majority of this quiescent current is
Rev. 0
12
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LTC7802
OPERATION
Therefore, if Burst Mode is selected and the switching
frequency is synchronized to an external clock applied to
the PLLIN/SPREAD pin, the LTC7802 switches from Burst
Mode to forced continuous mode.
approximately the frequency of the external clock. The
LTC7802’s PLL is guaranteed to lock to an external clock
source whose frequency is between 100kHz and 3MHz.
The PLLIN/SPREAD pin is TTL compatible with thresholds
of 1.6V (rising) and 1.1V (falling) and is guaranteed to
operate with a clock signal swing of 0.5V to 2.2V.
Frequency Selection, Spread Spectrum, and Phase-
Locked Loop (FREQ and PLLIN/SPREAD Pins)
The free running switching frequency of the LTC7802
controllers is selected using the FREQ pin. Tying FREQ to
GND selects 350kHz while tying FREQ to INTV selects
2.25MHz. Placing a resistor between FREQ CaCnd GND
allows the frequency to be programmed between 100kHz
and 3MHz.
Output Overvoltage Protection
Each channel has an overvoltage comparator that guards
against transient overshoots as well as other more serious
conditions that may overvoltage the output. When the
V
pin rises more than 10% above its regulation point
FB1,2
of 0.8V, the top MOSFET is turned off and the bottom
MOSFET is turned on until the overvoltage condition is
cleared.
Switching regulators can be particularly troublesome for
applications where electromagnetic interference (EMI)
is a concern. To improve EMI, the LTC7802 can oper-
ate in spread spectrum mode, which is enabled by tying
the PLLIN/SPREAD pin to INTVCC. This feature varies
the switching frequency within typical boundaries of
–12% to +15% of the frequency set by the FREQ pin.
Foldback Current
When the output voltage falls to less than 50% of its
nominal level, foldback current limiting is activated, pro-
gressively lowering the peak current limit in proportion to
the severity of the overcurrent or short-circuit condition.
Foldback current limiting is disabled during the soft-start
A phase-locked loop (PLL) is available on the LTC7802
to synchronize the internal oscillator to an external
clock source connected to the PLLIN/SPREAD pin. The
LTC7802’s PLL aligns the turn-on of controller 1’s exter-
nal top MOSFET to the rising edge of the synchronizing
signal. Thus, the turn-on of controller 2’s external top
MOSFET is 180° out-of-phase to the rising edge of the
external clock source.
interval (as long as the V voltage is keeping up with the
FB
TRACK/SS1,2 voltage).
Power Good
Each channel has a PGOOD pin that is connected to an
open drain of an internal N-channel MOSFET. The MOSFET
turns on and pulls the PGOOD pin low when the VFB voltage
is not within 10% of the 0.8V reference. The PGOOD pin
is also pulled low when the RUN pin is low (shut down).
When the VFB voltage is within the 10% requirement, the
MOSFET is turned off and the pin is allowed to be pulled
up by an external resistor to a source no greater than 6V,
The PLL frequency is prebiased to the free running fre-
quency set by the FREQ pin before the external clock is
applied. If prebiased near the external clock frequency,
the PLL only needs to make slight changes in order to
synchronize the rising edge of the external clock to the
rising edge of TG1. For more rapid lock-in to the external
clock, use the FREQ pin to set the internal oscillator to
such as INTV .
CC
Rev. 0
13
For more information www.analog.com
LTC7802
APPLICATIONS INFORMATION
The Typical Application on the first page is a basic
LTC7802 application circuit. External component selection
is largely driven by the load requirement and begins with
the selection of the inductor, current sense components,
operating frequency, and light load operating mode. The
remaining power stage components, consisting of the
input and output capacitors, and power MOSFETs can
then be chosen. Next, feedback resistors are selected
to set the desired output voltage. Then, the remaining
external components are selected, such as for soft-start,
biasing, and loop compensation.
lower load currents, which can cause a dip in efficiency
in the upper range of low current operation.
Inductor Core Selection
Once the value for L is known, the type of inductor must
be selected. High efficiency regulators generally can-
not afford the core loss found in low cost powdered
iron cores, forcing the use of more expensive ferrite or
molypermalloy cores. Actual core loss is very dependent
on inductance value selected. As inductance increases,
core losses go down. Unfortunately, increased inductance
requires more turns of wire and therefore copper losses
will increase.
Inductor Value Calculation
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because
of MOSFET switching and gate charge losses. In addi-
tion to this basic trade-off, the effect of inductor value
on ripple current and low current operation must also
be considered. The inductor value has a direct effect on
ripple current.
Ferrite designs have very low core loss and are preferred
for high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates hard, which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Current Sense Selection
The LTC7802 can be configured to use either DCR (induc-
tor resistance) sensing or low value resistor sensing.
The choice between the two current sensing schemes
is largely a design trade-off between cost, power con-
sumption and accuracy. DCR sensing has become popular
because it saves expensive current sensing resistors and
is more power efficient, particularly in higher current and
lower frequency applications. However, current sensing
resistors provide the most accurate current limits for the
controller. Other external component selection is driven
by the load requirement and begins with the selection of
The maximum average inductor current I
is equal
L(MAX)
to the maximum output current. The peak current is equal
to the average inductor current plus half of the inductor
ripple current, ΔI , which decreases with higher induc-
L
tance or higher frequency and increases with higher V :
IN
⎛
⎞
1
VOUT
ΔIL =
VOUT 1−
⎜
⎟
(f)(L)
V
⎝
⎠
IN
Accepting larger values of ΔIL allows the use of low induc-
tances, but results in higher output voltage ripple and
greater core losses. A reasonable starting point for setting
ripple current is ΔIL = 0.3 • IL(MAX). The maximum ΔIL
occurs at the maximum input voltage.
R
SENSE
(if R
is used) and inductor value.
SENSE
+
–
The SENSE and SENSE pins are the inputs to the current
comparators. The common mode voltage range on these
pins is 0V to 40V (absolute maximum), enabling the
LTC7802 to regulate output voltages up to a maximum
of 40V. The SENSE+ pin is high impedance, drawing
less than ≈1μA. This high impedance allows the current
comparators to be used in inductor DCR sensing. The
The inductor value also has secondary effects. The tran-
sition to Burst Mode operation begins when the average
inductor current required results in a peak current below
25% of the current limit determined by RSENSE. Lower
inductor values (higher ΔI ) will cause this to occur at
L
–
impedance of the SENSE pin changes depending on the
Rev. 0
14
For more information www.analog.com
LTC7802
APPLICATIONS INFORMATION
To ensure that the application will deliver full load cur-
rent over the full operating temperature range, choose
the minimum value for VSENSE(MAX) in the Electrical
Characteristics table.
common mode voltage. When less than INTV – 0.5V,
CC
these pins are relatively high impedance, drawing ≈ 1μA.
When above INTV + 0.5V, a higher current (≈ 650μA)
CC
flows into each pin. Between INTV – 0.5V and INTV
CC
CC
+ 0.5V, the current transitions from the smaller current to
the higher current. Channel 1’s SENSE1– pin has an addi-
tional ≈ 50μA current when its voltage is above 3.2V to
To avoid potential jitter or instability due to PCB noise cou-
pling into the current sense signal, the AC current sensing
ripple of ΔV
= ΔI • R
should also be checked
SENSE
L
SENSE
bias internal circuitry from V
instead of V , thereby
OUT1
IN
to ensure a good signal-to-noise ratio. In general, for a
reasonably good PCB layout, a target ΔV voltage of
reducing the input-referred supply current.
SENSE
10mV to 20mV at nominal input voltage is recommended
for both R and DCR sensing applications.
Filter components mutual to the sense lines should be
placed close to the LTC7802, and the sense lines should
run close together to a Kelvin connection underneath the
current sense element (shown in Figure 1). Sensing cur-
rent elsewhere can effectively add parasitic inductance
and capacitance to the current sense element, degrading
the information at the sense terminals and making the
programmed current limit unpredictable. If DCR sensing
is used (Figure 2b), resistor R1 should be placed close to
the switching node, to prevent noise from coupling into
sensitive small signal nodes.
SENSE
The parasitic inductance (ESL) of the sense resistor
introduces significant error in the current sense signal
for lower inductor value (< 3μH) or higher current (> 5A)
applications. This error is proportional to input voltage
and may degrade line regulation or cause loop instability.
An RC filter into the sense pins, as shown in Figure 2a, can
be used to compensate for this error. Set the RC filter time
constant R • C =ESL/R for optimal cancellation of
F
F
SENSE
the ESL. In general, select C to be in the range of 1nF to
F
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ꢉꢈꢌꢅ ꢅꢆ ꢅꢍꢈ ꢎꢆꢉꢅRꢆꢋꢋꢈR
10nF and calculate the corresponding R Surface mount
F.
sense resistors in low ESL wide footprint geometries are
recommended to minimize this error. If not specified on
the manufacturer’s data sheet, the ESL can be approxi-
mated as 0.4nH for a resistor with a 1206 footprint and
0.2nH for a 1225 footprint.
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ꢀꢁ0ꢂ ꢃ0ꢄ
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ꢇꢈꢉꢇꢈ
Inductor DCR Current Sensing
Figure 1. Sense Lines Placement with Inductor or Sense Resistor
For applications requiring the highest possible efficiency
at high load currents, the LTC7802 is capable of sensing
the voltage drop across the inductor DCR, as shown in
Figure 2b. The DCR of the inductor represents the small
amount of DC winding resistance of the copper, which can
be less than 1mΩ for today’s low value, high current induc-
tors. In a high current application requiring such an induc-
tor, power loss through a sense resistor would cost several
points of efficiency compared to inductor DCR sensing.
Low Value Resistor Current Sensing
A typical sensing circuit using a discrete resistor is
shown in Figure 2a. RSENSE is chosen based on the
required output current. Each controller’s current com-
parator has a maximum threshold V
of 50mV.
SENSE(MAX)
The current comparator threshold voltage sets the peak
inductor current.
Using the maximum inductor current (I
) and ripple
L(MAX)
current (ΔI ) from the Inductor Value Calculation section,
If the external (R1||R2) • C1 time constant is chosen to be
exactly equal to the L/DCR time constant, the voltage drop
across the external capacitor is equal to the drop across
the inductor DCR multiplied by R2/(R1+R2). R2 scales the
voltage across the sense terminals for applications where
L
the target sense resistor value is:
VSENSE(MAX)
RSENSE(EQUIV)
≤
ΔIL
IL(MAX)
+
2
the DCR is greater than the target sense resistor value.
Rev. 0
15
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LTC7802
APPLICATIONS INFORMATION
ꢀ
the minimum value for VSENSE(MAX) in the Electrical
Characteristics table.
ꢀꢁꢂꢃꢄ
ꢀꢁ
ꢀꢁꢂꢀꢁ RꢁꢀꢃꢀꢄꢅR
ꢀꢁꢂꢃ ꢄꢅRꢅꢆꢁꢂꢁꢇ
ꢀꢁꢁꢂꢃ
ꢀꢁꢂꢃꢄꢅꢆꢁꢄꢇ
Next, determine the DCR of the inductor. When provided,
use the manufacturer’s maximum value, usually given at
20°C. Increase this value to account for the temperature
coefficient of copper resistance, which is approximately
R
ꢀ
ꢀꢁꢂ
R ꢀꢁ ꢀ ꢁꢂꢃꢄR
ꢀꢁꢂꢀꢁ
ꢀꢁꢂꢀꢁ
ꢀꢁ
ꢀ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂꢃꢄ0ꢅ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅꢃRꢁ
ꢀꢁꢂꢀꢃꢄꢄꢁꢅꢆꢇꢂ
ꢀꢁ
0.4%/°C. A conservative value for T
is 100°C. To
R
ꢀ
L(MAX)
ꢆ
ꢀꢁꢂꢀꢁꢃꢄꢅ
scale the maximum inductor DCR to the desired sense
resistor value, use the divider ratio:
ꢀ
ꢀ
ꢆ
ꢀꢁꢂꢀꢁꢃꢄꢅ
ꢀꢁꢂꢃꢄ R ꢀꢁꢂ ꢃ ꢀꢁꢂR ꢃꢁꢀꢃꢁ ꢄꢅꢀꢃ
ꢀ
ꢀ
ꢀꢁ0ꢂ ꢃ0ꢂꢄ
RSENSE(EQUIV)
RD =
(2a) Using a Resistor to Sense Current
DCRMAX atT
L(MAX)
ꢔ
ꢕꢎꢏꢐꢂ
C1 is usually selected to be in the range of 0.1μF to 0.47μF.
This forces R1||R2 to around 2k, reducing error that might
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ꢆꢋ
ꢕꢎꢓꢖꢇꢆꢉR
ꢓꢇR
+
have been caused by the SENSE pin’s ≈1μA current.
ꢅꢆꢇꢀꢁ0ꢂ
ꢅ
ꢔ
ꢊꢌ
ꢈꢋ
ꢉꢖꢆꢏꢐꢂ
The target equivalent resistance R1||R2 is calculated from
the nominal inductance, C1 value, and DCR:
Rꢏ
ꢑ
L
R1!R2 =
ꢊꢍꢎꢊꢍꢏꢐ ꢂ
ꢇꢏꢗ
Rꢂ
(DCR at 20°C)•C1
ꢒ
ꢊꢍꢎꢊꢍꢏꢐ ꢂ
The sense resistor values are:
ꢋꢎꢓ
ꢀꢁ0ꢂ ꢃ0ꢂꢄ
R1!R2
RD
R1•RD
1−RD
ꢚRꢏꢟꢟRꢂꢜ ꢠ ꢇꢏ ꢝ ꢅꢞꢓꢇR
R ꢝ ꢓꢇRꢚRꢂꢞꢚRꢏꢑRꢂꢜꢜ
ꢊꢍꢎꢊꢍꢚꢍꢛꢜ
R1=
; R2 =
ꢗꢘꢅꢙꢇꢍ ꢇꢏ ꢎꢍꢙR ꢊꢍꢎꢊꢍ ꢘꢕꢎꢊ
(2b) Using the Inductor DCR to Sense Current
Figure 2. Current Sensing Methods
The maximum power loss in R1 is related to duty cycle and
occurs in continuous mode at the maximum input voltage:
(VIN(MAX) − VOUT)• VOUT
To properly dimension the external filter components, the
DCR of the inductor must be known. It can be measured
using a good RLC meter, but the DCR tolerance is not
always the same and varies with temperature; consult
the manufacturers’ data sheets for detailed information.
PLOSS R1=
R1
Ensure that R1 has a power rating higher than this value.
If high efficiency is necessary at light loads, consider this
power loss when deciding whether to use DCR sensing
or sense resistors. Light load power loss can be mod-
estly higher with a DCR network than with a sense resis-
tor, due to the extra switching losses incurred through
R1. However, DCR sensing eliminates a sense resistor,
reduces conduction losses and provides higher efficiency
at heavy loads. Peak efficiency is about the same with
either method.
Using the maximum inductor current (I
) and ripple
L(MAX)
current (ΔI ) from the Inductor Value Calculation section,
L
the target sense resistor value is:
VSENSE(MAX)
RSENSE(EQUIV)
=
ΔIL
ILMAX
+
2
To ensure that the application will deliver full load cur-
rent over the full operating temperature range, choose
Rev. 0
16
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LTC7802
APPLICATIONS INFORMATION
Setting the Operating Frequency
ꢀ0ꢁ
Selection of the operating frequency is a trade-off between
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves efficiency by
reducing gate charge and transition losses, but requires
larger inductance values and/or more output capacitance
to maintain low output ripple voltage.
ꢀꢁ
In higher voltage applications transition losses contrib-
ute more significantly to power loss, and a good balance
between size and efficiency is generally achieved with a
switching frequency between 300kHz and 900kHz. Lower
voltage applications benefit from lower switching losses
and can therefore more readily operate at higher switch-
ing frequencies up to 3MHz if desired. The switching fre-
quency is set using the FREQ and PLLIN/SPREAD pins
as shown in Table 1.
ꢀ00ꢁ
ꢀ0ꢁ
ꢀ00ꢁ
ꢀ00ꢁ
FREQ PIN RESISTOR (Ω)
ꢀꢁ0ꢂ ꢃ0ꢄ
Figure 3. Relationship Between Oscillator Frequency and
Resistor Value at the FREQ Pin
A phase-locked loop (PLL) is also available on the
LTC7802 to synchronize the internal oscillator to an exter-
nal clock source connected to the PLLIN/SPREAD pin.
After the PLL locks, TG1 is synchronized to the rising edge
of the external clock signal, and TG2 is 180° out of phase
from TG1. See the Phase-Locked Loop and Frequency
Synchronization section for details.
Table 1.
FREQ PIN
PLLIN/SPREAD PIN
FREQUENCY
350kHz
0V
0V
0V
0V
INTV
2.25MHz
CC
Resistor to GND
Any of the Above
100kHz to 3MHz
Selecting the Light-Load Operating Mode
External Clock 100kHz Phase-Locked to
to 3MHz
External lock
The LTC7802 can be set to enter high efficiency Burst Mode
operation, constant frequency pulse-skipping mode or
forced continuous conduction mode at light load currents.
To select Burst Mode operation, tie the MODE to ground.
To select forced continuous operation, tie the MODE pin
to INTVCC. To select pulse-skipping mode, tie the MODE
Any of the Above
INTV
Spread Spectrum
Modulated
CC
Tying the FREQ pin to ground selects 350kHz while tying
FREQ to INTVCC selects 2.25MHz. Placing a resistor
between FREQ and ground allows the frequency to be pro-
grammed anywhere between 100kHz and 3MHz. Choose a
FREQ pin resistor from Figure 3 or the following equation:
pin to INTV through a 100k resistor. An internal 100k
CC
resistor from the MODE pin to ground selects Burst Mode
if the pin is floating. When synchronized to an external clock
through the PLLIN/SPREAD pin, the LTC7802 operates in
pulse-skipping mode if it is selected, or in forced contin-
uous mode otherwise. Table 2 summarizes the use of the
MODE pin to select the light load operating mode.
37MHz
RFREQ (in kΩ)=
fOSC
To improve electromagnetic interference (EMI) perfor-
mance, spread spectrum mode can optionally be selected
Table 2.
by tying the PLLIN/SPREAD pin to INTV . When spread
CC
LIGHT-LOAD
MODE WHEN
SYNCHRONIZED
MODE PIN
OPERATING MODE
spectrum is enabled, the switching frequency modulates
within –12% to +15% of the frequency selected by the
FREQ pin. Spread spectrum may be used in any operating
mode selected by the MODE pin (Burst Mode, pulse-skip-
ping, or forced continuous mode).
0V or Floating
100k to INTV
Burst Mode
Forced Continuous
Pulse-Skipping
Pulse-Skipping
Forced Continuous
CC
INTV
Forced Continuous
CC
Rev. 0
17
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LTC7802
APPLICATIONS INFORMATION
Power MOSFET Selection
In general, the requirements of each application will dictate
the appropriate choice for light-load operating mode. In
Burst Mode operation, the inductor current is not allowed
to reverse. The reverse current comparator turns off the
bottom MOSFET just before the inductor current reaches
zero, preventing it from reversing and going negative.
Thus, the regulator operates in discontinuous operation.
In addition, when the load current is very light, the inductor
current will begin bursting at frequencies lower than the
switching frequency and enter a low current sleep mode
when not switching. As a result, Burst Mode operation has
the highest possible efficiency at light load.
Two external power MOSFETs must be selected for each
controller in the LTC7802: one N-channel MOSFET for
the top (main) switch and one N-channel MOSFET for
the bottom (synchronous) switch. The peak-to-peak
gate drive levels are set by the INTV regulation point of
CC
5.1V. Consequently, logic level threshold MOSFETs must
be used in most applications. Pay close attention to the
BV
specification for the MOSFETs as well; many of the
logDicSSlevel MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the on
resistance RDS(ON), Miller capacitance CMILLER, input
voltage, and maximum output current. Miller capacitance,
In forced continuous mode, the inductor current is
allowed to reverse at light loads and switches at the same
frequency regardless of load. In this mode, the efficiency
at light loads is considerably lower than in Burst Mode
operation. However, continuous operation has the advan-
tage of lower output voltage ripple and less interference
to audio circuitry. In forced continuous mode, the output
ripple is independent of load current.
C
, can be approximated from the gate charge curve
MILLER
usually provided on the MOSFET manufacturers’ data
sheet. CMILLER is equal to the increase in gate charge
along the horizontal axis while the curve is approximately
flat divided by the specified change in V . This result is
DS
then multiplied by the ratio of the application applied V
to the gate charge curve specified VDS. When the ICDisS
operating in continuous mode the duty cycles for the top
and bottom MOSFETs are given by:
In pulse-skipping mode, constant frequency operation
is maintained down to approximately 1% of designed
maximum output current. At very light loads, the PWM
comparator may remain tripped for several cycles and
force the top MOSFET to stay off for the same number of
cycles (i.e., skipping pulses). The inductor current is not
allowed to reverse (discontinuous operation). This mode,
like forced continuous operation, exhibits low output rip-
ple as well as low audio noise and reduced RF interference
as compared to Burst Mode operation. It provides higher
light load efficiency than forced continuous mode, but not
nearly as high as Burst Mode operation. Consequently,
pulse-skipping mode represents a compromise between
light load efficiency, output ripple and EMI.
VOUT
MAIN SWITCH DUTY CYCLE =
V
IN
V – V
IN
OUT
SYNCHRONOUS SWITCH DUTY CYCLE =
V
IN
The MOSFET power dissipations at maximum output cur-
rent are given by:
2
)
VOUT
PMAIN_BUCK
=
I
(
1+ δ R
( )
DS(O
OUT(MAX)
V
IN
I
⎛
⎞
OUT(MAX)
(V )2
(RDR)(CMILLER)•
In some applications, it may be desirable to change light load
operating mode based on the conditions present in the sys-
tem. For example, if a system is inactive, one might select
high efficiency Burst Mode operation by keeping the MODE
pin set to 0V. When the system wakes, one might send an
IN
⎜
⎟
2
⎝
⎠
⎡
⎢
⎤
1
1
+
(f)
⎥
V
⎣ INTVCC − VTHMIN VTHMIN
⎦
2
)
external clock to PLLIN/SPREAD, or tie MODE to INTV to
V − V
CC
IN
OUT
PSYNC_BUCK
=
I
1+ δ
( )
(
OUT(MAX)
switch to low noise forced continuous mode. Such on-the-fly
mode changes can allow an individual application to benefit
from the advantages of each light load operating mode.
V
IN
Rev. 0
18
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LTC7802
APPLICATIONS INFORMATION
This formula has a maximum at V = 2V , where I
RMS
where δ is the temperature dependency of R
(δ ≈
IN
OUT
DS(ON)
= I /2. This simple worst-case condition is commonly
0.005/°C) and R is the effective driver resistance at the
OUT
DR
used for design because even significant deviations do
not offer much relief. Note that capacitor manufacturers’
ripple current ratings are often based on only 2000 hours
of life. This makes it advisable to further derate the capac-
itor, or to choose a capacitor rated at a higher temperature
than required. Several capacitors may be paralleled to
meet size or height requirements in the design. Due to
the high operating frequency of the LTC7802, ceramic
MOSFET’s Miller threshold voltage (R ≈ 2Ω). V
is
DR
the typical MOSFET minimum threshold voltage.THMIN
2
Both MOSFETs have I R losses while the main N-channel
equations include an additional term for transition losses,
which are highest at high input voltages. For V < 20V
IN
the high current efficiency generally improves with larger
MOSFETs, while for V > 20V the transition losses rap-
IN
idly increase to the point that the use of a higher R
DS(ON)
capacitors can also be used for C . Always consult the
IN
device with lower C
actually provides higher effi-
MILLER
manufacturer if there is any question.
ciency. The synchronous MOSFET losses are greatest at
high input voltage when the top switch duty factor is low
or during a short-circuit when the synchronous switch is
on close to 100% of the period.
The benefit of the LTC7802 2-phase operation can be
calculated by using this equation for the higher power
controller and then calculating the loss that would have
resulted if both controller channels switched on at the
same time. The total RMS power lost is lower when both
controllers are operating due to the reduced overlap of
current pulses required through the input capacitor’s
ESR. This is why the input capacitor’s requirement cal-
culated above for the worst-case controller is adequate
for the dual controller design. Also, the input protection
fuse resistance, battery resistance, and PC board trace
resistance losses are also reduced due to the reduced
peak currents in a 2-phase system. The overall benefit of
a multiphase design will only be fully realized when the
source impedance of the power supply/battery is included
in the efficiency testing.
C and C
IN
Selection
OUT
The selection of C is simplified by the 2-phase archi-
IN
tecture and its impact on the worst-case RMS current
drawn through the input network (battery/fuse/capacitor).
It can be shown that the worst-case capacitor RMS cur-
rent occurs when only one controller is operating. The
controller with the highest V
• I
product needs to
OUT OUT
be used in the equation below to determine the maximum
RMS capacitor current requirement.
Increasing the output current drawn from the other con-
troller will actually decrease the input RMS ripple current
from its maximum value. The out-of-phase technique typ-
ically reduces the input capacitor’s RMS ripple current by
a factor of 30% to 70% when compared to a single-phase
power supply solution.
The drains of the top MOSFETs should be placed within 1cm
of each other and share a common CIN(s). Separating the
drains and C may produce undesirable resonances at V .
IN
IN
A small (0.1μF to 1μF) bypass capacitor between the
In continuous mode, the source current of the top
chip V pin and ground, placed close to the LTC7802, is
IN
MOSFET is a square wave of duty cycle V /V . To pre-
OUT IN
also suggested. An optional 1Ω to 10Ω resistor placed
between CIN and the VIN pin provides further isolation
from a noisy input supply.
vent large voltage transients, a low ESR capacitor sized
for the maximum RMS current of one channel must be
used. At maximum load current IMAX, the maximum RMS
capacitor current is given by:
The selection of COUT is driven by the effective series
resistance (ESR). Typically, once the ESR requirement
is satisfied, the capacitance is adequate for filtering. The
IMAX
1/2
⎦
⎡
⎤
CIN Required IRMS
≈
V
OUT )(
V − V
IN
OUT
(
)
⎣
V
IN
output ripple (ΔV ) is approximated by:
OUT
⎛
⎜
⎝
⎞
1
ΔVOUT ≈ ΔIL ESR+
⎟
8fCOUT
⎠
Rev. 0
19
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LTC7802
APPLICATIONS INFORMATION
where f is the operating frequency, C
is the output
RUN Pins and Undervoltage Lockout
OUT
capacitance and ΔI is the ripple current in the inductor.
The output ripple iLs highest at maximum input voltage
The two channels of the LTC7802 are enabled using
the RUN1, and RUN2 pins. The RUN pins have a rising
threshold of 1.2V with 100mV of hysteresis. Pulling a
RUN pin below 1.1V shuts down the main control loop
and resets the soft-start for that channel. Pulling both
RUN pins below 0.7V disables the controllers and most
since ΔI increases with input voltage.
L
Setting the Output Voltage
The LTC7802 output voltages are each set by an external
feedback resistor divider carefully placed across the out-
put, as shown in Figure 4. The regulated output voltage
is determined by:
internal circuits, including the INTV LDOs. In this state,
CC
the LTC7802 draws only ≈1.5μA of quiescent current.
The RUN pins are high impedance and must be externally
pulled up/down or driven directly by logic. Each RUN pin
can tolerate up to 40V (absolute maximum), so it can be
⎛
⎞
RB
RA
V
OUT = 0.8V 1+
⎜
⎟
⎝
⎠
conveniently tied to V in always-on applications where
IN
the controller is enabled continuously and never shut
ꢊ
ꢍꢎꢈ
down. Do not float the RUN pins.
The RUN pins can also be configured as precise under-
voltage lockouts (UVLOs) on the input supply with a resis-
R
ꢋ
R
ꢌ
ꢉ
ꢃꢃ
ꢅꢆꢂ ꢇꢈꢉꢀꢁ0ꢂ
ꢊ
ꢃꢋ
tor divider from V to ground, as shown in Figure 5.
IN
The V UVLO thresholds can be computed as:
IN
ꢀꢁ0ꢂ ꢃ0ꢄ
⎛
⎞
R1
R2
UVLO RISING = 1.2V 1+
Figure 4. Setting Output Voltage
⎜
⎟
⎝
⎠
Place resistors R and R very close to the V pin to
A
B
FB
⎛
⎞
R1
R2
UVLO FALLING = 1.1V 1+
minimize PCB trace length and noise on the sensitive V
FB
⎜
⎟
⎝
⎠
node. Great care should be taken to route the V trace
FB
away from noise sources, such as the inductor or the
ꢌ
ꢍꢋ
SW trace. To improve frequency response, a feedforward
ꢅꢆꢂ ꢇꢈꢉꢀꢁ0ꢂ
Rꢊꢋ
Rꢅ
Rꢂ
capacitor (C ) may be used.
FF
For applications with multiple output voltage levels, select
channel 1 to be the lowest output voltage that is greater
ꢀꢁ0ꢂ ꢃ0ꢄ
–
than 3.2V. When the SENSE1 pin (connected to V
)
OUT1
Figure 5. Using the RUN Pins As a UVLD
is above 3.2V, it biases some internal circuitry instead of
V , thereby increasing light load Burst Mode efficiency.
SIiNmilarly, connect EXTVCC to the lowest output voltage
that is greater than the 4.8V maximum EXTVCC rising
switch-over threshold. EXTVCC then supplies the high
current gate drivers and relieves additional quiescent
The current that flows through the R1-R2 divider directly
adds to the shutdown, sleep, and active current of the
LTC7802, and care should be taken to minimize the
impact of this current on the overall efficiency of the
application circuit. Resistor values in the MΩ range may
be required to keep the impact on quiescent shutdown
and sleep currents low.
current from V , further reducing the V pin current to
IN
IN
≈1μA in sleep.
Rev. 0
20
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LTC7802
APPLICATIONS INFORMATION
Soft-Start and Tracking (TRACK/SS Pins)
ꢅ
ꢅ
ꢆꢇꢈꢉꢊꢋꢌRꢍ
The start-up of each V
is controlled by the voltage on
OUT
the TRACK/SS pin (TRACK/SS1 for channel 1, TRACK/
SS2 for channel 2). When the voltage on the TRACK/SS
pin is less than the internal 0.8V reference, the LTC7802
regulates the V pin voltage to the voltage on the TRACK/
SS pin insteadFBof the internal reference. The TRACK/SS
pin can be used to program an external soft-start function
ꢎꢏꢋꢇꢊꢐꢉꢅꢌꢍ
ꢀꢁ0ꢂ ꢃ0ꢀꢄ
ꢋꢒꢈꢌ
or to allow V
to track another supply during start-up.
OUT
(6a) Coincident Tracking
Soft-start is enabled by simply connecting a capacitor
from the TRACK/SS pin to ground. An internal 12.5μA
current source charges the capacitor, providing a linear
ramping voltage at the TRACK/SS pin. The LTC7802 will
ꢅ
ꢅ
ꢆꢇꢈꢉꢊꢋꢌRꢍ
regulate its feedback voltage (and hence V ) according
OUT
to the voltage on the TRACK/SS pin, allowing V
to
OUT
ꢎꢏꢋꢇꢊꢐꢉꢅꢌꢍ
rise smoothly from 0V to its final regulated value. For a
desired soft-start time, t , select a soft-start capacitor
SS
C
= t • 15μF/sec.
SS
SS
ꢀꢁ0ꢂ ꢃ0ꢀꢄ
ꢋꢒꢈꢌ
Alternatively, the TRACK/SS pins can be used to track two
or more supplies during start-up, as shown qualitatively
in Figure 6a and Figure 6b. To do this, a resistor divider
should be connected from the master supply (V ) to the
TRACK/SS pin of the slave supply (VOUT), as sXhown in
(6b) Ratiometric Tracking
Figure 6. Two Different Modes of Output Voltage Tracking
ꢇ
ꢏꢐꢅ
Figure 7. During start-up V
will track V according to
OUT
X
the ratio set by the resistor divider:
VX RA
TRACKA +RTRACKB
VOUT RTRACKA
R
ꢈ
ꢉ
ꢇ
ꢃꢈ
R
=
•
R
ꢇ
ꢑ
RA +RB
ꢄꢅꢆꢀꢁ0ꢂ
R
R
ꢅRꢉꢆꢊꢈ
ꢅRꢉꢆꢊꢉ
Set R
= R and R
X
= R for coincident track-
TRACKB B
TRACKA
A
ꢅRꢉꢆꢊꢋꢌꢌꢍꢎꢂ
ing (V
= V during start-up).
OUT
Single Output 2-Phase Operation
ꢀꢁ0ꢂ ꢃ0ꢁ
For high power applications, the two channels can be
operated in a 2-phase single output configuration. The
channels switch 180° out-of-phase, which reduces the
required output capacitance in addition to the required
input capacitance and power supply induced noise. To
Figure 7. Using the TRACK/SS Pin for Tracking
inductor currents. Figure 10 is a typical application con-
figured for single output 2-phase operation.
configure the LTC7802 for 2-phase operation, tie V to
FB2
INTV Regulators
CC
INTV , ITH2 to ground, and RUN2 to RUN1.
CC
The LTC7802 features two separate internal low dropout
The RUN1, VFB1, ITH1, TRACK/SS1 pins are then used
to control both channels, but each channel uses its own
ICMP and IR comparators to monitor their respective
linear regulators (LDOs) that supply power at the INTV
CC
pin from either the V pin or the EXTV pin depending
IN
CC
Rev. 0
21
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LTC7802
APPLICATIONS INFORMATION
on the EXTV pin voltage. INTV powers the MOSFET
LTC7802’s switching regulator outputs (4.8V ≤ VOUT ≤
gate driversCaCnd most of the intCeCrnal circuitry. The V
30V) during normal operation and from the V LDO when
IN
IN
LDO and the EXTV LDO each regulate INTV to 5.1V
the output is out of regulation (e.g., start-up, short-cir-
CC
CC
and can provide a peak current of at least 100mA.
cuit). If more current is required through the EXTV LDO
CC
than is specified, an external Schottky diode can be added
The INTV pin must be bypassed to ground with a min-
imum ofC4C.7μF ceramic capacitor, placed as close as
possible to the pin. An additional 1μF ceramic capacitor
between the EXTV and INTV pins. In this case, do not
CC
CC
apply more than 6V to the EXTV pin.
CC
placed directly adjacent to the INTV and GND pins is
Significant efficiency and thermal gains can be realized
CC
also highly recommended to supply the high frequency
by powering INTV from an output, since the V cur-
CC IN
transient currents required by the MOSFET gate drivers.
rent resulting from the driver and control currents will be
scaled by a factor of VOUT/(VIN • Efficiency). For 5V to 30V
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the max-
imum junction temperature rating for the LTC7802 to be
regulator outputs, this means connecting the EXTV pin
CC
directly to V . Tying the EXTV pin to an 8.5V supply
OUT
CC
reduces the junction temperature in the previous example
from 125°C to:
exceeded. The INTV current, which is dominated by the
CC
gate charge current, may be supplied by either the VIN
LDO or the EXTVCC LDO. When the voltage on the EXTVCC
T = 70°C + (35mA)(8.5V)(43°C/W) = 83°C
J
pin is less than 4.7V, the V LDO is enabled. Power dissi-
IN
However, for 3.3V and other low voltage outputs, addi-
pation for the IC in this case is equal to V • IINTV . The
IN
CC
tional circuitry is required to derive INTV power from
CC
gate charge current is dependent on operating frequency
as discussed in the Efficiency Considerations section. The
junction temperature can be estimated by using the equa-
tions given in Note 2 of the Electrical Characteristics. For
the output.
The following list summarizes the four possible connec-
tions for EXTV :
CC
example, the LTC7802 INTV current is limited to less
CC
1. EXTV grounded. This will cause INTV to be pow-
CC
CC
than 35mA from a 36V supply when not using the EXTV
supply at a 70°C ambient temperature:
CC
ered from the internal VIN LDO resulting in an efficiency
penalty of up to 10% or more at high input voltages.
T = 70°C + (35mA)(36V)(43°C/W) = 125°C
J
2. EXTV connected directly to one of the regulator out-
CC
puts. This is the normal connection for an application
with an output in the range of 5V to 30V and provides
the highest efficiency. If both outputs are in the 5V to
30V range, connect EXTVCC to the lesser of the two
outputs to maximize efficiency.
To prevent the maximum junction temperature from being
exceeded, the input supply current must be checked
while operating in continuous conduction mode (MODE
= INTV ) at maximum V .
CC
IN
When the voltage applied to EXTVCC rises above 4.7V (typ-
3. EXTV connected to an external supply. If an external
ical), the V LDO is turned off and the EXTV LDO is
CC
IN
enabled. The EXTVCC LDO remains on as loCnCg as the
supply is available, it may be used to power EXTV
CC
provided that it is compatible with the MOSFET gate
drive requirements. This supply may be higher or lower
than V ; however, a lower EXTV voltage results in
voltage applied to EXTV remains above approximately
CC
4.5V. The EXTV LDO attempts to regulate the INTV
CC
CC
voltage to 5.1V, so while EXTV is less than 5.1V, the
IN
CC
CC
higher efficiency.
LDO is in dropout and the INTVCC voltage is approximately
equal to EXTV . When EXTV is greater than 5.1V (up
CC
to an absolute maximum of C3C0V), INTV is regulated
4. EXTVCC connected to an output-derived boost or
charge pump. For regulators where both outputs are
below 5V, efficiency gains can still be realized by con-
CC
to 5.1V. Using the EXTVCC LDO allows the MOSFET
driver and control power to be derived from one of the
necting EXTV to an output-derived voltage that has
CC
been boosted to greater than 4.8V.
Rev. 0
22
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LTC7802
APPLICATIONS INFORMATION
Topside MOSFET Driver Supply (C , D )
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to
skip cycles. The output voltage will continue to be reg-
ulated, but the ripple voltage and current will increase.
The minimum on-time for the LTC7802 is approximately
40ns. However, as the peak sense voltage decreases the
minimum on-time for gradually increases up to about
60ns. This is of particular concern in forced continuous
applications with low ripple current at light loads. If the
duty cycle drops below the minimum on-time limit in this
situation, a significant amount of cycle skipping can occur
with correspondingly larger current and voltage ripple.
B
B
External bootstrap capacitors C connected to the BOOST
B
pins supply the gate drive voltages for the topside MOSFETs.
Capacitor C in the Functional Diagram is charged though
B
external diode D from INTV when the SW pin is low.
B
CC
When one of the topside MOSFETs is to be turned on, the
driver places the C voltage across the gate-source of the
B
desired MOSFET. This enhances the MOSFET and turns on
the topside switch. The switch node voltage, SW, rises to
VIN and the BOOST pin follows. With the topside MOSFET
on, the boost voltage is above the input supply: V
=
BOOST
B
V + V
. The value of the boost capacitor C needs
IN
INTVCC
to be 100 times that of the total input capacitance of the
topside MOSFET(s). For a typical application, a value of
Fault Conditions: Current Limit and Foldback
The LTC7802 includes current foldback to reduce the load
current when the output is shorted to ground. If the output
voltage falls below 50% of its regulation point, then the
maximum sense voltage is progressively lowered from
100% to 40% of its maximum value. Under short-circuit
conditions with very low duty cycles, the LTC7802 will
begin cycle skipping to limit the short circuit current. In
this situation the bottom MOSFET dissipates most of the
power but less than in normal operation. The short-circuit
ripple current is determined by the minimum on-time,
C = 0.1μF is generally sufficient.
B
The external diode DB can be a Schottky diode or sili-
con diode, but in either case it should have low leakage
and fast recovery. The reverse breakdown of the diode
must be greater than V
. Pay close attention to the
IN(MAX)
reverse leakage at high temperatures where it generally
increases substantially.
A leaky diode not only increases the quiescent current
of the regulator, but it can create current path from the
BOOST pin to INTVCC. This will cause INTVCC to rise if
the diode leakage exceeds the current consumption on
t
≈ 40ns, the input voltage and inductor value:
ON(MIN)
ΔI
L(SC)
= t
• V /L
ON(MIN) IN
INTV , which is primarily a concern in Burst Mode oper-
CC
The resulting average short-circuit current is:
= 40% • I − ΔI /2
ation where the load on INTV can be very small. There
CC
I
SC
is an internal voltage clamp on INTV that prevents the
LIM(MAX)
L(SC)
CC
INTV voltage from running away, but this clamp should
be reCgCarded as a failsafe only.
Fault Conditions: Overvoltage Protection (Crowbar)
The overvoltage crowbar is designed to blow a system
input fuse when the output voltage of the regulator rises
much higher than nominal levels. The crowbar causes
huge currents to flow that blow the fuse to protect against
a shorted top MOSFET if the short occurs while the con-
troller is operating.
Minimum On-Time Considerations
Minimum on-time t
is the smallest time duration
ON(MIN)
that the LTC7802 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the MOSFET. Low duty cycle
applications may approach this minimum on time limit
and care should be taken to ensure that:
If an output voltage rises 10% above the set regulation
point, the top MOSFET is turned off and the bottom
MOSFET is turned on until the overvoltage condition is
cleared. The bottom MOSFET remains on continuously
VOUT
tON(MIN)
<
V • f
IN
OSC
for as long as the overvoltage condition persists; if V
OUT
Rev. 0
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LTC7802
APPLICATIONS INFORMATION
returns to a safe level, normal operation automatically
resumes.
to at least 2.2V and down to 0.5V or less. Note that the
LTC7802 can only be synchronized to an external clock
frequency within the range of 100kHz to 3MHz.
A shorted top MOSFET will result in a high current con-
dition which will open the system fuse. The switching
regulator will regulate properly with a leaky top MOSFET
by altering the duty cycle to accommodate the leakage.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
Fault Conditions: Overtemperature Protection
At higher temperatures, or in cases where the internal
power dissipation causes excessive self-heating (such as
a short from INTV to ground) internal overtemperature
shutdown circuitrCyCwill shut down the LTC7802. When
%Efficiency = 100% – (L1 + L2 + L3 + ...)
the internal die temperature exceeds 180°C, the INTV
CC
where L1, L2, etc. are the individual losses as a percent-
age of input power.
LDO and gate drivers are disabled. When the die cools
to 160°C, the LTC7802 enables the INTVCC LDO and
resumes operation beginning with a soft-start startup.
Long-term overstress (TJ > 125°C) should be avoided
as it can degrade the performance or shorten the life of
the part.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC7802 circuits: 1) IC V current, 2) INTV
IN
CC
2
regulator current, 3) I R losses, 4) Topside MOSFET tran-
sition losses.
Phase-Locked Loop and Frequency Synchronization
1. The VIN current is the DC supply current given in
the Electrical Characteristics table, which excludes
MOSFET driver and control currents. Other than at very
The LTC7802 has an internal phase-locked loop (PLL)
which allows the turn-on of the top MOSFET of controller
1 to be synchronized to the rising edge of an external
clock signal applied to the PLLIN/SPREAD pin. The turn
on of controller 2’s top MOSFET is thus 180° out of phase
with the external clock.
light loads in burst mode, V current typically results
IN
in a small (<0.1%) loss.
2. INTV current is the sum of the MOSFET driver and
CC
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge, dQ, moves
from INTVCC to ground. The resulting dQ/dt is a current
Rapid phase-locking can be achieved by using the FREQ
pin to set a free-running frequency near the desired
synchronization frequency. Before synchronization,
the PLL is prebiased to the frequency set by the FREQ
pin. Consequently, the PLL only needs to make minor
adjustments to achieve phase-lock and synchronization.
Although it is not required that the free-running frequency
be near the external clock frequency, doing so will pre-
vent the oscillator from passing through a large range of
frequencies as the PLL locks.
out of INTV that is typically much larger than the
CC
control circuit current. In continuous mode, I
GATECHG
= f (Q Q ), where Q and Q are the gate charges
SW T +
B
T
B
of the top and bottom MOSFETs.
Supplying INTVCC from an output-derived source
through EXTVCC will scale the VIN current required
When synchronized to an external clock, the LTC7802
operates in pulse-skipping mode if it is selected by the
MODE pin, or in forced continuous mode otherwise. The
LTC7802 is guaranteed to synchronize to an external
clock applied to the PLLIN/SPREAD pin that swings up
for the driver and control circuits by a factor of V
/
OUT
(V • Efficiency). For example, in a 20V to 5V applica-
IN
tion, 10mA of INTV current results in approximately
CC
2.5mA of VIN current. This reduces the mid-current
loss from 10% or more (if the driver was powered
directly from V ) to only a few percent.
IN
Rev. 0
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LTC7802
APPLICATIONS INFORMATION
3. I R losses are predicted from the DC resistances of the
2
Checking Transient Response
input fuse (if used), MOSFET, inductor, current sense
resistor, and input and output capacitor ESR. In contin-
uous mode the average output current flows through
L and RSENSE, but is chopped between the top and
bottom MOSFETs. If the two MOSFETs have approx-
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V
shifts by an
OUT
amount equal to ΔILOAD • (ESR), where ESR is the effective
imately the same R
, then the resistance of one
DS(ON)
series resistance of C . ΔI
also begins to charge or
OUT
discharge C
generating tLhOeAfDeedback error signal that
MOSFET can simply be summed with the resistances
OUT
2
of L, R
and ESR to obtain I R losses.
SENSE
forces the regulator to adapt to the current change and
return VOUT to its steady-state value. During this recovery
For example, if each R
SENSE
= 30mΩ, R = 50mΩ,
L
DS(ON)
R
= 10mΩ and ESR = 40mΩ (sum of both input
time V
can be monitored for excessive overshoot or
OUT
and output capacitance losses), then the total resis-
tance is 130mΩ. This results in losses ranging from
3% to 13% as the output current increases from 1A to
5A for a 5V output, or a 4% to 20% loss for a 3.3V out-
put. This percentage loss varies as the inverse square
ringing, which would indicate a stability problem.
OPTI-LOOP compensation allows the transient response
to be optimized over a wide range of output capaci-
tance and ESR values. The availability of the ITH pin not
only allows optimization of control loop behavior, but it
also provides a DC coupled and AC filtered closed loop
response test point. The DC step, rise time and settling
at this test point truly reflects the closed loop response.
Assuming a predominantly second order system, phase
margin and/or damping factor can be estimated using the
percentage of overshoot seen at this pin. The bandwidth
can also be estimated by examining the rise time at the
pin. The ITH external components shown in the Typical
Applications circuits provide an adequate starting point
for most applications.
of V
for the same external components and output
OUT
power level. The combined effects of increasingly lower
output voltages and higher currents required by high
performance digital systems is not doubling but qua-
drupling the importance of loss terms in the switching
regulator system!
4. Transition losses apply only to the top MOSFETs and
become significant only when operating at higher
input voltages (typically 15V or greater). Transition
losses can be estimated from the equation for the
main switch power dissipation in the Power MOSFET
Selection section.
The ITH series R -C filter sets the dominant pole-zero
C
C
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their initial values) to optimize tran-
sient response once the final PC layout is done and the
particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 80%
of full-load current having a rise time of 1μs to 10μs will
produce output voltage and ITH pin waveforms that will
give a sense of the overall loop stability without breaking
the feedback loop.
Other hidden losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these system level losses during the
design phase. The internal battery and fuse resistance
losses can be minimized by making sure that C has ade-
IN
quate charge storage and very low ESR at the switching
frequency. A 25W supply will typically require a minimum
of 20μF to 40μF of capacitance having a maximum of
20mΩ to 50mΩ of ESR. The LTC7802 2-phase architec-
ture typically halves this input capacitance requirement
over competing solutions. Other losses including induc-
tor core losses generally account for less than 2% total
additional loss.
Placing a power MOSFET directly across the output
capacitor and driving the gate with an appropriate signal
generator is a practical way to produce a realistic load
step condition. The initial output voltage step resulting
Rev. 0
25
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LTC7802
APPLICATIONS INFORMATION
inductor value can then be calculated from the follow-
ing equation:
from the step change in output current may not be within
the bandwidth of the feedback loop, so this signal can-
not be used to determine phase margin. This is why it is
better to look at the ITH pin signal which is in the feed-
back loop and is the filtered and compensated control
loop response. The gain of the loop will be increased
⎛
⎞
VOUT
fSW ΔI
VOUT
L =
1–
= 0.4µH
⎜
⎟
V
(
)
⎝
⎠
L
IN(NOM)
The highest value of ripple current occurs at the maxi-
by increasing R and the bandwidth of the loop will be
C
mum input voltage. In this case the ripple at V = 22V
IN
increased by decreasing CC. If RC is increased by the same
factor that C is decreased, the zero frequency will be kept
the same, thCereby keeping the phase shift the same in the
most critical frequency range of the feedback loop. The
output voltage settling behavior is related to the stability
of the closed-loop system and will demonstrate the actual
overall supply performance.
is 35%
3. Verify that the minimum on-time of 40ns is not vio-
lated. The minimum on-time occurs at V
:
IN(MAX)
VOUT
IN(MAX)(fSW)
tON(MIN)
=
= 150ns
V
A second, more severe transient is caused by switching
in loads with large (>1μF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
This is more than sufficient to satisfy the minimum on
time requirement. If the minimum on time is violated,
the LTC7802 skips pulses at high input voltage, result-
ing in lower frequency operation and higher inductor
current ripple than desired. If undesirable, this behav-
ior can be avoided by decreasing the frequency (with
the inductor value accordingly adjusted) to avoid oper-
ation near the minimum on-time.
with C , causing a rapid drop in V . No regulator can
OUT
alter itOsUdTelivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
C
to C
is greater than 1:50, the switch rise time
LOAD
OUT
should be controlled so that the load rise time is limited
to approximately C • 25μs/μF. Thus a 10μF capacitor
4. Select the RSENSE resistor value. The peak inductor
current is the maximum DC output current plus half of
the inductor ripple current. Or 20A • (1+0.30/2) = 23A
in this case. The RSENSE resistor value can then be cal-
culated based on the minimum value for the maximum
current sense threshold (45mV):
LOAD
would require a 250μs rise time, limiting the charging
current to about 200mA.
Design Example
As a design example, assume VIN(NOMINAL) = 12V, VIN(MAX)
= 22V, V
= 3.3V, I
= 20A, and f = 1MHz.
OUT SW
OUT
45mV
23A
RSENSE
≤
≅ 2mΩ
1. Set the operating frequency. The frequency is not one
of the internal preset values, so a resistor from the
FREQ pin to GND is required, with a value of:
To allow for additional margin, a lower value R
SENSE
may be used (for example, 1.8mΩ); however, be sure
37MHz
1MHz
that the inductor saturation current has sufficient mar-
RFREQ(inkΩ)=
–37kΩ
gin above V
/R
, where the maximum
SENSE(MAX)
SENSE(MAX) SENSE
value of 55mV is used for V
.
2. Determine the inductor value. Initially select a value
based on an inductor ripple current of 30%. The
For this low inductor value and high current applica-
tion, an RC filter into the sense pins should be used
to compensate for the parasitic inductance (ESL) of
the sense resistor. Assuming an RSENSE geometry
of 1225 with a parasitic inductance of 0.2nH, the RC
Rev. 0
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filter time constant should be RC = ESL/RSENSE
=
output ripple in continuous mode will be highest at the
maximum input voltage. The output voltage ripple due
to ESR is approximately:
0.2nH/2mΩ = 100ns, which may be implemented with
+
100Ω resistor in series with the SENSE pin and 1nF
+
–
capacitor between SENSE and SENSE .
V
= ESR • ΔI = 3mΩ • 6A = 18mV
L P-P
ORIPPLE
5. Select the feedback resistors. If very light load effi-
ciency is required, high value feedback resistors may
be used to minimize the current due to the feedback
divider. However, in most applications a feedback
divider current in the range of 10μA to 100μA or more
is acceptable. For a 50μA feedback divider current,
On the 3.3V output, this is equal to 0.55% of peak to
peak voltage ripple.
8. Determine the bias supply components. Since the reg-
ulated output is not greater than the EXTV switcho-
CC
ver threshold (4.7V), it cannot be used to bias INTV .
CC
However, if another supply is available, for example
R = 0.8V/50μA = 16kΩ. R can then be calculated as
A
B
if the other channel is regulating to 5V, connect that
R = R (3.3V/0.8V – 1) = 50kΩ.
B
A
supply to EXTV to improve the efficiency.
CC
6. Select the MOSFETs. The best way to evaluate MOSFET
performance in a particular application is to build and
test the circuit on the bench, facilitated by an LTC7802
demo board. However, an educated guess about the
application is helpful to initially select MOSFETs. Since
this is a high current, low voltage application, I2R
losses will likely dominate over transition losses for the
top MOSFET. Therefore, choose a MOSFET with lower
For a 6.5ms soft-start, select a 0.1μF capacitor for the
TRACK/SS pin. As a first pass estimate for the bias
components, select CINTVCC = 4.7μF, boost supply
capacitor C = 0.1μF and low forward drop boost sup-
B
ply diode CMDSH-4E from Central Semiconductor.
9. Determine and set application-specific parameters.
Set the MODE pin based on the trade-off of light load
efficiency and constant frequency operation. Set the
PLLIN/SPREAD pin based on whether a fixed, spread
spectrum, or phase-locked frequency is desired. The
RUN pin can be used to control the minimum input
voltage for regulator operation or can be tied to VIN
for always-on operation. Use ITH compensation com-
ponents from the typical applications as a first guess,
check the transient response for stability, and modify
as necessary.
R
as opposed to lower gate charge to minimize
DS(ON)
the combined loss terms. The bottom MOSFET does
not experience transition losses, and its power loss is
2
generally dominated by I R losses. For this reason,
the bottom MOSFET is typically chosen to be of lower
R
DS(ON)
and subsequently higher gate charge than the
top MOSFET.
Due to the high current in this application, two MOSFETs
may needed in parallel to more evenly balance the dis-
sipated power and to lower the RDS(ON). Be sure to
select logic-level threshold MOSFETs, since the gate
PC Board Layout Checklist
drive voltage is limited to 5.1V (INTV ). Minimize the
CC
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. Figure 8 illustrates the current waveforms present
in the various branches of the synchronous regulators
operating in the continuous mode. Check the following
in your layout:
inductance of the TG and BG gate drive traces and their
respective return paths to the controller IC (SW and
GND) by using wide traces and multiple parallel vias.
7. Select the input and output capacitors. C is chosen
IN
for an RMS current rating of at least 10A (I /2, with
OUT
margin) at temperature assuming only this channel
1. Are the top N-channel MOSFETs located within 1cm of
each other with a common drain connection at CIN?
Decoupling capacitors for the two channels they should
be close to each other to avoid a large resonant loop.
is on. C
is chosen with an ESR of 3mΩ for low
OUT
output ripple. Multiple capacitors connected in parallel
may be required to reduce the ESR to this level. The
Rev. 0
27
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APPLICATIONS INFORMATION
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Figure 8. Branch Current Waveforms for Bucks
2. Are the signal and power grounds kept separate?
The combined IC ground pin and the ground return
The feedback resistor connections should not be along
the high current input feeds from the input capacitor(s).
of C
must return to the combined C
(–) ter-
4. Are the SENSE– and SENSE+ leads routed together with
minimum PC trace spacing? Route these traces away
from the high frequency switching nodes, on an inner
INTVCC
OUT
minals. The area of the “hot loop” formed by the top
N-channel MOSFET, bottom N-channel MOSFET and the
high frequency (ceramic) input capacitors, as shown
in Figure 8, should be minimized with short leads, pla-
nar connections, and multiple paralleled vias where
needed. The output capacitor (–) terminals should be
connected as close as possible to the (–) terminals of
the input capacitor.
+
layer if possible. The filter capacitor between SENSE
–
and SENSE should be as close as possible to the IC.
Ensure accurate current sensing with Kelvin connec-
tions at the sense resistor.
5. Is the INTV decoupling capacitor connected close
CC
to the IC, between the INTV and the power ground
CC
3. Do the LTC7802 V pins’ resistive dividers connect to
FB
pin? This capacitor carries the MOSFET drivers’ cur-
rent peaks. An additional 1μF ceramic capacitor placed
immediately next to the INTV and GND pins can help
improve noise performanceCsCubstantially. The boost
diodes should have separate routes directly to the
the (+) terminals of C ? The resistive divider must
OUT
be connected between the (+) terminal of COUT and
signal ground. Place the divider close to the V pin to
minimize noise coupling into the sensitive VFB node.
FB
INTV capacitor near the IC, not shared with any sig-
CC
nal connections to INTV .
CC
Rev. 0
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LTC7802
APPLICATIONS INFORMATION
Overcompensation of the loop can be used to tame a
poor PC layout if regulator bandwidth optimization is not
required. Only after each controller is checked for its indi-
vidual performance should both controllers be turned on
at the same time. A particularly difficult region of opera-
tion is when one controller channel is nearing its current
comparator trip point when the other channel is turning
on its top MOSFET. This occurs around 50% duty cycle
on either channel due to the phasing of the internal clocks
and may cause minor duty cycle jitter.
6. Keep the switching nodes (SW1, SW2), top gate nodes
(TG1, TG2), and boost nodes (BOOST1, BOOST2) away
from sensitive small-signal nodes, especially from the
other channel’s voltage and current sensing feedback
pins. All of these nodes have very large and fast-moving
signals and therefore should be kept on the output side
of the LTC7802 and occupy minimum PC trace area.
Minimize the inductance of the TG and BG gate drive
traces and their respective return paths to the controller
IC (SW and GND) by using wide traces and multiple
parallel vias.
Reduce VIN from its nominal level to verify operation
of the regulator in dropout. Check the operation of the
undervoltage lockout circuit by further lowering VIN while
monitoring the outputs to verify operation. Investigate
whether any problems exist only at higher output cur-
rents or only at higher input voltages. If problems coincide
with high input voltages and low output currents, look for
capacitive coupling between the BOOST, SW, TG, and pos-
sibly BG connections and the sensitive voltage and current
pins. The capacitor placed across the current sensing pins
needs to be placed immediately adjacent to the pins of
the IC. This capacitor helps to minimize the effects of dif-
ferential noise injection due to high frequency capacitive
coupling. If problems are encountered with high current
output loading at lower input voltages, look for inductive
7. Use a modified star ground technique: a low imped-
ance, large copper area central grounding point on the
same side of the PC board as the input and output
capacitors with tie-ins for the bottom of the INTVCC
decoupling capacitor, the bottom of the voltage feed-
back resistive divider and the GND pin of the IC.
For more detailed layout guidance, see Analog Devices
Application Notes AN136 “PCB Layout Considerations
for Non-Isolated Switching Power Supplies” and AN139
“Power Supply Layout and EMI”.
PC Board Layout Debugging
Start with one controller on at a time. It is helpful to use
a DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output
switching node (SW pin) to synchronize the oscilloscope
to the internal oscillator and probe the actual output
voltage as well. Check for proper performance over the
coupling between C , the top MOSFET, and the bottom
IN
MOSFET components to the sensitive current and voltage
sensing traces. In addition, investigate common ground
path voltage pickup between these components and the
GND pin of the IC.
operating voltage and current range expected in the appli
-
An embarrassing problem, which can be missed in an
otherwise properly working switching regulator, results
when the current sensing leads are hooked up backwards.
The output voltage under this improper hookup will still
be maintained but the advantages of current mode control
will not be realized. Compensation of the voltage loop
will be much more sensitive to component selection. This
behavior can be investigated by temporarily shorting out
the current sensing resistor—don’t worry, the regulator
will still maintain control of the output voltage.
cation. The frequency of operation should be maintained
over the input voltage range down to dropout and until
the output load drops below the low current operation
threshold—typically 25% of the maximum designed cur-
rent level in Burst Mode operation.
The duty cycle percentage should be maintained from
cycle to cycle in a well-designed, low noise PCB imple-
mentation. Variation in the duty cycle at a subharmonic
rate can suggest noise pickup at the current or voltage
sensing inputs or inadequate loop compensation.
Rev. 0
29
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LTC7802
TYPICAL APPLICATIONS
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ꢀꢁꢂꢃ
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ꢄꢄ
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ꢀ
ꢁꢂ
ꢀ0ꢁꢂ
ꢃꢄ
Rꢀꢁꢂ
ꢀꢁꢂ
ꢀ
ꢁꢂ
Rꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ
ꢃ00ꢄꢅ
ꢆꢇꢈ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢁꢂꢃꢄ
ꢀꢁꢁꢂꢃꢄ
ꢀꢁ
0.ꢂꢃꢄ
ꢀꢁ
ꢂ.ꢃꢄꢅ
0.ꢀꢁꢂ
0.ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ0ꢅ
20Ω
ꢄ
ꢄ
ꢀꢁꢂꢀꢁꢃ
ꢀꢁꢂꢀꢁꢃ
2mΩ
ꢀꢁ0ꢂ
ꢀꢁ.ꢂꢃ
3mΩ
ꢀꢁꢂ
ꢀꢁꢂ
ꢄ
ꢄ
ꢀꢁꢂꢀꢁꢃ
ꢀꢁꢂꢀꢁꢃ
ꢀ
ꢁꢂꢃꢄ
ꢅ.ꢅꢀꢆ ꢄꢇꢈ
ꢀ
ꢁꢂꢃꢄ
ꢆ
ꢀꢁꢂꢃ
ꢄꢄ
ꢀ
ꢁꢂꢃꢄ
ꢅꢀ ꢇ ꢈ0ꢉ
ꢀ00ꢁꢂ
ꢃꢄ
ꢀ
ꢅꢅ0ꢆꢇ
ꢈ.ꢅꢉ
ꢁꢂꢃꢄ
ꢀꢁꢂꢃ
ꢀꢁꢂꢂꢃꢄ
ꢀꢁꢂꢂꢃꢄ
ꢀ00ꢁꢂ
ꢃꢄ
ꢅꢅ0ꢆꢇ
ꢈ.ꢅꢉ
ꢀ
ꢀ
ꢁꢂꢃ
ꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁ.ꢂꢃ
ꢀRꢁꢂꢃꢄꢅꢅꢆ
ꢀRꢁꢂꢃꢄꢅꢅꢆ
ꢀꢀꢁ
ꢀ.ꢁꢂ
0.ꢀꢁꢂ
0.ꢀꢁꢂ
ꢀ00ꢁꢂ
ꢀꢁꢁꢂꢃꢄꢅꢀRꢆꢇꢈ
ꢀRꢁꢂ
ꢀ.ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢄꢄ
ꢀꢁꢂꢃ
ꢀ00ꢁꢂ
ꢀ.ꢀꢁꢂ
ꢀꢁꢂ
ꢀ.ꢁꢂꢃ
ꢀ
ꢃ ꢄꢅ0ꢆꢇꢈ
ꢁꢂ
ꢀꢁ0ꢂ ꢃ0ꢄꢅ
R
R
0 0
0
R
00
0
0
0
0
0
00
0
No-Load Burst Mode Input
Current vs Input Voltage
Efficiency vs Load Current
Short-Circuit Response
ꢀ00
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀ
ꢀꢁꢂꢃ ꢄꢃꢅꢆꢆꢇꢈꢉ ꢁꢆ
ꢀꢁRꢂꢃ ꢄꢅꢆꢇ ꢅꢈꢇRꢉꢃꢊꢅꢋ
ꢀꢁꢂꢃ ꢄꢅꢆꢁꢁꢇꢂ ꢈ ꢀꢁ
ꢀꢁꢂꢃ ꢄꢃꢅꢆꢆꢇꢈꢉ ꢁꢆ
ꢀ
ꢁꢂꢃꢄ
ꢅꢀꢆꢇꢈꢀ
ꢀꢁꢂꢃꢄꢅꢆR
ꢄꢃRRꢇꢁꢅ
ꢈꢉꢊꢂꢀꢋ
ꢀ ꢀ ꢁꢂꢃ
ꢀꢁ
ꢀꢁRꢂꢃꢄ ꢂꢁꢅꢆꢇꢅꢈꢁꢈꢉ ꢊꢁꢄꢃ
ꢀ
ꢀ ꢁꢂ
ꢀ
ꢀ ꢁ.ꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁ0ꢂ ꢃ0ꢄꢅ
ꢀ
ꢀ ꢁꢂꢃ
ꢀ
ꢀ ꢁꢂꢃ
ꢀ ꢁꢂꢃ
ꢀ ꢁꢂꢃ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ00ꢁꢂꢃꢄꢅꢆ
ꢀ
ꢀ ꢁꢂꢃ
ꢀ
ꢀ
ꢀ ꢁꢂꢃ
ꢀ
0
0
ꢀ
ꢀ
ꢀ
ꢀꢁ
ꢀ
ꢀ0
ꢀꢁ
ꢀ0
ꢀ ꢀꢁꢂꢃꢄꢅꢆ ꢇꢀꢈ
ꢀꢁ
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁ0ꢂ ꢃ0ꢄꢅ
ꢀꢁ0ꢂ ꢃ0ꢄꢅ
Figure 9. High Efficiency Dual 3.3V, 5V Step-Down Regulator with Spread Spectrum
Rev. 0
30
For more information www.analog.com
LTC7802
TYPICAL APPLICATIONS
ꢀꢁꢂꢃ
ꢄꢄ
ꢀ
ꢁꢂ
ꢀ
ꢁꢂ
ꢀꢁ
ꢃ.ꢄꢀ ꢅꢆ ꢇꢈꢀ
ꢉꢊꢀ ꢂꢆꢋꢁꢂꢌꢍ
ꢀ
ꢁꢂ
ꢀ0ꢁꢂ
ꢀ00ꢁꢂ
ꢀꢁꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂ 0.ꢁꢃꢄꢅ
Rꢀꢁꢂ
ꢀꢁꢂ
Rꢀꢁꢂ
0.ꢀꢁꢂ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂꢃ
ꢁꢂꢃ
ꢄꢄ
ꢀꢁꢂꢃꢄ0ꢅ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃ
150Ω
ꢀRꢁꢂ
ꢄ
ꢀꢁꢂꢀꢁꢃ
ꢀꢁꢂꢃ
ꢄꢄ
3mΩ
ꢀꢁꢂ
ꢀ.ꢁꢂꢃ
ꢄ
ꢀꢁꢂꢀꢁꢃ
ꢀ
ꢁꢂꢃ
ꢄ.ꢄꢀꢅ ꢆꢇꢈ
ꢄ
ꢀꢁꢂꢀꢁꢃ
ꢀꢁꢂꢂꢃꢄ
ꢀꢁꢂꢂꢃꢄ
ꢀꢁꢂꢃ
ꢀ
ꢀ.ꢁꢂꢃ
ꢄꢅ
ꢁꢂꢃ
ꢄꢅ0ꢆꢇ
ꢄꢈ
3mΩ
ꢀꢁ0ꢂ
ꢀꢁꢂ
150Ω
ꢄ
ꢀꢁꢂꢀꢁꢃ
ꢀ
ꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀRꢁꢂꢃꢄꢅꢅꢆ
ꢄꢄ
ꢀꢁ.ꢂꢃ
ꢀꢁ
ꢀꢁꢂꢃ
ꢀꢁ
0.ꢀꢁꢂ
ꢀ
ꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁꢁꢂꢃꢄ
ꢀꢁ0ꢂꢃ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂ 0.ꢃꢄꢅꢆ
ꢀꢁꢂ
ꢀRꢁꢂꢃꢄꢅꢅꢆ
0.ꢀꢁꢂ
ꢀꢁꢁꢂꢃꢄꢅꢀRꢆꢇꢈ
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢄꢄ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂ
ꢀꢁ0ꢂ ꢃꢄ0ꢅ
.
0
0
0
0
0 0
0
R
0
00
0
Load Step Transient Response
Efficiency vs Load Current
Output Voltage Noise Spectrum
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ0
ꢀꢁ00
ꢀꢁRꢂꢃꢄ ꢂꢁꢅꢆꢇꢅꢈꢁꢈꢉ ꢁꢊꢃRꢋꢆꢇꢁꢅ
ꢀꢁꢂꢁꢃꢂꢄR ꢅ ꢆꢁꢇꢈꢉꢊꢄꢋꢀ
Rꢀꢁ ꢂ ꢃ.ꢄꢅꢆꢇ
ꢀ
ꢁꢂꢃ
ꢄ00ꢅꢀꢆꢇꢈꢀ
ꢀꢁꢂꢃꢄꢅꢆR ꢇꢈ
ꢄꢃRRꢉꢁꢅ
ꢈ0ꢊꢋꢂꢀꢌ
ꢀꢁꢁꢂꢃꢄꢅꢀRꢆꢇꢈ ꢉ ꢊꢃꢈ
ꢀꢁꢁꢂꢃꢄꢅꢀRꢆꢇꢈ ꢉ ꢂꢃꢊꢋ
ꢀꢀ
ꢀꢁꢂꢃꢄꢅꢆR ꢇꢈ
ꢄꢃRRꢉꢁꢅ
ꢊ0ꢋꢌꢂꢀꢍ
ꢀꢁ0ꢂ ꢃꢄ0ꢅ
ꢀ
ꢀ ꢁꢂ
ꢀ ꢁꢂꢃ
ꢀ ꢁꢂꢃ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ0ꢁꢂꢃꢄꢅꢆ
0ꢀ ꢁꢂ ꢃꢄꢀ ꢅꢂꢀꢆ ꢇꢁꢈꢉ
ꢀ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢁ
ꢀ
0
ꢀ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀ0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ0
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊꢋ
ꢀꢁ0ꢂ ꢃꢄ0ꢅ
ꢀꢁ0ꢂ ꢃꢄ0ꢅ
Figure 10. 2.25MHz 2-Phase Single Output 3.3V, 24A Step-Down Regulator
Rev. 0
31
For more information www.analog.com
LTC7802
TYPICAL APPLICATIONS
ꢀ
ꢁꢂ
ꢃ.ꢄꢀ ꢅꢆ ꢇꢈꢀ
ꢀꢁꢂꢃ
ꢄꢄ
ꢀꢁꢂꢃ
ꢄꢄ
ꢀ
ꢁꢂ
ꢀ.ꢁꢂꢃ
ꢄꢀ
ꢀꢁ
Rꢀꢁꢂ
ꢀꢁꢂ
ꢀ
ꢁꢂ
Rꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ
ꢃ00ꢄꢅ
ꢆꢇꢈ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢁꢂꢃꢄ
ꢀꢁꢁꢂꢃꢄ
ꢀꢁ
ꢁꢂꢃ
ꢀꢁ
0.ꢁꢂꢃ
0.ꢀꢁꢂ
0.ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄ
33Ω
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ0ꢅ
60Ω
ꢄ
ꢄ
ꢀꢁꢂꢀꢁꢃ
ꢀꢁꢂꢀꢁꢃ
3mΩ
1.5mΩ
ꢀ.ꢀꢁꢂ
ꢀ.ꢀꢁꢂ
ꢄ
ꢄ
ꢀꢁꢂꢀꢁꢃ
ꢀꢁꢂꢀꢁꢃ
ꢀ
ꢁꢂꢃꢄ
ꢅ.ꢆꢀꢇ ꢄ0ꢈ
ꢀ
ꢁꢂꢃꢄ
ꢅꢀꢆ ꢄ0ꢇ
ꢀ
ꢁꢂꢃꢄ
ꢀꢀꢁꢂ
ꢀ
ꢀ00ꢁꢂ
ꢅꢅ0ꢆꢇ
ꢈꢉ
ꢀꢁꢂ
ꢁꢂꢃꢄ
ꢀꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢂꢃꢄ
ꢀꢁꢂꢂꢃꢄ
ꢀ00ꢁꢂ
ꢃꢄ
ꢅꢆ0ꢇꢈ
ꢄ.ꢉꢊ
ꢀ
ꢁꢂꢃ
ꢀ
ꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀ0.ꢁꢂ
ꢀRꢁꢂꢃꢄꢅꢅꢆ
ꢀRꢁꢂꢃꢄꢅꢅꢆ
ꢀꢁ
ꢀꢁ
0.ꢀꢁꢂ
0.ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀRꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁꢁꢂꢃꢄꢅꢀRꢆꢇꢈ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢄꢄ
ꢀꢁꢂꢃ
ꢀ.ꢀꢁꢂ
ꢄꢄ
ꢀ.ꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ.ꢁꢂꢃ
ꢀ
ꢃ ꢄ00ꢅꢆꢇ
ꢁꢂ
ꢀꢁ0ꢂ ꢃꢄꢄꢅ
R
R
00
0 0 0
R
0
0
00
R
00
00
R 0
R
00
Operating Waveforms
at VIN = 36V
VOUT1 Efficiency vs Load Current
VOUT2 Efficiency vs Load Current
ꢀ00
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ00
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀꢁRꢂꢃꢄ ꢂꢁꢅꢆꢇꢅꢈꢁꢈꢉ ꢁꢊꢃRꢋꢆꢇꢁꢅ
ꢀꢁRꢂꢃꢄ ꢂꢁꢅꢆꢇꢅꢈꢁꢈꢉ ꢁꢊꢃRꢋꢆꢇꢁꢅ
ꢀ
ꢁꢂꢃ
ꢀ
ꢀꢁꢂꢃ
ꢀ ꢁ.ꢂꢃ
ꢀ
ꢀꢁꢂꢃ
ꢀ ꢁꢂ
ꢄ0ꢀꢅꢆꢇꢀ
ꢀꢁꢂꢃꢄꢅꢆR ꢇꢈ
ꢄꢃRRꢉꢁꢅ
ꢊꢋꢌꢂꢀꢍ
ꢀ
ꢁꢂꢃ
ꢃ0ꢀꢄꢅꢆꢀ
ꢀꢁꢂꢃꢄꢅꢆR ꢇꢈ
ꢄꢃRRꢉꢁꢅ
ꢊꢋꢌꢂꢀꢍ
ꢀꢁ0ꢂ ꢃꢄꢄꢅ
ꢀ
ꢀ
ꢀ
ꢀ ꢁꢂ
ꢀ ꢁꢂꢃ
ꢀ ꢁꢂꢃ
ꢀ
ꢀ
ꢀ
ꢀ ꢁꢂ
ꢀ ꢁꢂꢃ
ꢀ ꢁꢂꢃ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ00ꢁꢂꢃꢄꢅꢆ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢁ
ꢀꢁ ꢂꢃꢁꢄ ꢃꢅ ꢆꢁꢇꢈ ꢇꢈꢁꢅꢅꢆꢂ
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ0
ꢀꢁ
0
ꢀ
ꢀ0
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁ0ꢂ ꢃꢄꢄꢅ
ꢀꢁ0ꢂ ꢃꢄꢄꢅ
Figure 11. High Efficiency 500kHz 1V, 20A and 2.5V, 10A Regulator with Spread Spectrum
Rev. 0
32
For more information www.analog.com
LTC7802
PACKAGE DESCRIPTION
UFDM Package
28-Lead Plastic Side Wettable QFN (4mm × 5mm)
ꢂReꢨeꢩeꢪꢫe ꢓꢍꢒ ꢆꢐꢑ ꢬ 0ꢉꢭ0ꢡꢭꢁꢟꢡꢃ Rev ꢧꢈ
ꢗꢅꢋ ꢁ ꢋꢌꢍꢒꢛ
ꢃ.ꢉ0 Rꢇꢊ
R ꢤ 0.ꢁꢁꢉ
ꢍꢞꢗ
R ꢤ 0.ꢃ0 ꢌR 0.ꢕꢉ
R ꢤ 0.0ꢉ
ꢍꢞꢗ
× ꢀꢉ° ꢒꢛꢏꢔꢊꢇR
0.ꢠꢉ ±0.0ꢉ
ꢀ.00 ±0.ꢁ0
ꢂꢃ ꢄꢅꢆꢇꢄꢈ
ꢃꢠ
ꢃꢡ
0.ꢀ0 ±0.ꢁ0
ꢗꢅꢋ ꢁ
ꢍꢌꢗ ꢔꢏRꢙ
ꢂꢋꢌꢍꢇ ꢟꢈ
ꢁ
ꢃ
ꢉ.00 ±0.ꢁ0
ꢂꢃ ꢄꢅꢆꢇꢄꢈ
ꢕ.ꢉ0 Rꢇꢊ
ꢕ.ꢟꢉ ±0.ꢁ0
ꢃ.ꢟꢉ ±0.ꢁ0
ꢆꢇꢍꢏꢅꢓ ꢏ
ꢂꢚꢊꢆꢔꢃꢡꢈ ꢦꢊꢋ ꢁꢃꢁꢡ Rꢇꢢ ꢧ
0.ꢃꢉ ±0.0ꢉ
0.ꢃ00 Rꢇꢊ
0.ꢉ0 ꢘꢄꢒ
0.00 ꢥ 0.0ꢉ
ꢘꢌꢍꢍꢌꢔ ꢢꢅꢇꢐꢣꢇꢖꢗꢌꢄꢇꢆ ꢗꢏꢆ
ꢋꢌꢍꢇꢎ
ꢆꢇꢍꢏꢅꢓ ꢏ
ꢁ. ꢆRꢏꢐꢅꢋꢑ ꢋꢌꢍ ꢍꢌ ꢄꢒꢏꢓꢇ
ꢍꢇRꢔꢅꢋꢏꢓ ꢓꢇꢋꢑꢍꢛ
0.ꢀ0 0.ꢁ0
ꢃ. ꢏꢓꢓ ꢆꢅꢔꢇꢋꢄꢅꢌꢋꢄ ꢏRꢇ ꢅꢋ ꢔꢅꢓꢓꢅꢔꢇꢍꢇRꢄ
ꢕ. ꢆꢅꢔꢇꢋꢄꢅꢌꢋꢄ ꢌꢊ ꢇꢖꢗꢌꢄꢇꢆ ꢗꢏꢆ ꢌꢋ ꢘꢌꢍꢍꢌꢔ ꢌꢊ ꢗꢏꢒꢙꢏꢑꢇ ꢆꢌ ꢋꢌꢍ ꢅꢋꢒꢓꢚꢆꢇ
ꢔꢌꢓꢆ ꢊꢓꢏꢄꢛ. ꢔꢌꢓꢆ ꢊꢓꢏꢄꢛꢜ ꢅꢊ ꢗRꢇꢄꢇꢋꢍꢜ ꢄꢛꢏꢓꢓ ꢋꢌꢍ ꢇꢖꢒꢇꢇꢆ 0.ꢁꢉꢝꢝ ꢌꢋ ꢏꢋꢞ ꢄꢅꢆꢇ
ꢀ. ꢄꢛꢏꢆꢇꢆ ꢏRꢇꢏ ꢅꢄ ꢌꢋꢓꢞ ꢏ RꢇꢊꢇRꢇꢋꢒꢇ ꢊꢌR ꢗꢅꢋ ꢁ ꢓꢌꢒꢏꢍꢅꢌꢋ
ꢌꢋ ꢍꢛꢇ ꢍꢌꢗ ꢏꢋꢆ ꢘꢌꢍꢍꢌꢔ ꢌꢊ ꢗꢏꢒꢙꢏꢑꢇ
0.ꢃ0ꢕ Rꢇꢊ
ꢍꢇRꢔꢅꢋꢏꢓ ꢍꢛꢅꢒꢙꢋꢇꢄꢄ
0.ꢁ0 Rꢇꢊ
0.0ꢉ Rꢇꢊ
ꢗꢓꢏꢍꢇꢆ ꢏRꢇꢏ
0.ꢠ0 ±0.0ꢉ
ꢀ.ꢉ0 ±0.0ꢉ
ꢕ.ꢁ0 ±0.0ꢉ
ꢃ.ꢉ0 Rꢇꢊ
ꢃ.ꢟꢉ ±0.0ꢉ
ꢕ.ꢟꢉ ±0.0ꢉ
ꢗꢏꢒꢙꢏꢑꢇ ꢌꢚꢍꢓꢅꢋꢇ
0.ꢃꢉ ±0.0ꢉ
0.ꢉ0 ꢘꢄꢒ
ꢕ.ꢉ0 Rꢇꢊ
ꢀ.ꢁ0 ±0.0ꢉ
ꢉ.ꢉ0 ±0.0ꢉ
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
33
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
LTC7802
TYPICAL APPLICATION
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ꢊꢡꢉ
Figure 12. High Efficiency 360W 2-Phase Single Output 12V Step-Down Regulator
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC7802-3.3
40V Dual Low I , 3MHz, 2-Phase Synchronous Step-Down 4.5V ≤ V ≤ 40V, V
Up to 40V, I = 12µA Fixed Frequency
Q
IN
OUT Q
Controller with Spread Spectrum and Fixed 3.3V
100kHz to 3MHz, 4mm × 5mm QFN-28
OUT1
LTC7803
LTC3807
40V Low I , 100% Duty Cycle, Synchronous Step-Down
4.5V ≤ V ≤ 40V, V Up to 40V, I = 12µA Fixed Frequency
Q
IN
OUT
Q
Controller with Spread Spectrum
100kHz to 3MHz, 3mm × 3mm QFN-16/MSOP-16
38V Low I , Synchronous Step-Down Controller with
4V ≤ V ≤ 38V, 0.8V ≤ V ≤ 24V, I = 50µA PLL Fixed Frequency
Q
IN
OUT
Q
24V Output Voltage Capability
50kHz to 900kHz, 3mm × 4mm QFN-20/TSSOP-20
LTC3890/LTC3890-1/ 60V, Low I , Dual 2-Phase Synchronous Step-Down
4V ≤ V ≤ 60V, 0.8V ≤ V
≤ 24V, I = 50µA PLL Fixed Frequency
Q
Q
IN
OUT
LTC3890-2/LTC3890-3 DC/DC Controller with 99% Duty Cycle
50kHz to 900kHz
LTC3892
60V Low I , Dual, 2-Phase Synchronous Step-Down
4V ≤ V ≤ 60V, 0.8V ≤ V
≤ 24V, I = 29µA PLL Fixed Frequency
Q
Q
IN
OUT
DC/DC Controller with Adjustable Gate Drive Voltage
50kHz to 900kHz
LTC3850
LTC3855
Dual, 2-Phase Synchronous Step-Down DC/DC Controller 4V ≤ V ≤ 24V, V
Up to 5.5V PLL Fixed Frequency 250kHz to 750kHz
IN
OUT
Dual, Multiphase, Synchronous Step-Down DC/DC Controller 4.5V ≤ V ≤ 38V, 0.8V ≤ V
≤ 12V PLL Fixed Frequency 250kHz
IN
OUT
with Diff Amp and DCR Temperature Compensation
to 770kHz, Excellent Current Share
LTC3869/LTC3869-2
LTC3875
Dual Output, 2-Phase Synchronous Step-Down DC/DC
Controller, with Accurate Current Share
4V ≤ V ≤ 38V, V
Up to 12.5V PLL Fixed 250kHz to 750kHz
OUT
IN
Frequency
Dual, 2-Phase, Synchronous Controller with Sub-Milliohm 4.75V ≤ V ≤ 38V, 0.6V ≤ V
DCR Sensing and Temperature Compensation
≤ 3.5V/5V, Excellent Current Share
IN
OUT
LTC3774
Dual, Multiphase Current Mode Synchronous Step-Down Operates with DrMOS, Power Blocks or External Drivers/MOSFETs,
DC/DC Controller for Sub-Milliohm DCR Sensing
4.5V≤ V ≤ 38V, 0.6V ≤ V
≤ 3.5V
IN
OUT
Rev. 0
09/20
www.analog.com
34
ANALOG DEVICES, INC. 2020
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