LT8392 [ADI]
60V Synchronous 4-Switch Buck-Boost Controller with Spread Spectrum;
| 型号： | LT8392 |
| 厂家： | 
ADI |
| 描述： | 60V Synchronous 4-Switch Buck-Boost Controller with Spread Spectrum |
| 文件： | 总28页 (文件大小：3051K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT8392
60V Synchronous 4-Switch Buck-Boost
Controller with Spread Spectrum
FEATURES
DESCRIPTION
4-Switch Single Inductor Architecture Allows V
The LT®8392 is a synchronous 4-switch buck-boost DC/
DC controller that regulates output voltage, input or out-
put current from input voltage above, below, or equal to
the output voltage. The proprietary peak-buck peak-boost
current mode control scheme allows adjustable and syn-
chronizable 150kHz to 650kHz fixed frequency operation,
or internal 15% triangle spread spectrum operation for
low EMI. With 3V to 60V input voltage range, 1V to 60V
output voltage capability, and seamless low noise tran-
sitions between operation regions, the LT8392 is ideal
for voltage regulator, battery and super-capacitor charger
applications in automotive, industrial, telecom, and even
battery-powered systems.
n
IN
Above, Below or Equal to V
Up to 98% Efficiency
OUT
n
n
n
n
n
n
n
n
n
n
Proprietary Peak-Buck Peak-Boost Current Mode
Wide V Range: 3V (Need EXTV ≥ 4.5V) to 60V
IN
CC
1.5% Output Voltage Accuracy: 1V ≤ V
≤ 60V
OUT
4% Input or Output Current Accuracy with Monitor
Spread Spectrum Frequency Modulation for Low EMI
Integrated Bootstrap Diodes
Adjustable and Synchronizable: 150kHz to 650kHz
V
Disconnected from V During Shutdown
OUT
IN
Available in 28-Lead TSSOP with Exposed Pad and
28-Lead QFN (4mm × 5mm)
The LT8392 provides input or output current monitor and
power good flag. Fault protection function detects output
short-circuit condition, during which the LT8392 retries,
latches off, or keeps running.
APPLICATIONS
n
Automotive, Industrial, Telecom Systems
n
High Frequency Battery-Powered System
All registered trademarks and trademarks are the property of their respective owners.
TYPICAL APPLICATION
98% Efficient 96W (12V 8A) Buck-Boost Voltage Regulator
ꢀ
ꢀꢁꢂ
ꢀꢁꢂ
ꢃꢄ
ꢀꢁꢂ
1mΩ
5mΩ
ꢀ
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ꢃꢀ ꢄꢅ ꢆꢇꢀ
ꢈꢅꢂꢄꢁꢂꢉꢅꢉꢊ
ꢋꢀ ꢄꢅ ꢋꢃꢀ
Efficiency vs VIN
0.ꢀꢁꢂ
0.ꢀꢁꢂ
ꢀꢀꢁꢂ
ꢃꢄ
ꢀꢁꢂ ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀ0ꢁꢂ
ꢃꢄ
ꢀꢁ0ꢂꢃ
ꢄꢅ
ꢀꢁ0ꢂꢃ
ꢀꢁ0ꢂꢃ
ꢀ00
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ0
ꢀꢀ
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ꢀꢁꢂꢃ
ꢄꢄ
ꢀꢁ0ꢂ
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ꢀꢁꢂ
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ꢀRꢁꢂ
0.ꢀꢁꢂꢃ
ꢀꢁRꢂ
ꢀꢁꢂꢃꢄ
ꢀ0ꢁ
ꢀ
ꢀ ꢁꢂ
ꢀꢁꢂ
PGOOD
ꢀꢁꢂ
ꢀꢁꢂꢀ
ꢀ00ꢁ
0
ꢀ
ꢀ
ꢀꢁ ꢀꢁ ꢀ0 ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀ0
ꢀꢁꢂꢃꢄꢀꢅRꢆ
ꢀꢁꢂꢃꢄ ꢅꢆꢇꢄꢈꢉꢊ ꢋꢅꢌ
ꢀꢁꢂꢃ
ꢄꢄ
ꢀꢁꢂꢃ ꢄꢅ0ꢆꢇ
ꢀꢀ
Rꢀ
ꢀ
ꢀ
ꢀ.ꢁꢂꢃ
ꢀꢁꢂꢃ ꢄꢅ0ꢆꢇ
ꢀꢀꢁꢂ
ꢀ00ꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂꢃ
0.ꢀꢁꢂ
Rev. 0
1
Document Feedback
For more information www.analog.com
LT8392
ABSOLUTE MAXIMUM RATINGS
(Note 1)
V , EN/UVLO, V , ISP, ISN ................................... 60V FB, TRIM, SYNC/SPRD, CTRL, PGOOD....................... 6V
IN
OUT
(ISP-ISN) ......................................................... –1V to 1V Operating Junction Temperature Range (Notes 2, 3)
BST1, BST2............................................................... 66V
SW1, SW2, LSP, LSN.....................................–6V to 60V
LT8392E .............................................–40°C to 125°C
LT8392J..............................................–40°C to 150°C
LT8392H.............................................–40°C to 150°C
INTV , (BST1-SW1), (BST2-SW2)............................. 6V
CC
(BST1-LSP), (BST1-LSN)............................................ 6V Storage Temperature Range ...................–65°C to 150°C
EXTV ..................................................................... 40V
CC
PIN CONFIGURATION
ꢉꢊꢋ ꢌꢍꢎꢏ
ꢂꢃꢄ ꢅꢆꢇꢈ
ꢀ
ꢁ
ꢤꢔꢁ
ꢤꢘꢉꢁ
ꢘꢏꢁ
ꢉꢔꢁ
ꢁꢇ
ꢁꢆ
ꢁꢅ
ꢁꢄ
ꢁꢃ
ꢁꢂ
ꢁꢁ
ꢁꢀ
ꢁ0
ꢀꢈ
ꢀꢇ
ꢀꢆ
ꢀꢅ
ꢀꢄ
ꢤꢔꢀ
ꢤꢘꢉꢀ
ꢘꢏꢀ
ꢉꢔꢀ
ꢉꢒ ꢉꢥ ꢉꢦ ꢉꢘ ꢉꢖ ꢉꢞ
ꢂ
ꢂꢊꢁ
ꢔꢚꢄ
ꢔꢚꢋ
ꢁ
ꢉ
ꢞ
ꢖ
ꢘ
ꢦ
ꢥ
ꢒ
ꢉꢉ
ꢉꢁ
ꢉ0
ꢁꢀ
ꢁꢒ
ꢁꢥ
ꢁꢦ
ꢁꢘ
ꢂꢊꢉ
ꢃ
ꢅ
ꢃꢍꢂ
ꢄ
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ꢊꢣꢉ
ꢖꢘꢋ
ꢇꢢꢂꢅ
ꢐꢐ
ꢅ
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ꢖꢘꢠ
ꢒꢒ
ꢅ
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Rꢂ
ꢆꢋ
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Rꢉ
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ꢐꢐ
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ꢇꢋꢠꢍꢅꢔꢃ
ꢒꢒ
ꢅ
ꢐ
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ꢌ
ꢒ
ꢎꢠꢜꢣꢌꢖꢊ
ꢉꢎꢘꢉ
ꢂꢇꢚꢂ
ꢂRꢆꢣ
ꢎꢤ
ꢀ0
ꢀꢀ
ꢀꢁ
ꢀꢂ
ꢀꢃ
ꢐꢤ
ꢚꢚ
ꢀ
ꢁ0 ꢁꢁ ꢁꢉ ꢁꢞ ꢁꢖ
ꢍꢎꢌ ꢄꢏꢐꢑꢏꢊꢇ
ꢘꢘ
ꢉRꢍꢢ
PGOOD
ꢍꢘꢢꢊꢠ
ꢍꢘꢠ
ꢌ
Rꢎꢐ
ꢒꢉRꢖ
ꢍꢘꢋ
ꢉꢒꢓꢔꢇꢏꢌ ꢕꢖꢗꢗ × ꢘꢗꢗꢙ ꢄꢔꢏꢚꢂꢆꢐ ꢛꢎꢋ
ꢐꢎ ꢋꢑꢒꢓꢑꢔꢎ
ꢁꢇꢕꢖꢎꢑꢗ ꢋꢖꢑꢘꢉꢍꢒ ꢉꢘꢘꢊꢋ
θ
ꢝ ꢖꢞꢟꢐꢠꢈꢡ θ ꢝ ꢞ.ꢖꢟꢐꢠꢈ
ꢜꢏ
ꢜꢐ
ꢇꢢꢄꢃꢚꢇꢌ ꢄꢏꢌ ꢕꢄꢆꢋ ꢉꢀꢙ ꢆꢚ ꢊꢋꢌꢡ ꢣꢍꢚꢂ ꢤꢇ ꢚꢃꢔꢌꢇRꢇꢌ ꢂꢃ ꢄꢐꢤ
θ
ꢙꢑ
ꢚ ꢂ0ꢛꢒꢜꢏꢝ θ ꢚ ꢄꢛꢒꢜꢏ
ꢙꢒ
ꢎꢞꢋꢊꢘꢎꢗ ꢋꢑꢗ ꢟꢋꢍꢠ ꢁꢈꢡ ꢍꢘ ꢔꢠꢗꢝ ꢢꢣꢘꢉ ꢤꢎ ꢘꢊꢖꢗꢎRꢎꢗ ꢉꢊ ꢋꢒꢤ
ORDER INFORMATION
LEAD FREE FINISH
LT8392EFE#PBF
LT8392JFE#PBF
LT8392HFE#PBF
LT8392EUFD#PBF
LT8392JUFD#PBF
LT8392HUFD#PBF
TAPE AND REEL
PART MARKING*
LT8392FE
LT8392FE
LT8392FE
8392
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT8392EFE#TRPBF
LT8392JFE#TRPBF
LT8392HFE#TRPBF
LT8392EUFD#TRPBF
LT8392JUFD#TRPBF
LT8392HUFD#TRPBF
28-Lead Plastic TSSOP
–40°C to 125°C
–40°C to 150°C
–40°C to 150°C
–40°C to 125°C
–40°C to 150°C
–40°C to 150°C
28-Lead Plastic TSSOP
28-Lead Plastic TSSOP
28-Lead (4mm × 5mm) Plastic QFN
28-Lead (4mm × 5mm) Plastic QFN
28-Lead (4mm × 5mm) Plastic QFN
8392
8392
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
Rev. 0
2
For more information www.analog.com
LT8392
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, VEN/UVLO = 1.5V unless otherwise noted.
PARAMETER
Supply
CONDITIONS
MIN
TYP
MAX
UNITS
V
IN
Operating Voltage Range
EXTV = 0V
l
l
4
3
60
60
V
V
CC
EXTV = 8V
CC
V
V
Shutdown Current
V
= 0.3V
1
2
µA
IN
EN/UVLO
Active Current (Not Switching)
V
V
= 1.5V, EXTV = 0V
= 1.5V, EXTV = 8V
2
250
3
500
mA
µA
IN
EN/UVLO
EN/UVLO
CC
CC
l
l
EXTV Voltage Range
0
40
V
µA
mA
V
CC
EXTV Shutdown Current
V
V
= 0.3V, EXTV = 8V
0.1
1.8
0.5
CC
EN/UVLO
EN/UVLO
CC
EXTV Active Current (Not Switching)
= 1.5V, EXTV = 8V
CC
CC
V
OUT
V
OUT
Voltage Range
0
60
Quiescent Current
V
V
= 0.3V, V
= 1.5V, V
= 12V
= 12V
0.1
20
0.5
30
µA
µA
EN/UVLO
EN/UVLO
OUT
OUT
10
Linear Regulators
INTV Regulation Voltage
I
= 20mA
INTVCC
4.8
130
3.34
5.0
190
3.54
0.22
2.00
2.5
5.2
250
3.74
V
mA
V
CC
INTV Current Limit
V
= 4.5V
INTVCC
CC
INTV Undervoltage Lockout Threshold
Falling
CC
INTV Undervoltage Lockout Hysteresis
V
CC
l
V
REF
V
REF
Regulation Voltage
Current Limit
I
= 100µA
1.96
2
2.04
3.2
V
VREF
V
= 1.8V
mA
REF
Control Inputs
l
l
EN/UVLO Shutdown Threshold
EN/UVLO Enable Threshold
EN/UVLO Enable Hysteresis
EN/UVLO Hysteresis Current
0.3
0.6
1.220
13
1.0
V
V
Falling
1.196
1.244
mV
V
V
= 1.1V
= 1.3V
2.1
–0.1
2.5
0
2.9
0.1
µA
µA
EN/UVLO
EN/UVLO
Error Amplifier
l
l
Full-Scale Current Regulation V
V
CTRL
V
CTRL
= 2V, V = 12V
48
48
50
50
52
52
mV
mV
(ISP-ISN)
ISP
= 2V, V = 0V
ISP
l
l
1/10th Current Regulation V
V
V
= 0.35V, V = 12V
3
3
5
5
7
7
mV
mV
(ISP-ISN)
CTRL
CTRL
ISP
= 0.35V, V = 0V
ISP
l
l
l
ISMON Monitor Output V
V
V
V
= 50mV, V = 12V/0V
1.15
0.30
0.20
1.25
0.35
0.25
1.35
0.40
0.30
V
V
V
ISMON
(ISP–ISN)
(ISP–ISN)
(ISP–ISN))
ISP
= 5mV, V = 12V/0V
ISP
= 0mV, V = 12V/0V
ISP
l
ISP/ISN Input Common Mode Range
ISP Input Bias Current
0
60
V
V
V
V
= V = 12V
20
–10
0
µA
µA
µA
ISP
ISP
ISN
= V = 0V
ISN
= 0V, V = V = 12V or 0V
EN/UVLO
ISP
ISN
ISN Input Bias Current
V
V
V
= V = 12V
20
–10
0
µA
µA
µA
ISP
ISP
ISN
= V = 0V
ISN
= 0V, V = V = 12V or 0V
EN/UVLO
ISP
ISN
ISP/ISN Current Regulation Amplifier g
FB Regulation Voltage
8000
1.00
0.2
µs
V
m
l
V = 1.2V
0.985
1.015
0.5
C
FB Line Regulation
V
IN
= 4V to 60V
%
Rev. 0
3
For more information www.analog.com
LT8392
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, VEN/UVLO = 1.5V unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
0.2
660
20
MAX
UNITS
%
FB Load Regulation
0.8
FB Voltage Regulation Amplifier g
FB Input Bias Current
µs
m
FB in regulation, Current out of Pin
40
nA
V Output Impedance
C
10
MΩ
Current Comparator
Maximum Current Sense Threshold V
Buck, V = 0.8V
l
l
35
40
50
50
65
60
mV
mV
(LSP-LSN)
FB
Boost, V = 0.8V
FB
Fault
FB Short Threshold (V
FB Short Hysteresis
)
Falling
0.23
35
0.25
50
0.27
65
V
mV
%
%
Ω
FB
PGOOD Upper Threshold Offset from V
Rising
Falling
6
8
10
FB
PGOOD Lower Threshold Offset from V
PGOOD Pull-Down Resistance
SS Hard Pull-Down Resistance
SS Pull-Up Current
–10
–8
–6
FB
100
100
12.5
1.25
1.7
0.2
200
200
15
V
V
V
= 1.1V
Ω
EN/UVLO
= 0V
= 2V
10
1
µA
µA
V
SS
SS
SS Pull-Down Current
1.5
SS Fault Latch-Off Threshold
SS Fault Reset Threshold
Oscillator
V
l
Switching Frequency
V
= 0V, R = 100kΩ
380
150
0.4
12
400
420
650
1.5
18
kHz
kHz
V
SYNC/SPRD
T
SYNC Frequency
SYNC/SPRD Threshold Voltage
Highest Spread Spectrum Above Oscillator Frequency
Lowest Spread Spectrum Below Oscillator Frequency
NMOS Drivers
V
V
= 5V
= 5V
15
%
SYNC/SPRD
–18
–15
–12
%
SYNC/SPRD
TG1, TG2 Gate Driver On-Resistance
Gate Pull-Up
Gate Pull-Down
V = 5V
(BST–SW)
2.6
1.4
Ω
Ω
BG1, BG2 Gate Driver On-Resistance
Gate Pull-Up
Gate Pull-Down
V
= 5V
INTVCC
3.2
1.2
Ω
Ω
TG Off to BG On Delay
BG Off to TG On Delay
60
60
ns
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT8392E is guaranteed to meet performance specifications
from 0°C to 125°C operating junction temperature. Specifications over
the –40°C to 125°C operating junction temperature range are assured by
design, characterization and correlation with statistical process controls.
The LT8392J is guaranteed over the –40°C to 150°C operating junction
temperature range. The LT8392H is guaranteed over the –40°C to 150°C
operating junction temperature range. High junction temperatures degrade
operating lifetimes. Operating lifetime is derated at junction temperatures
greater than 125°C.
Note 3: The LT8392 includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 150°C when overtemperature protection is active.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability.
Rev. 0
4
For more information www.analog.com
LT8392
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Load Current
(Buck Region)
Efficiency vs Load Current
(Buck-Boost Region)
Efficiency vs Load Current
(Boost Region)
ꢀ00
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ00
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ00
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀRꢁꢂꢃ ꢄꢅꢆꢇ ꢅꢄꢄꢈꢉꢊꢅꢃꢉꢁꢂ
ꢀRꢁꢂꢃ ꢄꢅꢆꢇ ꢅꢄꢄꢈꢉꢊꢅꢃꢉꢁꢂ
ꢀRꢁꢂꢃ ꢄꢅꢆꢇ ꢅꢄꢄꢈꢉꢊꢅꢃꢉꢁꢂ
ꢀ ꢀ ꢁ ꢃ ꢂ ꢀ ꢁꢂ ꢄ ꢅ ꢀ ꢁ00ꢂꢃꢄ
ꢀꢁ
ꢀ
ꢀꢁ
ꢀ ꢁꢂ ꢄ ꢃ
ꢀ ꢁꢂ ꢄ ꢅ ꢀ ꢁ00ꢂꢃꢄ
ꢀ
ꢀ ꢁꢂ ꢄ ꢃ
ꢀ ꢁꢂ ꢄ ꢅ ꢀ ꢁ00ꢂꢃꢄ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁ
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢃ ꢄ0ꢅ
ꢀꢁꢂꢃ ꢄ0ꢃ
ꢀꢁꢂꢃ ꢄ0ꢁ
Switching Waveforms
(Buck Region)
Switching Waveforms
(Buck-Boost Region)
Switching Waveforms
(Boost Region)
ꢀ
ꢀ
ꢁꢂꢃ
ꢀ
ꢁꢂꢃ
ꢁꢂꢃ
ꢃ0ꢀꢄꢅꢆꢀ
ꢃ0ꢀꢄꢅꢆꢀ
ꢃ0ꢀꢄꢅꢆꢀ
ꢀ
ꢁꢂꢃ
ꢀ
ꢁꢂꢃ
ꢀ
ꢁꢂꢃ
ꢄ0ꢀꢅꢆꢇꢀ
ꢄ0ꢀꢅꢆꢇꢀ
ꢄ0ꢀꢅꢆꢇꢀ
ꢀ
ꢀ
ꢁ
ꢀ
ꢁ
ꢁ
ꢂꢃꢄꢅꢀꢆ
ꢂꢃꢄꢅꢀꢆ
ꢂꢃꢄꢅꢀꢆ
ꢀ
ꢀ
ꢀ
ꢁꢂꢃ
ꢁꢂꢃ
ꢁꢂꢃ
ꢄ00ꢅꢀꢆꢇꢈꢀ
ꢄ00ꢅꢀꢆꢇꢈꢀ
ꢄ00ꢅꢀꢆꢇꢈꢀ
ꢀꢁꢂꢃ ꢄ0ꢅ
ꢀꢁꢂꢃ ꢄ0ꢅ
ꢀꢁꢂꢃ ꢄ0ꢅ
ꢀRꢁꢂꢃ ꢄꢅꢆꢇ ꢅꢄꢄꢈꢉꢊꢅꢃꢉꢁꢂ
ꢀRꢁꢂꢃ ꢄꢅꢆꢇ ꢅꢄꢄꢈꢉꢊꢅꢃꢉꢁꢂ
ꢀRꢁꢂꢃ ꢄꢅꢆꢇ ꢅꢄꢄꢈꢉꢊꢅꢃꢉꢁꢂ
ꢋ
ꢌ ꢍꢎ ꢏ ꢉ
ꢌ ꢑꢅ
ꢋ
ꢌ ꢍ ꢎ ꢉ
ꢌ ꢐꢅ
ꢋ
ꢌ ꢍꢎ ꢏ ꢉ
ꢌ ꢑꢅ
ꢉꢂ
ꢁꢐꢃ
ꢉꢂ
ꢁꢏꢃ
ꢉꢂ
ꢁꢐꢃ
V
OUT vs IOUT (CV/CC)
VIN Shutdown Current
VIN Operating Current
ꢀꢁ
ꢀꢁ
ꢀ0
ꢀ
ꢀ.0
ꢀ.ꢁ
ꢀ.0
ꢀ.ꢁ
ꢀ.0
0.ꢀ
0
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢀ
ꢀ.0
ꢀ.ꢁ
ꢀ
ꢀꢁ
ꢀ ꢁ0ꢂ
ꢀ
ꢀꢁ
ꢀ ꢁ0ꢂ
ꢀ
ꢀ
ꢀ ꢁꢂꢃ
ꢀ
ꢀ ꢁꢂꢃ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀ
ꢀꢁ
ꢀ ꢁꢂ
ꢀ
ꢀ ꢁꢂ
ꢀꢁ
ꢀ
ꢀꢁꢂꢃ ꢀ 0ꢁ
ꢀꢀ
0
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ0
ꢀꢁ
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃ ꢄ0ꢅ
ꢀꢁꢂꢃ ꢄ0ꢀ
ꢀꢁꢂꢃ ꢄ0ꢂ
Rev. 0
5
For more information www.analog.com
LT8392
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
INTVCC Voltage vs Temperature
INTVCC Voltage vs VIN
INTVCC UVLO Threshold
ꢕ.0
ꢀ.0ꢁ
ꢀ.0ꢁ
ꢀ.0ꢁ
ꢀ.00
ꢀ.ꢁꢁ
ꢀ.ꢁꢂ
ꢀ.ꢁꢂ
ꢀ.ꢁꢀ
ꢀ.ꢁ0
ꢀ.0ꢀ
ꢀ.00
ꢀ.ꢁꢂ
ꢀ.ꢁ0
ꢀ.ꢁꢂ
ꢀ
ꢀ ꢁ0ꢂꢃ
ꢀꢁꢂꢃꢄꢄ
ꢌ.ꢒ
ꢌ.ꢑ
ꢌ.ꢓ
ꢌ.ꢔ
ꢌ.ꢋ
ꢌ.ꢕ
ꢌ.ꢌ
ꢌ.ꢍ
Rꢏꢘꢏꢐꢗ
ꢀ
ꢀ ꢁ0ꢂꢃ
ꢀꢁꢂꢃꢄꢄ
ꢀ
ꢀꢁ
ꢀ ꢁꢂ ꢄ ꢃ
ꢀ 0ꢁ
ꢀꢁꢂꢃꢄꢄ
ꢙꢄꢚꢚꢏꢐꢗ
ꢀ
ꢀ ꢁ ꢃ ꢂ
ꢀ ꢁꢂꢃ
ꢀꢁꢂꢃꢄꢄ
ꢀꢁ
ꢊꢋ0 ꢊꢍꢋ
0
ꢍꢋ ꢋ0 ꢓꢋ ꢖ00 ꢖꢍꢋ ꢖꢋ0
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁꢂꢃ ꢄꢅ0
ꢀꢁꢂꢃ ꢄꢅꢅ
ꢑꢌꢒꢍ ꢗꢖꢍ
V
REF Voltage vs Temperature
VREF Voltage vs VIN
VREF UVLO Threshold
ꢑ.0ꢕ
ꢑ.0ꢒ
ꢑ.0ꢑ
ꢑ.0ꢌ
ꢑ.00
ꢌ.ꢍꢍ
ꢌ.ꢍꢓ
ꢌ.ꢍꢔ
ꢌ.ꢍꢎ
ꢊ.0ꢎ
ꢊ.0ꢋ
ꢊ.0ꢊ
ꢊ.0ꢅ
ꢊ.00
ꢅ.ꢆꢆ
ꢅ.ꢆꢌ
ꢅ.ꢆꢍ
ꢅ.ꢆꢇ
ꢒ.00
ꢌ.ꢐꢋ
ꢌ.ꢐ0
ꢌ.ꢑꢋ
ꢌ.ꢑ0
ꢌ.ꢍꢋ
ꢌ.ꢍ0
Rꢕꢖꢕꢗꢔ
ꢁ
ꢑ ꢅ00ꢒꢓ
ꢀRꢈꢉ
ꢗ
ꢗ
ꢘ 0ꢙꢄ
ꢘ ꢌꢙꢄ
ꢏRꢁꢐ
ꢏRꢁꢐ
ꢏꢄꢘꢘꢕꢗꢔ
ꢊꢋ0 ꢊꢑꢋ
0
ꢑꢋ ꢋ0 ꢔꢋ ꢌ00 ꢌꢑꢋ ꢌꢋ0
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
0
ꢅ0
ꢊ0
ꢋ0
ꢃꢀꢄ
ꢎ0
ꢏ0
ꢇ0
ꢊꢋ0 ꢊꢒꢋ
0
ꢒꢋ ꢋ0 ꢍꢋ ꢌ00 ꢌꢒꢋ ꢌꢋ0
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀ
ꢁꢂ
ꢓꢒꢍꢑ ꢖꢌꢒ
ꢌꢋꢆꢊ ꢐꢅꢎ
ꢑꢓꢐꢒ ꢔꢌꢋ
EN/UVLO Enable Threshold
EN/UVLO Hysteresis Current
V(ISP–ISN) Regulation vs VCTRL
ꢌ.ꢍꢔ0
ꢌ.ꢍꢓꢋ
ꢌ.ꢍꢓ0
ꢌ.ꢍꢍꢋ
ꢌ.ꢍꢍ0
ꢌ.ꢍꢌꢋ
ꢌ.ꢍꢌ0
ꢌ.ꢍ0ꢋ
ꢌ.ꢍ00
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
0
ꢕ.0
ꢌ.ꢒ
ꢌ.ꢓ
ꢌ.ꢔ
ꢌ.ꢌ
ꢌ.0
Rꢚꢛꢚꢏꢗ
ꢜꢄꢑꢑꢚꢏꢗ
ꢊꢋ0 ꢊꢍꢋ
0
ꢍꢋ ꢋ0 ꢙꢋ ꢌ00 ꢌꢍꢋ ꢌꢋ0
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢊꢋ0 ꢊꢌꢋ
0
ꢌꢋ ꢋ0 ꢙꢋ ꢖ00 ꢖꢌꢋ ꢖꢋ0
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
0
0.ꢀꢁ 0.ꢀ0 0.ꢀꢁ
ꢀ
ꢀ.ꢁꢂ ꢀ.ꢁ0 ꢀ.ꢁꢂ
ꢀꢁꢂ
ꢀ
ꢀ
ꢀꢁRꢂ
ꢀꢁꢂꢃ ꢄꢅꢀ
ꢕꢓꢖꢍ ꢗꢌꢘ
ꢒꢕꢗꢌ ꢘꢖꢙ
Rev. 0
6
For more information www.analog.com
LT8392
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
V(ISP-ISN) Regulation
V(ISP-ISN) Regulation vs VISP
V(ISP-ISN) Regulation vs VISP
vs VFB
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ0
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ.0
ꢀꢁ.0
ꢀꢁ.0
ꢀ0.0
ꢀꢁ.0
ꢀꢁ.0
ꢀꢁ.0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀꢁꢂ ꢃ 0ꢄ
ꢀ0
ꢀꢁꢂ ꢃ ꢄꢅꢆ
ꢀꢁꢂ ꢃ ꢄ0ꢅ
0
0
ꢀ0
ꢀ0
ꢀ0
ꢀꢁꢂ
ꢀ0
ꢀ0
ꢀ0
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
0.ꢀꢁ 0.ꢀꢁ 0.ꢀꢁ 0.ꢀꢀ
ꢀ
ꢀ.0ꢀ ꢀ.0ꢁ ꢀ.0ꢁ ꢀ.0ꢁ
ꢀ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃ ꢄꢅꢂ
ꢀꢁꢂꢃ ꢄꢃ0
ꢀꢁꢂꢃ ꢄꢃꢅ
Maximum Current Sense
vs Temperature
FB Regulation vs Temperature
FB Short Threshold
ꢀ.0ꢁ
ꢀ.0ꢁ
ꢀ.0ꢀ
ꢀ.00
0.ꢀꢀ
0.ꢀꢁ
0.ꢀꢁ
ꢀ0.0
ꢀꢁ.0
ꢀ0.0
ꢀꢀ.0
ꢀ0.0
ꢀꢁ.0
ꢀ0.0
ꢀꢁ.0
ꢀ0.0
0. 0
0.
R
0. 0
0.
0. 0
0.
ꢀ
ꢀ
ꢀ
ꢀ ꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ ꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢁꢂꢃ
ꢀ ꢁ0ꢂ
0. 0
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
0
0
0
00
0
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
R
R
ꢀꢁꢂꢃ ꢄꢃꢃ
ꢀꢁꢂꢃ ꢄꢃꢁ
PGOOD Thresholds
ISMON Voltage vs V(ISP–ISN)
SS Current vs Temperature
ꢀꢁ.0
ꢀ.0
ꢀ.ꢁ0
ꢀ.ꢁꢂ
ꢀ.00
0.ꢀꢁ
0.ꢀ0
0.ꢀꢁ
0
.0
.
ꢀꢁꢁꢂR Rꢃꢄꢃꢅꢆ
ꢀꢁꢁꢂR ꢃꢄꢅꢅꢆꢇꢈ
ꢀ.0
0.0
.
0
ꢀꢁ.0
ꢀꢁ.0
ꢀꢁꢂ.0
.0
.
ꢀꢁꢂꢃR Rꢄꢅꢄꢆꢇ
ꢀꢁꢂꢃR ꢄꢅꢀꢀꢆꢇꢈ
0.0
ꢀꢁ0 ꢀꢁꢂ
0
ꢀꢁ ꢀ0 ꢀꢁ ꢀ00 ꢀꢁꢂ ꢀꢁ0
0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
ꢀ0
0
0
0
00
0
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀ
ꢀꢁꢂ
R
R
ꢀꢁꢂꢃꢄꢁꢂꢅꢆ
ꢀꢁꢂꢃ ꢄꢃꢅ
ꢀꢁꢂꢃ ꢄꢃꢅ
Rev. 0
7
For more information www.analog.com
LT8392
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
Oscillator Frequency
vs Temperature
ꢜ00
R
ꢟ ꢋꢞ.0ꢗ
ꢟ ꢍ00ꢗ
ꢟ ꢌꢌꢙꢗ
ꢀ
ꢙ00
ꢋ00
ꢚ00
ꢛ00
ꢌ00
ꢍ00
R
ꢀ
ꢀ
R
ꢊꢋ0 ꢊꢌꢋ
0
ꢌꢋ ꢋ0 ꢜꢋ ꢍ00 ꢍꢌꢋ ꢍꢋ0
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢝꢛꢞꢌ ꢓꢌꢝ
PIN FUNCTIONS
BG1: Buck Side Bottom Gate Drive. Drives the gate of
INTV : Internal 5V Linear Regulator Output. The INTV
CC CC
buck side bottom N-Channel MOSFET with a voltage
swing from ground to INTV .
linear regulator is supplied from either the V pin or the
IN
BIAS pin, and powers the internal control circuitry and
gate drivers. Locally bypass this pin to ground with a
minimum 4.7µF ceramic capacitor.
CC
BST1: Buck Side Bootstrap Floating Driver Supply. The
BST1 pin has an integrated bootstrap Schottky diode from
the INTV pin and requires an external bootstrap capac-
EN/UVLO: Enable and Undervoltage Lockout. Force the
CC
itor to the SW1 pin.
pin below 0.3V to shut down the part and reduce V qui-
IN
escent current below 2µA. Force the pin above 1.233V for
normal operation. The accurate 1.220V falling threshold
can be used to program an undervoltage lockout (UVLO)
SW1: Buck Side Switch Node.
TG1: Buck Side Top Gate Drive. Drives the gate of buck
side top N-Channel MOSFET with a voltage swing from
SW1 to BST1.
threshold with a resistor divider from V to ground. An
IN
accurate 2.5µA pull-down current allows the program-
ming of V UVLO hysteresis. If neither function is used,
IN
LSP: Positive Terminal of the Buck Side Inductor Current
tie this pin directly to V .
IN
Sense Resistor (R ). Ensure accurate current sense
SENSE
with Kelvin connection.
LSN: Negative Terminal of the Buck Side Inductor Current
Sense Resistor (R ). Ensure accurate current sense
TEST: Factory Test. This pin is used for testing purpose
only and must be directly connected to ground for the
part to operate properly.
SENSE
with Kelvin connection.
TRIM: Factory Trim. This pin is used for trim purposes
only and must be directly connected to V
to operate properly.
for the part
REF
V : Input Supply. The V pin must be tied to the power
IN
IN
input to determine the buck, buck-boost, or boost oper-
ation regions. Locally bypass this pin to ground with a
minimum 1µF ceramic capacitor.
V
: Voltage Reference Output. The V pin provides an
REF
accurate 2V reference capable of suppRlyEiFng 1mA current.
Locally bypass this pin to ground with a 0.47µF ceramic
capacitor.
Rev. 0
8
For more information www.analog.com
LT8392
PIN FUNCTIONS
CTRL: Control Input for ISP/ISN Current Sense Threshold.
The CTRL pin is used to program the ISP/ISN current limit:
FB: Voltage Loop Feedback Input. The FB pin is used for
constant-voltage regulation and output fault protection. The
internal error amplifier with its output V regulates V to
C
FB
Min V
−0.25V,1V
20•RIS
(
)
CTRL
1.00V through the DC/DC converter. During output short-cir-
cuit (VFB < 0.25V) condition, the part gets into one fault mode
IIS(MAX)
=
per customer setting. During an overvoltage (V > 1.08V)
FB
The V
can be set by an external voltage reference or
CTRL
condition, the part turns off all TG1, BG1, TG2, and BG2.
a resistor divider from V to ground. For 0.25V ≤ V
REF
CTRL
VC: Error Amplifier Output to Set Inductor Current
Comparator Threshold. The VC pin is used to compensate
the control loop with an external RC network.
≤ 1.15V, the current sense threshold linearly goes up
from 0mV to 45mV. For V ≥ 1.35V, the current sense
CTRL
threshold is constant at 50mV full-scale value. For 1.15V
≤ VCTRL ≤ 1.35V, the current sense threshold smoothly
RT: Switching Frequency Setting. Connect a resistor from
this pin to ground to set the internal oscillator frequency
from 150kHz to 650kHz.
transitions from the linear function of V
to the 50mV
CTRL
constant value. Tie CTRL to V
threshold.
for the 50mV full-scale
REF
SYNC/SPRD: Switching Frequency Synchronization or
Spread Spectrum. Ground this pin for switching at inter-
nal oscillator frequency. Apply a clock signal for external
ISP: Positive Terminal of the ISP/ISN Current Sense
Resistor (RIS). Ensure accurate current sense with
Kelvin connection.
frequency synchronization. Tie to INTV for 15% trian-
CC
gle spread spectrum around internal oscillator frequency.
ISN: Negative Terminal of the ISP/ISN Current Sense
Resistor (RIS). Ensure accurate current sense with
Kelvin connection.
EXTV : Second Input Supply for Powering INTV . The part
CC
CC
intelligently chooses either V or EXTVC for INTV LDO to
IN
C
CC
improve efficiency. See EXTVCC Connection in the Applications
ISMON: ISP/ISN Current Sense Monitor Output. The
ISMON pin generates a voltage that is equal to twenty
times V(ISP-ISN) plus 0.25V offset voltage. For parallel
applications, tie the master LT8392 ISMON pin to the
slave LT8392 CTRL pin.
Information Section. Tie this pin ground if not used.
V
: Output Supply. The V
pin must be tied to the
OUT
OUT
power output to determine the buck, buck-boost, or boost
operation regions. Locally bypass this pin to ground with
a minimum 1µF ceramic capacitor.
PGOOD: Power Good Open Drain Output. The PGOOD
pin is pulled low when the FB pin is within 8% of the
final regulation voltage. To function, the pin requires an
external pull-up resistor.
TG2: Boost Side Top Gate Drive. Drives the gate of boost
side top N-Channel MOSFET with a voltage swing from
SW2 to BST2.
SW2: Boost Side Switch Node.
SS: Soft-Start Timer Setting. The SS pin is used to set
soft-start timer by connecting a capacitor to ground. An
internal 12.5µA pull-up current charging the external SS
capacitor gradually ramps up FB regulation voltage. A
0.1µF capacitor is recommended on this pin. Any UVLO or
thermal shutdown immediately pulls SS pin to ground and
BST2: Boost Side Bootstrap Floating Driver Supply. The
BST2 pin has an integrated bootstrap Schottky diode from
the INTV pin and requires an external bootstrap capac-
CC
itor to the SW2 pin.
BG2: Boost Side Bottom Gate Drive. Drives the gate of
stops switching. Using a single resistor from SS to V
,
REF
boost side bottom N-Channel MOSFET with a voltage
the LT8392 can be set in three different fault protection
modes during output short-circuit condition: hiccup (no
resistor), latch-off (499kΩ), and keep-running (100kΩ).
See more details in the Application Information section.
swing from ground to INTV .
CC
GND (Exposed Pad): Ground. Solder the exposed pad
directly to the ground plane.
Rev. 0
9
For more information www.analog.com
LT8392
BLOCK DIAGRAM
ꢉ
ꢎꢏ
ꢂꢣꢐꢉ
ꢊꢒꢏ
ꢊꢒꢕ
ꢑꢑ
ꢎꢏꢐꢉ
ꢑꢑ
ꢎꢏꢐꢉ
ꢑꢑ
ꢀ
ꢁ
ꢈꢉ ꢊꢋꢌ
ꢖꢒꢐꢅ
ꢐꢝꢅ
ꢀ
ꢁ
ꢃꢅ
ꢃꢇ
ꢉ
Rꢂꢍ
ꢄꢉ Rꢂꢍ
ꢒꢠꢅ
ꢕꢂꢃꢙꢚꢖꢜꢑꢙ
ꢖꢜꢑꢙ
ꢊꢌꢝꢎꢑ
ꢊꢌꢃꢋ
ꢌꢏ
ꢎꢏꢐꢉ
ꢑꢑ
Rꢐ
ꢒꢓꢏꢑꢔꢒꢕRꢋ
ꢛꢌꢋꢂ
ꢖꢝꢅ
ꢌꢒꢑ
ꢉ
ꢌꢒ
0.ꢇꢉ
ꢀ
ꢑꢐRꢊ
ꢉ
ꢔꢖꢒꢐꢄ
ꢔꢖꢒꢐꢅ
ꢑꢢꢃRꢝꢂ
ꢑꢌꢏꢐRꢌꢊ
ꢁ
ꢌꢜꢐ
ꢉ
ꢎꢏ
ꢀ
ꢁ
ꢍꢖ
ꢍꢖꢌꢉ
ꢎꢒꢛꢌꢏ
ꢅ.ꢅꢉ
ꢅꢣ
ꢉ
ꢎꢒ
ꢎꢏꢢꢎꢖꢎꢐ
ꢒꢠꢎꢐꢑꢢ
ꢖꢝꢄ
ꢂꢏꢔꢜꢉꢊꢌ
ꢁ
ꢀ
ꢀ
ꢁ
ꢉ
ꢎꢒꢕꢗꢎꢒꢏ
ꢖꢌꢌꢒꢐ
ꢊꢌꢝꢎꢑ
ꢎꢏꢐꢉ
ꢑꢑ
ꢅ.ꢄꢄ0ꢉ
ꢄ.ꢈꢡꢃ
ꢎꢒꢌꢑ
ꢊꢌꢃꢋ
ꢌꢏ
ꢒꢠꢄ
ꢐꢝꢄ
0.ꢘꢈꢉ
ꢕꢂꢃꢙꢚꢖꢌꢌꢒꢐ
ꢀ
ꢃꢤ
ꢖꢒꢐꢄ
ꢐRꢎꢛ
ꢐꢂꢒꢐ
ꢁ
ꢉ
Rꢂꢍ
ꢎꢏꢐꢉ
ꢅꢄ.ꢈꢡꢃ
ꢑꢑ
0.ꢄꢈꢉ
ꢍꢖ
ꢀ
ꢁ
ꢒꢢꢌRꢐ
ꢀ
ꢀ
ꢁ
ꢉ
ꢌꢜꢐ
ꢂꢃꢅ
ꢅꢉ
ꢍꢖ
ꢅ0ꢡꢃ
ꢍꢃꢜꢊꢐ
ꢊꢌꢝꢎꢑ
ꢀ
ꢁ
ꢅ.ꢅꢉ
ꢑꢐRꢊ
ꢅ.ꢄꢈꢉ
ꢀ
ꢀ
PGOOD
ꢍꢖ
ꢂꢃꢄ
ꢅ.ꢄꢈꢡꢃ
ꢎꢒꢕ
ꢎꢒꢏ
ꢀ
ꢁ
ꢀ
ꢁ
ꢍꢖ
ꢃꢄꢆꢅ0
ꢀ
ꢊꢌꢃꢋ
ꢌꢏ
ꢁ
0.ꢟꢉ
ꢉ
ꢎꢒ
ꢒꢒ
ꢉ
ꢝꢏꢋ
0.ꢄꢈꢉ
ꢑ
ꢞꢇꢟꢄ ꢖꢋ
Rev. 0
10
For more information www.analog.com
LT8392
OPERATION
The LT8392 is a current mode DC/DC controller that can
regulate output voltage, input or output current from input
voltage above, below, or equal to the output voltage. The
ADI proprietary peak-buck peak-boost current mode con-
trol scheme uses a single inductor current sense resistor
and provides smooth transition between buck region,
buck-boost region, and boost region. Its operation is best
understood by referring to the Block Diagram.
ꢀ
ꢀ
ꢁꢂꢃ
ꢒꢓ
ꢃꢊꢈ
ꢋꢊꢈ
ꢅ
ꢄ
ꢃꢊꢉ
R
ꢑ
ꢆꢔꢓꢆꢔ
ꢆꢇꢈ
ꢆꢇꢉ
ꢋ
ꢐ
ꢋꢊꢉ
ꢌꢍꢎꢉ ꢏ0ꢈ
Figure 1. Simplified Diagram of the Power Switches
Power Switch Control
Figure 1 shows a simplified diagram of how the four
power switches A, B, C, and D are connected to the induc-
ꢀꢁꢂꢃꢄꢅꢆꢇꢃ
tor L, the current sense resistor R
, power input V ,
SENSE
IN
power output V , and ground. The current sense resis-
OUT
tor R
connected to the LSP and LSN pins provides
SENSE
inductor current information for both peak current mode
control and reverse current detection in buck region,
buck-boost region, and boost region. Figure 2 shows the
ꢀꢁꢂꢃꢄꢅꢈꢈꢉꢊ
current mode control as a function of V /V
ratio and
ꢐꢓꢏꢒ ꢔ0ꢒ
IN OUT
0.ꢏꢐ ꢑ.00 ꢑ.0ꢒ
ꢎꢋ
ꢋ
Figure 3 shows the operation region as a function of V /
ꢌꢍ ꢈꢆꢊ
V
ratio. The power switches are properly controllIeNd
OUT
Figure 2. Current Mode vs VIN/VOUT Ratio
to smoothly transition between modes and regions.
Hysteresis is added to prevent chattering between modes
and regions.
ꢄꢅꢆ
ꢀꢁꢂꢃ
There are a total of four states: (1) peak-buck current
mode control in buck region, (2) peak-buck current mode
control in buck-boost region, (3) peak-boost current
mode control in buck-boost region, and (4) peak-boost
current mode control in boost region. The following sec-
tions give detailed description for each state with wave-
forms, in which the shoot-through protection dead time
between switches A and B, between switches C and D are
ignored for simplification.
ꢄꢈꢆ
ꢀꢁꢂꢃꢌꢀꢉꢉꢊꢋ
ꢀꢉꢉꢊꢋ
ꢄꢇꢆ
ꢄꢖꢆ
0.ꢓꢒ 0.ꢑꢒ
ꢅ.00
ꢐꢍ
ꢅ.ꢅꢑ ꢅ.ꢈꢈ
ꢑꢈꢔꢇ ꢕ0ꢈ
ꢍ
ꢎꢏ ꢉꢁꢋ
Figure 3. Operation Region vs VIN/VOUT Ratio
Rev. 0
11
For more information www.analog.com
LT8392
OPERATION
(1) Peak-Buck in Buck Region (V >> V
)
(2) Peak-Buck in Buck-Boost Region (V ~> V
)
IN
OUT
IN
OUT
When V is much higher than V , the LT8392 uses
When V is slightly higher than V , the LT8392 uses
IN OUT
IN
OUT
peak-buck current mode control in buck region (Figure 4).
Switch C is always off and switch D is always on. At the
beginning of every cycle, switch A is turned on and the
inductor current ramps up. When the inductor current
hits the peak buck current threshold commanded by V
voltage at buck current comparator A3 during (A+DC)
phase, switch A is turned off and switch B is turned on
for the rest of the cycle. Switches A and B will alternate,
behaving like a typical synchronous buck regulator.
peak-buck current mode control in buck-boost region
(Figure 5). Switch C is always turned on for the begin-
ning 15% cycle and switch D is always turned on for the
remaining 85% cycle. At the beginning of every cycle,
switches A and C are turned on and the inductor current
ramps up. After 15% cycle, switch C is turned off and
switch D is turned on, and the inductor keeps ramping
up. When the inductor current hits the peak buck current
threshold commanded by V voltage at buck current com-
C
parator A3 during (A+D) phase, switch A is turned off and
switch B is turned on for the rest of the cycle.
ꢀ
ꢁ
ꢅ
ꢆ
ꢂ
ꢇ
ꢈ
ꢀ00ꢁ ꢂꢃꢃ
ꢀ00ꢁ ꢂꢄ
ꢃꢄꢅ
ꢃꢄꢅ
ꢇ
ꢆꢄꢅ
ꢆꢄꢅ
ꢈ
ꢉ
ꢉ
ꢊ
ꢀꢊꢇ
ꢀꢊꢇ
ꢆꢋꢈ
ꢆꢋꢈ
ꢀꢊꢂ
ꢀꢊꢂ
ꢁꢊꢇ
ꢁꢊꢇ
ꢅꢋꢈ
ꢅꢋꢈ
ꢆꢋꢌꢍ ꢎ0ꢄ
ꢌꢍꢎꢏ ꢃ0ꢐ
Figure 4. Peak-Buck in Buck Region (VIN >> VOUT
)
Figure 5. Peak-Buck in Buck-Boost Region (VIN ~> VOUT)
Rev. 0
12
For more information www.analog.com
LT8392
OPERATION
(3) Peak-Boost in Buck-Boost Region (V <~ V
)
(4) Peak-Boost in Boost Region (V << V
)
IN
OUT
IN
OUT
When V is slightly lower than V , the LT8392 uses
peak-boIoNst current mode controlOinUTbuck-boost region
(Figure 6). Switch A is always turned on for the begin-
ning 85% cycle and switch B is always turned on for the
remaining 15% cycle. At the beginning of every cycle,
switches A and C are turned on and the inductor current
ramps up. When the inductor current hits the peak boost
current threshold commanded by VC voltage at boost
current comparator A4 during (A+C) phase, switch C is
turned off and switch D is turned on for the rest of the
cycle. After 85% cycle, switch A is turned off and switch
B is turned on for the rest of the cycle.
When VIN is much lower than VOUT, the LT8392 uses peak-
boost current mode control in boost region (Figure 7).
Switch A is always on and switch B is always off. At the
beginning of every cycle, switch C is turned on and the
inductor current ramps up. When the inductor current
hits the peak boost current threshold commanded by
V voltage at boost current comparator A4 during (A+C)
C
phase, switch C is turned off and switch D is turned on
for the rest of the cycle. Switches C and D will alternate,
behaving like a typical synchronous boost regulator.
ꢀ
ꢁ
ꢆꢄꢅ
ꢆꢄꢅ
ꢀ
ꢁ
ꢃ00ꢄ ꢅꢆ
ꢃ00ꢄ ꢅꢇꢇ
ꢃꢄꢅ
ꢃꢄꢅ
ꢂ
ꢇ
ꢂ
ꢈ
ꢀꢊꢇ
ꢀꢊꢇ
ꢈ
ꢉ
ꢊ
ꢉ
ꢀꢊꢂ
ꢀꢊꢂ
ꢀꢋꢂ
ꢀꢋꢈ
ꢀꢋꢂ
ꢀꢋꢈ
ꢁꢊꢇ
ꢁꢊꢇ
ꢌꢍꢎꢏ ꢇ0ꢐ
ꢆꢋꢌꢍ ꢎ0ꢏ
Figure 6. Peak-Boost in Buck-Boost Region (VIN <~ VOUT
)
Figure 7. Peak-Boost in Boost Region (VIN << VOUT)
Rev. 0
13
For more information www.analog.com
LT8392
OPERATION
Main Control Loop
Internal Charge Path
The LT8392 is a fixed frequency current mode control-
ler. The inductor current is sensed through the inductor
sense resistor between the LSP and LSN pins. The current
sense voltage is gained up by amplifier A1 and added
to a slope compensation ramp signal from the internal
oscillator. The summing signal is then fed into the positive
terminals of the buck current comparator A3 and boost
current comparator A4. The negative terminals of A3 and
Each of the two top MOSFET drivers is biased from its
floating bootstrap capacitor, which is normally re-charged
by INTV through both the external and internal boot-
CC
strap diodes when the top MOSFET is turned off. When
the LT8392 operates exclusively in the buck or boost
regions, one of the top MOSFETs is constantly on. An
internal charge path, from VOUT and BST2 to BST1 or from
V and BST1 to BST2, charges the bootstrap capacitor to
IN
A4 are controlled by the voltage on the V pin, which is
4.6V so that the top MOSFET can be kept on.
C
the diode-OR of error amplifiers EA1 and EA2.
Shutdown and Power-On-Reset
Depending on the state of the peak-buck peak-boost cur-
rent mode control, either the buck logic or the boost logic
is controlling the four power switches so that either the
FB voltage is regulated to 1V or the current sense voltage
between the ISP and ISN pins is regulated by the CTRL
pin during normal operation. The gains of EA1 and EA2
have been balanced to ensure smooth transition between
constant-voltage and constant-current operation with the
same compensation network.
The LT8392 enters shutdown mode and drains less than
2µA quiescent current when the EN/UVLO pin is below
its shutdown threshold (0.3V minimum). Once the EN/
UVLO pin is above its shutdown threshold (1V maximum),
the LT8392 wakes up startup circuitry, generates band-
gap reference, and powers up the internal INTV LDO.
CC
The INTV LDO supplies the internal control circuitry
CC
and gate drivers. Now the LT8392 enters undervoltage
lockout (UVLO) mode with a hysteresis current (2.5µA
Light Load Current Operation
typical) pulled into the EN/UVLO pin. When the INTV pin
CC
is charged above its rising UVLO threshold (3.76V typi-
cal), the EN/UVLO pin passes its rising enable threshold
(1.233V typical), and the junction temperature is less than
its thermal shutdown (165°C typical), the LT8392 enters
enable mode, in which the EN/UVLO hysteresis current is
turned off and the voltage reference VREF is being charged
up from ground. From the time of entering enable mode to
the time of VREF passing its rising UVLO threshold (1.89V
typical), the LT8392 is going through a power-on-reset
(POR), waking up the entire internal control circuitry and
settling to the right initial conditions. After the POR, the
LT8392 starts switching.
At light load, the LT8392 runs either at full switching fre-
quency discontinuous conduction mode or pulse-skip-
ping mode, where the switches are held off for multiple
cycles (i.e., skipping pulses) to maintain the regulation
and improve the efficiency.
In the buck region, switch B is turned off whenever the
buck reverse current threshold is triggered during (B+D)
phase. In the boost region, switch D is turned off when-
ever the boost reverse current threshold is triggered
during (A+D) phase. In the buck-boost region, switch D
is turned off whenever the boost reverse current thresh-
old is triggered during (A+D) phase, and both switches B
and D are turned off whenever the buck reverse current
threshold is triggered during (B+D) phase.
Rev. 0
14
For more information www.analog.com
LT8392
OPERATION
Start-Up and Fault Protection
During the UP/RUN state, the switching is enabled and
the start-up of the output voltage V
is controlled by
OUT
Figure 8 shows the start-up and fault sequence for the
LT8392. During the POR state, the SS pin is hard pulled
down with a 100Ω to ground. In a pre-biased condition,
the SS pin has to be pulled below 0.2V to enter the INIT
state, where the LT8392 wait 10µs so that the SS pin can
be fully discharged to ground. After the 10µs, the LT8392
enters the UP/PRE state.
the voltage on the SS pin. When the SS pin voltage is less
than 1V, the LT8392 regulates the FB pin voltage to the SS
pin voltage instead of the 1V reference. This allows the SS
pin to program soft-start by connecting an external capac-
itor from the SS pin to GND. The internal 12.5µA pull-up
current charges up the capacitor, creating a voltage ramp
on the SS pin. As the SS pin voltage rises linearly from
During the UP/PRE state, the SS pin is charged up by a
12.5µA pull-up current while the switching is disabled.
Once the SS pin is charged above 0.25V, the LT8392
enters the UP/TRY state. After 10µs in the UP/TRY state,
the LT8392 enters the UP/RUN state.
0.25V to 1V (and beyond), the output voltage V
smoothly to its final regulation voltage.
rises
OUT
Once the SS pin is charged above 1.75V, the LT8392
enters the OK/RUN state, where the output short detection
is activated. The output short means V < 0.25V. When
FB
the output short happens, the LT8392 enters the FAULT/
RUN state, where a 1.25µA pull-down current slowly dis-
charges the SS pin with the other conditions the same as
the OK/RUN state. Once the SS pin is discharged below
1.7V, the LT8392 enters the DOWN/STOP state, where
the switching is disabled and the short detection is deac-
tivated with the previous fault latched. Once the SS pin
is discharged below 0.2V, the LT8392 goes back to the
UP/RUN state.
ꢓꢔR ꢕ ꢖꢗ ꢉꢄ
ꢗꢁꢔꢘ ꢕ ꢖꢗ
POR
INIT
ꢀ ꢁꢁ ꢂꢃꢄꢅ ꢆꢇꢈꢈ ꢅꢉꢊꢋ
ꢀ ꢁꢊꢌꢍꢎꢂꢌꢋꢏ ꢅꢌꢐꢃꢑꢈeꢅ
ꢀ ꢒꢉ ꢐꢂꢉꢄꢍ ꢅeꢍeꢎꢍꢌꢉꢋ
ꢀ ꢁꢁ ꢂꢃꢄꢅ ꢆꢇꢈꢈ ꢅꢉꢊꢋ
ꢀ ꢁꢊꢌꢍꢎꢂꢌꢋꢏ ꢅꢌꢐꢃꢑꢈeꢅ
ꢀ ꢒꢉ ꢐꢂꢉꢄꢍ ꢅeꢍeꢎꢍꢌꢉꢋ
ꢁꢁ ꢙ 0.ꢚꢛ
ꢁꢁ ꢡ 0.ꢚꢝꢛ
ꢁꢁ ꢡ ꢜ.ꢢꢝꢛ
ꢁꢁ ꢙ ꢜ.ꢢꢛ
ꢠꢃꢌꢍ ꢜ0ꢞꢐ
UP/TRY
UP/PRE
ꢀ ꢁꢁ ꢜꢚ.ꢝꢞꢟ ꢆꢇꢈꢈ ꢇꢆ
ꢀ ꢁꢊꢌꢍꢎꢂꢌꢋꢏ ꢅꢌꢐꢃꢑꢈeꢅ
ꢀ ꢒꢉ ꢐꢂꢉꢄꢍ ꢅeꢍeꢎꢍꢌꢉꢋ
ꢀ ꢁꢁ ꢜꢚ.ꢝꢞꢟ ꢆꢇꢈꢈ ꢇꢆ
ꢀ ꢁꢊꢌꢍꢎꢂꢌꢋꢏ ꢅꢌꢐꢃꢑꢈeꢅ
ꢀ ꢒꢉ ꢐꢂꢉꢄꢍ ꢅeꢍeꢎꢍꢌꢉꢋ
In an output short condition, the LT8392 can be set to
hiccup, latch-off, or keep-running fault protection mode
with a resistor between the SS and VREF pins. Without any
resistor, the LT8392 will hiccup between 0.2V and 1.75V
and go around the UP/RUN, OK/RUN, FAULT/RUN, and
DOWN/STOP states until the fault condition is cleared.
With a 499kΩ resistor, the LT8392 will latch off until the
EN/UVLO is toggled. With a 100kΩ resistor, the LT8392
will keep running regardless of the fault.
ꢠꢃꢌꢍ ꢜ0ꢞꢐ
UP/RUN
OK/RUN
ꢀ ꢁꢁ ꢜꢚ.ꢝꢞꢟ ꢆꢇꢈꢈ ꢇꢆ
ꢀ ꢁꢊꢌꢍꢎꢂꢌꢋꢏ eꢋꢃꢑꢈeꢅ
ꢀ ꢒꢉ ꢐꢂꢉꢄꢍ ꢅeꢍeꢎꢍꢌꢉꢋ
ꢀ ꢁꢁ ꢜꢚ.ꢝꢞꢟ ꢆꢇꢈꢈ ꢇꢆ
ꢀ ꢁꢊꢌꢍꢎꢂꢌꢋꢏ eꢋꢃꢑꢈeꢅ
ꢀ ꢁꢂꢉꢄꢍ ꢅeꢍeꢎꢍꢌꢉꢋ
ꢁꢁ ꢙ 0.ꢚꢛ ꢃꢋꢅ
ꢣꢔꢟꢤ ꢕ ꢖꢗ
ꢁꢖꢔRꢥ
ꢔꢒ
DOWN/STOP
FAULT/RUN
ꢀ ꢁꢁ ꢜ.ꢚꢝꢞꢟ ꢆꢇꢈꢈ ꢅꢉꢊꢋ
ꢀ ꢁꢊꢌꢍꢎꢂꢌꢋꢏ ꢅꢌꢐꢃꢑꢈeꢅ
ꢀ ꢒꢉ ꢐꢂꢉꢄꢍ ꢅeꢍeꢎꢍꢌꢉꢋ
ꢀ ꢁꢁ ꢜ.ꢚꢝꢞꢟ ꢆꢇꢈꢈ ꢅꢉꢊꢋ
ꢀ ꢁꢊꢌꢍꢎꢂꢌꢋꢏ eꢋꢃꢑꢈeꢅ
ꢀ ꢁꢂꢉꢄꢍ ꢅeꢍeꢎꢍꢌꢉꢋ
ꢦꢧꢨꢚ ꢩ0ꢦ
Figure 8. Start-Up and Fault Sequence
Rev. 0
15
For more information www.analog.com
LT8392
APPLICATIONS INFORMATION
The front page shows a typical LT8392 application circuit.
This Applications Information section serves as a guideline
of selecting external components for typical applications.
The examples and equations in this section assume con-
tinuous conduction mode unless otherwise specified.
implements a triangle spread spectrum frequency mod-
ulation scheme. With the SYNC/SPRD pin tied to INTV ,
CC
the LT8392 starts to spread its switching frequency
15% around the internal oscillator frequency. Figure 9
and Figure 10 show the noise spectrum of the front page
application when spread spectrum enabled.
Switching Frequency Selection
ꢍ0
ꢛꢛꢀꢈ ꢜꢄ ꢝꢒꢞꢉ ꢁꢈꢒ ꢀꢒꢟꢞꢁR
ꢄꢜꢒꢛꢁ ꢀꢟꢜꢜR
ꢅꢒꢛꢠꢁR ꢘꢐ ꢅꢟꢡꢛꢛ ꢐ ꢠꢁꢡꢢ ꢟꢒꢈꢒꢞꢛ
ꢌ0
The LT8392 uses a constant frequency control scheme
between 150kHz and 650kHz. Selection of the switching
frequency is a trade-off between efficiency and compo-
nent size. Low frequency operation improves efficiency
by reducing MOSFET switching losses, but requires larger
inductor and capacitor values. For high power applica-
tions, consider operating at lower frequencies to minimize
MOSFET heating from switching losses. For low power
applications, consider operating at higher frequencies to
minimize the total solution size.
ꢎ0
ꢏ0
ꢟꢝ
ꢐ0
ꢑ0
ꢗ0
ꢘ0
ꢙ0
0
ꢈꢝ
ꢛꢝ
ꢅꢔ
ꢚꢙ0
0.ꢙ
ꢙ
ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊꢋ
ꢙ0
ꢌꢗꢍꢘ ꢀ0ꢍ
Figure 9. Average Conducted EMI
In addition, the specific application also plays an import-
ant role in switching frequency selection. In a noise-sensi-
tive system, the switching frequency is usually selected to
keep the switching noise out of a sensitive frequency band.
ꢍ0
ꢌ0
ꢎ0
ꢏ0
ꢐ0
ꢑ0
ꢗ0
ꢘ0
ꢙ0
0
ꢛꢛꢀꢈ ꢜꢄ ꢝꢒꢞꢉ ꢁꢈꢒ ꢀꢒꢟꢞꢁR
ꢄꢜꢒꢛꢁ ꢀꢟꢜꢜR
ꢅꢒꢛꢠꢁR ꢘꢐ ꢅꢟꢡꢛꢛ ꢐ ꢠꢁꢡꢢ ꢟꢒꢈꢒꢞꢛ
ꢟꢝ
ꢈꢝ
ꢛꢝ
ꢅꢔ
Switching Frequency Setting
The switching frequency of the LT8392 can be set by
the internal oscillator. With the SYNC/SPRD pin pulled to
ground, the switching frequency is set by a resistor from
ꢚꢙ0
the RT pin to ground. Table 1 shows R resistor values
T
0.ꢙ
ꢙ
ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊꢋ
ꢙ0
for common switching frequencies.
ꢌꢗꢍꢘ ꢀꢙ0
Figure 10. Peak Conducted EMI
Table 1. Switching Frequency vs RT Value (1% Resistor)
f
(kHz)
R (k)
OSC
T
Frequency Synchronization
150
309
226
140
100
75
200
300
400
500
600
650
The LT8392 switching frequency can be synchronized to
an external clock using the SYNC/SPRD pin. Driving the
SYNC/SPRD with a 50% duty cycle waveform is always a
good choice, otherwise maintain the duty cycle between
10% and 90%. Due to the use of a phase-locked loop
(PLL) inside, there is no restriction between the synchro-
nization frequency and the internal oscillator frequency.
The rising edge of the synchronization clock represents
the beginning of a switching cycle, turning on switches A
and C, or switches A and D.
59
51.1
Spread Spectrum Frequency Modulation
Switching regulators can be particularly troublesome for
applications where electromagnetic interference (EMI) is
a concern. To improve the EMI performance, the LT8392
Rev. 0
16
For more information www.analog.com
LT8392
APPLICATIONS INFORMATION
Inductor Selection
R
Selection and Maximum Output Current
SENSE
The switching frequency and inductor selection are inter-
related in that higher switching frequencies allow the use
of smaller inductor and capacitor values. The inductor
value has a direct effect on ripple current. The highest cur-
R
is chosen based on the required output current.
SENSE
The duty cycle independent maximum current sense
thresholds (50mV in peak-buck and 50mV in peak-boost)
set the maximum inductor peak current in buck region,
buck-boost region, and boost region.
rent ripple ∆I % happens in the buck region at V
,
L
IN(MAX)
and the lowest current ripple ∆I % happens in the boost
L
In boost region, the lowest maximum average load cur-
rent happens at V
region at V
. For any given ripple allowance set by
customers, the minimum inductance can be calculated as:
IN(MIN)
and can be calculated as:
IN(MIN)
VIN(MIN)
ΔIL(BOOST)
⎛
⎞
50mV
IOUT(MAX_BOOST)
=
−
•
VOUT • VIN(MAX) − V
(
)
OUT
⎜
⎟
R
2
VOUT
⎝
⎠
LBUCK
>
SENSE
f •IOUT(MAX) • ΔIL% • V
IN(MAX)
where ∆I
is peak-to-peak inductor ripple current
L(BOOST)
V
2 • V
− V
(
)
IN(MIN)
IN(MIN)
OUT
in boost region and can be calculated as:
LBOOST
where:
ΔIL% =
>
2
f •IOUT(MAX) • ΔIL% • VOUT
V
• V
− V
IN(MIN)
OUT
(
)
IN(MIN)
ΔIL(BOOST)
=
f •L • VOUT
ΔIL
IL(AVG)
In buck region, the lowest maximum average load current
happens at V and can be calculated as:
IN(MAX)
ΔIL(BUCK)
⎛
⎞
50mV
f is switching frequency
IOUT(MAX_BUCK)
=
−
⎜
⎟
R
2
⎝
⎠
SENSE
V
V
V
is minimum input voltage
is maximum input voltage
IN(MIN)
IN(MAX)
where ∆IL(BUCK) is peak-to-peak inductor ripple current in
buck region and can be calculated as:
is output voltage
OUT
VOUT • VIN(MAX) − V
(
)
OUT
I
is maximum output current
OUT(MAX)
ΔIL(BUCK)
=
f •L • V
IN(MAX)
Slope compensation provides stability in constant fre-
quency current mode control by preventing subharmonic
oscillations at certain duty cycles. The minimum induc-
tance required for stability when duty cycles are larger
than 50% can be calculated as:
The maximum current sense R
in boost region is:
SENSE
2 • 50mV • V
IN(MIN)
RSENSE(BOOST)
=
2 •IOUT(MAX) • VOUT + ΔIL(BOOST) • V
IN(MIN)
10 • VOUT •RSENSE
L >
The maximum current sense R
in buck region is
SENSE
f
2 • 50mV
2 •IOUT(MAX) + ΔIL(BUCK)
RSENSE(BUCK)
=
For high efficiency, choose an inductor with low core loss,
such as ferrite. Also, the inductor should have low DC
2
resistance to reduce the I R losses, and must be able to
The final R
SENSE
value should be lower than the calculated
R
in SbEoNtShEbuck and boost regions. A 20% to 30%
handle the peak inductor current without saturating. To
minimize radiated noise, use a shielded inductor.
margin is usually recommended. Always choose a low
ESL current sense resistor.
Rev. 0
17
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LT8392
APPLICATIONS INFORMATION
Power MOSFET Selection
RC,D is the maximum RDS(ON) of MOSFETs C or D
at 25°C
The LT8392 requires four external N-channel power
MOSFETs, two for the top switches (switches A and D
shown in Figure 1) and two for the bottom switches
(switches B and C shown in Figure 1). Important param-
eters for the power MOSFETs are the breakdown voltage
VBR(DSS), threshold voltage VGS(TH), on-resistance
RDS(ON), reverse transfer capacitance CRSS and maximum
R is the maximum DCR resistor of inductor at 25°C
L
The RDS(ON) and DCR increase at higher junction
temperatures and the process variation have been
included in the calculation above.
In order to select the power MOSFETs, the power dis-
sipated by the device must be known. For switch A, the
maximum power dissipation happens in boost region,
when it remains on all the time. Its maximum power dis-
sipation at maximum output current is given by:
current I
.
DS(MAX)
Since the gate drive voltage is set by the 5V INTVCC
supply, logic-level threshold MOSFETs must be used in
LT8392 applications. Switching four MOSFETs at higher
frequency like 2MHz, the substantial gate charge current
2
I
OUT(MAX) • VOUT
⎛
⎞
PA(BOOST)
=
• ρT •RDS(ON)
from INTV can be estimated as:
CC
⎜
⎟
V
⎝
⎠
IN
IINTVCC = f • QgA +QgB +Q +QgD
gC
where ρT is a normalization factor (unity at 25°C) account-
ing for the significant variation in on-resistance with tem-
perature, typically 0.4%/°C as shown in Figure 11. For a
maximum junction temperature of 125°C, using a value
where:
f is the switching frequency
of ρ = 1.5 is reasonable.
QgA, QgB, QgC, QgD are the total gate charges of
MOSFETs A, B, C, D
T
Switch B operates in buck region as the synchronous
rectifier. Its power dissipation at maximum output cur-
rent is given by:
Make sure the total required INTV current not exceeding
CC
the INTV current limit in the data sheet.
CC
V − V
The LT8392 uses the V /V
ratio to transition between
IN
OUT
IN OUT
P
=
•IOUT(MAX)2 • ρT •RDS(ON)
B(BUCK)
modes and regions. Bigger IR drop in the power path
caused by improper MOSFET and inductor selection may
prevent the LT8392 from smooth transition. To ensure
smooth transitions between buck, buck-boost, and boost
V
IN
2.0
modes of operation, choose low R
low DCR inductor to satisfy:
MOSFETs and
DS(ON)
1.5
1.0
0.5
0
0.025 • VOUT
A,B +RC,D +RSENSE +RL
IOUT(MAX)
≤
R
where:
RA,B is the maximum RDS(ON) of MOSFETs A or B
at 25°C
50
100
–50
150
0
JUNCTION TEMPERATURE (°C)
8392 F11
Figure 11. Normalized RDS(ON) vs Temperature
Rev. 0
18
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LT8392
APPLICATIONS INFORMATION
Switch C operates in boost region as the control switch.
Its power dissipation at maximum current is given by:
D turn-off and switch C turn-on. They improve converter
efficiency and reduce switch voltage stress. In order for
the diode to be effective, the inductance between it and
the synchronous switch must be as small as possible,
mandating that these components be placed adjacently.
V
− V • V
IN
(
=
)
PC(BOOST)
•IOUT(MAX)2 • ρT
OUT
OUT
3
2
V
IN
IOUT(MAX)
C and C
Selection
•RDS(ON) + k • VOUT
•
•CRSS • f
IN
OUT
V
IN
Input and output capacitance is necessary to suppress
voltage ripple caused by discontinuous current moving
in and out the regulator. A parallel combination of capac-
itors is typically used to achieve high capacitance and low
equivalent series resistance (ESR). Dry tantalum, special
polymer, aluminum electrolytic and ceramic capacitors are
all available in surface mount packages. Capacitors with
low ESR and high ripple current ratings, such as OS-CON
and POSCAP are also available.
where C
is usually specified by the MOSFET manufac-
RSS
turers. The constant k, which accounts for the loss caused
by reverse recovery current, is inversely proportional to
the gate drive current and has an empirical value of 1.7.
For switch D, the maximum power dissipation happens in
boost region, when its duty cycle is higher than 50%. Its
maximum power dissipation at maximum output current
is given by:
Ceramic capacitors should be placed near the regulator
input and output to suppress high frequency switching
spikes. Ceramic capacitors, of at least 1µF, should also
VOUT
P
=
•IOUT(MAX)2 • ρT •RDS(ON)
D(BOOST)
V
IN
be placed from V to GND and V
to GND as close to
IN
OUT
For the same output voltage and current, switch A has the
highest power dissipation and switch B has the lowest
power dissipation unless a short occurs at the output.
the LT8392 pins as possible. Due to their excellent low
ESR characteristics, ceramic capacitors can significantly
reduce input ripple voltage and help reduce power loss
in the higher ESR bulk capacitors. X5R or X7R dielec-
trics are preferred, as these materials retain their capac-
itance over wide voltage and temperature ranges. Many
ceramic capacitors, particularly 0805 or 0603 case sizes,
have greatly reduced capacitance at the desired operating
voltage.
From a known power dissipated in the power MOSFET, its
junction temperature can be obtained using the following
formula:
T = T + P • R
TH(JA)
J
A
The junction-to-ambient thermal resistance RTH(JA)
includes the junction-to-case thermal resistance R
TH(JC)
. This
Input Capacitance CIN: Discontinuous input current is
and the case-to-ambient thermal resistance R
TH(CA)
highest in the buck region due to the switch A toggling
value of T can then be compared to the original, assumed
value useJd in the iterative calculation process.
on and off. Make sure that the C capacitor network has
IN
low enough ESR and is sized to handle the maximum RMS
current. In buck region, the input RMS current is given by:
Optional Schottky Diode (D , D ) Selection
B
D
VOUT
V
IN
VOUT
The optional Schottky diodes D (in parallel with switch
B
I
RMS ≈IOUT(MAX)
The formula has a maximum at V = 2V , where I
RMS
•
•
−1
B) and D (in parallel with switch D) conduct during the
D
V
IN
dead time between the conduction of the power MOSFET
switches. They are intended to prevent the body diode
of synchronous switches B and D from turning on and
storing charge during the dead time. In particular, DB
significantly reduces reverse recovery current between
IN
OUT
= I
/2. This simple worst-case condition is com-
monly used for design because even significant deviations
do not offer much relief.
OUT(MAX)
switch B turn-off and switch A turn-on, and D signifi-
D
cantly reduces reverse recovery current between switch
Rev. 0
19
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LT8392
APPLICATIONS INFORMATION
Output Capacitance C : Discontinuous current shifts
for the power dissipation calculation. The total LT8392
power dissipation in this case is V • I , and overall
OUT
from the input to the output in the boost region. Make
IN INTVCC
sure that the C
capacitor network is capable of reduc-
efficiency is lowered. The junction temperature can be
OUT
ing the output voltage ripple. The effects of ESR and the
bulk capacitance must be considered when choosing the
right capacitor for a given output ripple voltage. The max-
imum steady state ripple due to charging and discharging
the bulk capacitance is given by:
estimated by using the equation:
T = T + P • θ
JA
J
A
D
where θ (in °C/W) is the package thermal resistance.
JA
To prevent maximum junction temperature from being
exceeded, the input supply current must be checked oper-
IOUT(MAX) • V
− V
IN(MIN)
(
)
OUT
ating in continuous mode at maximum V .
ΔVCAP(BOOST)
=
IN
COUT • VOUT • f
Top Gate MOSFET Driver Supply (C
, C
)
BST1 BST2
⎛
⎞
VOUT
V
OUT • ⎜1−
⎟
The top MOSFET drivers, TG1 and TG2, are driven between
their respective SW and BST pin voltages. The boost volt-
V
⎝
⎠
IN(MAX)
ΔVCAP(BUCK)
=
8 •L • f2 •COUT
ages are biased from floating bootstrap capacitors C
BST1
and C , which are normally recharged through both the
BST2
The maximum steady ripple due to the voltage drop
across the ESR is given by:
external and internal bootstrap diodes when the respec-
tive top MOSFET is turned off. External bootstrap diodes
are recommended because the internal bootstrap diodes
are not always strong enough to refresh top MOSFETs at
2MHz. Both capacitors are charged to the same voltage
as the INTV voltage. The bootstrap capacitors C
VOUT •IOUT(MAX)
ΔV
=
•ESR
ESR(BOOST)
V
IN(MIN)
⎛
⎞
⎟
VOUT
CC
BST1
V
OUT • ⎜1−
and C
, need to store about 100 times the gate charge
BST2
V
⎝
⎠
IN(MAX)
required by the top switches A and D. In most applica-
tions, a 0.1µF to 0.47µF, X5R or X7R dielectric capacitor
is adequate.
ΔV
=
•ESR
ESR(BUCK)
L • f
INTV Regulator
CC
Programming V UVLO
IN
An internal P-channel low dropout regulator produces
5V at the INTV pin from the V supply pin. The INTV
A resistor divider from V to the EN/UVLO pin imple-
CC
IN
CC
IN
powers internal circuitry and gate drivers in the LT8392.
The INTV regulator can supply a peak current of 145mA
and musCtCbe bypassed to ground with a minimum of
4.7µF ceramic capacitor. Good local bypass is necessary
to supply the high transient current required by MOSFET
gate drivers.
ments VIN undervoltage lockout (UVLO). The EN/UVLO
enable falling threshold is set at 1.220V with 13mV hyster-
esis. In addition, the EN/UVLO pin sinks 2.5µA when the
voltage on the pin is below 1.220V. This current provides
user programmable hysteresis based on the value of R1.
The programmable UVLO thresholds are:
Higher input voltage applications with large MOSFETs
being driven at higher switching frequencies may cause
the maximum junction temperature rating for the LT8392
to be exceeded. The system supply current is normally
dominated by the gate charge current. Additional external
R1+R2
V
IN(UVLO+) = 1.233V •
+ 2.5µA •R1
R2
R1+R2
R2
VIN(UVLO−) = 1.220V •
loading of the INTV also needs to be taken into account
CC
Rev. 0
20
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LT8392
APPLICATIONS INFORMATION
Figure 12 shows the implementation of external shut-
down control while still using the UVLO function. The
NMOS grounds the EN/UVLO pin when turned on, and
puts the LT8392 in shutdown with quiescent current less
than 2µA.
When V
is larger than 1.35V, the current threshold
CTRL
is regulated to:
50mV
RIS
I
=
IS(MAX)
ꢆ
ꢇꢈ
The CTRL pin should not be left open (tie to V
if not
REF
used). The CTRL pin can also be used in conjunction with
Rꢉ
a thermistor to provide overtemperature protection for
ꢓꢈꢊꢔꢆꢀꢌ
ꢀꢁꢂꢃꢄꢅ
the output load, or with a resistor divider to V to reduce
IN
ꢀꢁꢂꢊꢋꢁꢌꢍ
ꢎꢌꢈꢁRꢌꢀ
ꢏꢌꢍꢁꢇꢌꢈꢐꢀꢑ
Rꢅ
output power and switching current when V is low.
IN
The presence of a time varying differential voltage rip-
ple signal across the ISP and ISN pins at the switching
ꢕꢈꢖ
ꢂꢃꢄꢅ ꢒꢉꢅ
frequency is expected. If the current sense resistor R
IS
Figure 12. VIN Undervoltage Lockout (UVLO)
is placed between power input and input bulk capacitor
(Figure 13a), or between output bulk capacitor and sys-
tem output (Figure 14a), a filter is typically not neces-
Programming Input or Output Current Limit
The input or output current limit can be programmed by
sary. If the R is placed between input bulk capacitor
IS
placing an appropriate value current sense resistor, R , in
IS
and input decoupling capacitor (Figure 13b), or between
output decoupling capacitor and output bulk capacitor
the input or output power path. The voltage drop across
R is (Kelvin) sensed by the ISP and ISN pins. The CTRL
IS
(Figure 14b), a low pass filter formed by R and C is
F
F
pin should be tied to a voltage higher than 1.35V to get
the full-scale 50mV (typical) threshold across the sense
resistor. The CTRL pin can be used to reduce the current
threshold to zero, although relative accuracy decreases
with the decreasing sense threshold. When the CTRL pin
voltage is between 0.3V and 1.15V, the current limit is:
recommended to reduce the current ripple and stabilize
R
ꢆꢇ
ꢉRꢎꢔ ꢈꢎꢑꢕR
ꢆꢌꢈꢖꢁ
ꢁꢎ ꢏRꢐꢆꢌ ꢎꢉ
ꢇꢑꢆꢁꢒꢓ ꢐ
ꢍ
ꢆꢇꢈ
ꢆꢇꢌ
V
CTRL −0.25V
20•RIS
I
=
IS(MAX)
ꢀꢁꢂꢃꢄꢅ
ꢂꢃꢄꢅ ꢉꢊꢃꢋ
When V
is between 1.15V and 1.35V the current limit
CTRL
varies with V
(13a)
, but departs from the equation above
CTRL
by an increasing amount as V
increases. Ultimately,
CTRL
R
ꢆꢇ
ꢉRꢏꢔ ꢈꢏꢒꢕR
ꢆꢌꢈꢖꢁ
ꢁꢏ ꢐRꢑꢆꢌ ꢏꢉ
ꢇꢒꢆꢁꢍꢓ ꢑ
when V
is larger than 1.35V, the current limit no lon-
ger varCieTsR.LThe typical V(ISP-ISN) threshold vs VCTRL is
listed in Table 2.
ꢎ
R
ꢉ
R
ꢉ
ꢍ
ꢉ
Table 2. V(ISP-ISN) Threshold vs VCTRL
ꢆꢇꢈ
ꢆꢇꢌ
V
(V)
V
(mV)
CTRL
(ISP-ISN)
ꢀꢁꢂꢃꢄꢅ
1.15
45
ꢂꢃꢄꢅ ꢉꢊꢃꢋ
1.20
1.25
1.30
1.35
47.2
49
(13b)
49.8
50
Figure 13. Programming Input Current Limit
Rev. 0
21
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LT8392
APPLICATIONS INFORMATION
ꢆ
R
ꢇꢈꢁ
ꢆꢇ
ꢉRꢏꢒ ꢔRꢕꢆꢍ ꢏꢉ
ꢇꢖꢆꢁꢗꢘ ꢔ
ꢁꢏ ꢇꢐꢇꢁꢑꢒ
ꢏꢓꢁꢈꢓꢁ
ꢎ
Rꢃ
ꢀꢁꢂꢃꢄꢅ
ꢊꢍ
Rꢉ
ꢆꢇꢈ
ꢆꢇꢍ
ꢂꢃꢄꢅ ꢊꢋꢌ
ꢀꢁꢂꢃꢄꢅ
Figure 15. Feedback Resistor Connection
ꢂꢃꢄꢅ ꢉꢊꢋꢌ
(14a)
R3+R4
VOUT = 1V •
R4
R
ꢆꢇ
ꢉRꢏꢒ ꢕRꢖꢆꢍ ꢏꢉ
ꢇꢗꢆꢁꢎꢘ ꢕ
ꢁꢏ ꢇꢐꢇꢁꢑꢒ
ꢏꢓꢁꢈꢓꢁ
ꢔ
In addition, the FB pin also sets output overvoltage
threshold, output power good thresholds, and output
short threshold. For an application with small output
capacitors, the output voltage may overshoot a lot during
load transient event. Once the FB pin hits its overvoltage
threshold 1.08V, the LT8392 stops switching by turning
R
ꢉ
R
ꢉ
ꢎ
ꢉ
ꢆꢇꢈ
ꢆꢇꢍ
ꢀꢁꢂꢃꢄꢅ
ꢂꢃꢄꢅ ꢉꢊꢋꢌ
off TG1, BG1, TG2, and BG2, and also turns off EXTV
CC
(14b)
to disconnect the output load for protection. The output
overvoltage threshold can be set as:
Figure 14. Programming Output Current Limit
R3+R4
V
OUT(OVP) = 1.08V •
the current loop. Since the bias currents of the ISP and
R4
ISN pins are matched, no offset is introduced by R . If
F
input or output current limit is not used, the ISP and ISN
To provide the output short-circuit detection and protec-
tion, the output short falling threshold can be set as:
pins should be shorted to V , V , or ground.
IN OUT
R3+R4
ISMON Current Monitor
V
OUT(SHORT) = 0.25V •
R4
The ISMON pin provides a buffered monitor output of
the current flowing through the ISP/ISN current sense
resistor, RIS. The VISMON voltage is calculated as V(ISP-ISN)
• 20 + 0.25V. Since the ISMON pin has the same 0.25V
offset as the CTRL pin, the master LT8392 ISMON pin can
be directly tied to the slave LT8392 CTRL pin for equal
current sharing in parallel applications.
Power GOOD (PGOOD) Pin
The LT8392 provides an open-drain status pin, PGOOD,
which is pulled low when V is within 8% of the 1.00V
FB
regulation voltage. The PGOOD pin is allowed to be pulled
up by an external resistor to INTV or an external voltage
CC
source of up to 6V.
Programming Output Voltage and Thresholds
Soft-Start and Short-Circuit Protection
The LT8392 has a voltage feedback pin FB that can be
used to program a constant-voltage output. The output
voltage can be set by selecting the values of R3 and R4
(Figure 15) according to the following equation:
As shown in Figure 8 and explained in the Operation sec-
tion, the SS pin can be used to program the output voltage
soft-start by connecting an external capacitor from the
SS pin to ground. The internal 12.5µA pull-up current
charges up the capacitor, creating a voltage ramp on the
Rev. 0
22
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LT8392
APPLICATIONS INFORMATION
SS pin. As the SS pin voltage rises linearly from 0.25V
to 1V (and beyond), the output voltage rises smoothly
into its final voltage regulation. The soft-start time can
be calculated as:
and capacitor on the V pin are set to optimize control
C
loop response and stability. For a typical voltage regulator
application, a 2.2nF compensation capacitor on the V pin
C
is adequate, and a series resistor should always be used
to increase the slew rate on the V pin to maintain tighter
C
CSS
12.5µA
t
SS = 1V •
output voltage regulation during fast transients on the
input supply of the converter.
Make sure the C is at least five to ten times larger than
SS
Efficiency Considerations
the compensation capacitor on the V pin for a well-con-
C
The power efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Although all dissipative
elements in circuits produce losses, four main sources
account for most of the losses in LT8392 circuits:
trolled output voltage soft-start. A 22nF ceramic capacitor
is a good starting point.
The SS pin is also used as a fault timer. Once an output
short-circuit fault is detected, a 1.25µA pull-down current
source is activated. Using a single resistor from the SS
pin to the V pin, the LT8392 can be set to three differ-
REF
ent fault protection modes: hiccup (no resistor), latch-off
2
1. DC I R losses. These arise from the resistances of the
(499k), and keep-running (100k).
MOSFETs, sensing resistor, inductor and PC board
traces and cause the efficiency to drop at high output
currents.
With a 100k resistor in keep-running mode, the LT8392
continues switching normally and regulates the current
into ground. With a 499k resistor in latch-off mode, the
LT8392 stops switching until the EN/UVLO pin is pulled
low and high to restart. With no resistor in hiccup mode,
the LT8392 enters low duty cycle auto-retry operation.
The 1.25µA pull-down current discharges the SS pin to
0.2V and then 12.5µA pull-up current charges the SS
pin up. If the output short-circuit condition has not been
removed when the SS pin reaches 1.75V, the 1.25µA pull-
down current turns on again, initiating a new hiccup cycle.
This will continue until the fault is removed. Once the
output short-circuit condition is removed, the output will
have a smooth short-circuit recovery due to soft-start.
2. Transition loss. This loss arises from the brief amount
of time switch A or switch C spends in the saturated
region during switch node transitions. It depends upon
the input voltage, load current, driver strength and
MOSFET capacitance, among other factors.
3. INTV current. This is the sum of the MOSFET driver
CC
and control currents.
4. CIN and COUT loss. The input capacitor has the diffi-
cult job of filtering the large RMS input current to the
regulator in buck region. The output capacitor has the
difficult job of filtering the large RMS output current in
boost region. Both C and C
are required to have
Loop Compensation
IN
low ESR to minimize the ACOIU2TR loss and sufficient
capacitance to prevent the RMS current from causing
additional upstream losses in fuses or batteries.
The LT8392 uses an internal transconductance error
amplifier, the output of which, V , compensates the con-
C
trol loop. The external inductor, output capacitor, and the
compensation resistor and capacitor determine the loop
stability.
5. Other losses. Schottky diode D and D are responsi-
B
D
ble for conduction losses during dead time and light
load conduction periods. Inductor core loss occurs
predominately at light loads. Switch A causes reverse
The inductor and output capacitor are chosen based on
performance, size and cost. The compensation resistor
Rev. 0
23
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LT8392
APPLICATIONS INFORMATION
n
n
recovery current loss in buck region, and switch C
causes reverse recovery current loss in boost region.
Keep the high dV/dT SW1, SW2, BST1, BST2, TG1 and
TG2 nodes away from sensitive small-signal nodes.
When making adjustments to improve efficiency, the
input current is the best indicator of changes in effi-
ciency. If you make a change and the input current
decreases, then the efficiency has increased. If there is
no change in the input current, then there is no change
in efficiency.
The path formed by switch A, switch B, DB and the
C
capacitor should have short leads and PCB trace
IN
lengths. The path formed by switch C, switch D, DD and
the C
PCB trace lengths.
capacitor also should have short leads and
OUT
n
n
The output capacitor (–) terminals should be connected
as close as possible to the (–) terminals of the input
capacitor.
PC Board Layout Checklist
The basic PC board layout requires a dedicated ground
plane layer. Also, for high current, a multilayer board pro-
vides heat sinking for power components.
Connect the top driver bootstrap capacitor CBST1
closely to the BST1 and SW1 pins. Connect the top
driver bootstrap capacitor C
and SW2 pins.
closely to the BST2
BST2
n
The ground plane layer should not have any traces and
it should be as close as possible to the layer with power
MOSFETs.
n
n
Connect the input capacitors C and output capacitors
IN
C
closely to the power MOSFETs. These capacitors
OUT
n
Place C , switch A, switch B and D in one compact
IN
area. Place C , switch C, switch BD and D in one
carry the MOSFET AC current.
OUT
compact area.
D
Route LSP and LSN traces together with minimum
PCB trace spacing. Avoid sense lines pass through
noisy areas, such as switch nodes. The filter capacitor
between LSP and LSN should be as close as possible
to the IC. Ensure accurate current sensing with Kelvin
connections at the RSENSE resistor. Low ESL sense
resistor is recommended.
n
Use immediate vias to connect the components to the
ground plane. Use several large vias for each power
component.
n
n
Use planes for V and V
to maintain good voltage
IN
OUT
filtering and to keep power losses low.
n
Connect the VC pin compensation network close to
Flood all unused areas on all layers with copper.
Flooding with copper will reduce the temperature rise
of power components. Connect the copper areas to any
the IC, between V and the signal ground. The capac-
C
itor helps to filter the effects of PCB noise and output
voltage ripple voltage from the compensation loop.
DC net (V or GND).
IN
n
Connect the INTV bypass capacitor, C
, close to
n
CC
INTVCC
Separate the signal and power grounds. All small-sig-
nal components should return to the exposed GND pad
from the bottom, which is then tied to the power GND
close to the sources of switch B and switch C.
the IC, between the INTVCC and the power ground. This
capacitor carries the MOSFET drivers’ current peaks.
n
Place switch A and switch C as close to the controller as
possible, keeping the PGND, BG and SW traces short.
Rev. 0
24
For more information www.analog.com
LT8392
TYPICAL APPLICATIONS
98% Efficient 48W (12V 4A) Buck-Boost Voltage Regulator
ꢀꢁ
ꢂꢃꢄ
4mΩ
10mΩ
ꢀ
ꢄꢅꢀ
ꢆꢇ
ꢀꢁ
ꢀꢁ
ꢁꢂꢃ
ꢀ
ꢀꢁ
ꢀꢁ ꢂꢃ ꢄꢅꢁ
ꢀꢀꢁꢂ
ꢃꢄꢅ
ꢆꢀ
ꢀ.ꢁꢂꢃ
ꢄ00ꢅ
ꢆꢇ
ꢀ0ꢁꢂ
ꢃꢄꢅ
ꢆꢃ
0.ꢀꢁꢂ
ꢀꢁ0ꢂꢃ
ꢀꢄꢅ
ꢀꢁ0ꢂꢃ
ꢀꢄꢅ
0.ꢀꢁꢂ
ꢀꢁꢂ ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂꢃꢄꢅ
ꢀ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢄꢄ
ꢀꢁꢀꢂ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ
ꢀ00ꢁ
ꢀꢁꢂꢃ
ꢀꢁꢂꢀ
ꢀꢀꢁꢂ ꢃꢁꢁ
ꢀ.0ꢀꢁ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁRꢂ
ꢀRꢁꢂ
ꢀꢁꢂꢃꢄꢀꢅRꢆ
ꢀꢁꢂꢃ
ꢀ
ꢀꢁꢂꢁꢃ ꢄꢅ
ꢀꢁꢂ
ꢀꢀꢁꢂ ꢃꢄ
ꢀꢀ
ꢀ.ꢁꢂꢃ
ꢀ00ꢁ
ꢀꢁꢂ ꢃꢄRꢅꢆ ꢇꢈꢈꢉꢊꢊꢁꢋ00 ꢋꢌꢆ
ꢀ
PGOOD
Rꢀ
PGOOD
ꢀꢁꢂ ꢀꢃꢄ ꢅꢆꢇꢅꢆꢈꢉꢆ ꢊꢋꢌꢁ00ꢆ0ꢍꢎꢋꢏ
ꢀꢁꢂ ꢀꢃꢄ ꢅꢆꢇꢅꢆꢈꢉꢆ ꢊꢋꢌ0ꢁꢁꢆꢈꢍꢎꢋꢏ
Rꢀꢁ
ꢀꢀ
ꢀ
ꢀ
0.ꢀꢁꢂꢃ
ꢀ00ꢁ
ꢂ00ꢁꢃꢄ
ꢀ00ꢁꢂ
0.ꢀꢁꢂ
ꢀꢁꢂ
ꢀ.ꢁꢂꢃ
ꢀꢁꢂꢃ ꢄꢅ0ꢃꢆ
Rev. 0
25
For more information www.analog.com
LT8392
PACKAGE DESCRIPTION
FE Package
28-Lead Plastic TSSOP (4.4mm)
ꢀReꢁeꢂeꢃꢄe ꢅꢆꢇ ꢈꢉꢊ ꢋ 0ꢌꢍ0ꢎꢍꢏꢐꢐꢑ Rev ꢅꢒ
Exposed Pad Variation EB
9.60 – 9.80*
(.378 – .386)
4.75
(.187)
4.75
(.187)
28 27 26 2524 23 22 21 20 1918 17 16 15
2.74
6.60 ±0.10
EXPOSED
PAD HEAT SINK
ON BOTTOM OF
PACKAGE
(.108)
4.50 ±0.10
SEE NOTE 4
6.40
(.252)
BSC
2.74
(.108)
0.45 ±0.05
1.05 ±0.10
0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT
5
7
1
2
3
4
6
8
9 10 12 13 14
11
1.20
(.047)
MAX
4.30 – 4.50*
(.169 – .177)
0.25
REF
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
0.05 – 0.15
(.002 – .006)
FE28 (EB) TSSOP REV L 0117
0.195 – 0.30
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
2. DIMENSIONS ARE IN
FOR EXPOSED PAD ATTACHMENT
MILLIMETERS
(INCHES)
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
3. DRAWING NOT TO SCALE
Rev. 0
26
For more information www.analog.com
LT8392
PACKAGE DESCRIPTION
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
ꢂReꢩeꢪeꢫꢬe ꢙꢍꢖ ꢆꢐꢑ ꢭ 0ꢉꢚ0ꢤꢚꢁꢣꢁꢃ Rev ꢖꢈ
0.ꢣ0 ±0.0ꢉ
ꢀ.ꢉ0 ±0.0ꢉ
ꢝ.ꢁ0 ±0.0ꢉ
ꢃ.ꢉ0 Rꢇꢊ
ꢃ.ꢢꢉ ±0.0ꢉ
ꢝ.ꢢꢉ ±0.0ꢉ
ꢒꢏꢖꢗꢏꢑꢇ ꢌꢘꢍꢙꢅꢋꢇ
0.ꢃꢉ ±0.0ꢉ
0.ꢉ0 ꢓꢄꢖ
ꢝ.ꢉ0 Rꢇꢊ
ꢀ.ꢁ0 ±0.0ꢉ
ꢉ.ꢉ0 ±0.0ꢉ
Rꢇꢖꢌꢔꢔꢇꢋꢆꢇꢆ ꢄꢌꢙꢆꢇR ꢒꢏꢆ ꢒꢅꢍꢖꢜ ꢏꢋꢆ ꢆꢅꢔꢇꢋꢄꢅꢌꢋꢄ
ꢏꢒꢒꢙꢡ ꢄꢌꢙꢆꢇR ꢔꢏꢄꢗ ꢍꢌ ꢏRꢇꢏꢄ ꢍꢜꢏꢍ ꢏRꢇ ꢋꢌꢍ ꢄꢌꢙꢆꢇRꢇꢆ
ꢒꢅꢋ ꢁ ꢋꢌꢍꢖꢜ
R ꢦ 0.ꢃ0 ꢌR 0.ꢝꢉ
× ꢀꢉ° ꢖꢜꢏꢔꢊꢇR
ꢃ.ꢉ0 Rꢇꢊ
R ꢦ 0.ꢁꢁꢉ
ꢍꢡꢒ
R ꢦ 0.0ꢉ
ꢍꢡꢒ
0.ꢣꢉ ±0.0ꢉ
ꢀ.00 ±0.ꢁ0
ꢂꢃ ꢄꢅꢆꢇꢄꢈ
ꢃꢣ
ꢃꢤ
0.ꢀ0 ±0.ꢁ0
ꢒꢅꢋ ꢁ
ꢍꢌꢒ ꢔꢏRꢗ
ꢂꢋꢌꢍꢇ ꢢꢈ
ꢁ
ꢃ
ꢉ.00 ±0.ꢁ0
ꢂꢃ ꢄꢅꢆꢇꢄꢈ
ꢝ.ꢉ0 Rꢇꢊ
ꢝ.ꢢꢉ ±0.ꢁ0
ꢃ.ꢢꢉ ±0.ꢁ0
ꢂꢘꢊꢆꢃꢤꢈ ꢨꢊꢋ 0ꢤꢁꢢ Rꢇꢛ ꢖ
0.ꢃꢉ ±0.0ꢉ
0.ꢃ00 Rꢇꢊ
0.ꢉ0 ꢓꢄꢖ
0.00 ꢧ 0.0ꢉ
ꢓꢌꢍꢍꢌꢔ ꢛꢅꢇꢐꢥꢇꢞꢒꢌꢄꢇꢆ ꢒꢏꢆ
ꢋꢌꢍꢇꢎ
ꢁ. ꢆRꢏꢐꢅꢋꢑ ꢒRꢌꢒꢌꢄꢇꢆ ꢍꢌ ꢓꢇ ꢔꢏꢆꢇ ꢏ ꢕꢇꢆꢇꢖ ꢒꢏꢖꢗꢏꢑꢇ ꢌꢘꢍꢙꢅꢋꢇ ꢔꢌꢚꢃꢃ0 ꢛꢏRꢅꢏꢍꢅꢌꢋ ꢂꢐꢑꢜꢆꢚꢝꢈ.
ꢃ. ꢆRꢏꢐꢅꢋꢑ ꢋꢌꢍ ꢍꢌ ꢄꢖꢏꢙꢇ
ꢝ. ꢏꢙꢙ ꢆꢅꢔꢇꢋꢄꢅꢌꢋꢄ ꢏRꢇ ꢅꢋ ꢔꢅꢙꢙꢅꢔꢇꢍꢇRꢄ
ꢀ. ꢆꢅꢔꢇꢋꢄꢅꢌꢋꢄ ꢌꢊ ꢇꢞꢒꢌꢄꢇꢆ ꢒꢏꢆ ꢌꢋ ꢓꢌꢍꢍꢌꢔ ꢌꢊ ꢒꢏꢖꢗꢏꢑꢇ ꢆꢌ ꢋꢌꢍ ꢅꢋꢖꢙꢘꢆꢇ
ꢔꢌꢙꢆ ꢊꢙꢏꢄꢜ. ꢔꢌꢙꢆ ꢊꢙꢏꢄꢜꢟ ꢅꢊ ꢒRꢇꢄꢇꢋ ꢟ ꢄꢜꢏꢙꢙ ꢋꢌꢍ ꢇꢞꢖꢇꢇꢆ 0.ꢁꢉꢠꢠ ꢌꢋ ꢏꢋꢡ ꢄꢅꢆꢇ
ꢉ. ꢇꢞꢒꢌꢄꢇꢆ ꢒꢏꢆ ꢄꢜꢏꢙꢙ ꢓꢇ ꢄꢌꢙꢆꢇR ꢒꢙꢏꢍꢇꢆ
ꢢ. ꢄꢜꢏꢆꢇꢆ ꢏRꢇꢏ ꢅꢄ ꢌꢋꢙꢡ ꢏ RꢇꢊꢇRꢇꢋꢖꢇ ꢊꢌR ꢒꢅꢋ ꢁ ꢙꢌꢖꢏꢍꢅꢌꢋ
ꢌꢋ ꢍꢜꢇ ꢍꢌꢒ ꢏꢋꢆ ꢓꢌꢍꢍꢌꢔ ꢌꢊ ꢒꢏꢖꢗꢏꢑꢇ
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
27
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
LT8392
TYPICAL APPLICATION
125W (25V 5A) Solar Panel to 12V Battery Charger
ꢀꢁ
ꢂ.ꢃꢄꢅ
ꢉRꢁꢊ ꢋꢁꢌꢆR ꢍꢆꢎꢇꢌ
ꢀꢁ ꢂꢃꢄ ꢅꢆꢀꢀꢇRꢈ
8mΩ
2.5mΩ
ꢀꢁ
ꢀꢁ
ꢀ
ꢁꢂ
ꢀ
ꢁꢂꢃ
0ꢀ ꢃꢄ ꢅꢆꢀ
ꢀꢁꢂꢃ
ꢄ0ꢅ
ꢆꢇ
ꢀꢁꢂꢃ
ꢄ0ꢅ
ꢆꢇ
ꢀ.ꢁꢂꢃ
ꢄ00ꢅ
ꢆꢇ
ꢀ0ꢁꢂ
ꢃ0ꢄ
ꢅꢆ
ꢀꢁꢂꢃ
ꢄ0ꢅ
ꢆꢇ
0.ꢀꢁꢂ
0.ꢀꢁꢂ
ꢀꢁꢂ ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂ
10Ω
ꢀꢁꢂꢃꢄꢅ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ.ꢀꢁꢂ
ꢀꢁꢂꢃ
10Ω
ꢄꢄ
ꢀꢁ0ꢂ
ꢀꢁꢂ
ꢀꢁ
ꢀ
ꢀꢁ
ꢀꢁꢂꢃꢄꢀꢅRꢆ
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁ.ꢁꢂ
ꢀꢁꢂꢃ
ꢀꢀ
ꢀꢁ ꢁ ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀ.ꢁꢂꢃ
ꢀꢁ
ꢀꢁꢂꢃꢄ ꢅꢃRRꢆꢁꢄ ꢅꢇꢁꢄRꢇꢈ
ꢀꢁRꢂ
ꢀꢁꢂꢀ
ꢀꢁꢀꢂ
0.ꢀꢁꢂ ꢃꢄ ꢅꢂ ꢆꢄR 0ꢇ ꢃꢄ ꢁꢇ
ꢀ0ꢁꢂ
PGOOD
ꢀRꢁꢂ
ꢀ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
Rꢀꢁ
ꢀ0ꢁꢂ
0.ꢀꢁꢂꢃ
ꢀ00ꢁ
ꢀꢁꢂ ꢃꢄRꢅꢆ ꢇꢈꢈꢉꢊꢈ0ꢈꢇ0 ꢈ.ꢇꢋꢆ
ꢀꢁꢂ ꢃꢄꢅꢃꢄꢆꢇꢄ ꢈꢉꢊ0ꢋꢌꢄ0ꢋꢍꢉꢎ
ꢀꢁꢂ ꢃꢄꢅꢃꢄꢆꢇꢄ ꢈꢉꢊ0ꢁꢋꢄ0ꢌꢍꢉꢎ
ꢀꢁꢂ ꢀꢃꢄ ꢅꢆꢇꢅꢆꢈꢉꢆ ꢊꢋꢌ0ꢍ0ꢆ0ꢃꢎꢋ
ꢀꢀ
ꢀ
Rꢀ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁ0ꢂꢃꢄ
0.ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ ꢄꢅ0ꢁ
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
V : 4V to 60V, V : 0V to 60V, 1.5% Voltage Accuracy, 3% Current
LT8390/LT8390A 60V Synchronous 4-Switch Buck-Boost Controller
with Spread Spectrum
IN
OUT
Accuracy, TSSOP-28 and 4mm × 5mm QFN-28
LT3790
LT8705
60V Synchronous 4-Switch Buck-Boost Controller
V : 4.7V to 60V, V : 1.2V to 60V, Regulates V , I , I , TSSOP-38
IN
OUT
OUT OUT IN
80V V and V
Synchronous 4-Switch Buck-Boost V : 2.8V to 80V, V : 1.3V to 80V, Regulates V , I , V , I ,
IN OUT OUT OUT IN IN
IN
OUT
DC/DC Controller
5mm × 7mm QFN-38 and Modified TSSOP-38 for High Voltage
LTC®3789
LTC3780
High Efficiency Synchronous 4-Switch Buck-Boost
Controller
V : 4V to 38V, V : 0.8V to 38V, Regulates V , I or I , 5mm × 5mm
IN
OUT
OUT OUT
IN
QFN-32 and SSOP-24
High Efficiency Synchronous 4-Switch Buck-Boost
Controller
V : 4V to 36V, V : 0.8V to 30V, Regulates V , 4mm × 5mm QFN-28 and
IN
OUT
OUT
SSOP-28
LT3757/LT3757A Boost, Flyback, SEPIC and Inverting Controller
V : 2.9V to 40V, Positive or Negative V , 3mm × 3mm DFN-10, MSOP-10
IN OUT
LT3758
High Input Voltage, Boost, Flyback, SEPIC and
Inverting Controller
V : 5.5V to 100V, Positive or Negative V , 3mm × 3mm DFN-10, MSOP-10
IN OUT
LT8710
Synchronous SEPIC/Inverting/Boost Controller with V : 4.5V to 80V, Rail-to-Rail Output Current Monitor and Control, TSSOP-28
IN
Output Current Control
Rev. 0
06/20
www.analog.com
28
ANALOG DEVICES, INC. 2020
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