LT1103CT7#PBF_技术文档

LT1103/LT1105

Offline Switching Regulator

THE LT1103 IS OBSOLETE:

THE LT1105 IS AVAILABLE, BUT NOT

RECOMMENDED FOR NEW DESIGNS

FOR INFORMATION PURPOSES ONLY

Contact Analog Devices for Potential Replacement

FEATURES

DESCRIPTION

®

The LT 1105 Offline Switching Regulator is designed

n

1% Line and Load Regulation with ꢀo Optocoupler

n

Switch Frequency Up to 200kHz

for high input voltage applications using an external FET

switch. The LT1105 is available and its totem pole out-

put drives the gate of an external FET. Unique design of

the LT1105 eliminates the need for an optocoupler while

still providing 1% load and line regulation in a magnetic

flux-sensed converter. This significantly simplifies the

design of offline power supplies and reduces the number

of components which must cross the isolation barrier to

one, the transformer.

n

Internal 2A Switch and Current Sense (LT1103)

n

Internal 1A Totem-Pole Driver (LT1105)

n

Start-Up Mode Draws Only 200µA

n

Fully Protected Against Overloads

n

Overvoltage Lockout of Main Supply

n

Protected Against Underdrive or Overdrive to FET

n

Operates in Continuous or Discontinuous Mode

n

Ideal for Flyback and Forward Topologies

n

Isolated Flyback Mode Has Fully Floating Outputs

The LT1105 current mode switching techniques are well

suited to transformer isolated flyback and forward topolo-

gies while providing ease of frequency compensation with

a minimum of external components.

APPLICATIONS

n

Up to 250W Isolated Mains Converter

All registered trademarks and trademarks are the property of their respective owners.

n

Up to 50W Isolated Telecom Converter

n

Fully Isolated Multiple Outputs

n

Distributed Power Conversion ꢀetworks

TYPICAL APPLICATION

Fully Isolated Flyback 100kHz 50W Converter with Load Regulation Compensation

OPTIONAL OUTPUT FILTER

MBR2045

85V TO 270V

AC

10µH

AC

5V

10A

1.5KE300A

5W

+

50V

470µF

220k

1W

+

*50V

3600µF

+

MUR150

220µF

385V

499Ω

*OUTPUT CAPACITOR IS THREE 1200µF,

50V CAPACITORS IN PARALLEL TO

ACHIEVE REQUIRED RIPPLE CURRENT

RATING AND LOW ESR.

–

1N4148

1000pF

100Ω

BRIDGE

RECTIFIER

+

Load Regulation

BAV21

WINDINGS FOR

OPTIONAL

5.25

5.20

5.15

5.10

5.05

5.00

4.95

4.90

4.85

4.80

4.75

LINE

BUK426-800A

BAV21

1N4148

V

12V OUTPUTS

DC

FILTER

SW

IN

+

39µF

35V

LT1103

13k

1%

10Ω

TRANSFORMER DATA:

COILTRONICS CTX110228-3

= 1.6mH

18.7k

220V

AC

15V

OSC

FB

GND

L

(PRI)

+

V

C

1µF

N

:N

PRI SEC

= 1:0.05

4.75k

1%

25V

N

:N

BIAS SEC

= 1:0.27

85V

AC

110V

AC

0.047µF

390pF

270V

AC

330Ω

0.1µF

0.047µF

LT1103 TA13

0

1

2

3

4

5

6

7

8

9

10

I

(A)

OUT

LT1103 TA02

Danger!! Lethal Voltages Present – See Text

Rev. E

1

Document Feedback

For more information www.analog.com

LT1103/LT1105

DESCRIPTION

WARNING

200kHz maximum switching frequency to achieve high

power density. Performance at switching frequencies

above 100kHz may be degraded due to internal timing

constraints associated with fully isolated flyback mode.

DANGEROUS AND LETHAL POTENTIALS ARE

PRESENT IN OFFLINE CIRCUITS!

BEFORE PROCEEDING ANY FURTHER, THE

READER IS WARNED THAT CAUTION MUST

BE USED IN THE CONSTRUCTION, TESTING

AND USE OF OFFLINE CIRCUITS. HIGH

VOLTAGE, AC LINE-CONNECTED POTENTIALS

ARE PRESENT IN THESE CIRCUITS. EXTREME

CAUTION MUST BE USED IN WORKING WITH

AND MAKING CONNECTIONS TO THESE

CIRCUITS. REPEAT: OFFLINE CIRCUITS

CONTAIN DANGEROUS, AC LINE-CONNECTED

HIGH VOLTAGE POTENTIALS. USE CAUTION.

Included are the oscillator, control, and protection cir-

cuitry such as current limit and overvoltage lockout.

Switch frequency and maximum duty cycle are adjustable.

Bootstrap circuitry draws 200µA for start-up of isolated

topologies. A 5V reference as well as a 15V gate bias

are available to power external primary-side circuitry. ꢀo

external current sense resistor is necessary with LT1103

because it is integrated with the high current switch. The

LT1105 brings out the input to the current limit amplifier

and requires the use of an external sense resistor.

ALL TESTING PERFORMED ON AN OFFLINE

CIRCUIT MUST BE DONE WITH AN ISOLATION

TRANSFORMER CONNECTED BETWEEN THE

OFFLINE CIRCUIT’S INPUT AND THE AC LINE.

USERS AND CONSTRUCTORS OF OFFLINE

CIRCUITS MUST OBSERVE THIS PRECAUTION

WHEN CONNECTING TEST EQUIPMENT TO

THE CIRCUIT TO AVOID ELECTRIC SHOCK.

REPEAT: AN ISOLATION TRANSFORMER MUST

BE CONNECTED BETWEEN THE CIRCUIT INPUT

AND THE AC LINE IF ANY TEST EQUIPMENT IS

TO BE CONNECTED.

The LT1103/LT1105 have unique features not found on

other offline switching regulators. Adaptive antisat switch

drive allows wide ranging load currents while maintain-

ing high efficiency. The external FET is protected from

insufficient or excessive gate drive voltage with a drive

detection circuit. An externally activated shutdown mode

reduces total supply current to less than 200µA, typical

for standby operation. Fully isolated and regulated outputs

can be generated in the optional isolated flyback mode

without the need for optocouplers or other isolated feed-

back paths.

ABSOLUTE MAXIMUM RATINGS (Note 1)

V ............................................................................30V

Iꢀ

Maximum Operating Ambient Temperature Range

LT1103C (OBSOLETE).............................. 0°C to 70°C

LT1105C................................................... 0°C to 70°C

Maximum Operating Temperature Range

V

Output Voltage (LT1103)....................................50V

SW

V

Output Current (200ns)(LT1105) .................... 1.5A

SW

V , FB, OSC, SS ..........................................................6V

C

I

(LT1105)...............................................................3V

LT1103C (OBSOLETE)............................ 0°C to 100°C

LT1105C................................................. 0°C to 100°C

LT1105I.............................................. –40°C to 125°C

Storage Temperature Range .................. –65°C to 150°C

LIM

OVLO Input Current..................................................1mA

Lead Temperature (Soldering, 10 sec.)..................300°C

Rev. E

2

For more information www.analog.com

LT1103/LT1105

PIN CONFIGURATION

LT1105

LT1103

TOP VIEW

FRONT VIEW

1

2

3

4

5

6

7

V

SW

14

13

12

11

10

9

PWRGND

OVLO

FB

TOP VIEW

7

6

5

4

3

2

1

15V

NC

V

IN

OSC

GND

1

2

3

4

8

7

6

5

V

SW

NC

I

15V

LIM

V

C

15V

V

C

FB

V

FB

IN

V

5V

SS

IN

V

SW

OSC

V

C

OSC

T7 PACKAGE

7-LEAD TO-220

I

8

GND

LIM

N8 PACKAGE

8-LEAD PDIP

CASE IS CONNECTED TO GROUND. LEADS ARE FORMED

= 100°C, ꢀ = 50°C/W

T

JMAX

JA

N PACKAGE

14-LEAD PDIP

T

= 100°C, ꢀ = 130°C/W

JA

JMAX

PINS 1 AND 7 MUST BE TIED TOGETHER

= 100°C, ꢀ = 100°C/W

OBSOLETE PACKAGE

T

JMAX

JA

ORDER INFORMATION

LEAD FREE FINISH

LT1105Cꢀ#PBF

LT1105Iꢀ#PBF

TAPE AND REEL

PART MARKING

LT1105Cꢀ

PACKAGE DESCRIPTION

14-Lead PDIP

TEMPERATURE RANGE

LT1105Cꢀ#TRPBF

LT1105Iꢀ#TRPBF

LT1105Cꢀ8#TRPBF

LT1105Iꢀ8#TRPBF

0°C to 100°C

–40°C to 125°C

0°C to 100°C

–40°C to 125°C

LT1105Iꢀ

14-Lead PDIP

LT1105Cꢀ8#PBF

LT1105Iꢀ8#PBF

LT1105Cꢀ8

LT1105Iꢀ8

8-Lead PDIP

OBSOLETE PACKAGE

LT1103CT7#PBF

LT1103CT7#TRPBF

LT1103CT7

7-Lead TO-220

0°C to 100°C

Contact the factory for parts specified with wider operating temperature ranges.

Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.

ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T = 25°C. V = 20V, V = 0.85V, OVLO = 0V, V Open, unless otherwise noted.

A IN C SW

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

20

MAX

UNITS

l

I

Supply Current

Start-Up Current

8V < V < 30V, After Device Has Started

Iꢀ

10

30

mA

Q

l

I

V

Iꢀ

< V Start Threshold

Iꢀ

200

400

450

µA

START

Industrial Grade

l

V

Start Threshold

14.5

5.0

16.0

7.0

17.5

8.0

V

Iꢀ

V

Iꢀ

Shutdown Threshold

ꢀote: Switching Stops When V < 10V (LT1103)

SW

ꢀote: Switching Stops When V

< 10V (LT1105)

GATE

l

V

REF

5V Reference Voltage

4.80

4.95

0.025

60

5.20

0.1

V

%V

V

REF

V

REF

V

REF

Line Regulation

10V < V < 30V

Iꢀ

Load Regulation

Short-Circuit Current

0mA < I < 20mA

L

0.05

%mA

l

Commercial Grade

Industrial Grade

25

20

110

120

mA

l

15V Short-Circuit Current

Commercial Grade

Industrial Grade

30

25

130

140

mA

Rev. E

3

For more information www.analog.com

LT1103/LT1105

ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T = 25°C. V = 20V, V = 0.85V, OVLO = 0V, V Open, unless otherwise noted.

A IN C SW

SYMBOL PARAMETER

V 15V Gate Bias Reference

GATE

CONDITIONS

MIN

TYP

15.0

2.0

MAX

16.2

2.5

UNITS

l

17 < V < 30V, 0mA < I < 30mA

Iꢀ L

13.8

V

15V Dropout Voltage

V

Iꢀ

= 15V, I = 30mA

L

15V Short-Circuit Current

Oscillator Scaling Factor

30

70

130

mA

SF

FB = 4V, V = Open, Measured at V , I = 25mA,

C SW SW

36

32

40

44

48

Hz • µF

l

OVLO = 5V, f

= SF/C , 40kHz < f

OSC

< 200kHz

OSC

Oscillator Valley Voltage

Oscillator Peak Voltage

2.0

4.5

65

V

l

DC

Preset Max Switch Duty Cycle

(LT1103)

FB = 4V, V = Open, f

C

= 40kHz, I = 25mA,

SW

58

72

%

OSC

ꢀote: Maximum Duty Cycle Can Be Altered at OSC Pin

l

Preset Max Switch Duty Cycle

(LT1105)

FB = 4V, V = Open, f = 40kHz, I = 25mA,

C OSC SW

56

63

70

%

ꢀote: Maximum Duty Cycle Can Be Altered at OSC Pin

Industrial Grade

l

55

75

%

l

OVLO Threshold

Overvoltage Lockout Threshold at Which Switching is Inhibited

Industrial Grade

2.3

2.2

2.5

2.7

2.8

V

l

OVLO Input Bias Current

FB Threshold Voltage

OVLO = 2V, Measured Out of Pin (ꢀote 2)

1.0

3.0

µA

V

FB

I(V ) = 0mA

C

4.425

4.400

4.50

4.575

4.600

V

l

FB Input Bias Current

FB = V (ꢀote 3)

FB

5

4

10

20

22

µA

Industrial Grade

Change in FB Input

FB = V , V = 1V to 4V (ꢀote 3)

FB C

8

7

6

11

13

14

15

µA/V

l

Bias Current with Change in V

C

Industrial Grade

l

FB Threshold Line Regulation

Error Amp Transconductance

10V < V < 30V

Iꢀ

0.025

0.10

%/V

g

m

∆I(V ) = 50µA

C

9000 12000 17500

6000 12000 20000

µmho

l

5000

24000

l

A

V

Error Amp Voltage Gain

1V < V < 3V

C

500

450

1250

V/V

Industrial Grade

l

V Switching Threshold

C

Switch Duty Cycle = 0%

0.85

1.25

150

1.4

mA

l

Shutdown Threshold Voltage

50

250

300

mV

Industrial Grade

l

Error Amp Source Current

Error Amp Sink Current

150

275

3

µA

l

1.5

0.7

4.5

mA

Industrial Grade

l

Error Amp Clamp Voltage

Soft-Start Charging Current

Soft-Start Reset Current

FB = 4.75V

FB = 4.0V

0.3

4.2

0.7

4.4

0.9

4.6

V

l

SS = 0V

25

20

40

60

75

µA

Industrial Grade

l

V

Iꢀ

= 6V, SS = 0.3V

1

2

mA

l

Output Switch Leakage

(LT1103)

V

= 45V

500

200

µA

SW

= 15V

SW

l

BV

Switch Breakdown Voltage

(LT1103)

I

= 5mA

50

70

V

SW

l

V

Current Limit (LT1103)

Duty Cycle = 25% (ꢀote 4)

2.0

2.5

0.4

3.0

A

SW

Output Switch On Resistance

(LT1103)

0.75

Ω

Rev. E

4

For more information www.analog.com

LT1103/LT1105

ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T = 25°C. V = 20V, V = 0.85V, OVLO = 0V, V Open, unless otherwise noted.

A IN C SW

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

∆I

Iꢀ

I Increase During Switch On Time

Q

I

SW

= 0.5A to 1.5A

30

50

mA/A

∆I

SW

(LT1103)

l

Switch Output High Level

(LT1105)

I

SW

I

SW

I

SW

I

SW

= 200mA, V

= 750mA, V

= 200mA, V

= 750mA, V

= 15V

13.00

12.50

12.75

12.25

13.5

13.2

V

GATE

Switch Output High Level

Industrial Grade

l

Switch Output Low Level

(LT1105)

I

= 200mA

= 750mA

0.25

0.75

0.50

1.50

V

SW

Rise Time (LT1105)

Fall Time (LT1105)

C = 1000pF

L

50

20

ns

C = 1000pF

L

l

I

Threshold Voltage (LT1105)

Duty Cycle = 25% (ꢀote 5)

300

9.0

375

9.5

450

mV

V

LIM

Low Switch Drive Lockout

Threshold

Measured at V (LT1103)

SW

10.5

Measured at 15V Gate Bias Reference (LT1105)

l

High Switch Drive Lockout

Threshold

Measured at V (LT1103)

SW

17.0

18.5

20.0

V

Measured at 15V Gate Bias Reference (LT1105)

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 4: Current limit on V is constant for DC < 35% and decreases for

SW

DC > 35% due to internal slope compensation circuity. The LT1103 switch

current limit is given by I = 1.76 (1.536 – DC) above 35% duty cycle.

LIM

Note 5: The current limit threshold voltage is constant for DC < 35% and

Note 2: The OVLO pin is clamped with a 5.5V Zener and can sink a

decreases for DC > 35% due to internal slope compensation circuitry. The

maximum input current of 1mA.

LT1105 switch current limit threshold voltage is given by V = 0.225

LIM

(1.7 – DC) above 35% duty cycle.

Note 3: FB input bias current changes as a function of the V pin voltage.

C

Rate of change of FB input bias current is 11µA/V of change on V . By

C

including a resistor in series with the FB pin, load regulation can be set to

zero.

TYPICAL PERFORMANCE CHARACTERISTICS

Start-Up Supply Current vs

Quiescent Supply Current vs

Input Voltage

Supply Current vs Input Voltage

Input Voltage

25

20

15

10

500

450

400

350

300

250

200

150

100

50

22

21

20

19

18

17

16

15

14

13

12

25°C

125°C

25°C

125°C

–55°C

5

I

SHUT

I

START

0

10

15

20

25

30

0

3

6

9

12

15

5

35

0

20

INPUT VOLTAGE (V)

30

5

10 15

25

40

INPUT VOLTAGE (V)

LT1103 G01

LT1103 G02

LT1103 G03

Rev. E

5

For more information www.analog.com

LT1103/LT1105

TYPICAL PERFORMANCE CHARACTERISTICS

Quiescent Supply Current vs

Temperature

Shutdown Supply Current vs Input

Voltage

Shutdown Supply Current vs

V Voltage

C

22

21

20

19

18

17

16

15

14

13

12

500

450

400

350

300

250

200

150

100

50

500

450

400

350

300

250

200

150

100

50

30V

125°C

V

= 75mV

25°C

8V

C

V

= 0

C

–55°C

0

100

120

140

180

160

200

–25

0

25 50 75 100 125 150 175

0

20 40 60 80

–75 –50

20

INPUT VOLTAGE (V)

35

0

10

15

25

30

5

TEMPERATURE (°C)

V

(mV)

C

LT1103 G04

LT1103 G06

LT1103 G05

V

Start-Up Threshold vs

V

Shutdown Threshold vs

Output Switch Frequency vs

Temperature

IN

Temperature

17.5

8.0

7.7

7.4

45

C

= 1000pF

OSC

17.0

43

16.5

41

16.0

7.1

6.8

6.5

39

37

35

15.5

15.0

14.5

–25

0

25 50 75 100 125 150 175

–75 –50 –25

0

25

75

125 150 175

100

–75 –50

50

–75 –50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

LT1103 G07

LT1103 G08

LT1103 G09

Preset Switch Maximum Duty

Cycle vs Temperature

Switch Oscillator Frequency vs

Capacitance

Overvoltage Lockout Threshold vs

Temperature

75

72

69

1000

100

10

3.0

2.8

2.6

C

= 1000pF

OSC

66

63

60

2.4

2.2

2.0

–75

–25

25 50 75 100 125

175

–75

–25

25 50 75 100 125

175

150

–50

0

150

–50

0

100

1000

CAPACITANCE (pF)

10000

TEMPERATURE (°C)

LT1103 G10

LT1103 G12

LT1103 G11

Rev. E

6

For more information www.analog.com

LT1103/LT1105

TYPICAL PERFORMANCE CHARACTERISTICS

OVLO Input Bias Current vs

Temperature

Soft-Start Charging Current vs

Temperature

Soft-Start Reset Current vs

Temperature

0

60

5

4

3

OVLO = 2V

–0.5

50

–1.0

40

–1.5

30

2

1

0

–2.0

–2.5

–3.0

20

10

0

–25

0

25 50 75 100 125 150 175

–25

0

25 50 75 100 125 150 175

–75

–25

25 50 75 100 125

175

150

–75 –50

–50

0

TEMPERATURE (°C)

LT1103 G13

LT1103 G14

LT1103 G15

5V Reference Voltage vs

Temperature

5V Load Regulation vs

Temperature

5V Line Regulation vs

Temperature

5.20

5.15

5.10

5.05

5.00

4.95

4.90

4.85

4.80

0.025

0.020

0.015

0.05

0.04

0.03

0.010

0.005

0

0.02

0.01

0

100

–75

–25

25 50 75 100 125

175

–75

–25

25 50 75 100 125

175

150

–50

0

150

–50

0

–25 0 25 50 75

125 150 175

–75 –50

TEMPERATURE (°C)

LT1103 G17

LT1103 G18

LT1103 G16

5V Reference Short-Circuit

Current vs Temperature

15V Gate Bias Reference vs

Temperature

15V Gate Bias Dropout Voltage vs

Temperature

110

100

90

16.2

2.5

2.0

1.5

15.8

15.4

80

15.0

70

1.0

0.5

0

60

14.6

14.2

13.8

50

40

30

100

–25

0

25 50 75 100 125 150 175

–75

–25

25 50 75 100 125

175

150

–75 –50

–50

0

–25 0 25 50 75

125 150 175

–75 –50

TEMPERATURE (°C)

TEMPERATURE (C)

LT1103 G20

LT1103 G21

LT1103 G19

Rev. E

7

For more information www.analog.com

LT1103/LT1105

TYPICAL PERFORMANCE CHARACTERISTICS

15V Gate Bias Short-Circuit

Current vs Temperature

Low Switch Drive Lockout

Threshold vs Temperature

High Switch Drive Lockout

Threshold vs Temperature

130

110

90

10.5

10.2

9.9

20.0

19.5

19.0

18.5

70

50

30

9.6

9.3

9.0

18.0

17.5

17.0

–75

–25

25 50 75 100 125

175

–75

–25

25 50 75 100 125

175

–25

–75 –50

0

25 50 75 100 125 150 175

–50

0

150

–50

0

150

TEMPERATURE (°C)

LT1103 G22

LT1103 G23

LT1103 G24

Change in FB Input Bias Current

Feedback Threshold vs

Temperature

FB Input Bias Current vs

Temperature (V = 1V)

C

with Change in V vs Temperature

C

(V = 1V to 4V)

C

4.60

4.56

4.52

20

16

12

14

13

12

11

10

9

4.48

4.44

4.40

8

4

0

8

7

–75

–25

25 50 75 100 125

175

–75

–25

25 50 75 100 125

175

150

–50

0

150

–50

0

–75

0

100

175

125 150

–50 –25

25 50 75

TEMPERATURE (°C)

LT1103 G25

LT1103 G26

LT1103 G27

Error Amplifier Transconductance

vs Temperature

Error Amplifier Transconductance

and Phase vs Frequency

Error Amplifier Voltage Gain vs

Temperature

0.020

0.018

200

180

2500

2000

1500

1000

500

25000

20000

15000

10000

5000

PHASE

0.016

160

g

m

0.014

0.012

0.010

0.008

0.006

0.004

0.002

0

140

120

100

80

60

40

g

m

20

PHASE

0

0.1

1

10

FREQUENCY (kHz)

100

1000

100

75

125

100

50

150

175

–25

–75 –50

0

25

–25

25 50 75

125 150 175

–75 –50

0

TEMPERATURE (°C)

LT1103 G29

LT1103 G30

LT1103 G28

Rev. E

8

For more information www.analog.com

LT1103/LT1105

TYPICAL PERFORMANCE CHARACTERISTICS

Error Amplifier Source Current vs

Temperature

Error Amplifier Sink Current vs

Temperature

Error Amplifier High Clamp

Voltage vs Temperature (FB = 4V)

350

325

300

275

250

225

200

175

150

4.5

4.4

4.3

4.0

3.5

3.0

4.2

4.1

4.0

2.5

2.0

1.5

100

–25

0

25 50 75 100 125 150 175

–75

–25

25 50 75 100 125

175

150

–75 –50

–50

0

–25

25 50 75

125 150 175

–75 –50

0

TEMPERATURE (°C)

LT1103 G32

LT1103 G33

LT1103 G31

Error Amplifier Low Clamp

Voltage vs Temperature

(FB = 4.75V)

V Switching Threshold Voltage

C

LT1103 Output Switch Leakage

Current vs Temperature

vs Temperature

0.9

1.5

1.3

1.1

200

160

120

0.8

V

= 45V

SW

0.7

0.6

0.9

0.7

0.5

80

40

0

V

= 15V

SW

0.5

0.4

0.3

–25

0

25 50 75 100 125 150 175

–75

–25

25 50 75 100 125

175

–75

–25

25 50 75 100 125

175

150

–75 –50

–50

0

150

–50

0

TEMPERATURE (°C)

LT1103 G34

LT1103 G35

LT1103 G36

LT1103 Switch Saturation Voltage

vs Temperature

LT1103 V Current Limit vs

SW

LT1103 V Current Limit vs

SW

Duty Cycle

Temperature

1.2

3.0

2.5

2.0

1.5

1.0

0.5

0

3.0

2.9

2.8

2.7

2.6

2.5

2.4

2.3

2.2

2.1

2.0

–55°C

25°C

DC = 25%

1.0

125°C

0.8

I

= 1.5A

SW

0.6

0.4

0.2

0

I

= 0.5A

SW

60

0

20 30 40 50

DUTY CYCLE (%)

70 80

10

–25

0

25 50 75 100 125 150 175

–75 –50 –25

0

25

50

75

100

150

125

175

–75 –50

TEMPERATURE (°C)

LT1103 G39

LT1103 G38

LT1103 G40

Rev. E

9

For more information www.analog.com

LT1103/LT1105

TYPICAL PERFORMANCE CHARACTERISTICS

LT1103 Driver Current vs

Temperature

LT1105 V Low Saturation

SW

LT1105 V High Saturation

SW

Voltage vs Temperature

50

40

30

3.0

2.5

I

= 750mA

SW

2.0

1.5

I

= 200mA

SW

20

10

0

I

= 750mA

SW

1.0

0.5

0

1.0

0.5

0

I

= 200mA

SW

–75

–25

25 50 75 100 125

175

–25

0

25 50 75 100 125 150 175

–25

–75 –50

0

25 50 75 100 125 150 175

–50

0

150

–75 –50

TEMPERATURE (°C)

LT1103 G41

LT1103 G42

LT1103 G43

LT1105 Current Limit Threshold

Voltage vs Temperature

LT1105 V Rise Time vs

SW

LT1105 V Fall Time vs

SW

Temperature

450

100

DC = 25°C

425

80

400

C

= 4700pF

LOAD

60

375

C

= 4700pF

LOAD

40

20

0

40

20

0

C

= 1000pF

LOAD

350

325

300

C

= 1000pF

LOAD

–25

0

25 50 75 100 125 150 175

–75 –50

–75

–25

25 50 75 100 125

175

–75

–25

25 50 75 100 125

175

150

–50

0

150

–50

0

TEMPERATURE (°C)

LT1103 G46

LT1103 G44

LT1103 G45

Rev. E

10

For more information www.analog.com

LT1103/LT1105

PIN FUNCTIONS

LT1103

V

: The Switch Output pin is the collector of the internal

SW

ꢀPꢀ power switch. This pin has a typical Oꢀ resistance of

0.4Ω and a minimum breakdown voltage of 50V. This pin

also ties to the FET gate drive detection circuit.

FB: The Feedback pin is the inverting input to the sampling

error amplifier. The noninverting input is tied to a 4.5V

reference. The FB pin is used for output voltage sensing.

The input bias current is a function of the control pin V

C

LT1105

voltage and can be used for load regulation compensa-

tion by including a resistor in series with the FB pin. The

All functions on the LT1105 are equivalent to the LT1103

with the exception of the V pin and the I pin and the

sampling error amplifier has a typical g of 0.012 mhos

m

SW

LIM

and the output of the sampling error amplifier has asym-

metrical slew rate to reduce overshoot during start-up

conditions or following the release of an output overload.

availability of the OVLO, 5V, and SS functions.

OVLO: The Overvoltage Lockout pin inhibits switching

when the pin is pulled above its threshold voltage of 2.5V.

OVLO is implemented with a resistor divider network from

the rectified DC line and is used to protect the external

FET from an overvoltage condition in the off state. This

function is only available on the 14-lead PDIP.

V : The V control pin is used for frequency compensa-

C C

tion, current limiting and shutdown. It is the high imped-

ance output of the sampling error amplifier and the input

of the current limit comparator.

GND: The Ground pin acts as both the negative sense

point for the internal sampling error amplifier feedback

signal and as the high current path for the 2A switch. Also,

the case of the 7-lead TO-220 is connected to ground.

Proper connections to ground for signal paths and high

current paths must be made in order to insure good load

regulation.

5V: A 5V reference is available to power primary-side cir-

cuitry. The temperature coefficient is typically 50ppm/°C

and the output can source 25mA. This function is only

available on the 14-lead PDIP.

SS: The Soft-Start pin is used to either program start-up

time with a capacitor to ground or to set external current

limit with a resistor divider. The SS pin has a 40µA pull-up

current and is reset to 0V by a 1mA pull-down current dur-

ing start-up and shutdown. This function is only avail-able

on the 14-lead PDIP.

OSC: The Oscillator pin sets the operating frequency

of the regulator with one external capacitor to ground.

Maximum duty cycle can also be adjusted by using an

external resistor to alter the charge/discharge ratio.

V

: The Switch Output pin is the output of a 1A ꢀPꢀ

SW

V : The Input Supply pin is designed to operate with volt-

IN

totem-pole stage. The V pin turns the external FET

SW

ages of 12V to 30V. The supply current is typically 200µA

up to the start-up threshold of 16V. ꢀormal operating

supply current is fairly flat at 18mA down to the shutdown

on by pulling its gate high. Break-Before-Make action of

200ns on each switch edge is built in to eliminate cross

conduction currents.

threshold of 7V. Switching is inhibited for V less than

Iꢀ

I

: The I pin is the input to the current limit amplifier

LIM LIM

12V due to the gate drive detection circuit.

and requires the use of a noninductive, power sense resis-

15V: A 15V reference is used to bias the gate of an exter-

nal power FET. The voltage temperature coefficient is typi-

cally 3mV/°C and the output can source 30mA. Typical

tor from I to ground to set current limit. The typical

LIM

current limit threshold voltage is 350mV. The typical input

bias current is 100µA out of the pin.

dropout voltage is 1.5V for V less than 17V and 30mA

Iꢀ

of load current.

Rev. E

11

For more information www.analog.com

LT1103/LT1105

BLOCK DIAGRAM

LT1103

V

SW

OSC

GATE

BIAS

DETECT

15V

GATE

15V

BIAS

OSCILLATOR

START-UP

16V

V

IN

LOGIC

DRIVER

7V

SPIKE

BLANK

ANTISAT

COMP

4.5V

+

5V

CURRENT

LIMIT

V

REF

+

AMP

–

0.15Ω

A

= 10

V

SAMPLING

ERROR AMP

= 0.012

6V

–

FB

g

m

40µA

0VLO

SHUT

DOWN

RESET

OVERVOLTAGE

LOCKOUT

2.5V

0.15V

LT1103 BD

V

SS

GND

C

LT1105

OSC

GATE

BIAS

15V

GATE

BIAS

15V

DETECT

OSCILLATOR

START-UP

DRIVER

ANTISAT

16V

V

IN

LOGIC

V

SW

7V

SPIKE

BLANK

COMP

4.5V

5V

+

CURRENT

LIMIT

5V

V

REF

+

I

LIM

AMP

–

A

= 10

V

6V

–

SAMPLING

FB

ERROR AMP

g

m

= 0.012

40µA

0VLO

SHUT

DOWN

RESET

OVERVOLTAGE

LOCKOUT

2.5V

0.15V

LT1105 BD

V

C

SS

GND

Rev. E

12

For more information www.analog.com

LT1103/LT1105

OPERATION

LT1103

turning on if the gate voltage is less than 10V or greater than

20V, the industry standards for power MOSFET operation.

The LT1103 is a current mode switcher. Switch duty cycle

is controlled by switch current rather than directly by the

output voltage. Referring to the block diagram, the switch

is turned on at the start of each oscillator cycle. It is turned

off when switch current reaches a predetermined level.

Control of output voltage is obtained by using the output

of a voltage sensing error amplifier to set current trip

level. This technique has several advantages. First, it has

immediate response to input voltage variations, unlike

ordinary switchers which have notoriously poor line tran-

sient response. Second, it reduces the 90°phase shift at

mid frequencies in the transformer. This greatly simpli-

fies closed-loop frequency compensation under widely

varying input voltage or output load conditions. Finally, it

allows simple pulse-by-pulse current limiting to provide

maximum switch protection under output overload or

short-circuit conditions.

The switch current is sensed internally and amplified to

trip the comparator and turn off the switch according to

the V pin control voltage. A blanking circuit suppresses

C

the output of the current limit comparator for 500ns at

the beginning of each switch cycle. This prevents false

tripping of the comparator due to current spikes caused

by external parasitic capacitance and diode stored charge.

The 4.5V Zener-based reference biases the positive input

of the sampling error amplifier. The negative input (FB)

is used for output voltage sensing. The sampling error

amplifier allows the LT1103 to operate in fully isolated

flyback mode by regulating from the flyback voltage of

the bootstrap winding. The leakage inductance spike at

the leading edge of the flyback waveform is ignored with

a blanking circuit. The flyback waveform is directly pro-

portional to the output voltage in a transformer-coupled

flyback topology. Output voltages are fully floating up

to the breakdown voltage of the transformer windings.

Multiple floating outputs are easily obtained with addi-

tional windings.

A start-up loop with hysteresis allows the IC supply volt-

age to be bootstrapped from an extra primary side wind-

ing on the power transformer. From 0V to 16V on V , the

Iꢀ

LT1103 is in a prestart mode and total input current is typ-

ically 200µA. Above 16V, up to 30V, the 6V regulator that

biases the internal circuitry and the externally available

15V regulator is turned on. The internal circuitry remains

The error signal developed at the comparator input is

brought out externally. This V pin has three functions

C

including frequency compensation, current limit adjust-

ment and total regulator shutdown. During normal opera-

tion, this pin sits at a voltage between 1.2V (low output

current) and 4.4V (high output current). The error ampli-

biased on until V drops below 7V and the part returns to

Iꢀ

the prestart mode. Output switching stops when the V

SW

drive is less than 10V corresponding to V of about 12V.

Iꢀ

The oscillator provides the basic clock for all internal tim-

ing. Frequency is adjustable to 200kHz with one external

capacitor from OSC to ground. The oscillator turns on the

output switch via the logic and driver circuitry. Adaptive

antisat circuitry detects the onset of saturation in the

power switch and adjusts driver current instantaneously

to limit switch saturation. This minimizes driver dissipa-

tion and provides very rapid turn-off of the switch.

fier is a current output (g ) type, so this voltage can be

m

externally clamped for adjusting current limit. Switch duty

cycle goes to zero if the V pin is pulled to ground through

C

a diode, placing the LT1103 in an idle mode. Pulling the

V pin below 0.15V causes total regulator shutdown and

C

places the LT1103 in a prestart mode.

LT1105

The LT1103 is designed to drive the source of an exter-

nal power FET in common gate configuration. The 15V

regulator biases the gate to guarantee the FET is on when

the switch is on. Special drive detection circuitry senses

the gate bias voltage and prevents the output switch from

The LT1105 is a current mode switcher. Switch duty cycle

is controlled by switch current rather than directly by out-

put voltage. Referring to the block diagram, the switch is

turned on at the start of each oscillator cycle. It is turned

off when switch current reaches a predetermined level.

Rev. E

13

For more information www.analog.com

LT1103/LT1105

Control of output voltage is obtained by using the output

of a voltage sensing error amplifier to set current trip

level. This technique has several advantages. First, it has

immediate response to input voltage variations, unlike

ordinary switchers which have notoriously poor line tran-

sient response. Second, it reduces the 90°phase shift at

midfrequencies in the transformer. This greatly simpli-

fies closed-loop frequency compensation under widely

varying input voltage or output load conditions. Finally, it

allows simple pulse-by-pulse current limiting to provide

maximum switch protection under output overload or

short-circuit conditions.

circuit suppresses the output of the current limit com-

parator for 500ns at the beginning of each switch cycle.

This prevents false tripping of the comparator due to cur-

rent spikes caused by external parasitic capacitance and

diode stored charge.

A 4.5V Zener-based reference biases the positive input

of the sampling error amplifier. The negative input (FB)

is used for output voltage sensing. The sampling error

amplifier allows the LT1105 to operate in fully isolated

flyback mode by regulating the flyback voltage of the

bootstrap winding. The leakage inductance spike at the

leading edge of the flyback waveform is ignored with a

blanking circuit. The flyback waveform is directly propor-

tional to the output voltage in the transformer coupled

flyback topology. Output voltages are fully floating up

to the breakdown voltage of the transformer windings.

Multiple floating outputs are easily obtained with addi-

tional windings.

A start-up loop with hysteresis allows the IC supply volt-

age to be bootstrapped from an extra primary side wind-

ing on the power transformer. From 0V to 16V on V ,

Iꢀ

the LT1105 is in prestart mode and total input current is

typically 200µA. Above 16V, up to 30V, the 6V regulator

that biases the internal circuitry and the externally avail-

able 5V and 15V regulators are turned on. The internal

The error signal developed at the comparator input is

circuitry remains biased on until V drops below 7V and

Iꢀ

brought out externally. The V pin has three functions

C

the part returns to prestart mode. Output switching stops

when the 15V gate bias reference is less than 10V cor-

including frequency compensation, current limit adjust-

ment and total regulator shutdown. During normal opera-

tion, this pin sits at a voltage between 1.2V (low output

current) and 4.4V (high output current). The error ampli-

responding to V of about 12V.

Iꢀ

The oscillator provides the basic clock for all internal tim-

ing. Frequency is adjustable to 200kHz with one external

capacitor from OSC to ground. The oscillator turns on the

output switch via the logic and driver circuitry.

fier is a current output (g ) type, so this voltage can be

m

externally clamped for adjusting current limit. Switch duty

cycle goes to zero if the V pin is pulled to ground through

C

a diode, placing the LT1105 in an idle mode. Pulling the

The LT1105 is designed to drive the gate of an external

power FET in common source configuration. The drivers

and the 1A maximum totem-pole output stage are biased

from the 15V gate bias reference. Special drive detec-

tion circuity senses the gate bias reference voltage and

prevents the output switch from turning on if this voltage

is less than 10V or greater than 20V. Break-Before-Make

action of 200ns is built into each switch edge to eliminate

cross conduction currents.

V pin below 0.15V causes total regulator shutdown and

C

places the LT1105 in prestart mode.

The SS pin implements soft-start with one external capac-

itor to ground. The internal pull-up current and clamp

transistor limit the voltage at V to one diode drop above

C

the voltage at the SS pin, thereby controlling the rate of

rise of switch current in the regulator. The SS pin is reset

to 0V when the LT1105 is in prestart mode.

Switch current is sensed externally through a precision,

power resistor. This allows for greater flexibility in switch

current and output power than allowed by the LT1103.

A final protection feature includes overvoltage lockout

monitoring of the main supply voltage on the OVLO pin.

If the OVLO pin is greater than 2.5V, the output switch is

prevented from turning on. This function can be disabled

by grounding the OVLO pin.

The voltage across the sense resistor is fed into the I

LIM

pin and amplified to trip the comparator and turn off the

switch according to the V pin control voltage. A blanking

C

Rev. E

14

For more information www.analog.com

LT1103/LT1105

APPLICATIONS INFORMATION

Bootstrap Start

maximum rectified DC input voltage. A final consideration

for the start-up resistor is to insure that the maximum

voltage rating of the resistor is not exceeded. Typical car-

bon film resistors have a voltage rating of 250V. The most

reliable and economical solution for the start-up resistor

is generally provided by placing several 0.25W resistors

in series.

It is inefficient as well as impractical to power a switching

regulator control IC from the rectified DC input as this

voltage is several hundred volts. Self-biased switching

regulator topologies take advantage of a lower voltage

auxiliary winding on the power transformer or inductor to

power the regulator, but require a start-up cycle to begin

regulation.

The LT1103/LT1105 is designed to operate with supply

pin voltages up to 30V. However, the auxiliary bias wind-

ing should be designed for a typical output voltage of

17V to minimize IC power dissipation and efficiency loss.

Allowances must also be made for cross regulation of

the bias voltage due to variations in the rectified DC line

voltage and output load current.

Start-up circuitry with hysteresis built into the LT1103/

LT1105 allows the input voltage to increase from 0V to

16V before the regulator tries to start. During this time

the start-up current of the switching regulator is typi-

cally 200µA and all internal voltage regulators are off.

The low quiescent current allows the input voltage to be

trickled up with only 500µA of current from the rectified

DC line voltage, thereby minimizing power dissipation in

the start-up resistor. At 16V, the internal voltage regula-

tors are turned on and switching begins. If enough power

feeds back through the auxiliary winding to keep the input

voltage to the switching regulator above 12V, then switch-

ing continues and a bootstrap start is accomplished. If

the input voltage drops below 12V, then the FET drive

detection circuit locks out switching. The input voltage

Soft-Start

Soft-start refers to the controlled increase of switch cur-

rent from a start-up or shutdown state. This allows the

power supply to come up to voltage in a controlled man-

ner and charge the output capacitor without activating

current limit. In general, soft-start is not required on the

LT1105 due to the design of the sampling error amplifier

g stage which generates asymmetrical slew capability

m

on the V pin.

C

continues to fall as the V bypass capacitor is discharged

Iꢀ

by the normal quiescent current of the LT1103/LT1105.

Once the input voltage falls below 7V, the internal volt-

age regulators are turned off and the switching regulator

returns to the low start-up current state. A continuous

“burp start” mode indicates a fault condition or an incom-

plete power loop.

This feature exhibits itself as a typical 3mA sink current

capability on the V pin whereas source current is only

C

275µA. The low g of the error amplifier allows small-

m

valued compensation capacitors to be used on V . This

C

allows the sink current to slew the compensation capaci-

tor quickly. Therefore, overshoot of the output voltage on

start-up sequences and recovery from overload or short-

circuit conditions is prevented. However, if a longer start-

up period is required, the soft-start function can be used.

The trickle current required to bootstrap the regulator

input voltage is typically generated with a resistor from

the rectified DC input voltage. When combined with the

regulator input bypass capacitor, the start-up resistor cre-

ates a ramp whose slope governs the turn-on time of the

regulator as well as the period of the “burp start” mode.

The design trade-offs are power dissipated in the trickle

resistor, the turn-on time of the regulator, and the hold-up

time of the regulator input bypass capacitor. The value

of the start-up resistor is set by the minimum rectified

DC input voltage to guarantee sufficient start-up current.

The recommended minimum trickle current is 500µA.

The power rating of the start-up resistor is set by the

Soft-start is implemented with an internal 40µA pull-up

and a transistor clamp on the V pin so that a single exter-

C

nal capacitor from SS ground can define the linear ramp

function. The voltage at V is limited to one V above the

C BE

soft-start pin (SS). The time to maximum switch current is

defined as the capacitance on SS multiplied by the active

range in volts of the V pin divided by the pull-up current:

C

C •(3.2V)

T =

40µA

Rev. E

15

For more information www.analog.com

LT1103/LT1105

APPLICATIONS INFORMATION

SS is reset to 0V whenever V is less than 7V (prestart

Iꢀ

Ground (LT1103)

mode) or when shutdown is activated by pulling V below

C

The ground pin of the LT1103 is important because it acts

as the negative sense point for the internal error amplifier

feedback signal, the negative sense point for the current

limit amplifier, and as the high current path for the 2A

switch. The tab of the 7-lead TO-220 is internally con-

nected to GꢀD (Pin 4).

0.15V. The SS pin has a guaranteed reset sink current of

1mA when either the regulator supply voltage V falls

Iꢀ

below 7V or the regulator is placed in shutdown.

Shutdown

The LT1103/LT1105 can be put in a low quiescent cur-

To avoid degradation of load regulation, the feedback

resistor divider string and the reference side of the bias

winding should be directly connected to the ground pin

on the package. These ground connections should not

be mixed with high current carrying ground return paths.

The length of the switch current ground path should be

as short as possible to the input supply bypass capacitor

and low resistance for best performance. The case of the

LT1103 package is desirable to use as the high current

ground return path as this is a lower resistive and induc-

tive path than that of the actual package pin and will help

minimize voltage spikes associated with the high dI/dt

switch current.

rent shutdown mode by pulling V below 150mV. In the

C

shutdown mode the internal voltage regulators are turned

off, SS is reset to 0V and the part draws less than 200µA.

To initiate shutdown, about 400µA must be pulled out

of V until the internal voltage regulators turn off. Then,

C

less than 50µA pull-down current is required to maintain

shutdown. The shutdown function has about 60mV of

hysteresis on the V pin before the part returns to normal

C

operation. Soft-start, if used, controls the recovery from

shutdown.

5V Reference

A 5V reference output is available for the user’s conve-

nience to power primary-side circuitry or to generate a

clamp voltage for switch current limiting. The output will

source 25mA and the voltage temperature coefficient is

typically 50ppm/°C. If bypassing of the 5V reference is

required, a 0.1µF is recommended. Values of capacitance

greater than 1µF may be susceptible to ringing due to

decreased phase margin. In such cases, the capacitive

load can be isolated from the reference output with a

small series resistor at the expense of load regulation

performance.

Avoiding long wire runs to the ground pin minimizes

load regulation effects and inductive voltages created by

the high dI/dt switch current. Ground plane techniques

should also be used and will help keep EMI to a mini-

mum. Grounding techniques are illustrated in the Typical

Applications section.

Ground (LT1105)

The ground pin of the LT1105 is important because it acts

as the negative sense point for the internal error amplifier

feedback signal and as the negative sense point for the

current limit amplifier. The LT1105 8-pin PDIP has Pin

1 as its ground. The LT1105 14-pin PDIP has Pin 1 and

Pin 7 as grounds and must be tied together for proper

operation.

Overvoltage Lockout

The switching supply and primarily the external power

MOSFET can be protected from an extreme surge of the

input line voltage with the overvoltage lockout feature

implemented on the OVLO pin. If the voltage on OVLO

rises above its typical threshold voltage of 2.5V, output

switching is inhibited. This feature can be implemented

with a resistive divider off of the rectified DC input voltage.

This feature is only available on the LT1105 in the 14-lead

PDIP and must be tied to ground if left unused.

To avoid degradation of load regulation, the feedback

resistor divider should be directly connected to the pack-

age ground pin. These ground connections should not

be mixed with high current carrying ground return paths.

The length of the switch current ground path should be

as short as possible to the input supply bypass capacitor

and low resistance for best performance. This will help

Rev. E

16

For more information www.analog.com

LT1103/LT1105

APPLICATIONS INFORMATION

minimize voltage spikes associated with the high dI/dt

switch current.

ꢀote that the capacitor value must change to maintain the

same frequency. For example, a 24k resistor from 5V to

OSC and a 440pF capacitor from OSC to ground will yield

100kHz with 50% maximum duty cycle. A 56k resistor and

a 280pF capacitor from OSC to ground will yield 100kHz

with 80% maximum duty cycle.

Avoiding long wire runs to the ground pin minimizes

load regulation effects and inductive voltages created by

the high dI/dt switch current. Ground plane techniques

should also be used and will help keep EMI to a mini-

mum. Grounding techniques are illustrated in the Typical

Applications section.

The oscillator can be synchronized to an external clock by

coupling a sync pulse into the OSC pin. The width of this

pulse should be a minimum of 500ns. The oscillator can

only be synchronized up in frequency and the synchroniz-

ing frequency must be greater than the maximum pos-

sible unsynchronized frequency (for the chosen oscillator

capacitor value). The amplitude of the sync pulse must be

chosen so that the sum of the oscillator voltage amplitude

plus the sync pulse amplitude does not exceed the 6V

bias reference. Otherwise, the oscillator pull-up current

source will saturate and erroneous operation will result.

If the LT1103/LT1105 is positioned on the primary side

of the transformer and the external clock on the isolated

secondary output side, the sync signal must be coupled

into the OSC pin using a pulse transformer. The pulse

transformer must meet all safety/isolation requirements

as it also crosses the isolation boundary. An example of

externally synchronizing the oscillator is shown in the

Typical Applications section.

Oscillator

The oscillator of the LT1103/LT1105 is a linear ramp type

powered from the internal 6V bias line. The charging cur-

rents and voltage thresholds are generated internally so

that only one external capacitor is required to set the fre-

quency. The 150µA pull-up current, which is on all the

time, sets the preset maximum on-time of the switch and

the 450µA pull-down current which is turned on and off,

sets the dead time. The threshold voltages are typically 2V

and 4.5V, so for a 400pF capacitor the ramp-up time of the

voltage on the OSC pin is 6.67µs and the ramp-down time

is 3.3µs, resulting in an operating frequency of 100kHz.

Although the oscillator, as well as the rest of the switching

regulator, will function at higher frequencies, 200kHz is

the practical upper limit that will allow control range for

line and load regulation. The lowest operating frequency

is limited by the sampling error amplifier to about 10kHz.

Gate Biasing (LT1103)

The frequency temperature coefficient is typically

–80ppm/°C with a good low T.C. capacitor. This means

that with a low temperature coefficient capacitor, the tem-

perature coefficient of the currents and the temperature

coefficient of the thresholds sum to –80ppm/°C over the

commercial temperature range. Bowing in the tempera-

ture coefficient of the currents affects the frequency about

3% at the extremes of the military temperature range.

The capacitor type chosen will have a direct effect on the

frequency tempco.

The LT1103 is designed to drive an external power

MOSFET in the common gate or cascode connection with

the V pin. The advantage is that the switch current

SW

can be sensed internally, eliminating a low value, power

sense resistor. The gate needs to be biased at a voltage

high enough to guarantee that the FET is saturated when

the open-collector source drive is on. This means 10V as

specified in FET data sheets, plus 1V for the typical switch

saturation voltage, plus a couple of volts for temperature

variations and processing tolerances. This leads to 15V

for a practical gate bias voltage.

Maximum duty cycle is set internally by the pull-up and

pull-down currents, independent of frequency. It can be

adjusted externally by modifying the fixed pull-up current

with an additional resistor. In practice, one resistor from

the OSC pin to the 5V reference or to ground does the job.

Power MOSFETs are well suited to switching power sup-

plies because their high speed switching characteris-

tics promote high switching efficiency. To achieve high

switching speed, a special circuit in the LT1103 senses

Rev. E

17

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LT1103/LT1105

APPLICATIONS INFORMATION

the voltage at V prior to turning on the switch. V is

SW SW

itself to keep the switch just at the edge of saturation. Very

low switch current results in nearly zero driver current

and high switch currents automatically increase driver

current as necessary. The ratio of switch current to driver

current is approximately 30:1. This ratio is determined by

the sizing of the extra emitter and the value of the current

source feeding the driver circuitry. The quasisaturation

state of the switch permits rapid turn-off without the need

for reverse base emitter voltage drive.

tied to the source of the FET and should represent the

bias voltage on the gate when the switch is off. When

the switch first turns off, the drain flies back until it is

clamped by a snubber network. The source also flies

high due to parasitic capacitive coupling on the FET and

parasitic inductance of the leads. An extra diode from the

source to the gate or V will provide insurance against

Iꢀ

fault conditions that might otherwise damage the FET.

The diode clamps the source to one diode drop above

Gate Biasing (LT1105)

the gate or V , thereby limiting the gate source reverse

Iꢀ

bias. Once the energy in the leakage inductance spike

is dissipated and the primary is being regulated to its

flyback voltage, the diode shuts off. The source is then

floating and its voltage will be close to the gate voltage.

The LT1105 is designed to drive an external power

MOSFET in the common source configuration with the

totem-pole output V

pin. The advantage is added

SW

switch current flexibility (limited only by the choice of

external power FET) and higher output power applications

than allowed by LT1103. An external, noninductive, power

sense resistor must be used in series with the source of

the FET to detect switch current and must be tied to the

input of the current limit amplifier. The gate needs to be

biased at a voltage high enough to guarantee that the

FET is saturated when the totem-pole gate drive is on.

This means 10V as specified in FET data sheets, plus

the totem-pole high side saturation voltage plus a couple

of volts for temperature variations and processing toler-

ances. This leads to 15V for a practical gate bias voltage.

If the sensed voltage on V is less than 10V or greater

SW

than 20V, the circuit prevents the switch from turning on.

This protects the FET from dissipating high power in a

nonsaturated state or from excessive gate-source voltage.

The oscillator continues to run and the net effect is to skip

switching cycles until the gate bias voltage is corrected.

One consequence of the gate bias detection circuit is that

the start-up window is 6V if the gate is biased from V

Iꢀ

and to 4V if the gate is biased from the 15V output. This

influences the size of the bypass capacitor on V .

Iꢀ

V

Output (LT1103)

SW

Power MOSFETs are well suited to switching power sup-

plies because their high speed switching characteris-

tics promote high switching efficiency. To achieve high

switching speed, the gate capacitance must be charged

and discharged quickly with high peak currents. In par-

ticular, the turn-off current can be as high as the peak

switch current. The switching speed is controlled by

the impedance seen by the gate capacitance. Practically

speaking, zero impedance is not desirable because of the

high frequency noise spikes introduced to the system.

The gate bias supply which drives the totem-pole output

stage should be bypassed with a 1µF low ESR capacitor

to ground. This capacitor supplies the energy to charge

the gate capacitance during gate drive turn-on. The power

MOSFET should have a 5Ω resistor or larger in series with

The V pin of the LT1103 is the collector of an internal

SW

ꢀPꢀ power switch. This ꢀPꢀ has a typical on resistance

of 0.4Ω and a typical breakdown voltage (BV ) of 75V.

CBO

Fast switching times and high efficiency are obtained by

using a special driver loop which automatically adapts

base drive current to the minimum required to keep the

switch in a quasisaturated state. The key element in the

loop is an extra emitter on the output power transistor as

seen in the block diagram. This emitter carries no current

when the ꢀPꢀ output transistor collector is high (unsatu-

rated). In this condition, the driver circuit can deliver very

high base drive to the switch for fast turn-on. When the

switch saturates, the extra emitter acts as a collector of

an ꢀPꢀ operating in inverted mode and pulls base current

away from the driver. This linear feedback loop serves

its gate from the V pin to define the source impedance.

SW

Rev. E

18

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LT1103/LT1105

APPLICATIONS INFORMATION

The LT1105 provides a 15V regulated output intended

for driving the totem-pole output stage. It will source

30mA into a capacitive load with no stability problems.

The output voltage temperature coefficient is 3mV/°C. If

switch just at the edge of saturation. This results in nearly

zero driver current. The quasisaturation state of the low

side switch permits rapid turn-on of the external FET when

V

pulls high.

SW

V drops below 17V, the 15V output follows about 2.0V

Iꢀ

Fully Isolated Flyback Mode

below V until the part shuts down. If the 15V output is

Iꢀ

pulled above 17.5V, it will sink 5mA.

A unique sampling error amplifier included in the control

loop of the LT1103/LT1105 eliminates the need for an

optoisolator while providing 1% line and load regulation

in a magnetic flux-sensed flyback converter. In this mode,

the flyback voltage on the primary during “switch off” time

is sensed and regulated. It is difficult to derive a feedback

signal directly from the primary flyback voltage as this

voltage is typically several hundred volts. A dedicated

winding is not required because the bias winding for the

regulator lends itself to flux-sensing. Flux-sensing made

practical simplifies the design of off line power supplies

by minimizing the total number of external components

and reduces the components which must cross the isola-

tion barrier to one, the transformer. This inherently implies

greater safety and reliability. The transformer must be

optimized for coupling between the bias winding and

the secondary output winding(s) while maintaining the

required isolation and minimizing the parasitic leakage

inductances.

A special circuit in the LT1105 senses the voltage at the

15V regulated output prior to turning on the switch. The

15V regulator drives the totem-pole output stage and the

V

pin will pull the gate of the FET very close to the

SW

value of the 15V output when V turns on. Therefore,

SW

the 15V output represents what the gate bias voltage on

the FET will be when the FET is turned on. If the sensed

voltage on the 15V output is less than 10V or greater

than 20V, the circuit prevents the switch from turning

on. This protects the FET from dissipating high power

in a nonsaturated state or from excessive gate-source

voltage. The oscillator continues to run and the net effect

is to skip switching cycles until the gate bias voltage is

corrected. One consequence of the gate bias detection

circuit is that the start-up window is 4V. This influences

the size of the bypass capacitor on V .

Iꢀ

V

Output (LT1105)

SW

The V pin of the LT1105 is the output of a 1A totem-

SW

Although magnetic flux-sensing has been used in the

past, the technique has exhibited poor output voltage

regulation due to the parasitics present in a transformer

coupled design. Transformers which provide the safety

and isolation as required by various international safety/

regulatory agencies also provide the poorest output volt-

age regulation. Solutions to these parasitic elements have

been achieved with the novel sampling error amplifier of

the LT1103/LT1105. A brief review of flyback converter

operation and the problems which create a poorly regu-

lated output will provide insight on how the sampling error

amplifier of the LT1103/LT1105 addresses the regulation

issue of magnetic flux sensed converters.

pole driver stage. This output stage turns an external

power MOSFET on by pulling its gate high. Break-Before-

Make action of 200ns is built into each switch edge to

eliminate cross-conduction currents. Fast switching times

and high efficiency are obtained by using a low loss output

stage and a special driver loop which automatically adapts

base drive current to the totem-pole low side drive. The

key element in the loop is an extra emitter on the output

pull-down transistor as seen in the block diagram. This

emitter carries no current when the low side transistor

collector is high (unsaturated). In this condition, the driver

can deliver very high base drive to the output transistor

for fast turn-off. When the low side transistor saturates,

the extra emitter acts as a collector of an ꢀPꢀ operating

in inverted mode and pulls base current away from the

driver. This linear feedback loop serves itself to keep the

The following figure shows a simplified diagram of a fly-

back converter using magnetic flux sensing. The major

parasitic elements present in the transformer coupled

design are indicated. The relationships between the

Rev. E

19

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LT1103/LT1105

APPLICATIONS INFORMATION

primary voltage, the secondary voltage, the bias voltage

and the winding currents are indicated in the figures found

on the following page for both continuous and discontinu-

ous modes of operation.

to zero or changing polarity. Therefore, the voltage on

the bias winding is only valid as a representation of the

output voltage while the secondary is delivering current.

Although the bias winding flyback voltage is a representa-

tion of the output voltage, its voltage is not constant. For

a brief period following the leakage inductance spike, the

bias winding flyback voltage decreases due to nonlineari-

ties and parasitics present in the transformer. Following

this nonlinear behavior is a period where the bias winding

flyback voltage decreases linearly. This behavior is easily

explained. Current flow in the secondary decreases lin-

early at a rate determined by the voltage across the sec-

ondary and the inductance of the secondary. The parasitic

secondary leakage inductance appears as an impedance

in series with the secondary winding. In addition, parasitic

resistances exist in the secondary winding, the output

diode and the output capacitor. These impedances can

be combined to form a lumped sum equivalent and which

cause a voltage drop as secondary current flows. This

voltage drop is coupled from the secondary to the bias

winding flyback voltage and becomes more significant

as the output is loaded more heavily. This voltage drop is

largest at the beginning of “switch off” time and smallest

just prior to either all transformer energy being depleted

or the switch turning on again.

Simplified Flyback Converter

V

IN

L(Ik

)

PRI

D1

R

L(lk

)

SEC

1:N

V

OUT

C1

COMMON

S1

N = TURNS RATIO FROM SECONDARY TO PRIMARY.

N1 = TURNS RATIO FROM SECONDARY TO BIAS.

N2 = N/N1

V

BIAS

L(lk ) = PRIMARY LEAKAGE INDUCTANCE.

PRI

L(lk ) = SECONDARY LEAKAGE INDUCTANCE.

SEC

R = PARASITIC WINDING, DIODE AND OUTPUT

1:N1

CAPACITOR RESISTANCE.

LT1103 AI01

When the switch “turns on,” the primary winding sees the

input voltage and the secondary and bias windings go to

negative voltages as a function of the turns ratio. Current

builds in the primary winding as the transformer stores

energy. When the switch “turns off,” the voltage across

the switch flies back to a clamp level as defined by a snub-

ber network until the energy in the leakage inductance of

the primary dissipates. Leakage inductance is one of the

main parasitic elements in a flux-sensed converter and

is modeled as an inductor in series with the primary and

secondary of the transformer. These parasitic inductances

contribute to changes in the bias winding voltage and thus

the output voltage with increasing load current.

The best representation of the output voltage is just prior

to either all transformer energy being used up and the

bias winding voltage collapsing to zero or just prior to

the switch turning on again and the bias winding going

negative. This point in time also represents the small-

est forward voltage for the output diode. It is possible to

redefine the relationship between the secondary winding

voltage and the bias winding voltage as:

The energy stored in the transformer transfers through

the secondary and bias windings during “switch off” time.

Ideally, the voltage across the bias winding is set by the DC

output voltage, the forward voltage of the output diode,

and the turns ratio of the transformer after the energy in

the leakage inductance spike of the primary is dissipated.

V

OUT

+ Vf +I• R

(

=

)

P

V

BIAS

N1

where Vf is the forward voltage of the output diode, I is

the current flowing in the secondary, R is the lumped

P

This relationship holds until the energy in the transformer

drops to zero (discontinuous mode) or the switch turns on

again (continuous mode). Either case results in the volt-

age across the secondary and bias windings decreasing

sum equivalent secondary parasitic impedance and ꢀ1 is

the transformer turns ratio from the secondary to the bias

winding. It is apparent that even though the above point

Rev. E

20

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LT1103/LT1105

APPLICATIONS INFORMATION

Flyback Waveform for Continuous Mode Operation

Flyback Waveform for Discontinuous Mode Operation

V

ZENER

V

ZENER

PRIMARY SWITCH VOLTAGE

[V

+ Vf + (I • R )]/N

SEC P

OUT

IN

[V

OUT

+ Vf + (I • R )]/N

SEC P

a

V

IN

AREA “a” = AREA “b” TO MAINTAIN

ZERO VOLTS ACROSS PRIMARY

AREA “a” = AREA “b” TO MAINTAIN

ZERO VOLTS ACROSS PRIMARY

b

0V

SECONDARY WINDING VOLTAGE

[V

OUT

+ Vf + (I • R )]

SEC P

[V

OUT

+ Vf + (I • R )]

SEC P

c

0V

AREA “c” = AREA “d” TO MAINTAIN

ZERO VOLTS ACROSS SECONDARY

AREA “c” = AREA “d” TO MAINTAIN

ZERO VOLTS ACROSS SECONDARY

d

N • V

IN

N • V

IN

BIAS WINDING VOLTAGE

[V

+ Vf + (I • R )]/N1

SEC P

OUT

[V

+ Vf + (I • R )]/N1

SEC P

OUT

e

0V

AREA “e” = AREA “f” TO MAINTAIN

ZERO VOLTS ACROSS BIAS WINDING

AREA “e” = AREA “f” TO MAINTAIN

ZERO VOLTS ACROSS BIAS WINDING

f

N2 • V

IN

N2 • V

IN

I

PRI

∆I

PRIMARY CURRENT

0A

I

SEC = PRI

/N

I

SEC = PRI

/N

SECONDARY CURRENT

0A

I

PRI

∆I

SWITCH CURRENT

0A

I

PRI

I

PRI

SNUBBER DIODE CURRENT

0A

∆t = (I )[L(lk )]/V

PRI PRI SNUB

∆t = (I )[L(lk )]/V

PRI PRI SNUB

LT1103 WF01

Rev. E

21

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LT1103/LT1105

APPLICATIONS INFORMATION

in time is the most accurate representation of the output

voltage, the answer given by the bias winding voltage is

flyback waveform as it changes with time and amplifies

the difference between the flyback signal and the internal

4.5V reference. Tracking is maintained until the point in

time where the bias winding voltage collapses as a result

of all transformer energy being depleted (discontinuous

mode) or the switch turning on again (continuous mode).

The level detector circuit senses the fact that the bias

winding flyback voltage is no longer a representation of

the output voltage and activates an internal peak detector.

This effectively saves the most accurate representation of

the output voltage which is then buffered to the second

stage of the error amplifier.

still off from the “true” answer by the amount I • R /ꢀ1.

P

The sampling error amplifier of the LT1103/LT1105 pro-

vides solutions to the errors associated with the bias

winding flyback voltage. The error amplifier is comprised

of a leakage inductance spike blanking circuit, a slew rate

limited tracking amplifier, a level detector, a sample-and-

hold, an output g stage and load regulation compensa-

m

tion circuitry. This all seems complicated at first glance,

but its operation is straightforward and transparent to

the user of the IC. When viewed from a system or block

level, the sampling error amplifier behaves like a simple

transconductance amplifier. Here’s how it works.

The second stage of the error amplifier consists of a

sample-and-hold. When the switch turns on, the sample-

and-hold samples the buffered error voltage for 1µs and

then holds for the remainder of the switch cycle. This

The sampling error amplifier takes advantage of the fact

that the voltage across the bias winding during at least a

portion of switch off time is proportional to the DC output

voltage of the secondary winding. The feedback network

used to sense the bias winding voltage is no longer com-

prised of a traditional peak detector in conjunction with a

resistor divider network. The feedback network consists

of a diode in series with the bias winding feeding the resis-

tor divider network directly. The resultant error signal is

then fed into the input of the error amplifier. The purpose

of the diode in series with the bias winding is now not to

peak detect, but to prevent the FB pin (input of the error

amplifier) from being pulled negative and forward biasing

the substrate of the IC when the bias winding changes

polarity with “switch turn-on.”

held voltage is then processed by the output g stage and

m

converted into a control signal at the output of the error

amplifier, the V pin.

C

The final adjustment in regulation is provided by the load

regulation compensation circuitry. As stated earlier, output

regulation degrades with increasing load current (output

power). The effect is traced to secondary leakage induc-

tance and parasitic secondary winding, diode and output

capacitor resistances. Even though the tracking ampli-

fier has obtained the most accurate representation of the

output voltage, its answer is still flawed by the amount of

the voltage drop across the secondary parasitic lumped

sum equivalent impedance which is coupled to the bias

winding voltage. This error increases with increasing load

current. Therefore, a technique for sensing load current

conditions has been added to the LT1103/LT1105. The

switch current is proportional to the load current by the

turns ratio of the transformer. A small current proportional

to switch current is generated in the LT1103/LT1105 and

fed back to the FB pin. This allows the input bias current

of the sampling error amplifier to be a function of load

current. A resistor in series with the FB pin generates

a linear increase in the effective reference voltage with

increasing load current. This translates to a linear increase

in output voltage with increasing load current. By adjust-

ing the value of the series resistor, the slope of the load

The primary winding leakage inductance spike effects

are first eliminated with an internal blanking circuit in the

LT1103/LT1105 which suppresses the input of the FB

pin for 1.5µs at the start of “switch off” time. This pre-

vents the primary leakage inductance spike from being

propagated through the error amplifier and affecting the

regulated output voltage.

With the effects of the leakage inductance spike eliminated,

the effects of decreasing bias winding flyback voltage can

be addressed. With the traditional diode/capacitor peak

detector circuitry eliminated from the feedback network,

the tracking amplifier of the LT1103/LT1105 follows the

Rev. E

22

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LT1103/LT1105

APPLICATIONS INFORMATION

compensation can be set to cancel the effects of these

parasitic voltage drops. The feature can be ignored by

eliminating the series resistor and lowering the equivalent

divider impedance to swamp out the effects of the input

bias current.

drops back to 0° (actually 180° since FB is an inverting

input) when the reactance of C is small compared to

C

R . Thus, this RC series network forms a pole-zero pair.

C

The pole is set by the high impedance output of the error

amplifier and the value of C on the V pin. The zero is

C C

formed by the value of C and the value of R in series

C C

Frequency Compensation

with C on the V pin. The RC series network will have

C C

capacitor values in the range of 0.1µF to 1.0µF and series

resistor values in the range of 100Ω to 1000Ω .

In order to prevent a regulator loop using the LT1103/

LT1105 from oscillating, frequency compensation is

required. Although the architecture of the LT1103/LT1105

is simple enough to lend itself to a mathematical approach

to frequency compensation, the added complication of

input/or output filters, unknown capacitor ESR, and gross

operating point changes with input voltage and load cur-

rent variations all suggest a more practical empirical

approach. Many hours spent on breadboards have shown

that the simplest way to optimize the frequency compen-

sation of the LT1103/LT1105 is to use transient response

techniques and an “RC” box to quickly iterate toward the

final compensation network. Additional information on

this technique of frequency compensation can be found

in Linear Technology’s Application ꢀote 19.

It is noted that the RC network on the V pin forms

C

the main compensation network for the regulator loop.

However, if the load regulation compensation feature is

used as explained in the section on fully-isolated flyback

mode, additional frequency compensation components

are required. The load regulation compensation feature

involves the use of local positive feedback from the V

C

pin to the FB pin. Thus, it is possible to add enough load

regulation compensation to make the loop oscillate. In

order to prevent oscillation, it is necessary to roll off

this local positive feedback at high frequencies. This is

accomplished by placing a capacitor in parallel with the

compensation resistor which is in series with the FB pin.

A value for this capacitor in the range of 0.01µF to 0.1µF is

recommended. The time constant associated with this RC

combination will be longer than that associated with the

loop bandwidth. Thus, transient response will be affected

In general, frequency compensation is accomplished with

an RC series network on the V pin. The error amplifier

C

has a g (voltage “in” to current “out”) of ≈ 12000 µmhos.

m

Voltage gain is determined by multiplying g times the

m

in that settling time will be increased. However, this is typi

-

total equivalent error amplifier output loading, consisting

of the error amplifier output impedance in parallel with the

series RC external frequency compensation network. At

DC, the external RC can be ignored. The output imped-

ance of the error amplifier is typically 100kΩ resulting in

a voltage gain of ≈ 1200V/V. At frequencies just above DC,

the voltage gain is determined by the external compensa-

tion, R and C . The gain at mid frequencies is given by:

cally not as important as controlling the absolute under

or overshoot amplitude of the system in response to load

current changes which could cause deleterious system

operation.

Switching Regulator Topologies

Two basic switching regulator topologies are pertinent to

the LT1103/LT1105, the flyback and forward converter.

The flyback converter employs a transformer to convert

one voltage to either a higher or lower output voltage.

C

g

m

A =

V

2π • f •C

C

V

in continuous mode is defined as:

OUT

The gain at high frequencies is given by:

DC

A = g • R

V m

V

OUT

= V •N •

IN

C

(1–DC)

Phase shift from the FB pin to the V pin is 90° at mid

C

frequencies where the external C is controlling gain, then

C

Rev. E

23

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LT1103/LT1105

APPLICATIONS INFORMATION

where ꢀ is the transformer turns ratio of secondary to

primary and DC is the duty cycle. This formula can be

rewritten in terms of duty cycle as:

needed, a reasonable starting value is found by assigning

∆I a value of 20% of the peak switch current (2A for the

LT1103 and set by the external FET rating used with the

LT1105). With this design approach, L is defined as:

PRI

V

OUT

DC =

V

IN

V

OUT

+N • V

(

)

IN

L

=

PRI

⎛

⎞

V

IN

(ΔI)(f) 1+

It is important to define the full range of input voltage,

the range of output loading conditions and the regulation

requirements for a design. Duty cycle should be calcu-

lated for both minimum and maximum input voltage.

⎜

⎟

V

PRI

⎝

⎠

If maximum output power is not required, then ∆I can

be increased which results in lower primary inductance

and smaller magnetics. Maximum output power with an

isolated flyback converter is defined by the primary fly-

back voltage and the peak allowed switch current and is

limited to:

In many applications, ꢀ can vary over a wide range with-

out degrading performance. If maximum output power is

desired, ꢀ can be optimized:

V

OUT

+ Vf

N

=

V – V

OPT

(

)

V

PRI

(

PRI

)

ΔI

P

⎡

⎤

⎛

⎞

2

– V

P

=

V

IN

I

Ip R E

( )

(

M

)

SNUB

IN MAX

(

)

⎜

⎝

⎟

⎠

OUT(MAX)

⎢

⎥

V

+ V

2

(

)

⎣

⎦

IN

where

Vf = Forward voltage of the output diode

R = Total “switch” on resistance

V = Maximum switch voltage

M

I = Maximum switch current

P

V

= Snubber clamp level – primary flyback voltage.

SꢀUB

E = Overall efficiency ≈ 75%

In the isolated flyback mode, the LT1103/LT1105 sense

Peak primary current is used to determine core size for

the transformer and is found from:

and regulate the transformer primary voltage V during

PRI

“switch off” time. The secondary output voltage will be

regulated if V is regulated. V is related to V

PRI PRI

by:

V

I

)(

OUT OUT

V

PRI

+ V

OUT

(

)

+

(

)

ΔI

IN

I

=

PRI

E V

(

V

2

)(

)

V

OUT

+ Vf

PRI

IN

(

=

)

V

PRI

N

A second consideration on primary inductance is the

transition point from continuous mode to discontinuous

mode. At light loads, the flyback pulse across the primary

will drop to zero before the end of “switch off” time. The

load current at which this starts to occur can be calculated

from:

This allows duty cycle for an isolated flyback converter

to be rewritten as:

V

PRI

DC = Duty Cycle =

V

PRI

+ V

(

)

IN

2

An important transformer parameter to be determined is

V

• V

PRI IN

(

)

I

=

V

the primary inductance L . The value of this inductance

PRI

OUT(TRANSITION)

2

+ V

2V

f L

( )

)

(

)

(

)

(

PRI

IN

PRI

OUT

is a trade-off between core size, regulation requirements,

leakage inductance effects and magnetizing current ∆I.

Magnetizing current is the difference between the primary

current at the start of “switch on” time and the current at

the end of “switch on” time. If maximum output power is

The forward converter as shown below is another trans-

former-based topology that converts one voltage to either

a higher or a lower voltage.

Rev. E

24

For more information www.analog.com

LT1103/LT1105

APPLICATIONS INFORMATION

V

in continuous mode is defined as:

when S1 is off. This “reset” winding limits the maximum

duty cycle allowed for the switch. This topology trades

off reduced transformer size for increased complexity and

parts count. A separate isolated feedback path is required

for full isolation from input to output because voltages on

the primary are no longer related to the DC output voltage

during switch off time.

OUT

V

= V • ꢀ • DC

Iꢀ

OUT

The secondary voltage charges up L1 through D1 when

S1 is on. When S1 is off, energy in L1 is transferred

through free-wheeling diode D2 to C1. The extra trans-

former winding and diode D3 are needed in a single

switch forward converter to define the switch voltage

The isolated feedback path can take several forms. A

second transformer in a modulator/demodulator scheme

provides the isolation, but with significant complexity. An

optoisolator can be substituted for the transformer with a

savings in volume to be traded off with component varia-

tions and possible aging problems with the optoisolator

transfer function. Finally, an extra winding closely coupled

to the output inductor L1 can sense the flux in this ele-

ment and give a representation of the output voltage when

S1 is off.

Simplified Forward Converter

L1

V

IN

OUT

1:N

D1

C1

D2

COMMON

D3

S1

LT1103 AI02

TYPICAL APPLICATIONS

LT1103 FET Connection

15V

LT1103

V

SW

LT1103 TA03

LT1105 FET Connection

15V

V

LT1105

SW

I

LIM

LT1103 TA04

Rev. E

25

For more information www.analog.com

LT1103/LT1105

TYPICAL APPLICATIONS

Setting Oscillator Frequency

Setting Overvoltage Lockout

OVLO

TH

R2

LT1105

LT1103/LT1105

OVLO

R1

OSC

LT1103 TA09

C

OSC

LT1103 TA05

CHOOSE OVLO

TH

CHOOSE 20kHz ≤ f

≤ 200kHz

OSC

LET R1 = 5k

100µA

2.5V

I

SF

OVLO

TH

C

=

OSC

R2 =

–1 R1

)

f

∆V

f

(

OSC

2.5V

OSC

(

)

OSC

)

(

)

(

)

DC ꢁ 0.66 ꢂ 66%

Decreasing Oscillator

Increasing Oscillator

Maximum Duty Cycle

Synchronizing Oscillator Frequency

to an External Clock

Maximum Duty Cycle

5V

LT1105

LT1103/LT1105

500ns

5V

OSC

1µF

C

OSC

1:0.5

R

0V

I1

C

OSC

C

R

OSC

I1

LT1103 TA07

LT1103 TA08

LT1103 TA06

CHOOSE 0 ≤ DC ≤ 0.66

CHOOSE 0.66 ≤ DC ≤ 1.0

(6 – 9DC)

(9DC – 6)

SOLVE FOR X ꢂ X =

2

ISOLATION

BOUNDARY

2

0 ≤ X ≤ 3

0 ≤ X ≤ 1.5

ꢂ I1 = X • I = X • 100µA

1.75V

ꢂ R =

3.25V

ꢂ R =

I1

2

3X – 2X

(

)

100µA

2.5V

C

=

•

1 +

3X + 2X

(

)

OSC

100µA

C

OSC

=

• 1 –

9

f

(

)

OSC

)

(

9

2.5V

f

OSC

(

)

(

Rev. E

26

For more information www.analog.com

LT1103/LT1105

TYPICAL APPLICATIONS

LT1103 Ground Connections

15V

SWITCH CURRENT PATH

V

IN

KEEP RESISTANCE LOW

OSC

GND

V

C

FB

V

SW

LT1103 TA11a

TO BIAS

GND

WINDING OUTPUT

SEPARATE

GROUND PATH

SWITCH CURRENT PATH

KEEP RESISTANCE LOW

15V

V

IN

OSC

GND

V

C

FB

V

SW

LT1103 TA11b

TO BIAS

GND

WINDING OUTPUT

LT1105 Ground Connections

HIGH CURRENT

GROUND PATH

V

GND

SW

I

LIM

V

FB

IN

V

C

TO BIAS

WINDING

OUTPUT

LT1103 TA12a

Rev. E

27

For more information www.analog.com

LT1103/LT1105

PACKAGE DESCRIPTION

N Package

8-Lead PDIP (Narrow .300 Inch)

(Reference LTC DWG # 05-08-1510 Rev I)

.400*

(10.160)

MAX

8

7

6

5

.255 ±.015*

(6.477 ±0.381)

1

2

4

3

.130 ±.005

.300 – .325

.045 – .065

(3.302 ±0.127)

(1.143 – 1.651)

(7.620 – 8.255)

.065

(1.651)

TYP

.008 – .015

.120

(0.203 – 0.381)

.020

(3.048)

MIN

+.035

(0.508)

MIN

.325

–.015

.018 ±.003

(0.457 ±0.076)

.100

+0.889

8.255

–0.381

N8 REV I 0711

(2.54)

BSC

(

)

NOTE:

INCHES

1. DIMENSIONS ARE

MILLIMETERS

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)

Rev. E

28

For more information www.analog.com

LT1103/LT1105

PACKAGE DESCRIPTION

N Package

14-Lead PDIP (Narrow .300 Inch)

(Reference LTC DWG # 05-08-1510 Rev I)

.770*

(19.558)

MAX

14

13

12

11

10

9

8

.255 .015*

(6.477 0.381)

1

2

3

5

6

7

4

.300 – .325

.045 – .065

.130 .005

(7.620 – 8.255)

(3.302 0.127)

(1.143 – 1.651)

.020

(0.508)

MIN

.065

.008 – .015

(1.651)

TYP

(0.203 – 0.381)

+.035

.325

.005

(0.127)

MIN

–.015

.120

.018 .003

.100

(2.54)

BSC

+0.889

(3.048)

MIN

(0.457 0.076)

8.255

–0.381

(

)

N14 REV I 0711

NOTE:

INCHES

MILLIMETERS

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)

1. DIMENSIONS ARE

Rev. E

29

For more information www.analog.com

LT1103/LT1105

PACKAGE DESCRIPTION

T7 Package

7-Lead Plastic TO-220 (Standard)

(Reference LTC DWG # 05-08-1422)

.165 – .180

.147 – .155

.390 – .415

(4.191 – 4.572)

(3.734 – 3.937)

DIA

.045 – .055

(9.906 – 10.541)

(1.143 – 1.397)

.230 – .270

(5.842 – 6.858)

.570 – .620

(14.478 – 15.748)

.620

(15.75)

TYP

.460 – .500

(11.684 – 12.700)

.330 – .370

(8.382 – 9.398)

.700 – .728

(17.780 – 18.491)

.095 – .115

SEATING PLANE

(2.413 – 2.921)

.152 – .202

(3.860 – 5.130)

.155 – .195*

.260 – .320

(6.604 – 8.128)

(3.937 – 4.953)

.013 – .023

.050

BSC

.026 – .036

(0.660 – 0.914)

(0.330 – 0.584)

(1.27)

.135 – .165

(3.429 – 4.191)

*MEASURED AT THE SEATING PLANE

T7 (TO-220) 0801

OBSOLETE PACKAGE

Rev. E

30

For more information www.analog.com

LT1103/LT1105

REVISION HISTORY (Revision history begins at Rev B)

REV

DATE

DESCRIPTION

PAGE NUMBER

E

11/18 Reflects LT1103 being obsolete and the LT1105 being available.

All

Rev. E

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog

Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications

subject to change without notice. ꢀo license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

31

For more information www.analog.com

LT1103/LT1105

TYPICAL APPLICATION

Minimum Parts Count Fully-Isolated Flyback 100kHz 50W Converter

OPTIONAL OUTPUT FILTER

MBR2045

85V TO 270V

AC

10µH

AC

5V

10A

1.5KE300A

5W

+

50V

470µF

35V

3600µF

220k

1W

+

MUR150

220µF

385V

499Ω

*OUTPUT CAPACITOR IS THREE 1200µF,

50V CAPACITORS IN PARALLEL TO

ACHIEVE REQUIRED RIPPLE CURRENT

RATING AND LOW ESR.

–

1N4148

1000pF

100Ω

BRIDGE

RECTIFIER

+

WINDINGS FOR

OPTIONAL

BAV21

LINE

BUK426-800A

V

12V OUTPUTS

DC

FILTER

SW

IN

BAV21

+

39µF

25V

LT1103

16.2k

1%

10Ω

TRANSFORMER DATA:

COILTRONICS - CTX110228-3

= 1.6mH

15V

FB

L

(PRI)

+

GND

OSC

V

C

1µF

5.36k

1%

N

:N

PRI SEC

= 1:0.05

= 1:0.27

25V

N :N

BIAS SEC

390pF

330Ω

0.1µF

0.047µF

LT1103 TA01

Danger!! Lethal Voltages Present – See Text

Load Regulation

5.25

5.20

5.15

5.10

5.05

5.00

4.95

4.90

4.85

4.80

4.75

270V

AC

220V

AC

110V

AC

85V

AC

0

1

2

3

4

5

6

7

8

9

10

I

(A)

OUT

LT1103 TA14

RELATED PARTS

PART NUMBER DESCRIPTION

High Speed Current Mode Pulse Width Modulators

Off-Line Current Mode PWM

COMMENTS

Up to 500kHz Operation

1MHz Operation

Programmable Frequency, 16-Pin SO

100kHz, SO-8

LT1241

LT1246

LT1248

LT1249

LT1508

LT1509

Power Factor Controller

Power Factor and PWM Controller

Voltage Mode

Current Mode

Rev. E

11/18

www.analog.com

32

 ANALOG DEVICES, INC. 2018


型号：	LT1103CT7#PBF
厂家：	ADI
描述：	Switching Regulator 局域网开关
文件：	总32页 (文件大小：257K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LT1103CT7#PBF [ADI]

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LT1105CN8#PBF