HMC1049LP5E_18 [ADI]
Low Noise Amplifier;
| 型号： | HMC1049LP5E_18 |
| 厂家： | 
ADI |
| 描述： | Low Noise Amplifier |
| 文件： | 总14页 (文件大小：332K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GaAs, pHEMT, MMIC, Low Noise
Amplifier, 0.3 GHz to 20 GHz
Data Sheet
HMC1049LP5E
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Low noise figure: 1.8 dB
P1dB output power: 14.5 dBm
PSAT output power: 17.5 dBm
NC 1
24 NC
23
High gain: 15 dB
Output IP3: 29 dBm
HMC1049LP5E
2
V
NC
DD
NC 3
22 GND
Supply voltage: VDD = 7 V at 70 mA
50 Ω matched input/output (I/O)
32-lead, 5 mm × 5 mm LFCSP package: 25 mm2
GND 4
21 RFOUT/V
DD
5
6
7
20
19
18
RFIN
NC
NC
NC
NC
NC
APPLICATIONS
NC 8
17 NC
Test instrumentation
High linearity microwave radios
VSAT and SATCOM
Figure 1.
Military and space
GENERAL DESCRIPTION
The HMC1049LP5E is a GaAs MMIC low noise amplifier
(LNA) that operates between 0.3 GHz and 20 GHz. This LNA
provides 15 dB of small signal gain, 1.8 dB noise figure, and an
IP3 output of 29 dBm, yet requires only 70 mA from a 7 V
supply. The P1dB output power of 14.5 dBm enables the LNA to
function as a local oscillator (LO) driver for balanced, I/Q, or
image rejection mixers. VDD can also be applied to Pin 21,
although Pin 21 requires a bias tee with VDD = 4 V. The
HMC1049LP5E amplifier I/Os are internally matched to 50 Ω,
and the device is supplied in a compact, leadless 5 mm × 5 mm
LFCSP package.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Technical Support
©2018 Analog Devices, Inc. All rights reserved.
www.analog.com
HMC1049LP5E
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Pin Configuration and Function Descriptions..............................5
Interface Schematics .....................................................................6
Typical Performance Characteristics ..............................................7
Evaluation Printed Circuit Board................................................. 12
Packaging and Ordering Information ......................................... 14
Outline Dimensions................................................................... 14
Ordering Guide .......................................................................... 14
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings ....................................................... 4
ESD Caution.................................................................................. 4
REVISION HISTORY
5/2018—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to General Description .....................................................1
Change to Table 2, Thermal Resistance Parameter Column.......4
Added Figure 2...................................................................................5
Changes to Table 4.............................................................................5
Moved Figure 3 to Figure 9 to Interface Schematics Section ......6
Change to Figure 8 and Figure 9 .....................................................6
Changes to Figure 36...................................................................... 13
Added Ordering Guide Section.................................................... 15
Changed HMC1049 to HMC1049LP5E..................... Throughout
Changes to Features Section and General Description Section. 1
Change to Figure 27 Caption and Figure 28 Caption................ 10
Updated Outline Dimensions....................................................... 14
Changes to Ordering Guide .......................................................... 14
11/2014—Rev. 01.1213 to Rev. A
This Hittite Microwave Products data sheet has been reformatted
to meet the styles and standards of Analog Devices, Inc.
Rev. B | Page 2 of 14
Data Sheet
HMC1049LP5E
SPECIFICATIONS
TA = 25°C, VDD = 7 V, IDD = 70 mA1.
Table 1.
Parameter
Min
0.3
Typ
Max
Min
1
Typ
Max
Min
14
Typ
Max
Unit
GHz
dB
dB/°C
dB
FREQUENCY RANGE
1
14
20
GAIN
13.5
16.5
0.006
2.5
12
15
0.019
1.8
10
13
0.017
2.7
Gain Variation Over Temperature
NOISE FIGURE
3.5
2.5
4.0
RETURN LOSS
Input
Output
15
8
13
15
14
13
dB
dB
OUTPUT
Output Power for 1 dB Compression (P1dB)
15
18
31
70
14.5
17.5
29
13
16
26
70
dBm
dBm
dBm
mA
Saturated (PSAT
)
Output Third-Order Intercept (IP3)2
TOTAL SUPPLY CURRENT
70
1 Adjust VGG between −2 V to 0 V to achieve IDD = 70 mA typical.
2 Measurement taken at POUT/tone = 8 dBm.
Rev. B | Page 3 of 14
HMC1049LP5E
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Table 3. Typical Supply Current vs. VDD
VDD (V)
Rating
10 V
7 V
18 dBm
−2 V to +0.2 V
175°C
IDD1 (mA)
Drain Bias Voltage (VDD
Drain Bias Voltage (RF Out/VDD
RF Input Power
Gate Bias Voltage, VGG
Channel Temperature
Continuous PDISS (T = 85°C)
)
5
6
7
70
70
70
)
1 Adjust VGG to achieve IDD = 70 mA.
3.34 W
ESD CAUTION
(Derate 37.1 mW/°C Above 85°C)
Thermal Resistance (Channel to Ground
Paddle)
26.9°C/W
Temperature
Storage Temperature
Operating Temperature
ESD Sensitivity (HBM)
−65°C to +150°C
−40°C to +85°C
Class 1A
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. B | Page 4 of 14
Data Sheet
HMC1049LP5E
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NC
1
2
3
4
5
6
7
8
24 NC
23
22 GND
V
NC
DD
NC
GND
RFIN
NC
NC
NC
21 RFOUT/V
DD
HMC1049LP5E
20
19
18
NC
NC
NC
TOP VIEW
(Not to Scale)
17 NC
NOTES
1. NC = NO CONNECT. THESE PINS ARE NOT CONNECTED
INTERNALLY; HOWEVER, ALL DATA WAS MEASURED WITH
THESE PINS CONNECTED TO RF/DC GROUND EXTERNALLY.
2. EXPOSED PAD. THE EXPOSED GROUND PADDLE MUST BE
CONNECTED TO RF/DC GROUND.
Figure 2. Pin Configuration Diagram
Table 4. Pin Function Descriptions
Pin No.
Mnemonic Description1
1, 3, 6 to 12, 14, 17 to
20, 23 to 29, 31, 32
NC
No Connect. These pins are not connected internally; however, all data was measured with these pins
connected to RF/dc ground externally (see the Typical Performance Characteristics section for data
plots).
5
2
30
21
RFIN
VDD
ACG1
RF Input. This pin is dc-coupled and matched to 50 Ω.
Power Supply Voltage for the Amplifier. External bypass capacitors (100 pF and 0.01 μF) are required.
Low Frequency Termination. An external bypass capacitor of 100 pF is required.
RFOUT/VDD RF Output/Alternate Power Supply Voltage for the Amplifier. An external bias tee is required when
used as alternative VDD. This pin is dc-coupled and matched to 50 Ω.
15, 16
13
ACG2,
ACG3
VGG
Low Frequency Termination. External bypass capacitors of 100 pF are required.
Gate Control for Amplifier. Adjust the voltage to achieve IDD = 70 mA. External bypass capacitors of
100 pF, 0.01 μF, and 4.7μF are required.
4, 22
0
GND
EP
Ground. Connect Pin 4 and Pin 22 to RF/dc ground.
Exposed Pad. The exposed ground paddle must be connected to RF/dc ground.
1 See the Interface Schematics section for pin interfaces.
Rev. B | Page 5 of 14
HMC1049LP5E
Data Sheet
INTERFACE SCHEMATICS
V
RFIN
ACG2
ACG3
DD
Figure 7. ACG2 and ACG3 Interface
Figure 3. VDD Interface
GND
RFOUT/V
DD
Figure 8. RFOUT/VDD Interface
Figure 4. GND Interface
ACG1
RFOUT/V
DD
RFIN
ACG2
Figure 9. ACG1 Interface
Figure 5. RFIN Interface
V
GG
Figure 6. VGG Interface
Rev. B | Page 6 of 14
Data Sheet
HMC1049LP5E
TYPICAL PERFORMANCE CHARACTERISTICS
Data taken with VDD applied to Pin 2, VDD = 7 V.
20
0
–5
S21
S11
S22
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
15
10
5
–10
–15
–20
–25
–30
0
–5
–10
–15
–20
–25
0
2
4
6
8
10 12 14 16 18 20 22 24
FREQUENCY (GHz)
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (GHz)
Figure 10. Broadband Gain and Return Loss
Figure 13. Output Return Loss vs. Temperature
20
18
16
14
12
10
8
6
5
4
3
2
1
0
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
6
0
2
4
6
8
10
12
14
16
18
20
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 11. Gain vs. Temperature
Figure 14. Noise Figure vs. Temperature
0
–5
6
5
4
3
2
1
0
T
T
T
= +85°C
= +25°C
= –40°C
T
= +85°C
= +25°C
= –40°C
A
A
A
A
T
T
A
A
–10
–15
–20
–25
–30
0
2
4
6
8
10
12
14
16
18
20
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 12. Input Return Loss vs. Temperature
Figure 15. Noise Figure vs. Temperature, Low Frequency
Rev. B | Page 7 of 14
HMC1049LP5E
Data Sheet
20
17
14
11
8
6
5
4
3
2
1
0
T
T
T
= +85°C
= +25°C
= –40°C
V
V
V
= 6V
= 7V
= 8V
A
A
A
DD
DD
DD
5
0
0
0
2
2
2
4
6
8
10
12
14
16
18
20
20
20
0
0
0
2
2
2
4
4
4
6
8
10
12
14
16
18
20
20
20
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 19. P1dB vs. Temperature
Figure 16. Noise Figure vs. VDD
23
20
17
14
11
8
6
5
4
3
2
1
0
T
T
T
= +85°C
= +25°C
= –40°C
I
I
I
= 60mA
= 70mA
= 80mA
A
A
A
DD
DD
DD
4
6
8
10
12
14
16
18
6
8
10
12
14
16
18
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 17. Noise Figure vs. IDD
Figure 20. PSAT vs. Temperature
18
16
14
12
10
8
35
30
25
20
15
10
V
V
V
= 5V
= 6V
= 7V
T
T
T
= +85°C
= +25°C
= –40°C
DD
DD
DD
A
A
A
6
4
2
0
4
6
8
10
12
14
16
18
6
8
10
12
14
16
18
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 21. P1dB vs. VDD
Figure 18. Output IP3 vs. Temperature
Rev. B | Page 8 of 14
Data Sheet
HMC1049LP5E
20
18
16
14
12
10
8
24
20
16
12
8
V
V
V
= 5V
= 6V
= 7V
DD
DD
DD
4
GAIN
6
P
OUT
PAE
4
0
0
2
4
6
8
10
12
14
16
18
20
–10
–8
–6
–4
–2
0
2
4
6
8
10
FREQUENCY (GHz)
INPUT POWER (dBm)
Figure 22. PSAT vs. VDD
Figure 24. Power Compression at 2 GHz
24
20
16
12
8
0
–5
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
–10
–15
–20
–25
–30
–35
–40
–45
4
GAIN
P
OUT
PAE
0
–10
–8
–6
–4
–2
0
2
4
6
8
10
0
2
4
6
8
10
12
14
16
18
20
INPUT POWER (dBm)
FREQUENCY (GHz)
Figure 25. Power Compression at 10 GHz
Figure 23. Reverse Isolation vs. Temperature
Rev. B | Page 9 of 14
HMC1049LP5E
Data Sheet
20
16
12
8
24
18
12
6
4
3
2
1
4
GAIN
GAIN
P
P
OUT
SAT
PAE
NOISE FIGURE
0
0
0
–9
–6
–3
0
3
6
9
50
60
70
80
INPUT POWER (dBm)
I
(mA)
DD
Figure 26. Power Compression at 18 GHz
Figure 28. Gain, PSAT, and Noise Figure vs. IDD at 12 GHz
24
18
12
6
4
3
2
1
0
GAIN
P
SAT
NOISE FIGURE
0
5.0
5.5
6.0
(V)
6.5
7.0
V
DD
Figure 27. Gain, PSAT, and Noise Figure vs. VDD at 12 GHz
Rev. B | Page 10 of 14
Data Sheet
HMC1049LP5E
Data taken with VDD applied to the bias tee at Pin 21.
40
35
30
25
20
15
10
20
S21
S11
S22
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
10
0
–10
–20
–30
0
2
4
6
8
10
12
14
16
18
20
0
4
8
12
16
20
24
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 32. Output IP3 vs. Temperature, VDD = 4 V, Supply to Bias Tee
Figure 29. Broadband Gain and Return Loss, VDD = 4 V, Supply to Bias Tee
20
20
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
18
16
14
12
10
8
17
14
11
8
0
6
0
2
4
6
8
10
12
14
16
18
20
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 33. P1dB vs. Temperature, VDD = 4 V, Supply to Bias Tee
Figure 30. Gain vs. Temperature, VDD = 4 V, Supply to Bias Tee
24
6
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
T
T
T
= +85°C
= +25°C
= –40°C
A
A
A
22
20
18
16
14
12
10
8
5
4
3
2
1
0
0
2
4
6
8
10
12
14
16
18
20
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 34. PSAT vs. Temperature, VDD = 4 V, Supply to Bias Tee
Figure 31. Noise Figure vs. Temperature, VDD = 4 V, Supply to Bias Tee
Rev. B | Page 11 of 14
HMC1049LP5E
Data Sheet
EVALUATION PRINTED CIRCUIT BOARD
J5
J6
U1
J3
V
DD
C1
OUT
IN
C5
C2
H1049
XXXX
J2
J1
U1
J4
C3
C6
V
GG
Figure 35. Evaluation Board Layout
C1
100pF
1
24
23
22
21
20
19
18
17
V
DD
J3
2
3
4
5
6
7
8
V
DD
C5
10nF
C2
100pF
+
C8
4.7µF
HMC1049LP5E
GND
RFIN
OUT
RFOUT/V
J2
DD
IN
J1
PACKAGE
BASE
J4
GND
+
C6
10nF
C3
100pF
C9
4.7µF
C4
100pF
C7
10nF
Figure 36. Evaluation Board Schematic
Rev. B | Page 12 of 14
Data Sheet
HMC1049LP5E
Table 5. List of Materials for Evaluation PCB
The circuit board used in the application should use RF circuit
design techniques. Signal lines should have 50 Ω impedance;
connect the package ground leads and exposed paddle directly
to the ground plane. Use a sufficient number of via holes to
connect the top and bottom ground planes. The evaluation
circuit board shown is available from Analog Devices, Inc.,
upon request.
Item
Description
J1, J2, J5, J6
J3, J4
PCB mount SMA RF connector
DC pins
C1 to C4
C5 to C7
C8, C9
U1
100 pF capacitor, 0402 package
10000 pF capacitor, 0402 package
4.7 μF capacitor, tantalum
HMC1049LP5E
PCB1
600-00541-00-1 evaluation PCB
1 Circuit board material: Rogers 4350 or Arlon 25FR.
Rev. B | Page 13 of 14
HMC1049LP5E
Data Sheet
PACKAGING AND ORDERING INFORMATION
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
5.10
5.00 SQ
4.90
0.30
0.25
0.18
PIN 1
PIN 1
INDICATOR
NS
INDIC ATOR AREA OPTIO
(SEE DETAIL A)
25
32
24
1
0.50
BSC
3.80
3.70 SQ
3.60
EXPOSED
PAD
17
8
16
9
0.45
0.40
0.35
0.20 MIN
TOP VIEW
BOTTOM VIEW
3.50 REF
0.90
0.85
0.80
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-4.
Figure 37. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm and 0.85 mm Package Height
(HCP-32-1)
Dimensions shown in millimeters
ORDERING GUIDE
Moisture Sensitivity
Ordering Package
Package Description Quantity Option
Model1
Temperature Range Lead Finish
Level (MSL) Rating2
HMC1049LP5E
HMC1049LP5ETR
−40°C to +85°C
−40°C to +85°C
100% matte Sn MSL1
100% matte Sn MSL1
32-Lead LFCSP
32-Lead LFCSP,
7”Tape and Reel
HCP-32-1
HCP-32-1
500
EVAL01-HMC1049LP5
Evaluation Board
1 All models are RoHS Compliant Parts.
2 MSL1 rating indicates a maximum peak reflow temperature of 260°C.
©2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D16798-0-5/18(B)
www.analog.com/HMC1049LP5E
Rev. B | Page 14 of 14
相关型号：
©2020 ICPDF网 联系我们和版权申明