FDS6898A [ADI]
Dual 5 A, 20 V Synchronous Step-Down; 双5 A, 20 V同步降压型型号: | FDS6898A |
厂家: | ADI |
描述: | Dual 5 A, 20 V Synchronous Step-Down |
文件: | 总32页 (文件大小:831K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Dual 5 A, 20 V Synchronous Step-Down
Regulator with Integrated High-Side MOSFET
Data Sheet
ADP2325
FEATURES
TYPICAL APPLICATION CIRCUIT
Input voltage: 4.5 V to 20 V
1% output accuracy
V
R
IN
TOP1
C
C
IN1
C1
Integrated 48 mΩ typical high-side MOSFET
Flexible output configuration
Dual output: 5 A/5 A
C
SS1
R
BOT1
R
C1
C
BST1
L1
INTVCC
MODE
C
V
OUT1
INT
Parallel single output: 10 A
SW1
SCFG
TRK2
TRK1
Programmable switching frequency: 250 kHz to 1.2 MHz
External synchronization input with programmable phase
shift or internal clock output
M1
M2
C
OUT1
DL1
PGND
DL2
VDRV
C
DRV
ADP2325
GND
Selectable PWM or PFM mode operation
Adjustable current limit for small inductors
External compensation and soft start
Startup into precharged output
C
OUT2
L2
PGOOD2
V
OUT2
PGOOD1
SYNC
RT
SW2
C
BST2
Supported by ADIsimPowerTM design tool
R
OSC
R
C2
R
BOT2
V
APPLICATIONS
IN
C
C
C
IN2
C2
SS2
Communications infrastructure
Networking and servers
R
TOP2
Industrial and instrumentation
Healthcare and medical
Figure 1.
Intermediate power rail conversion
GENERAL DESCRIPTION
The ADP2325 is a full featured, dual output, step-down dc-to-dc
regulator based on a current mode architecture. The ADP2325
integrates two high-side power MOSFETs and two low-side drivers
for the external N-channel MOSFETs. The two pulse-width mod-
ulation (PWM) channels can be configured to deliver dual 5 A
outputs or a parallel-to-single 10 A output. The regulator operates
from input voltages of 4.5 V to 20 V, and the output voltage can
be as low as 0.6 V.
Independent enable inputs and power-good outputs provide
reliable power sequencing. To enhance system reliability, the device
includes undervoltage lockout (UVLO), overvoltage protection
(OVP), overcurrent protection, and thermal shutdown.
The ADP2325 operates over the −40°C to +125°C junction
temperature range and is available in a 32-lead LFCSP_WQ
package.
100
V
V
= 5.0V
= 3.3V
OUT
OUT
The switching frequency can be programmed from 250 kHz to
1.2 MHz, or it can be synchronized to an external clock to
minimize interference in multirail applications. The dual PWM
channels run 180° out of phase, thereby reducing input current
ripple as well as reducing the size of the input capacitor.
95
90
85
80
75
70
65
60
55
50
The bidirectional synchronization pin can be programmed at
a 60°, 90°, or 120° phase shift to provide for a stackable, multi-
phase power solution.
The ADP2325 can be configured to operate in pulse frequency
modulation (PFM) mode at a light load for higher efficiency or
in forced PWM mode for noise sensitive applications. External
compensation and soft start provide design flexibility.
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
OUTPUT CURRENT (A)
Figure 2. Efficiency vs. Output Current at VIN = 12 V, fSW = 600 kHz
Rev. 0
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2012 Analog Devices, Inc. All rights reserved.
ADP2325
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Overvoltage Protection.............................................................. 19
Undervoltage Lockout ............................................................... 19
Thermal Shutdown .................................................................... 19
Applications Information .............................................................. 20
Input Capacitor Selection.......................................................... 20
Output Voltage Setting .............................................................. 20
Voltage Conversion Limitations............................................... 20
Current-Limit Setting ................................................................ 20
Inductor Selection ...................................................................... 20
Output Capacitor Selection....................................................... 21
Low-Side Power Device Selection............................................ 22
Programming UVLO Input ...................................................... 22
Compensation Components Design ....................................... 22
Design Example.............................................................................. 24
Output Voltage Setting .............................................................. 24
Current-Limit Setting ................................................................ 24
Frequency Setting....................................................................... 24
Inductor Selection ...................................................................... 24
Output Capacitor Selection....................................................... 24
Low-Side MOSFET Selection ................................................... 25
Compensation Components..................................................... 25
Soft Start Time Programming .................................................. 26
Input Capacitor Selection.......................................................... 26
External Components Recommendations.................................. 27
Typical Application Circuits ......................................................... 28
Packaging and Ordering Information ......................................... 32
Outline Dimensions................................................................... 32
Ordering Guide .......................................................................... 32
Applications....................................................................................... 1
Typical Application Circuit ............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications..................................................................................... 4
Absolute Maximum Ratings ....................................................... 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 16
Control Scheme .......................................................................... 16
PWM Mode................................................................................. 16
PFM Mode................................................................................... 16
Precision Enable/Shutdown ...................................................... 16
Separate Input Voltages ............................................................. 16
Internal Regulator (INTVCC).................................................. 16
Bootstrap Circuitry .................................................................... 17
Low-Side Driver.......................................................................... 17
Oscillator ..................................................................................... 17
Synchronization.......................................................................... 17
Soft Start ...................................................................................... 17
Peak Current-Limit and Short-Circuit Protection................. 17
Voltage Tracking......................................................................... 18
Parallel Operation....................................................................... 18
Power Good................................................................................. 19
REVISION HISTORY
2/12—Revision 0: Initial Version
Rev. 0 | Page 2 of 32
Data Sheet
ADP2325
FUNCTIONAL BLOCK DIAGRAM
ADP2325
UVLO
PVIN1
1.2V
EN1_BUF
+
–
A
EN1
CS1
1µA 4µA
BOOST
REGULATOR
+
HICCUP
MODE
OCP
–
SLOPE RAMP1
I1
MAX
BST1
SW1
Σ
COMP1
NFET1
0.6V
DRIVER
I
+
+
SS1
+
SS1
TRK1
FB1
CMP1
–
AMP1
OVP
+
–
SKIP
–
+
CMP1
CONTROL
VDRV
LOGIC
SKIP MODE
THRESHOLD
AND MOSFET
DRIVER WITH
ANTICROSS
PROTECTION
DRIVER
DL1
MODE_BUF
CLK1
0.7V
–
PGND
+
–
LOW-SIDE
CURRENT
SENSE
–
+
0.54V
+
PGOOD1
MODE
CURRENT-
LIMIT
I1
MAX
SELECTION
VDRV
PVIN1
MODE_BUF
CLK1
EN1_BUF
EN2_BUF
INTVCC
GND
5V REGULATOR
SCFG
SYNC
RT
SLOPE RAMP1
CLK2
OSCILLATOR
SLOPE RAMP2
UVLO
PVIN2
1.2V
EN2_BUF
+
–
A
EN2
CS2
1µA 4µA
BOOST
REGULATOR
+
HICCUP
MODE
OCP
–
SLOPE RAMP2
I2
BST2
SW2
MAX
Σ
COMP2
NFET2
0.6V
+
DRIVER
I
SS2
+
SS2
TRK2
FB2
+
CMP2
–
AMP2
+
SKIP
CMP2
–
CONTROL
LOGIC
AND MOSFET
DRIVER WITH
ANTICROSS
PROTECTION
–
+
VDRV
SKIP MODE
THRESHOLD
DRIVER
DL2
OVP
MODE_BUF
CLK2
0.7V
–
+
–
LOW-SIDE
CURRENT
SENSE
–
+
0.54V
+
PGOOD2
CURRENT-
I2
MAX
LIMIT
SELECTION
Figure 3.
Rev. 0 | Page 3 of 32
ADP2325
Data Sheet
SPECIFICATIONS
PVIN1 = PVIN2 = 12 V at TJ = −40°C to +125°C, unless otherwise noted.
Table 1.
Parameters
Symbol Test Conditions/Comments
Min
Typ Max
Unit
POWER INPUT (PVINx PINS)
Power Input Voltage Range
Quiescent Current (PVIN1 + PVIN2)
Shutdown Current (PVIN1 + PVIN2)
PVINx Undervoltage Lockout Threshold
PVINx Rising
VPVIN
IQ
ISHDN
UVLO
4.5
20
5
40
V
mA
μA
MODE = GND, no switching
EN1 = EN2 = GND
3
30
4.2
3.7
4.4
V
V
PVINx Falling
3.5
FEEDBACK (FBx PINS)
FBx Regulation Voltage1
FBx Bias Current
VFB
IFB
PVINx = 4.5 V to 20 V
0.594 0.6
0.606
V
μA
0.01 0.1
ERROR AMPLIFIER (COMPx PINS)
Transconductance
Error Amplifier Source Current
Error Amplifier Sink Current
INTERNAL REGULATOR (INTVCC PIN)
INTVCC Voltage
gm
ISOURCE
ISINK
370
40
45
500 630
μS
μA
μA
65
65
90
85
4.75
80
5
5.25
V
mV
mA
Dropout Voltage
IINTVCC = 30 mA
300
100 120
Regulator Current Limit
SWITCH NODE (SWx PINS)
High-Side On Resistance2
High-Side Peak Current Limit
VBST to VSW = 5 V
RILIM = floating, VBST to VSW = 5 V
RILIM = 47 kΩ, VBST to VSW = 5 V
48
8
4.8
50
80
9.6
6.2
mΩ
A
A
6.4
3.4
Low-Side Negative Current-Limit Threshold
Voltage3
mV
SWx Minimum On Time3
SWx Minimum Off Time3
LOW-SIDE DRIVER (DLx PINS)
Rising Time3
tMIN_ON
tMIN_OFF
130
150
ns
ns
tR
tF
CDL = 2.2 nF, see Figure 23
CDL = 2.2 nF, see Figure 26
20
10
4
ns
ns
Ω
Falling Time3
Sourcing Resistor
Sinking Resistor
6
3
1.4
Ω
OSCILLATOR (RT PIN)
PWM Switching Frequency
PWM Frequency Range
SYNCHRONIZATION (SYNC PIN)
SYNC Input
fSW
ROSC = 100 kΩ
510
250
600 690
kHz
1200 kHz
SYNC configured as input
Synchronization Range
Minimum On Pulse Width
Minimum Off Pulse Width
High Threshold
300
100
100
1.3
1200 kHz
ns
ns
V
Low Threshold
SYNC Output
Frequency on SYNC Pin
Positive Pulse Time
SOFT START (SSx PINS)
SSx Pin Source Current
0.4
4.5
V
SYNC configured as output
fCLKOUT
fSW
kHz
ns
100
2.5
ISS
3.5
μA
Rev. 0 | Page 4 of 32
Data Sheet
ADP2325
Parameters
Symbol Test Conditions/Comments
Min
Typ Max
Unit
TRACKING INPUT (TRKx PINS)
TRKx Input Voltage Range
TRKx-to-FBx Offset Voltage
TRKx Input Bias Current
POWER GOOD (PGOODx PINS)
Power-Good Rising Threshold
Power-Good Hysteresis
Power-Good Deglitch Time
PGOODx Leakage Current
PGOODx Output Low Voltage
ENABLE (ENx PINS)
0
−12
600
+12
100
mV
mV
nA
TRKx = 0 mV to 500 mV
87
90
5
16
0.1
50
93
%
%
From FBx to PGOODx
VPGOOD = 5 V
IPGOOD = 1 mA
Clock cycles
µA
mV
1
100
ENx Rising Threshold
ENx Falling Threshold
ENx Source Current
1.2
1.1
5
1.28
V
V
µA
1.02
1.3
EN voltage below falling
threshold
EN voltage above rising
threshold
1
µA
MODE (MODE PIN)
Input High Voltage
Input Low Voltage
V
V
0.4
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
150
15
°C
°C
1 Tested in a feedback loop that adjusts VFB to achieve a specified voltage on the COMPx pin.
2 Pin-to-pin measurements.
3 Guaranteed by design.
Rev. 0 | Page 5 of 32
ADP2325
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 2.
Parameter
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Rating
PVIN1, PVIN2, EN1, EN2
SW1, SW2
BST1, BST2
FB1, FB2, SS1, SS2, COMP1, COMP2,
PGOOD1, PGOOD2, TRK1, TRK2, SCFG,
SYNC, RT, MODE
−0.3 V to +22 V
−1 V to +22 V
VSW + 6 V
Boundary Condition
θJA is measured using natural convection on a JEDEC 4-layer
board, and the exposed pad is soldered to the printed circuit
board (PCB) with thermal vias.
−0.3 V to +6 V
INTVCC, VDRV, DL1, DL2
PGND to GND
−0.3 V to +6 V
−0.3 V to +0.3 V
Table 3. Thermal Resistance
Package Type
θJA
Unit
Temperature Range
Operating (Junction)
Storage
32-Lead LFCSP_WQ
32.7
°C/W
−40°C to +125°C
−65°C to +150°C
JEDEC J-STD-020
ESD CAUTION
Soldering Conditions
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 6 of 32
Data Sheet
ADP2325
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PGOOD1
SCFG
SYNC
GND
INTVCC
RT
1
2
3
4
5
6
7
8
24 SW1
23
22 DL1
BST1
ADP2325
TOP VIEW
(Not to Scale)
21 PGND
20
19
VDRV
DL2
MODE
PGOOD2
18 BST2
17 SW2
NOTES
1. THE EXPOSED PAD SHOULD BE SOLDERED
TO AN EXTERNAL GND PLANE.
Figure 4. Pin Configuration (Top View)
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1
2
PGOOD1
SCFG
Power-Good Output (Open Drain) for Channel 1. A pull-up resistor of 10 kΩ to 100 kΩ is recommended.
Synchronization Configuration Input. The SCFG pin configures the SYNC pin as an input or an output. Connect
SCFG to INTVCC to configure SYNC as an output. Connecting a pull-down resistor to GND configures SYNC as an
input with various phase shift degrees.
3
SYNC
Synchronization. This pin can be configured as an input or an output. When configured as an output, it provides a
clock at the switching frequency. When configured as an input, this pin accepts an external clock to which the
regulators are synchronized. The phase shift is configured by SCFG. Note that when SYNC is configured as an input,
the PFM mode is disabled and the device works in continuous conduction mode (CCM) only.
4
5
GND
INTVCC
Analog Ground. Connect to the ground plane.
Internal 5 V Regulator Output. The IC control circuits are powered from this voltage. Place a 1 μF ceramic capacitor
between INTVCC and GND.
6
7
RT
MODE
Connect a resistor between RT and GND to program the switching frequency from 250 kHz to 1.2 MHz.
Mode Selection. When this pin is connected to INTVCC, the PFM mode is disabled and the regulator works only in
CCM. When this pin is connected to ground, the PFM mode is enabled. If the low-side device is a diode, the MODE
pin must be connected to ground.
8
9
PGOOD2
FB2
Power-Good Output (Open Drain) for Channel 2. A pull-up resistor of 10 kΩ to 100 kΩ is recommended.
Feedback Voltage Sense Input for Channel 2. Connect FB2 to a resistor divider from the Channel 2 output voltage,
V
OUT2. Connect FB2 to INTVCC for parallel applications.
10
COMP2
SS2
Error Amplifier Output for Channel 2. Connect an RC network from COMP2 to GND. Connect COMP1 and COMP2
together for parallel applications.
Soft Start Control for Channel 2. To program the soft start time, connect a capacitor from SS2 to GND. For parallel
applications, SS2 remains open.
11
12
TRK2
EN2
Tracking Input for Channel 2. To track a master voltage, connect this pin to a resistor divider from the master
voltage. If the tracking function is not used, connect TRK2 to INTVCC.
Enable Pin for Channel 2. An external resistor divider can be used to set the turn-on threshold. When not using the
enable pin, connect EN2 to PVIN2.
13
14, 15
PVIN2
Power Input for Channel 2. Connect PVIN2 to the input power source, and connect a bypass capacitor between
PVIN2 and ground.
16, 17
18
19
SW2
BST2
DL2
Switch Node for Channel 2.
Supply Rail for the Gate Drive of Channel 2. Place a 0.1 ꢀF capacitor between SW2 and BST2.
Low-Side Gate Driver Output for Channel 2. Connect a resistor between DL2 and PGND to program the current-
limit threshold of Channel 2.
20
21
22
VDRV
PGND
DL1
Low-Side Driver Supply Input. Connect VDRV to INTVCC. Place a 1 ꢀF ceramic capacitor between the VDRV pin and PGND.
Driver Power Ground. Connect to the source of the synchronous N-channel MOSFET.
Low-Side Gate Driver Output for Channel 1. Connect a resistor between DL1 and PGND to program the current-
limit threshold of Channel 1.
23
BST1
Supply Rail for the Gate Drive of Channel 1. Place a 0.1 ꢀF capacitor between SW1 and BST1.
Rev. 0 | Page 7 of 32
ADP2325
Data Sheet
Pin No. Mnemonic Description
24, 25
26, 27
SW1
PVIN1
Switch Node for Channel 1.
Power Input for Channel 1. These pins are the power inputs for Channel 1 and provide power for the internal
regulator. Connect to the input power source and connect a bypass capacitor between PVIN1 and ground.
28
29
EN1
Enable Pin for Channel 1. An external resistor divider can be used to set the turn-on threshold. When not using
the enable pin, connect EN1 to PVIN1.
Tracking Input for Channel 1. To track a master voltage, connect this pin to a resistor divider from the master
voltage. If the tracking function is not used, connect TRK1 to INTVCC.
TRK1
30
31
SS1
COMP1
Soft Start Control for Channel 1. To program the soft start time, connect a capacitor from SS1 to GND.
Error Amplifier Output for Channel 1. Connect an RC network from COMP1 to GND. Connect COMP1 and COMP2
together for parallel applications.
32
N/A1
FB1
EP
Feedback Voltage Sense Input for Channel 1. Connect FB1 to a resistor divider from the Channel 1 output voltage, VOUT1
Exposed Pad. Solder the exposed pad to an external GND plane.
.
1 N/A means not applicable.
Rev. 0 | Page 8 of 32
Data Sheet
ADP2325
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VIN = 12 V, VOUT = 3.3 V, L = 2.2 µH, COUT = 2 × 100 µF, fSW = 600 kHz, unless otherwise noted.
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
55
50
INDUCTOR: FDVE1040-4R7M
MOSFET: FDS8880
INDUCTOR: FDVE1040-2R2M
MOSFET: FDS8880
V
V
V
V
V
V
= 5.0V
= 3.3V
= 2.5V
= 1.8V
= 1.5V
= 1.2V
OUT
OUT
OUT
OUT
OUT
OUT
V
V
V
V
V
V
= 5.0V
= 3.3V
= 2.5V
= 1.8V
= 1.5V
= 1.2V
OUT
OUT
OUT
OUT
OUT
OUT
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 5. Efficiency at VIN = 12 V, fSW = 600 kHz, FPWM
Figure 8. Efficiency at VIN = 12 V, fSW = 300 kHz, FPWM
100
100
INDUCTOR: FDVE1040-4R7M
MOSFET: FDS8880
INDUCTOR: FDVE1040-2R2M
MOSFET: FDS8880
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
V
V
V
V
= 5.0V, FPWM
V
V
V
V
= 5.0V, FPWM
= 3.3V, FPWM
= 5.0V, PFM
= 3.3V, PFM
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
= 3.3V, FPWM
= 5.0V, PFM
= 3.3V, PFM
0.01
0.1
OUTPUT CURRENT (A)
1
0.01
0.1
OUTPUT CURRENT (A)
1
Figure 6. Efficiency at VIN = 12 V, fSW = 600 kHz, FPWM and PFM
Figure 9. Efficiency at VIN = 12 V, fSW = 300 kHz, FPWM and PFM
100
100
INDUCTOR: FDVE1040-1R5M
MOSFET: FDS8880
INDUCTOR: FDVE1040-4R7M
MOSFET: FDS8880
95
95
90
85
80
75
70
65
90
85
80
75
70
65
V
V
V
V
V
V
= 5.0V
= 3.3V
= 2.5V
= 1.8V
= 1.5V
= 1.2V
OUT
OUT
OUT
OUT
OUT
OUT
V
V
V
V
V
= 3.3V
= 2.5V
= 1.8V
= 1.5V
= 1.2V
OUT
OUT
OUT
OUT
OUT
60
55
50
60
55
50
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 10. Efficiency at VIN = 18 V, fSW = 300 kHz, FPWM
Figure 7. Efficiency at VIN = 5 V, fSW = 600 kHz, FPWM
Rev. 0 | Page 9 of 32
ADP2325
Data Sheet
40
3.10
3.05
3.00
2.95
2.90
2.85
2.80
T
J
= –40°C
= +25°C
= +125°C
T
T
T
= –40°C
= +25°C
= +125°C
J
J
J
T
J
T
J
35
30
25
20
15
10
4
6
8
10
12
(V)
14
16
18
20
4
6
8
10
12
(V)
14
16
18
20
V
V
IN
IN
Figure 11. Shutdown Current vs. VIN
Figure 14. Quiescent Current vs. VIN
4.5
1.30
1.25
1.20
1.15
1.10
1.05
1.00
RISING
RISING
FALLING
FALLING
4.4
4.3
4.2
4.1
4.0
3.9
3.8
3.7
3.6
3.5
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100 120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 12. UVLO Threshold vs. Temperature
Figure 15. EN Threshold vs. Temperature
5.30
5.25
5.20
5.15
5.10
5.05
5.00
4.95
4.90
4.85
4.80
4.75
4.70
1.10
1.08
1.06
1.04
1.02
1.00
0.98
0.96
0.94
0.92
0.90
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 13. EN Source Current vs. Temperature at VEN = 1.5 V
Figure 16. EN Source Current vs. Temperature at VEN = 1 V
Rev. 0 | Page 10 of 32
Data Sheet
ADP2325
604
603
602
601
600
599
598
597
596
600
580
560
540
520
500
480
460
440
420
400
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 17. Feedback Voltage vs. Temperature
Figure 20. Transconductance (gm) vs. Temperature
660
5.4
5.2
5.0
4.8
4.6
4.4
4.2
4.0
R
= 100kΩ
OSC
640
620
600
580
560
540
–40
–20
0
20
40
60
80
100
120
4
6
8
10
12
(V)
14
16
18
20
TEMPERATURE (°C)
V
IN
Figure 18. Frequency vs. Temperature
Figure 21. INTVCC Voltage vs. VIN
80
75
70
65
60
55
50
45
40
35
30
4.5
4.3
4.1
3.9
3.7
3.5
3.3
3.1
2.9
2.7
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 19. MOSFET RDSON vs. Temperature
Figure 22. SSx Pin Source Current vs. Temperature
Rev. 0 | Page 11 of 32
ADP2325
Data Sheet
SW
SW
1
1
DL
DL
2
2
CH1 5V
CH2 2V
M20ns
A CH1
4V
CH1 5V
CH2 2V
M20ns
40.4%
A CH2
4.04V
T
40.4%
T
Figure 23. Low-Side Driver Rising Edge Waveform, CDL = 2.2 nF
Figure 26. Low-Side Driver Falling Edge Waveform, CDL = 2.2 nF
6.5
6.0
5.5
5.0
4.5
4.0
3.5
9.5
9.0
8.5
8.0
7.5
7.0
6.5
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 24. Peak Current-Limit Threshold vs. Temperature, RILIM = Floating
Figure 27. Peak Current-Limit Threshold vs. Temperature, RILIM = 47 kΩ
V
(AC)
V
(AC)
OUT
OUT
1
1
I
L
I
L
4
2
SW
SW
4
2
B
B
W
CH2 10V
CH4 1A Ω
CH1 10mV
CH2 10V
CH4 2A Ω
M 1µs
42.6%
A CH2
4.6V
CH1 10mV
M 1µs
47.2%
A CH2
8.4V
W
T
T
Figure 25. Continuous Conduction Mode (CCM)
Figure 28. Discontinuous Conduction Mode (DCM)
Rev. 0 | Page 12 of 32
Data Sheet
ADP2325
V
(AC)
OUT
SW1
1
4
2
1
2
SW2
I
L
I
I
L1
L2
SW
4
B
CH2 10V
CH4 1A Ω
M 1µs
50.4%
A CH2
5.6V
CH1 100mV
M 1ms
47.2%
A CH2
8.4V
CH1 10V
CH3 2A
CH2 10V
CH4 2A
W
B
B
W
Ω
Ω
T
T
W
Figure 29. Power Saving Mode
Figure 32. Dual Phase, Single Output, VOUT = 3.3 V, IOUT = 10 A
EN
EN
3
3
V
OUT
V
OUT
1
2
1
2
PGOOD
PGOOD
I
I
L
OUT
4
4
B
B
CH1 2V
CH3 10V
CH2 5V
CH4 2A Ω
M 1ms
20.2%
A CH3
3.4V
CH1 2V
CH3 10V
CH2 5V
CH4 5A Ω
M 1ms
20.2%
A CH3
3.4V
W
W
T
T
Figure 33. Soft Start with Precharged Output
Figure 30. Soft Start with Full Load
V
(AC)
V
(AC)
OUT
OUT
1
1
V
IN
I
OUT
4
3
B
B
B
CH1 100mV
M 200µs
20.2%
A CH4
3.4A
CH1 20mV
CH3 5V
M 400µs
73.8%
A CH3
11.5V
W
W
W
CH4 2A
Ω
T
T
Figure 31. Load Transient Response, 1 A to 4 A
Figure 34. Line Transient Response, VIN from 8 V to 14 V, IOUT = 5 A
Rev. 0 | Page 13 of 32
ADP2325
Data Sheet
V
V
OUT
OUT
1
2
1
2
4
SW
SW
I
I
L
L
4
B
B
CH2 10V
CH4 5A Ω
CH1 2V
CH1 2V
M 10ms
19.8%
A CH1
1.32V
CH2 10V
CH4 5A Ω
M 10ms
60.2%
A CH1
1.32V
W
W
T
T
Figure 35. Output Short
Figure 38. Output Short Recovery
SYNC
SYNC
3
3
SW1
SW1
1
2
1
2
SW2
SW2
CH1 10V
CH3 5V
CH2 10V
M 1µs
50.4%
A CH3
2.8V
CH1 10V
CH3 5V
CH2 10V
M 1µs
50.4%
A CH3
2.8V
T
T
Figure 36. External Synchronization with 60° Phase Shift
Figure 39. External Synchronization with 90° Phase Shift
SYNC
SYNC
3
3
SW1
SW1
1
2
1
2
SW2
SW2
CH1 10V
CH3 5V
CH2 10V
M 1µs
50.0%
A CH3
2.5V
CH1 10V
CH3 5V
CH2 10V
M 1µs
50.4%
A CH3
2.8V
T
T
Figure 37. External Synchronization with 120° Phase Shift
Figure 40. SYNC Pin Configured as Output
Rev. 0 | Page 14 of 32
Data Sheet
ADP2325
V
MASTER
V
MASTER
V
SLAVE
V
SLAVE
2
2
B
B
B
B
W
CH1 1V
CH1 1V
CH2 1V
M 1ms
50.4%
A CH1
1.56V
CH2 1V
M 1ms
49.8%
A CH1
1.58V
W
W
W
T
T
Figure 41. Coincident Tracking
Figure 43. Ratiometric Tracking
6
6
V
= 1.2V
= 3.3V
= 500kHz
V
V
= 1.2V
OUT1
OUT2
OUT1
OUT2
V
f
= 3.3V
f
= 500kHz
SW
SW
5
4
3
2
1
0
5
4
3
2
1
0
CH2 = 0A
CH2 = 1A
CH2 = 2A
CH2 = 3A
CH2 = 4A
CH2 = 5A
CH1 = 0A
CH1 = 1A
CH1 = 2A
CH1 = 3A
CH1 = 4A
CH1 = 5A
25
40
55
70
85
100
25
40
55
70
85
100
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
Figure 42. Thermal Derating Performance at 110°C Case Temperature Based
on ADP2325-EVALZ Board
Figure 44. Thermal Derating Performance at 110°C Case Temperature Based
on ADP2325-EVALZ Board
Rev. 0 | Page 15 of 32
ADP2325
Data Sheet
THEORY OF OPERATION
The ADP2325 is a full featured, dual output, step-down dc-to-dc
regulator based on a current mode architecture. It integrates two
high-side power MOSFETs and two low-side drivers for external
MOSFETs. The ADP2325 is designed for high performance
applications that require high efficiency and design flexibility.
PRECISION ENABLE/SHUTDOWN
The ADP2325 has two independent enable pins (EN1 and
EN2), one for each channel. The ENx pin has an internal pull-
down current source of 5 μA to provide a default turn-off whenever
an ENx pin is open.
The ADP2325 can operate with an input voltage from 4.5 V
to 20 V and can regulate the output voltage to as low as 0.6 V.
Additional features for flexible design include programmable
switching frequency, programmable soft start, external compen-
sation, independent enable inputs, and power-good outputs.
When the voltage on the EN1 or EN2 pin exceeds 1.2 V (typical),
Channel 1 (per the EN1 pin) or Channel 2 (per the EN2 pin) is
enabled and the internal pull-down current source at the EN1
or EN2 pin is reduced to 1 μA, which allows the user to program
the UVLO lockout of the input voltage.
CONTROL SCHEME
When the voltage on the EN1 or EN2 pin drops below 1.1 V
(typical), Channel 1 or Channel 2 turns off. When EN1 and
EN2 are both below 1.1 V, all of the internal circuits turn off
and the device enters the shutdown mode.
The ADP2325 uses a fixed frequency, current mode PWM control
architecture during medium to full loads, but shifts to a power
save mode (PFM) at light loads when the PFM mode is enabled.
The power save mode reduces switching losses and boosts effi-
ciency under light loads.
SEPARATE INPUT VOLTAGES
The ADP2325 supports two separate input voltages. This means
that the PVIN1 and PVIN2 voltages can be connected to two
different supply voltages. In these types of applications, because
the PVIN1 voltage provides the power supply for the internal regu-
lator and control circuitry, the PVIN1 voltage must be above the
UVLO voltage before the PVIN2 voltage begins to rise.
When operating in the fixed frequency PWM mode, the duty
cycle of the integrated N-channel MOSFET (referred to inter-
changeably as NFET or MOSFET) is adjusted, this, in turn,
regulates the output voltage. When the device operates in
power save mode, the switching frequency is adjusted to regu
late the output voltage.
This feature allows for a cascading supply operation, as shown in
Figure 45 where PVIN2 is sourced from the Channel 1 output.
In this configuration, the Channel 1 output voltage needs to be high
enough to maintain Channel 2 in regulation, and the Channel 1
output voltage must be higher than the input voltage UVLO
threshold.
PWM MODE
In PWM mode, the ADP2325 operates at a fixed frequency
set by an external resistor. At the start of each oscillator cycle, the
high-side NFET turns on, placing a positive voltage across the
inductor. The inductor current increases until the current sense
signal crosses the peak inductor current threshold, turning off the
high-side NFET and turning on the low-side NFET (diode). This
places a negative voltage across the inductor, causing a reduction in
the inductor current. The low-side NFET (diode) stays on for the
remainder of the cycle or until the inductor current reaches zero.
V
PVIN1
PVIN2
IN
ADP2325
L1
L2
V
V
OUT2
OUT1
SW1
SW2
PFM MODE
To enable the PFM mode, pull the MODE pin to ground. When
the COMPx voltage is below the PFM threshold voltage, the
device enters the PFM mode.
C
C
OUT2
OUT1
M2
M1
DL1
DL2
PGND
When the device enters the PFM mode, it monitors the FBx voltage
to regulate the output voltage. Because the high-side and low-
side NFETs are turned off, the load current discharges the output
capacitor causing the output voltage to drop. When the FBx
voltage drops below 0.605 V, the device starts switching and the
output voltage increases as the output capacitor is charged by the
inductor current. When the FBx voltage exceeds 0.62 V, the device
turns off both the high-side and low-side NFETs until the FBx
voltage drops to 0.605 V. In the PFM mode, the output voltage
ripple is larger than the ripple in the PWM mode.
Figure 45. Cascading Supply Operation
INTERNAL REGULATOR (INTVCC)
The internal regulator provides a stable voltage supply for the
internal control circuits and a bias voltage for the low-side gate
drivers. It is recommended that a 1 μF ceramic capacitor be placed
between INTVCC and GND. The internal regulator also includes a
current-limit circuit for protection.
The internal regulator is active when either of the channels is
enabled. The PVIN1 pin provides power for the internal regulator,
which is used by both channels.
Rev. 0 | Page 16 of 32
Data Sheet
ADP2325
When the SYNC pin is configured as an input, the ADP2325 syn-
chronizes to the external clock that is applied to the SYNC pin, and
the internal clock must be programmed lower than the external
clock. The phase shift can be programmed by the SCFG pin.
BOOTSTRAP CIRCUITRY
The ADP2325 integrates the boot regulators to provide the gate
drive voltage for the high-side NFETs. The regulators generate
5 V bootstrap voltages between the BSTx and the SWx pins.
When working in synchronization mode, the ADP2325 disables
the PFM mode and works only in the CCM mode.
It is recommended that an X7R or X5R, 0.1 μF ceramic
capacitor be placed between the BSTx and the SWx pins.
SOFT START
LOW-SIDE DRIVER
Use the SSx pins to program the soft start time. Place a capacitor
between SSx and GND; an internal current charges this capacitor
to establish the soft start ramp. The soft start time can be calculated
using the following equation:
The DLx pin provides the gate drive for the low-side N-channel
MOSFET. Internal circuitry monitors the gate driver signal to
ensure break-before-make switching to prevent crossconduction.
The VDRV pin provides the power supply to the low-side drivers.
It is limited to a 5.5 V maximum input; placing a 1 μF ceramic
capacitor close to this pin is recommended.
0.6 VCSS
t
SS
ISS
OSCILLATOR
where:
SS is the soft start capacitance.
SS is the soft start pull-up current (3.5 μA).
C
I
A resistor from RT to GND programs the switching frequency
according to the following equation:
If the output voltage is precharged prior to power-up, the ADP2325
prevents the low-side MOSFET from turning on until the soft
start voltage exceeds the voltage on the FBx pin.
60,000
f
SW [kHz] =
ROSC[kΩ]
A 200 kꢀ resistor sets the frequency to 300 kHz, and a 100 kꢀ
resistor sets the frequency to 600 kHz. Figure 46 shows the
typical relationship between fSW and ROSC
During soft start, the ADP2325 uses frequency foldback to
prevent output current runaway. The switching frequency is
reduced according to the voltage present at the FBx pin, which
allows more time for the inductor to discharge. The correlation
between the switching frequency and the FBx pin voltage is listed
in Table 6.
.
1200
1100
1000
900
800
700
600
500
400
300
200
Table 6. FBx Pin Voltage and Switching Frequency
FBx Pin Voltage
Switching Frequency
VFB ≥ 0.4 V
fSW
0.4 V > VFB ≥ 0.2 V
VFB < 0.2 V
1/2 fSW
1/4 fSW
PEAK CURRENT-LIMIT AND SHORT-CIRCUIT
PROTECTION
The ADP2325 uses a peak current-limit protection circuit to
prevent current runaway. Place a resistor between DLx and PGND
to program the peak current-limit value, as listed in Table 7.
The programmable peak current-limit threshold feature allows
for the use of a small size inductor for low current applications.
50
70
90
110 130 150 170 190 210 230 250
(kΩ)
R
OSC
Figure 46. fSW vs. ROSC
SYNCHRONIZATION
The SYNC pin can be configured as an input or an output by
setting the SCFG pin, as shown in Table 5.
Table 7. Peak Current-Limit Threshold Setting
RILIM
Peak Current-Limit Threshold
Table 5. SCFG Configuration
Floating
47 kΩ
8 A
4.8 A
SCFG
SYNC
Output
Input
Input
Input
Phase Shift
INTVCC
GND
0°
The ADP2325 uses hiccup mode for overcurrent protection.
When the peak inductor current reaches the current-limit
threshold, the high-side MOSFET turns off and the low-side
driver turns on until the next cycle while the overcurrent counter
is incremented.
90°
120°
60°
180 kΩ to GND
100 kΩ to GND
When the SYNC pin is configured as an output, it generates a
clock with a frequency that is equal to the internal switching
frequency.
Rev. 0 | Page 17 of 32
ADP2325
Data Sheet
If the overcurrent counter reaches 10, or if the FBx pin voltage
falls to 0.2 V after the soft start, the device enters hiccup mode.
During this mode, the high-side MOSFET and low-side driver are
both turned off. The device remains in this mode for seven soft
start cycles and then attempts to restart from soft start. If the
current-limit fault is cleared, the device resumes normal
operation; otherwise, it reenters hiccup mode.
Coincident Tracking
A common application is coincident tracking, which is shown in
Figure 48. Coincident tracking limits the slave output voltage to
be the same as the master voltage until it reaches regulation. To
enable coincident tracking, set RTRK_TOP = RTOP and RTRK_BOT = RBOT
.
V
V
MASTER
The ADP2325 provides a negative current limit. When the low-side
FET voltage exceeds the negative current-limit threshold voltage
(50 mV typical), the low-side FET turns off immediately for the
remainder of this cycle. Both the high-side and low-side FETs
turn off until the next cycle.
SLAVE
TIME
In some cases, the input voltage (PVIN) ramp rate is too slow
or the output capacitor is too large to support the set regulation
voltage during the soft start, causing the device to enter the
hiccup mode. To prevent such cases, use a resistor divider at the
ENx pin to program the UVLO of the input voltage or use a
longer soft start time.
Figure 48. Coincident Tracking
Ratiometric Tracking
In ratiometric tracking, the slave output voltage is limited to a frac-
tion of the master voltage. In this application, the slave and master
voltages reach their final values at the same time (see Figure 49).
V
MASTER
VOLTAGE TRACKING
The ADP2325 has a tracking input, TRKx, that allows the output
voltage to track an external (master) voltage. Voltage tracking
allows power sequencing applicable for FPGAs, DSPs, and ASICs,
which may require a power sequence between the core and the I/O
voltages.
V
SLAVE
TIME
Figure 49. Ratiometric Tracking
The internal error amplifier includes three positive inputs: the
internal reference voltage, the soft start voltage, and the tracking
input voltage. The error amplifier regulates the feedback voltage
to the lowest of the three voltages. To track a master voltage,
connect the TRKx pin to a resistor divider from the master
voltage, as shown in Figure 47.
The ratio of the slave output voltage to the master voltage is a
function of the two dividers, as follows:
RTOP
RBOT
1+
VSLAVE
VMASTER
=
RTRK _TOP
RTRK _ BOT
V
MASTER
1+
R
TRK_TOP
V
SLAVE
The final TRKx pin voltage must be higher than 0.54 V. If the
tracking function is not used, connect the TRKx pin to INTVCC.
TRKx
SWx
ADP2325
PARALLEL OPERATION
R
R
R
TRK_BOT
TOP
The ADP2325 supports a 2-phase parallel operation to provide
a single output of 10 A. To configure the ADP2325 as a 2-phase
single output
FBx
BOT
1. Connect the FB2 pin to INTVCC, thereby disabling the
Channel 2 error amplifier.
Figure 47. Voltage Tracking
2. Connect COMP1 to COMP2 and connect EN1 to EN2.
3. Use SS1 to set the soft start time and keep SS2 open.
During parallel operation, the voltages of PVIN1 and PVIN2
should be the same.
Rev. 0 | Page 18 of 32
Data Sheet
ADP2325
driver turn off until the voltage at the FBx pin is reduced to
0.63 V, at which time the ADP2325 resumes normal operation.
POWER GOOD
The power-good (PGOODx) pin is an active high, open-drain
output that indicates whether the regulator output voltage is
within regulation. Logic high indicates that the voltage at the
FBx pin (and, therefore, the output voltage) is above 90% of the
reference voltage. Logic low indicates that the voltage at the FBx
pin (and, therefore, the output voltage) is below 85% of the
reference voltage. There is a 16-cycle deglitch time between FBx
and PGOODx.
UNDERVOLTAGE LOCKOUT
The UVLO threshold is 4.2 V with 0.5 V hysteresis to prevent
power-on glitches on the device. When the PVIN1 or PVIN2
voltage rises above 4.2 V, Channel 1 or Channel 2 is enabled and the
soft start period initiates. When either PVIN1 or PVIN2 drops
below 3.7 V, it turns off Channel 1 or Channel 2, respectively.
THERMAL SHUTDOWN
OVERVOLTAGE PROTECTION
In the event that the ADP2325 junction temperature exceeds
150°C, the thermal shutdown circuit turns off the regulator. A
15°C hysteresis is included so that the ADP2325 does not recover
from thermal shutdown until the on-chip temperature drops
below 135°C. Upon recovery, soft start initiates prior to normal
operation.
The ADP2325 provides an OVP feature to protect the system
against an output shorting to a higher voltage supply or for
when a strong load transient occurs. If the feedback voltage
increases to 0.7 V, the internal high-side MOSFET and low-side
Rev. 0 | Page 19 of 32
ADP2325
Data Sheet
APPLICATIONS INFORMATION
The maximum output voltage for a given input voltage and
INPUT CAPACITOR SELECTION
switching frequency is also limited by the minimum off time
and the maximum duty cycle. The minimum off time is typically
150 ns and the maximum duty is typically 90% in the ADP2325.
The input decoupling capacitor attenuates high frequency noise
on the input and acts as an energy reservoir. This capacitor should
be a ceramic capacitor in the range of 10 µF to 47 µF and must
be placed close to the PVINx pin. The loop composed of this
input capacitor, high-side NFET, and low-side NFET must be
kept as small as possible. The voltage rating of the input capacitor
must be greater than the maximum input voltage. Ensure that the
rms current rating of the input capacitor is larger than that
expressed in following equation:
The maximum output voltage that is limited by the minimum off
time at a given input voltage and frequency can be calculated
using the following equation:
V
OUT_MAX = VIN × (1 − tMIN_OFF × fSW) − (RDSON1 − RDSON2) ×
OUT_MAX × (1 − tMIN_OFF × fSW) − (RDSON2 + RL) × IOUT_MAX
where:
OUT_MAX is the maximum output voltage.
MIN_OFF is the minimum off time.
I
ICIN
= IOUT × D×
(1− D
)
V
t
_rms
OUTPUT VOLTAGE SETTING
IOUT_MAX is the maximum output current.
The output voltage of the ADP2325 can be set by an external
resistor divider using the following equation:
The maximum output voltage that is limited by the maximum
duty cycle at a given input voltage can be calculated using the
following equation:
RTOP
RBOT
VOUT = 0.6× 1+
VOUT_MAX = DMAX × VIN
where DMAX is the maximum duty cycle.
To limit output voltage accuracy degradation due to FBx pin
bias current (0.1 µA maximum) to less than 0.5% (maximum),
ensure that RBOT is less than 30 kΩ. Table 8 provides the recom-
mended resistor divider for various output voltage options.
As the previous equations demonstrate, reducing the switching
frequency alleviates the minimum on time and minimum off time
limitation.
Table 8. Resistor Divider for Various Output Voltages
CURRENT-LIMIT SETTING
VOUT (V)
RTOP
,
1% (kΩ)
RBOT, 1% (kΩ)
The ADP2325 has two selectable current-limit thresholds. Make
sure that the selected current-limit value is larger than the peak
1.0
10
15
1.2
10
10
current of the inductor, IPEAK
.
1.5
15
10
INDUCTOR SELECTION
1.8
20
10
The inductor value is determined by the operating frequency,
input voltage, output voltage, and inductor ripple current. Using
a small inductor provides faster transient response but degrades
efficiency due to larger inductor ripple current, whereas a large
inductor value provides smaller ripple current and better effi-
ciency but results in a slower transient response. Thus, there is a
trade-off between the transient response and efficiency. As a
guideline, the inductor ripple current, ΔIL, is typically set to
one-third of the maximum load current. The inductor value can
be calculated by using the following equation:
2.5
3.3
5.0
47.5
10
22
15
2.21
3
VOLTAGE CONVERSION LIMITATIONS
The minimum output voltage for a given input voltage and
switching frequency is limited by the minimum on time. The
minimum on time of the ADP2325 is typically 130 ns. The
minimum output voltage in CCM mode at a given input voltage
and frequency can be calculated using the following equation:
V
t
OUT_MIN = VIN × tMIN_ON × fSW − (RDSON1 − RDSON2) × IOUT_MIN
MIN_ON × fSW − (RDSON2 + RL) × IOUT_MIN
where:
OUT_MIN is the minimum output voltage.
MIN_ON is the minimum on time.
×
(
VIN
−
VOUT
)
×D
L
=
∆
IL × fSW
where:
V
t
I
V
V
IN is the input voltage.
OUT is the output voltage.
ΔIL is the inductor ripple current.
SW is the switching frequency.
OUT_MIN is the minimum output current.
SW is the switching frequency.
DSON1 is the high-side MOSFET on resistance.
DSON2 is the low-side MOSFET on resistance.
f
R
R
f
D is the duty cycle.
VOUT
D =
RL is the series resistance of the output inductor.
VIN
Rev. 0 | Page 20 of 32
Data Sheet
ADP2325
The ADP2325 uses adaptive slope compensation in the current
loop to prevent subharmonic oscillations when the duty cycle is
larger than 50%. The internal slope compensation limits the min-
imum inductor value.
OUTPUT CAPACITOR SELECTION
The output capacitor selection affects both the output voltage
ripple and the loop dynamics of the regulator. For example,
during load step transient on the output, when the load is sud-
denly increased, the output capacitor supplies the load until the
control loop can ramp up the inductor current, which causes an
undershoot of the output voltage. Use the following equation to
calculate the output capacitance that is required to meet the voltage
droop requirement:
For a duty cycle that is larger than 50%, the minimum inductor
value is determined by the following equation:
VOUT
1 D
2 fSW
The inductor peak current is calculated by
K
UV ISTEP 2 L
VIN VOUT VOUT_UV
COUT_UV
IL
IPEAK IOUT
2
2
where:
ΔISTEP is the load step.
ΔVOUT_UV is the allowable undershoot on the output voltage.
The saturation current of the inductor must be larger than the
peak inductor current. For the ferrite core inductors with a
quick saturation characteristic, the saturation current rating of the
inductor should be higher than the current-limit threshold of the
switch to prevent the inductor from entering saturation.
KUV is a factor, typically setting KUV = 2.
Another example is when a load is suddenly removed from the
output and the energy stored in the inductor rushes into the
output capacitor, which causes the output to overshoot. The
output capacitance required to meet the overshoot requirement
can be calculated using the following equation:
The rms current of the inductor can be calculated by
2
IL
12
IRMS
IOUT 2
K
OV ISTEP2 L
Shielded ferrite core materials are recommended for low core
loss and low EMI.
COUT_OV
2 VOUT
2
VOUT VOUT _OV
where:
Table 9. Recommended Inductors
ΔVOUT_OV is the allowable overshoot on the output voltage.
KOV is a factor, typically setting KOV = 2.
Value ISAT
(A)
IRMS
(A)
DCR
(mΩ)
Vendor
Part No.
(μH)
0.8
1.5
2.2
3.3
4.7
6.8
1.5
2.2
3.3
4.7
6.8
1.1
1.8
3.0
4.7
6.2
The output ripple is determined by the ESR of the output
capacitor and its capacitance value. Use the following equation to
select a capacitor that can meet the output ripple requirements:
Sumida
CDRH105RNP-0R8N
CDRH105RNP-1R5N
CDRH105RNP-2R2N
CDRH105RNP-3R3N
CDRH105RNP-4R7N
CDRH105RNP-6R8N
MSS1048-152NL
MSS1048-222NL
MSS1048-332NL
MSS1048-472NL
MSS1048-682NL
7447797110
13.5 9.5
10.5 8.3
9.25 7.5
7.8
6.4
5.4
4.3
5.8
7.2
10.4
12.3
18
6.5
6.1
5.4
IL
COUT_RIPPLE
8 fSW VOUT_RIPPLE
Coilcraft
10.5 10.8 5.1
8.4 9.78 7.2
7.38 7.22 10.1
6.46 6.9 11.4
5.94 6.01 15.4
VOUT_RIPPLE
IL
RESR
where:
ΔVOUT_RIPPLE is the allowable output voltage ripple.
RESR is the equivalent series resistance of the output capacitor.
Wurth
Elektronik
16
7.6
14
16
18
27
30
7447797180
7447797300
7447797470
7447797620
13.3 7.3
10.5 7.0
8.0
7.5
Select the largest output capacitance given by COUT_UV, COUT_OV
and COUT_RIPPLE to meet both load transient and output ripple
performance.
,
5.8
5.5
The selected output capacitor voltage rating must be greater
than the output voltage. The minimum rms current rating of
the output capacitor is determined by the following equation:
IL
12
IC
OUT _rms
Rev. 0 | Page 21 of 32
ADP2325
Data Sheet
LOW-SIDE POWER DEVICE SELECTION
PROGRAMMING THE UVLO INPUT
The ADP2325 has integrated low-side MOSFET drivers, which
can drive the low-side N-channel MOSFETs (NFETs). The selec-
tion of the low-side N-channel MOSFET affects the dc-to-dc
regulator performance.
The precision enable input can be used to program the UVLO
threshold and hysteresis of the input voltage, as shown in Figure 50.
PVINx
R
The selected MOSFET must meet the following requirements:
TOP_EN
EN CMP
ENx
•
•
Drain source voltage (VDS) must be higher than 1.2 × VIN.
Drain current (ID) must be greater than 1.2 × ILIMIT_MAX, where
1.2V
R
BOT_EN
I
LIMIT_MAX is the selected maximum current-limit threshold.
1µA 4µA
The ADP2325 low-side gate drive voltage is 5 V. Make sure that
the selected MOSFET can be fully turned on at 5 V.
Figure 50. Programming the UVLO Input
Total gate charge (Qg at 5 V) must be less than 50 nC. Lower Qg
characteristics constitute higher efficiency.
Use the following equation to calculate RTOP_EN and RBOT_EN
:
1.1V ×VIN_RISING −1.2V ×VIN_FALLING
RTOP_EN
=
When the high-side MOSFET is turned off, the low-side MOSFET
carries the inductor current. For low duty cycle applications, the
low-side MOSFET carries the current for most of the period. To
achieve higher efficiency, it is important to select a low on-resist-
ance MOSFET. The power conduction loss for the low-side
MOSFET can be calculated by
1.1 V×5 μA −1.2 V×1 μA
1.2 V×RTOP _ EN
RBOT _ EN
=
VIN _ RISING − RTOP _ EN ×5 μΑ −1.2 V
where:
V
V
IN_RISING is the VIN rising threshold.
IN_FALLING is the VIN falling threshold.
P
FET_LOW = IOUT2 × RDSON × (1 − D)
where RDSON is the on resistance of the low-side MOSFET.
COMPENSATION COMPONENTS DESIGN
Make sure that the MOSFET can handle the thermal dissipation
due to the power loss.
In peak current mode control, the power stage can be simplified
to a voltage controlled current source supplying current to the
output capacitor and load resistor. It is composed of one domain
pole and a zero contributed by the output capacitor ESR. The
control-to-output transfer function is shown in the following
equations:
In some cases, efficiency is not critical for the system; therefore,
the diode can be selected as the low-side power device. The
average current of the diode can be calculated by
IDIODE (AVG) = (1 − D) × IOUT
s
The reverse breakdown voltage rating of the diode must be
greater than the input voltage with an appropriate margin to
allow for ringing, which may be present at the SWx node. A
Schottky diode is recommended because it has a low forward
voltage drop and a fast switching speed.
1+
1+
2×π × fZ
V
OUT (s)
GVD (s) =
= AVI × R×
VCOMP (s)
s
2×π × fP
1
If a diode is used for the low-side device, the ADP2325 must
enable the PFM mode by connecting the MODE pin to ground.
fZ =
2×π × RESR ×COUT
1
Table 10. Recommended MOSFETs
fP =
2×π ×
(
R + RESR ×COUT
)
Vendor
Fairchild
Fairchild
Fairchild
Vishay
Vishay
AOS
Part No.
VDS
ID
RDSON
Qg
FDS8880
FDMS7578
FDS6898A
Si4804CDY
SiA430DJ
AON7402
AO4884L
30 V 10.7 A 12 mΩ
12 nC
8 nC
16 nC
7 nC
5.3 nC
7.1 nC
13.6 nC
where:
VI = 8.33 A/V.
R is the load resistance.
OUT is the output capacitance.
ESR is the equivalent series resistance of the output capacitor.
25 V 14 A
20 V 9.4 A
30 V 7.9 A
20 V 10.8 A 18.5 mΩ
30 V 39 A
40 V 10 A
8 mΩ
14 mΩ
27 mΩ
A
C
R
15 mΩ
16 mΩ
AOS
Rev. 0 | Page 22 of 32
Data Sheet
ADP2325
The ADP2325 uses a transconductance amplifier for the error
amplifier to compensate the system. Figure 51 shows the
simplified peak current mode control small signal circuit.
The following design guidelines show how to select the compen-
sation components, RC, CC, and CCP, for ceramic output capacitor
applications.
V
V
OUT
OUT
4. Determine the cross frequency (fC). Generally, the fC is
between fSW/12 and fSW/6.
R
TOP
5. RC can be calculated by using the following equation:
V
C
R
COMP
C
OUT
–
gm
+
–
A
VI
2×π ×VOUT ×COUT × fC
RC =
+
R
R
BOT
R
C
0.6V × gm × AVI
CP
ESR
C
C
6. Place the compensation zero at the domain pole (fP).
CC can be determined by
(
R + RESR ×COUT
)
Figure 51. Simplified Peak Current Mode Control Small Signal Circuit
CC =
RC
The compensation components, RC and CC, contribute a zero,
and the optional CCP and RC contribute an optional pole.
7. CCP is optional. It can be used to cancel the zero caused by
the ESR of the output capacitor.
The closed-loop transfer equation is as follows:
R
ESR ×COUT
1+ RC ×CC× s
RC ×CC ×CCP
RBOT
BOT + RTOP CC+ CCP
−gm
CCP
=
TV(s) =
×
×
×GVD(s)
RC
R
s × 1+
× s
CC +CCP
The ADP2325 has an internal 10 pF capacitor at the COMPx
pin; therefore, if CCP is smaller than 10 pF, no external capacitor
is required.
Rev. 0 | Page 23 of 32
ADP2325
Data Sheet
DESIGN EXAMPLE
This section describes the design procedure and component
selection for the example application shown in Figure 54, and
Table 11 provides a list of the required settings.
Calculate the peak-to-peak inductor ripple current as follows:
VIN −VOUT × D
(
)
∆IL =
L × fSW
Table 11. Dual Step-Down DC-to-DC Regulator Requirements
For VOUT1 = 1.2 V, ΔIL1 = 1.44 A. For VOUT2 = 3.3 V, ΔIL2 = 1.45 A.
Find the peak inductor current using the following equation:
∆IL
Parameter
Specification
Channel 1
Input Voltage
VIN1 = 12.0 V 10%
VOUT1 = 1.2 V
IOUT1 = 5 A
ΔVOUT1_RIPPLE = 12 mV
5%, 1 A to 4 A, 1 A/µs
IPEAK = IOUT
+
Output Voltage
Output Current
Output Voltage Ripple
Load Transient
Channel 2
2
For the 1.2 V rail, the peak inductor current is 5.73 A, and for
the 3.3 V rail, the peak inductor current is 5.73 A.
The rms current through the inductor can be estimated by
Input Voltage
VIN2 = 12.0 V 10%
VOUT2 = 3.3 V
IOUT2 = 5 A
ΔVOUT2_RIPPLE = 33 mV
5%, 1 A to 4 A, 1 A/µs
fSW = 500 kHz
2
∆IL
12
2
IRMS
=
IOUT
+
Output Voltage
Output Current
Output Voltage Ripple
Load Transient
Switching Frequency
The rms current of the inductor for both the 1.2 V and 3.3 V
rails is approximately 5.02 A.
For the 1.2 V rail, select an inductor with a minimum rms
current rating of 5.01 A and a minimum saturation current
rating of 5.73 A. For the 3.3 V rail, select an inductor with a
minimum rms current rating of 5.02 A and a minimum
saturation current rating of 5.73 A.
OUTPUT VOLTAGE SETTING
Choose a 10 kΩ top feedback resistor (RTOP); calculate the
bottom feedback resistor using the following equation:
Based on these requirements, for the 1.2 V rail, select a
1.5 µH inductor, such as the Sumida CDRH105RNP-1R5N,
with a DCR = 5.8 mΩ; for the 3.3 V rail, select a 3.3 µH
inductor, such as the Sumida CDRH105RNP-3R3N, with a
DCR = 10.4 mΩ.
0.6
VOUT − 0.6
RBOT = RTOP
×
To set the output voltage to 1.2 V, the resistor values are RTOP1
10 kΩ and RBOT1 = 10 kΩ. To set the output voltage to 3.3 V,
the resistors values are RTOP2 = 10 kΩ and RBOT2 = 2.21 kΩ.
=
OUTPUT CAPACITOR SELECTION
CURRENT-LIMIT SETTING
The output capacitor is required to meet the output voltage
ripple and load transient requirements. To meet the output
voltage ripple requirement, use the following equation to
calculate the capacitance and ESR:
For 5 A output current operation, the typical peak current
limit is 8 A. In this case, no RILIM is required.
FREQUENCY SETTING
∆IL
COUT_RIPPLE
=
To set the switching frequency to 500 kHz, use the following
equation to calculate the resistor value, ROSC
8× fSW ×∆VOUT _ RIPPLE
:
∆VOUT _ RIPPLE
60,000
RESR
=
ROSC kΩ =
( )
IL
fSW
kHz
( )
For VOUT1 = 1.2 V, COUT_RIPPLE1 = 30 µF and RESR1 = 8.3 mΩ. For
OUT2 = 3.3 V, COUT_RIPPLE2 = 11 µF and RESR2 = 23 mΩ.
Therefore, ROSC =120 kΩ.
V
INDUCTOR SELECTION
The peak-to-peak inductor ripple current, ΔIL, is set to 30%
of the maximum output current. Use the following equation
to estimate the value of the inductor:
(
VIN −VOUT × D
)
L =
∆IL × fSW
For VOUT1 = 1.2 V, Inductor L1 = 1.4 µH, and for VOUT2 = 3.3 V,
Inductor L2 = 3.2 µH.
Select the standard inductor value of 1.5 µH and 3.3 µH for
the 1.2 V and 3.3 V rails.
Rev. 0 | Page 24 of 32
Data Sheet
ADP2325
To meet the 5% overshoot and undershoot requirement, use
the following equation to calculate the capacitance:
Figure 52 shows the 1.2 V rail bode plot at 5 A. The cross
frequency is 42 kHz and the phase margin is 50°.
60
180
144
108
72
K
OV ×∆ISTEP 2 ×L
COUT_OV
=
=
48
36
VOUT + ∆VOUT _OV
2−VOUT
2
KUV × ∆ISTEP 2 × L
24
COUT_UV
2×
(
VIN −VOUT × ∆VOUT _UV
)
12
36
For estimation purposes, use KOV = KUV = 2. For VOUT1 = 1.2 V,
use COUT_OV1 = 188 µF and COUT_UV1 = 21 µF. For VOUT2 = 3.3 V,
use COUT_OV2 = 55 µF and COUT_UV2 = 21 µF.
0
0
–12
–24
–36
–48
–60
–36
–72
–108
–144
–180
For the 1.2 V rail, ESR of the output capacitor must be smaller
than 8.3 mΩ, and the output capacitance must be larger than
188 µF. It is recommend that three 100 µF, X5R, 6.3 V ceramic
capacitors be used, such as the GRM32ER60J107ME20 from
Murata, with an ESR = 2 mΩ.
1
2
1k
10k
100k
FREQUENCY (Hz)
1M
Figure 52. Bode Plot for 1.2 V Rail
For the 3.3 V rail, the ESR of the output capacitor must be
smaller than 23 mΩ, and the output capacitance must be
larger than 55 µF. It is recommended that two 47 µF, X5R,
6.3 V ceramic capacitors be used, such as the Murata
GRM32ER60J476ME20, with an ESR = 2 mΩ.
For the 3.3 V rail, the 47 µF ceramic output capacitor has a
derated value of 32 µF.
2×π ×3.3V×2×32 μF×50 kHz
RC2
CC2
CCP2
=
= 26.5 kΩ
0.6 V×500 μS×8.33 A/V
0.66Ω + 0.001Ω ×2×32μF
26.5kΩ
LOW-SIDE MOSFET SELECTION
(
)
=
=
1594pF
A low RDSON N-channel MOSFET is selected for high efficiency
solutions. The MOSFET breakdown voltage must be greater
than 1.2 V × VIN, and the drain current must be greater than
0.001 Ω×2×32μF
=
= 2.4 pF
1.2 V × ILIMIT
.
26.5kΩ
It is recommended that a 30 V, N-channel MOSFET be used, such
as the FDS8880 from Fairchild. The RDSON of the FDS8880 at a
4.5 V driver voltage is 12 mΩ, and the total gate charge is 12 nC.
By using standard component values of RC2 = 27 kΩ and
C2 = 1500 pF, no CCP2 is needed.
C
Figure 53 shows the 3.3 V rail bode plot at 5 A. The cross
frequency is 55 kHz and phase margin is 67°.
COMPENSATION COMPONENTS
60
180
144
108
72
For better load transient and stability performance, set the
cross frequency, fC, to fSW/10. In this case, fSW runs at 500 kHz;
therefore, the fC is set to 50 kHz.
48
36
For the 1.2 V rail, the 100 µF ceramic output capacitor has
a derated value of 64 µF.
24
12
36
2×π ×1.2V ×3×64 μF×50 kHz
0
0
RC1
CC1
=
=
= 28.9 kΩ
0.6 V
0.24Ω + 0.001Ω
28.9kΩ
×
500 μS
×
8.33 A/V
–12
–24
–36
–48
–60
–36
–72
–108
–144
–180
(
)
×3×64μF
= 1598pF
0.001Ω×3×64μF
CCP1
=
= 6.6pF
1
2
1k
10k
100k
FREQUENCY (Hz)
1M
28.9kΩ
By choosing standard components where RC1 = 28 kΩ and CC1
1500 pF, no CCP1 is needed.
=
Figure 53. Bode Plot for 3.3 V Rail
Rev. 0 | Page 25 of 32
ADP2325
Data Sheet
SOFT START TIME PROGRAMMING
INPUT CAPACITOR SELECTION
The soft start feature allows the output voltage to ramp up in
a controlled manner, eliminating output voltage overshoot
during soft start and limiting inrush current. The soft start
time is set to 3 ms.
A minimum 10 µF ceramic capacitor is required, placed near
the PVINx pin. In this application, one X5R ceramic capacitor of
10 µF and 25 V is recommended.
3.5 μA×3 ms
I
SS ×tSS
0.6 V
CSS
=
=
=17.5 nF
0.6 V
Choose a standard component value of CSS1 = CSS2 = 22 nF.
Rev. 0 | Page 26 of 32
Data Sheet
ADP2325
EXTERNAL COMPONENTS RECOMMENDATIONS
Table 12. Recommended External Components for Typical Applications with 5 A Output Current
fSW (kHz)
VIN (V)
12
12
12
12
12
12
12
5
5
5
5
5
VOUT (V)
L (µH)
2.2
2.2
3.3
3.3
4.7
4.7
6.8
1.5
2.2
2.2
2.2
2.2
2.2
1.5
1.5
2.2
2.2
3.3
1
1
1
1.5
1.5
1.5
1
1
1.5
2
0.56
0.56
0.68
0.8
0.8
0.8
COUT (µF)1
2 × 330
2 × 330
2 × 330
330
RTOP (kΩ)
RBOT (kΩ)
RC (kΩ)
47
59
75
43
62
33
36
49
59
37
43
22
15
75
53
47
47
47
49
59
27
33
33
30
56
39
53
39
47
37
47
43
43
27
CC (pF)
2700
2700
2700
2700
2700
2700
2700
2700
2700
2700
2700
2700
2700
1500
1500
1500
1500
1500
1500
1500
1500
1500
1500
1500
820
CCP (pF)
56
56
47
68
300
1
10
10
15
20
47.5
10
22
10
10
15
20
47.5
10
15
10
10
10
15
2.21
3
15
10
10
10
15
2.21
10
10
15
2.21
3
15
10
10
10
15
2.21
10
15
2.21
3
15
1.2
1.5
1.8
2.5
3.3
5
330
56
2 × 100
100 + 47
2 × 330
2 × 330
330
330
2 × 100
100
3.3
3.3
68
56
82
1
1.2
1.5
1.8
2.5
3.3
1.5
1.8
2.5
3.3
5
68
4.7
4.7
47
2.2
2.2
2.2
2.2
68
5
600
12
12
12
12
12
5
5
5
5
5
330
15
20
47.5
10
22
10
10
15
20
3 × 100
2 × 100
100 + 47
100
330
330
2 × 100
2 × 100
100 + 47
100
1
1.2
1.5
1.8
2.5
3.3
1.8
2.5
3.3
5
56
4.7
3.3
2.2
4.7
2.2
2.2
2.2
2.2
2.2
6.8
4.7
4.7
4.7
2.2
47.5
10
5
1000
12
12
12
12
5
5
5
5
5
2 × 100
100
100
20
47.5
10
22
10
10
15
20
47.5
10
820
820
820
820
820
820
820
820
47
1
3 × 100
2 × 100
2 × 100
100 + 47
100
1.2
1.5
1.8
2.5
3.3
10
10
10
15
5
47
2.21
820
1 330 µF: 6.3 V, Sanyo 6TPD330M; 100 µF: 6.3 V, X5R, Murata GRM32ER60J107ME20; 47 µF: 6.3 V, X5R, Murata GRM32ER60J476ME20.
Rev. 0 | Page 27 of 32
ADP2325
Data Sheet
TYPICAL APPLICATION CIRCUITS
C
C1
1500pF
C
V
R
10kΩ
IN
12V
TOP1
C
10µF,
25V
IN1
SS1
22nF
R
BOT1
10kΩ
R
C1
28kΩ
C
BST1
0.1µF
L1
1.5µH
INTVCC
C
INT
1µF
V
OUT1
MODE
SW1
1.2V
5A
SCFG
TRK2
TRK1
M1
C
100µF
C
100µF
C
OUT1
OUT2
OUT3
100µF
FDS8880
DL1
PGND
DL2
VDRV
C
DRV
1µF
ADP2325
M2
FDS8880
GND
C
C
47µF
OUT4
OUT5
47µF
PGOOD2
V
OUT2
3.3V
5A
PGOOD1
SYNC
RT
SW2
L2
3.3µH
C
R
BST2
0.1µF
OSC
120kΩ
R
27kΩ
R
C2
BOT2
V
2.21kΩ
IN
12V
C
C
C
10µF,
25V
C2
SS2
22nF
IN2
1500pF
R
TOP2
10kΩ
Figure 54. Using an External MOSFET Application, VIN1 = VIN2 = 12 V, VOUT1 = 1.2 V, IOUT1 = 5 A, VOUT2 = 3.3 V, IOUT2 = 5 A, fSW = 500 kHz
C
C1
2.2nF
C
V
R
IN
12V
TOP1
22kΩ
C
10µF,
25V
IN1
SS1
10nF
R
BOT1
R
C1
3kΩ
20kΩ
C
BST1
0.1µF
L1
INTVCC
C
INT
1µF
4.7µH
V
OUT1
SW1
5V
SCFG
TRK2
TRK1
VDRV
3A
D1
B320B
C
C
OUT1
22µF
OUT2
22µF
DL1
PGND
DL2
R
ILIM1
47kΩ
C
DRV
1µF
ADP2325
R
GND
MODE
ILIM2
47kΩ
C
C
OUT3
22µF
OUT4
22µF
D2
B220A
PGOOD2
V
OUT2
PGOOD1
SYNC
RT
SW2
3.3V
1.5A
L2
8.2µH
C
BST2
R
OSC
0.1µF
100kΩ
R
R
C2
BOT2
18kΩ
V
2.21kΩ
IN
12V
C
C
C
C2
4.7nF
SS2
10nF
IN2
10µF,
25V
R
TOP2
10kΩ
Figure 55. Using an External Diode Application, VIN1 = VIN2 = 12 V, VOUT1 = 5 V, IOUT1 = 3 A, VOUT2 = 3.3 V, IOUT2 = 1.5 A, fSW = 600 kHz
Rev. 0 | Page 28 of 32
Data Sheet
ADP2325
R
TOP1
10kΩ
C
C1
1200pF
R
C
BOT1
10kΩ
SS1
22nF
R
59kΩ
C1
V
IN
12V
C
CP1
56pF
C
10µF,
25V
IN1
C
BST1
0.1µF
V
OUT1
1.2V,
10A
TRK1
SW1
SW1
L1
1µH
PGOOD1
SCFG
SYNC
C
INT
1µF
C
C
C
M1
FDS8880
OUT1
330µF
OUT2
330µF
OUT3
10µF
INTVCC
DL1
ADP2325
RT
R
OSC
PGND
MODE
200kΩ
DL2
PGOOD2
TRK2
M2
C
DRV
1µF
FDS8880
SW2
SW2
VDRV
GND
L2
1µH
C
BST2
0.1µF
V
IN
12V
C
IN2
10µF,
25V
Figure 56. Parallel Single Output Application, VIN = 12 V, VOUT = 1.2 V, IOUT = 10 A, fSW = 300 kHz
R
TOP1
15kΩ
C
C1
1200pF
V
IN
12V
R
C
BOT1
10kΩ
SS1
22nF
R
47kΩ
C
10µF,
25V
C1
IN1
C
BST1
0.1µF
INTVCC
SCFG
TRK2
V
1.5V,
5A
OUT1
C
INT
1µF
SW1
L1
1.5µH
TRK1
C
C
C
OUT3
100µF
M1
FDS8880
OUT1
100µF
OUT2
100µF
VDRV
C
DRV
1µF
DL1
ADP2325
GND
MODE
PGND
PGOOD2
PGOOD1
SYNC
DL2
C
C
C
OUT4
47µF
OUT5
47µF
OUT6
47µF
M2
FDS8880
V
OUT1
RT
SW2
2.5V,
5A
R
OSC
L2
100kΩ
C
2.2µH
BST2
0.1µF
R
39kΩ
C2
V
IN
12V
R
BOT2
C
22nF
SS2
15kΩ
R
C
TOP2
C2
C
10µF,
25V
IN2
47.5kΩ
1200pF
Figure 57. Enable PFM Mode with the MODE Pin Pulled to GND, VIN1 = VIN2 = 12 V, VOUT1 = 1.5 V, IOUT1 = 5 A, VOUT2 = 2.5 V, IOUT2 = 5 A, fSW = 600 kHz
Rev. 0 | Page 29 of 32
ADP2325
Data Sheet
R
TOP1
20kΩ
C
C1
1200pF
V
IN
12V
R
BOT1
10kΩ
C
IN1
R
53kΩ
C
C1
SS1
22nF
10µF,
25V
C
BST1
SYNC
0.1µF
V
OUT1
1.8V,
SW1
SCFG
INTVCC
MODE
TRK2
TRK1
VDRV
L1
3A
1.5µH
C
INT1
1µF
C
100µF
C
100µF
C
M1
OUT1
OUT2
OUT3
100µF
FDS8880
DL1
ADP2325
C
DRV1
1µF
PGND
GND
C
100µF
C
100µF
DL2
OUT4
OUT5
M2
FDS8880
PGOOD2
PGOOD1
V
OUT2
3.3V,
5A
SW2
RT
L2
2.2µH
C
R
BST2
0.1µF
OSC1
100kΩ
R
C
C2
62kΩ
SS2
22nF
V
IN
12V
R
C
10µF,
25V
BOT2
IN2
C
C2
1200pF
2.21kΩ
R
TOP2
10kΩ
R
TOP3
20kΩ
C
C3
V
1200pF
IN
12V
R
10kΩ
C
SS3
22nF
BOT3
C
10µF,
25V
R
IN3
C3
53kΩ
C
0.1µF
BST3
SYNC
SCFG
V
OUT3
1.8V,
3A
SW1
L3
1.5µH
INTVCC
MODE
TRK2
C
INT2
1µF
M3
FDS8880
C
100µF
C
100µF
C
OUT6
OUT7
OUT8
100µF
DL1
ADP2325
TRK1
VDRV
PGND
C
DRV2
1µF
GND
C
100µF
C
100µF
DL2
OUT9
OUT10
M4
FDS8880
PGOOD2
PGOOD1
V
3.3V,
5A
OUT4
SW2
RT
L4
2.2µH
C
R
BST4
0.1µF
OSC2
120kΩ
C
SS4
22nF
R
C4
62kΩ
V
IN
12V
R
BOT4
C
10µF,
25V
IN4
C
C4
1200pF
2.21kΩ
R
TOP4
10kΩ
Figure 58. Synchronization with 90° Phase Shift Between Each Channel
Rev. 0 | Page 30 of 32
Data Sheet
ADP2325
R
R
EN_BOT
68kΩ
EN_TOP
330kΩ
R
V
TOP1
10kΩ
IN
12V
C
10µF,
25V
IN1
C
C1
2200pF
R
C
22nF
BOT1
2.21kΩ
SS1
R
C1
47kΩ
C
0.1µF
BST1
SYNC
V
OUT1
PGOOD2
PGOOD1
3.3V,
5A
SW1
L1
4.7µH
R
PGOOD1
100kΩ
M1
C
C
C
OUT1
100µF
OUT2
100µF
OUT3
100µF
INTVCC
MODE
SCFG
TRK2
FDS8880
C
INT
1µF
DL1
ADP2325
PGND
TRK1
DL2
C
C
OUT4
330µF
OUT5
330µF
M2
FDS8880
VDRV
C
DRV
1µF
GND
RT
V
OUT2
1.8V,
5A
SW2
R
L2
3.3µH
OSC
C
200kΩ
BST2
0.1µF
V
12V
R
82kΩ
IN
C2
C
SS2
22nF
R
10kΩ
C
36pF
BOT2
CP2
C
10µF,
25V
IN2
R
TOP2
20kΩ
C
C2
2200pF
Figure 59. Programmable VIN_RISING = 8.7 V, VIN_FALLING = 6.7 V, 3.3 V Startup Prior to 1.8 V,
VIN1 = VIN2 = 12 V, VOUT1 = 3.3 V, IOUT1 = 5 A, VOUT2 = 1.8 V, IOUT2 = 5 A, fSW = 300 kHz
V
IN
12V
R
TOP1
C
10µF,
25V
IN1
47.5kΩ
C
C1
1200pF
R
15kΩ
C
BOT1
SS1
22nF
R
33kΩ
C1
R
R
TRK_TOP
47.5kΩ
C
0.1µF
BST1
TRK2
V
2.5V,
5A
TRK_BOT
15kΩ
PGOOD2
PGOOD1
SYNC
OUT1
SW1
L1
2.2µH
M1
FDS8880
C
47µF
C
47µF
C
OUT3
47µF
INTVCC
TRK1
OUT1
OUT2
C
1µF
INT
DL1
ADP2325
MODE
SCFG
VDRV
PGND
C
DL2
C
330µF
C
10µF
DRV
1µF
OUT4
OUT5
M2
GND
RT
FDS8880
V
OUT2
1.25V,
5A
SW2
R
OSC
120kΩ
L2
1.5µH
C
BST2
0.1µF
C
SS2
10nF
R
49kΩ
C2
V
IN
12V
R
C
BOT2
12kΩ
CP2
56pF
C
IN2
10µF,
25V
R
C
TOP2
C2
13kΩ
1500pF
Figure 60. Channel 2 Tracking with Channel 1
IN1 = VIN2 = 12 V, VOUT1 = 2.5 V, IOUT1 = 5 A, VOUT2 = 1.25 V, IOUT2 = 5 A, fSW = 500 kHz
V
Rev. 0 | Page 31 of 32
ADP2325
Data Sheet
PACKAGING AND ORDERING INFORMATION
OUTLINE DIMENSIONS
5.10
5.00 SQ
4.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
25
24
32
1
0.50
BSC
3.25
3.10 SQ
2.95
EXPOSED
PAD
17
16
8
9
0.50
0.40
0.30
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD.
Figure 61. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
5 mm × 5 mm Body, Very Very Thin Quad
(CP-32-7)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Output Voltage
Package Description2
Package Option
CP-32-7
ADP2325ACPZ-R7
ADP2325-EVALZ
ADP2325-BL1-EVZ
ADP2325-BL2-EVZ
−40°C to +125°C
Adjustable
32-Lead LFCSP_WQ
Evaluation Board
Blank Dual Output Evaluation Board
Blank Single Output Evaluation Board
1 Z = RoHS Compliant Part.
2 For the blank evaluation boards, users can request an unpopulated board from Analog Devices, Inc., through the ADIsimPower tool found at
www.analog.com/ADIsimPower, as well as generate schematics and a bill of materials from the tool.
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
www.analog.com/ADP2325
D10036-0-2/12(0)
Rev. 0 | Page 32 of 32
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