EVAL-INAMP-62RZ [ADI]
Single-Supply, Rail-to-Rail, Low Cost Instrumentation Amplifier; 单电源，轨到轨，低成本仪表放大器
| 型号： | EVAL-INAMP-62RZ |
| 厂家： | 
ADI |
| 描述： | Single-Supply, Rail-to-Rail, Low Cost Instrumentation Amplifier |
| 文件： | 总24页 (文件大小：1299K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Single-Supply, Rail-to-Rail, Low Cost
Instrumentation Amplifier
AD623
FEATURES
CONNECTION DIAGRAM
AD623
Easy to use
1
2
3
4
8
7
6
5
–R
+R
G
G
Higher performance than discrete design
Single-supply and dual-supply operation
Rail-to-rail output swing
–IN
+IN
+V
S
OUTPUT
REF
–V
S
Input voltage range extends 150 mV below
ground (single supply)
TOP VIEW
(Not to Scale)
Low power, 550 μA maximum supply current
Gain set with one external resistor
Gain range: 1 (no resistor) to 1000
High accuracy dc performance
Figure 1. 8-Lead PDIP (N), SOIC (R), and MSOP (RM) Packages
120
110
0.10% gain accuracy (G = 1)
0.35% gain accuracy (G > 1)
100
×1000
10 ppm maximum gain drift (G = 1)
200 μV maximum input offset voltage (AD623A)
2 μV/°C maximum input offset drift (AD623A)
100 μV maximum input offset voltage (AD623B)
1 μV/°C maximum input offset drift (AD623B)
25 nA maximum input bias current
Noise: 35 nV/√Hz RTI noise @ 1 kHz (G = 1)
Excellent ac specifications
90
×100
80
70
×10
60
50
×1
40
90 dB minimum CMRR (G = 10); 70 dB minimum CMRR (G = 1)
at 60 Hz, 1 kΩ source imbalance
800 kHz bandwidth (G = 1)
30
1
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 2. CMR vs. Frequency, 5 VS, 0 VS
20 μs settling time to 0.01% (G = 10)
APPLICATIONS
The AD623 holds errors to a minimum by providing superior
ac CMRR that increases with increasing gain. Line noise, as
well as line harmonics, are rejected because the CMRR remains
constant up to 200 Hz. The AD623 has a wide input common-
mode range and can amplify signals that have a common-mode
voltage 150 mV below ground. Although the design of the AD623
was optimized to operate from a single supply, the AD623 still
provides superior performance when operated from a dual
voltage supply ( 2.5 V to 6.0 V).
Low power medical instrumentation
Transducer interfaces
Thermocouple amplifiers
Industrial process controls
Difference amplifiers
Low power data acquisition
GENERAL DESCRIPTION
The AD623 is an integrated single-supply instrumentation
amplifier that delivers rail-to-rail output swing on a 3 V to 12 V
supply. The AD623 offers superior user flexibility by allowing
single gain set resistor programming and by conforming to the
8-lead industry standard pinout configuration. With no external
resistor, the AD623 is configured for unity gain (G = 1), and
with an external resistor, the AD623 can be programmed for
gains up to 1000.
Low power consumption (1.5 mW at 3 V), wide supply voltage
range, and rail-to-rail output swing make the AD623 ideal
for battery-powered applications. The rail-to-rail output stage
maximizes the dynamic range when operating from low supply
voltages. The AD623 replaces discrete instrumentation amplifier
designs and offers superior linearity, temperature stability, and
reliability in a minimum of space.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©1997–2008 Analog Devices, Inc. All rights reserved.
AD623
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications Information.............................................................. 16
Basic Connection ....................................................................... 16
Gain Selection............................................................................. 16
Reference Terminal .................................................................... 16
Input and Output Offset Voltage.............................................. 17
Input Protection ......................................................................... 17
RF Interference ........................................................................... 17
Grounding................................................................................... 18
Applications....................................................................................... 1
General Description......................................................................... 1
Connection Diagram ....................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Single Supply ................................................................................. 3
Dual Supplies ................................................................................ 4
Both Dual and Single Supplies.................................................... 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 15
Input Differential and Common-Mode Range vs. Supply and
Gain .............................................................................................. 20
Outline Dimensions....................................................................... 22
Ordering Guide .......................................................................... 23
REVISION HISTORY
7/08—Rev. C to Rev. D
Updated Format..................................................................Universal
Changes to Features Section and General Description Section. 1
Changes to Table 3............................................................................ 6
Changes to Figure 40...................................................................... 14
Changes to Theory of Operation Section.................................... 15
Changes to Figure 42 and Figure 43............................................. 16
Changes to Table 7.......................................................................... 19
Updated Outline Dimensions....................................................... 22
Changes to Ordering Guide .......................................................... 23
9/99—Rev. B to Rev. C
Rev. D | Page 2 of 24
AD623
SPECIFICATIONS
SINGLE SUPPLY
Typical @ 25°C single supply, VS = 5 V, and RL = 10 kΩ, unless otherwise noted.
Table 1.
AD623A
Typ Max
AD623ARM
Typ Max
AD623B
Typ Max
Parameter
Conditions
Min
Min
Min
Unit
GAIN
G =
1 + (100 k/RG)
Gain Range
Gain Error1
1
1000
1
1000
1
1000
G1 VOUT
0.05 V to 3.5 V
G > 1 VOUT
0.05 V to 4.5 V
=
=
G = 1
G = 10
G = 100
0.03 0.10
0.10 0.35
0.10 0.35
0.10 0.35
0.03 0.10
0.10 0.35
0.10 0.35
0.10 0.35
0.03 0.05
0.10 0.35
0.10 0.35
0.10 0.35
%
%
%
%
G = 1000
Nonlinearity
G1 VOUT
0.05 V to 3.5 V
G > 1 VOUT
=
=
0.05 V to 4.5 V
G = 1 to 1000
Gain vs. Temperature
G = 1
50
50
50
ppm
5
50
10
5
50
10
5
50
10
ppm/°C
ppm/°C
G > 11
VOLTAGE OFFSET
Total RTI error =
VOSI + VOSO/G
Input Offset, VOSI
Over Temperature
Average Tempco
Output Offset, VOSO
Over Temperature
Average Tempco
25
200
350
2
200 500
650
25
100
160
1
μV
μV
μV/°C
μV
μV
0.1
0.1
2
0.1
200 1000
1500
2.5
500 2000
2600
200 500
1100
10
10
2.5
10
2.5
μV/°C
Offset Referred to the
Input vs. Supply (PSR)
G = 1
G = 10
G = 100
G = 1000
80
100
120
140
140
80
100
120
140
140
80
100
120
140
140
dB
dB
dB
dB
100
120
120
100
120
120
100
120
120
INPUT CURRENT
Input Bias Current
Over Temperature
Average Tempco
Input Offset Current
Over Temperature
Average Tempco
17
25
27.5
17
25
27.5
17
25
27.5
nA
nA
pA/°C
nA
nA
25
0.25
25
0.25
25
0.25
2
2.5
2
2.5
2
2.5
5
5
5
pA/°C
Rev. D | Page 3 of 24
AD623
AD623A
Typ Max
AD623ARM
Typ Max
AD623B
Typ Max
Parameter
Conditions
Min
Min
Min
Unit
INPUT
Input Impedance
Differential
Common-Mode
Input Voltage Range2
2||2
2||2
2||2
2||2
2||2
2||2
GΩ||pF
GΩ||pF
V
VS = 3 V to 12 V
(−VS) −
0.15
(+VS) − (−VS) −
(+VS) − (−VS) −
(+VS) −
1.5
1.5
0.15
1.5
0.15
Common-Mode Rejection
at 60 Hz with 1 kΩ Source
Imbalance
G = 1
G = 10
G = 100
VCM = 0 V to 3V
VCM = 0 V to 3V
VCM = 0 V to 3V
VCM = 0 V to 3V
70
90
105
105
80
70
90
105
105
80
77
94
105
105
86
dB
dB
dB
dB
100
110
110
100
110
110
100
110
110
G = 1000
OUTPUT
Output Swing
RL = 10 kΩ
0.01
0.01
(+VS) − 0.01
0.5
(+VS) − 0.01
0.15
(+VS) − 0.01
0.5
(+VS) − 0.01
0.15
(+VS) −
0.5
(+VS) −
0.15
V
V
RL = 100 kΩ
DYNAMIC RESPONSE
Small Signal −3 dB Bandwidth
G = 1
G = 10
G = 100
G = 1000
Slew Rate
Settling Time to 0.01%
G = 1
800
100
10
2
0.3
800
100
10
2
0.3
800
100
10
2
0.3
kHz
kHz
kHz
kHz
V/μs
VS = 5 V
Step size: 3.5 V
Step size: 4 V,
VCM = 1.8 V
30
20
30
20
30
20
μs
μs
G = 10
1 Does not include effects of external resistor, RG.
2 One input grounded. G = 1.
DUAL SUPPLIES
Typical @ 25°C dual supply, VS = 5 V, and RL = 10 kΩ, unless otherwise noted.
Table 2.
AD623A
Typ Max
AD623ARM
Typ Max
AD623B
Typ Max
Parameter
Conditions
Min
Min
Min
Unit
GAIN
G =
1 + (100 k/RG)
Gain Range
Gain Error1
1
1000
1
1000
1
1000
G1 VOUT
−4.8 V to +3.5 V
G > 1 VOUT
0.05 V to 4.5 V
=
=
G = 1
0.03 0.10
0.10 0.35
0.10 0.35
0.10 0.35
0.03 0.10
0.10 0.35
0.10 0.35
0.10 0.35
0.03 0.05
0.10 0.35
0.10 0.35
0.10 0.35
%
%
%
%
G = 10
G = 100
G = 1000
Rev. D | Page 4 of 24
AD623
AD623A
Typ Max
AD623ARM
Typ Max
AD623B
Typ Max
Parameter
Conditions
G1 VOUT
−4.8 V to +3.5 V
G > 1 VOUT
Min
Min
Min
Unit
Nonlinearity
=
=
−4.8 V to +4.5 V
G = 1 to 1000
50
50
50
ppm
Gain vs. Temperature
G = 1
G > 11
5
50
10
5
50
10
5
50
10
ppm/°C
ppm/°C
VOLTAGE OFFSET
Total RTI error =
VOSI + VOSO/G
Input Offset, VOSI
Over Temperature
Average Tempco
Output Offset, VOSO
Over Temperature
Average Tempco
25
200
350
2
200 500
650
25
100
160
1
μV
μV
μV/°C
μV
μV
0.1
0.1
2
0.1
200 1000
1500
2.5
500 2000
2600
200 500
1100
2.5
10
2.5
10
10
μV/°C
Offset Referred to the Input
vs. Supply (PSR)
G = 1
G = 10
G = 100
G = 1000
80
100
120
140
140
80
100
120
140
140
80
100
120
140
140
dB
dB
dB
dB
100
120
120
100
120
120
100
120
120
INPUT CURRENT
Input Bias Current
Over Temperature
Average Tempco
Input Offset Current
Over Temperature
Average Tempco
INPUT
17
25
27.5
17
25
27.5
17
25
27.5
nA
nA
pA/°C
nA
nA
25
0.25
25
0.25
25
0.25
2
2.5
2
2.5
2
2.5
5
5
5
pA/°C
Input Impedance
Differential
Common-Mode
Input Voltage Range2
2||2
2||2
2||2
2||2
2||2
2||2
GΩ||pF
GΩ||pF
V
VS = +2.5 V to
6 V
(−VS) –
0.15
(+VS) – (−VS) –
(+VS) – (−VS) –
(+VS) –
1.5
1.5
0.15
1.5
0.15
Common-Mode Rejection at
60 Hz with 1 kΩ Source
Imbalance
G = 1
VCM = +3.5 V to
−5.15 V
VCM = +3.5 V to
−5.15 V
VCM = +3.5 V to
−5.15 V
VCM = +3.5 V to
−5.15 V
70
80
70
80
77
86
dB
dB
dB
dB
G = 10
G = 100
G = 1000
90
100
110
110
90
100
110
110
94
100
110
110
105
105
105
105
105
105
OUTPUT
Output Swing
RL = 10 kΩ,
VS = 5 V
RL = 100 kΩ
(−VS) +
0.2
(−VS) +
0.05
(+VS) − (−VS) +
0.5 0.2
(+VS) − (−VS) +
0.15 0.05
(+VS) − (−VS) +
0.5 0.2
(+VS) − (−VS) +
0.15 0.05
(+VS) −
0.5
(+VS) −
0.15
V
V
Rev. D | Page 5 of 24
AD623
AD623A
Typ Max
AD623ARM
Typ Max
AD623B
Typ Max
Parameter
Conditions
Min
Min
Min
Unit
DYNAMIC RESPONSE
Small Signal −3 dB Bandwidth
G = 1
G = 10
G = 100
G = 1000
Slew Rate
800
100
10
2
0.3
800
100
10
2
0.3
800
100
10
2
0.3
kHz
kHz
kHz
kHz
V/μs
Settling Time to 0.01%
VS = 5 V,
5 V step
G = 1
G = 10
30
20
30
20
30
20
μs
μs
1 Does not include effects of external resistor, RG.
2 One input grounded. G = 1.
BOTH DUAL AND SINGLE SUPPLIES
Table 3.
AD623A
Min Typ
AD623ARM
Max Min Typ
AD623B
Max Min Typ
Parameter
NOISE
Conditions
Max Unit
Voltage Noise, 1 kHz
Total RTI noise =
2
2
(
eni
)
+
(
eno /G
)
Input, Voltage Noise, eni
Output, Voltage Noise, eno
RTI, 0.1 Hz to 10 Hz
G = 1
35
50
35
50
35
50
nV/√Hz
nV/√Hz
3.0
1.5
100
1.5
3.0
1.5
100
1.5
3.0
1.5
100
1.5
μV p-p
μV p-p
fA/√Hz
pA p-p
G = 1000
Current Noise
0.1 Hz to 10 Hz
REFERENCE INPUT
RIN
f = 1 kHz
100
100
100
kΩ
20%
20%
20%
IIN
VIN+, VREF = 0 V
50
60
+VS
50
60
+VS
50
60
+VS
μA
V
V
Voltage Range
Gain to Output
−VS
−VS
−VS
1
1
1
0.0002
0.0002
0.0002
POWER SUPPLY
Operating Range
Dual supply
Single supply
Dual supply
Single supply
2.5
2.7
6
12
550
480
625
2.5
2.7
6
12
550
480
625
2.5
2.7
6
12
550
480
625
V
V
μA
μA
μA
Quiescent Current
375
305
375
305
375
305
Over Temperature
TEMPERATURE RANGE
For Specified Performance
−40
+85
−40
+85
−40
+85
°C
Rev. D | Page 6 of 24
AD623
ABSOLUTE MAXIMUM RATINGS
Table 4.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
Supply Voltage
6 V
Internal Power Dissipation1
Differential Input Voltage
Output Short-Circuit Duration
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec)
650 mW
6 V
Indefinite
−65°C to +125°C
−40°C to +85°C
300°C
ESD CAUTION
1 Specification is for device in free air:
8-Lead PDIP Package: θJA = 95°C/W
8-Lead SOIC Package: θJA = 155°C/W
8-Lead MSOP Package: θJA = 200°C/W.
Rev. D | Page 7 of 24
AD623
TYPICAL PERFORMANCE CHARACTERISTICS
At 25°C, VS = 5 V, and RL = 10 kΩ, unless otherwise noted.
300
280
260
240
220
200
180
160
140
120
100
80
22
20
18
16
14
12
10
8
6
60
4
40
2
20
0
0
–600 –500 –400 –300 –200 –100
0
100 200 300 400 500
–100 –80 –60 –40 –20
0
20 40 60 80 100 120 140
OUTPUT OFFSET VOLTAGE (µV)
INPUT OFFSET VOLTAGE (µV)
Figure 6. Typical Distribution of Output Offset Voltage, VS = 5 V,
Single Supply, VREF = −0.125 V; Package Option N-8, R-8
Figure 3. Typical Distribution of Input Offset Voltage; Package Option N-8, R-8
210
180
150
120
90
480
420
360
300
240
180
120
60
60
30
0
0
–800 –600 –400 –200
0
200
400
600
800
–0.245 –0.240 –0.235 –0.230 –0.225 –0.220 –0.215 –0.210
OUTPUT OFFSET VOLTAGE (µV)
INPUT OFFSET CURRENT (nA)
Figure 7. Typical Distribution for Input Offset Current; Package Option N-8, R-8
Figure 4. Typical Distribution of Output Offset Voltage; Package Option N-8, R-8
20
18
16
14
12
10
8
22
20
18
16
14
12
10
8
6
6
4
4
2
2
0
0
–80 –60 –40 –20
0
20
40
60
80
100
–0.025 –0.020 –0.015 –0.010 –0.005
0
0.005 0.010
INPUT OFFSET VOLTAGE (µV)
INPUT OFFSET CURRENT (nA)
Figure 8. Typical Distribution for Input Offset Current, VS = 5 V,
Single Supply, VREF = −0.125 V; Package Option N-8, R-8
Figure 5. Typical Distribution of Input Offset Voltage, VS = 5 V,
Single Supply, VREF = −0.125 V; Package Option N-8, R-8
Rev. D | Page 8 of 24
AD623
1600
1400
1200
1000
800
600
400
200
0
30
25
20
15
10
5
0
75 80 85 90 95 100 105 110 115 120 125 130
CMRR (dB)
–60 –40 –20
0
20
40
60
80
100 120 140
TEMPERATURE (°C)
Figure 9. Typical Distribution for CMRR (G = 1)
Figure 12. IBIAS vs. Temperature
1k
100
10
1k
100
10
G = 1
G= 10
G= 100
G= 1000
1
10
100
FREQUENCY (Hz)
1k
1
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 13. Current Noise Spectral Density vs. Frequency
Figure 10. Voltage Noise Spectral Density vs. Frequency
20.0
22
19.5
19.0
18.5
18.0
17.5
17.0
16.5
16.0
21
20
19
18
17
16
15
14
–4
–3
–2
–1
0
1
2
–4
–2
0
2
4
CMV (V)
CMV (V)
Figure 14. IBIAS vs. CMV, VS = 2.5 V
Figure 11. IBIAS vs. CMV, VS = 5 V
Rev. D | Page 9 of 24
AD623
120
110
100
90
CH1 10mV
A
1s
100mV VERT
×1000
×100
80
70
60
×10
50
×1
40
30
1
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 15. 0.1 Hz to 10 Hz Current Noise (0.71 pA/DIV)
Figure 18. CMR vs. Frequency, 5 VS
70
60
1µV/DIV
1s
G = 1000
50
G = 100
G = 10
G = 1
40
30
20
10
0
–10
–20
–30
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 19. Gain vs. Frequency (VS = 5 V, 0 V), VREF = 2.5 V
Figure 16. 0.1 Hz to 10 Hz RTI Voltage Noise (1 DIV = 1 μV p-p)
120
110
5
4
3
V
= ±5V
S
100
×1000
2
90
V
= ±2.5V
S
×100
1
80
0
70
–1
–2
–3
–4
–5
×10
60
50
×1
40
30
1
10
100
1k
10k
100k
–6
–5
–4
–3
–2
–1
0
1
2
3
4
5
FREQUENCY (Hz)
COMMON-MODE INPUT (V)
Figure 20. Maximum Output Voltage vs. Common-Mode Input, G = 1, RL = 100 kΩ
Figure 17. CMR vs. Frequency, = 5 VS, 0 VS, VREF = 2.5 V
Rev. D | Page 10 of 24
AD623
5
4
140
120
100
80
V
= ±5V
S
V
= ±2.5V
S
G = 1000
3
2
G = 100
1
0
60
–1
–2
–3
–4
–5
G = 10
40
G = 1
20
0
–6
–5
–4
–3
–2
–1
0
1
2
3
4
5
1
10
100
1k
10k
100k
COMMON-MODE INPUT (V)
FREQUENCY (Hz)
Figure 21. Maximum Output Voltage vs. Common-Mode Input, G ≥ 10, RL = 100 Ω
Figure 24. Positive PSRR vs. Frequency, 5 VS
5
140
120
100
80
G = 1000
4
3
2
1
0
G = 100
60
G = 10
40
G = 1
20
0
–1
0
1
2
3
4
5
1
10
100
1k
10k
100k
COMMON-MODE INPUT (V)
FREQUENCY (Hz)
Figure 22. Maximum Output Voltage vs. Common-Mode Input,
G = 1, VS = 5 V, RL = 100 kΩ
Figure 25. Positive PSRR vs. Frequency, 5 VS, 0 VS
5
4
3
2
1
0
140
120
100
80
G = 1000
G = 100
G = 10
60
G = 1
40
20
0
–1
0
1
2
3
4
5
1
10
100
1k
10k
100k
COMMON-MODE INPUT (V)
FREQUENCY (Hz)
Figure 23. Maximum Output Voltage vs. Common-Mode Input,
G ≥ 10, VS = 5 V, RL = 100 kΩ
Figure 26. Negative PSRR vs. Frequency, 5 VS
Rev. D | Page 11 of 24
AD623
10
500µV
1V
10µs
8
6
4
V
= ±5V
S
V
= ±2.5V
S
2
0
0
20
40
60
80
100
FREQUENCY (kHz)
Figure 30. Large Signal Pulse Response and Settling Time,
G = −10 (0.250 mV = 0.01%), CL = 100 pF
Figure 27. Large Signal Response, G ≤ 10
1k
100
10
10mV
2V
50µs
1
1
10
100
1k
GAIN (V/V)
Figure 28. Settling Time to 0.01% vs. Gain, for a 5 V Step at Output,
CL = 100 pF, VS = 5 V
Figure 31. Large Signal Pulse Response and Settling Time,
G = 100, CL = 100 pF
500µV
1V
20µs
20mV
2V
500µs
Figure 32. Large Signal Pulse Response and Settling Time,
G = −1000 (5 mV = 0.01%), CL = 100 pF
Figure 29. Large Signal Pulse Response and Settling Time,
G = −1 (0.250 mV = 0.01%), CL = 100 pF
Rev. D | Page 12 of 24
AD623
20mV
2µs
20mV
500µs
Figure 33. Small Signal Pulse Response, G = 1, RL = 10 kΩ, CL = 100 pF
Figure 36. Small Signal Pulse Response, G = 1000, RL = 10 kΩ, CL = 100 pF
20mV
5µs
200µV
1V
Figure 34. Small Signal Pulse Response, G = 10, RL = 10 kΩ, CL = 100 pF
Figure 37. Gain Nonlinearity, G = −1 (50 ppm/DIV)
20mV
50µs
20µV
1V
Figure 35. Small Signal Pulse Response, G = 100, RL = 10 kΩ, CL = 100 pF
Figure 38. Gain Nonlinearity, G = −10 (6 ppm/DIV)
Rev. D | Page 13 of 24
AD623
V+
(V+) –0.5
(V+) –1.5
(V+) –2.5
(V–) +0.5
V–
50µV
1V
0
0.5
1.0
1.5
2.0
OUTPUT CURRENT (mA)
Figure 39. Gain Nonlinearity, G = −100, 15 ppm/DIV
Figure 40. Output Voltage Swing vs. Output Current
Rev. D | Page 14 of 24
AD623
THEORY OF OPERATION
The AD623 is an instrumentation amplifier based on a modified
classic 3-op-amp approach, to assure single or dual supply
operation even at common-mode voltages at the negative
supply rail. Low voltage offsets, input and output, as well as
absolute gain accuracy, and one external resistor to set the
gain, make the AD623 one of the most versatile instrumentation
amplifiers in its class.
The output voltage at Pin 6 is measured with respect to the
potential at Pin 5. The impedance of the reference pin is 100 kΩ;
therefore, in applications requiring V/I conversion, a small
resistor between Pin 5 and Pin 6 is all that is needed.
POSITIVE SUPPLY
7
The input signal is applied to PNP transistors acting as voltage
buffers and providing a common-mode signal to the input
amplifiers (see Figure 41). An absolute value 50 kΩ resistor in
each amplifier feedback assures gain programmability.
INVERTING
2
4
50kΩ
50kΩ
50kΩ
50kΩ
50kΩ
50kΩ
1
GAIN
8
OTUPUT
6
The differential output is
REF
5
⎛
⎜
⎝
100 kꢀ ⎞
⎜
⎟
VC
VO = 1+
7
4
⎟
RG
⎠
The differential voltage is then converted to a single-ended
voltage using the output amplifier, which also rejects any
common-mode signal at the output of the input amplifiers.
NONINVERTING
3
NEGATIVE SUPPLY
Because the amplifiers can swing to either supply rail, as well as
have their common-mode range extended to below the negative
supply rail, the range over which the AD623 can operate is further
enhanced (see Figure 20 and Figure 21).
Figure 41. Simplified Schematic
Note that the bandwidth of the in-amp decreases as gain is
increased. This occurs because the internal op-amps are the
standard voltage feedback design. At unity gain, the output
amplifier limits the bandwidth.
Rev. D | Page 15 of 24
AD623
APPLICATIONS INFORMATION
The input voltage, which can be either single-ended (tie either
−IN or +IN to ground), or differential is amplified by the
programmed gain. The output signal appears as the voltage
difference between the OUTPUT pin and the externally applied
voltage on the REF input. For a ground-referenced output, REF
should be grounded.
BASIC CONNECTION
Figure 42 and Figure 43 show the basic connection circuits for
the AD623. The +VS and −VS terminals are connected to the
power supply. The supply can be either bipolar (VS = 2.5 V to
6 V) or single supply (−VS = 0 V, +VS = 3.0 V to 12 V). Power
supplies should be capacitively decoupled close to the power pins of
the device. For the best results, use surface-mount 0.1 μF ceramic
chip capacitors and 10 μF electrolytic tantalum capacitors.
GAIN SELECTION
The gain of the AD623 is resistor programmed by RG, or more
precisely, by whatever impedance appears between Pin 1 and
Pin 8. The AD623 is designed to offer accurate gains using 0.1%
to 1% tolerance resistors. Table 5 shows the required values of
RG for the various gains. Note that for G = 1, the RG terminals
are unconnected (RG = ∞). For any arbitrary gain, RG can be
calculated by
+V
S
0.1µF
10µF
+2.5V TO +6V
R
G
V
V
R
OUTPUT
REF
OUT
IN
G
R
G
REF (INPUT)
RG = 100 kΩ/(G − 1)
0.1µF
10µF
REFERENCE TERMINAL
–V
S
–2.5V TO –6V
The reference terminal potential defines the zero output voltage
and is especially useful when the load does not share a precise
ground with the rest of the system. It provides a direct means of
injecting a precise offset to the output. The reference terminal is
also useful when bipolar signals are being amplified because it
can be used to provide a virtual ground voltage. The voltage on
the reference terminal can be varied from −VS to +VS.
Figure 42. Dual-Supply Basic Connection
+V
S
0.1µF
10µF
+3V TO +12V
R
R
G
V
V
R
OUTPUT
REF
OUT
IN
G
G
REF (INPUT)
Figure 43. Single-Supply Basic Connection
Table 5. Required Values of Gain Resistors
Desired Gain
1% Standard Table Value of RG (Ω)
100 k
Calculated Gain Using 1% Resistors
2
2
5
10
20
33
40
50
65
100
200
500
1000
24.9 k
11 k
5.02
10.09
20.12
33.36
40.21
49.78
64.29
99.04
201.4
501
5.23 k
3.09 k
2.55 k
2.05 k
1.58 k
1.02 k
499
200
100
1001
Rev. D | Page 16 of 24
AD623
the in-amp. Resistor R1 and Capacitor C1 (and likewise, R2 and
INPUT AND OUTPUT OFFSET VOLTAGE
C2) form a low-pass RC filter that has a −3 dB bandwidth equal
to F = 1/(2 π R1C1). Using the component values shown, this
filter has a −3 dB bandwidth of approximately 40 kHz. Resistors
R1 and R2 were selected to be large enough to isolate the input of
the circuit from the capacitors, but not large enough to significantly
increase the noise of the circuit. To preserve common-mode rejection
in the amplifier’s pass band, Capacitors C1 and C2 need to be 5%
or better units, or low cost 20% units can be tested and binned
to provide closely matched devices.
The low errors of the AD623 are attributed to two sources,
input and output errors. The output error is divided by the
programmed gain when referred to the input. In practice,
the input errors dominate at high gains and the output errors
dominate at low gains. The total VOS for a given gain is calculated
as the following:
Total Error RTI = Input Error + (Output Error/G)
Total Error RTO = (Input Error × G) + Output Error
+V
S
RTI offset errors and noise voltages for different gains are
shown in Table 6.
0.33µF
0.01µF
C1
1000pF
5%
R1
4.02kΩ
1%
INPUT PROTECTION
–IN
+IN
Internal supply referenced clamping diodes allow the input,
reference, output, and gain terminals of the AD623 to safely
withstand overvoltages of 0.3 V above or below the supplies.
This is true for all gains and for power on and power off. This
last case is particularly important because the signal source
and amplifier may be powered separately.
R2
4.02kΩ
1%
C3
0.047µF
R
V
AD623
G
OUT
REFERENCE
C2
1000pF
5%
0.33µF
0.01µF
+V
S
NOTES:
1. LOCATE C1 TO C3 AS CLOSE TO THE INPUT PINS AS POSSIBLE.
If the overvoltage is expected to exceed this value, the current
through these diodes should be limited to about 10 mA using
external current limiting resistors (see Figure 44). The size of
this resistor is defined by the supply voltage and the required
overvoltage protection.
Figure 45. Circuit to Attenuate RF Interference
Capacitor C3 is needed to maintain common-mode rejection at
the low frequencies. R1/R2 and C1/C2 form a bridge circuit whose
output appears across the input pins of the in-amp. Any mismatch
between C1 and C2 unbalances the bridge and reduces the
common-mode rejection. C3 ensures that any RF signals are
common mode (the same on both in-amp inputs) and are not
applied differentially. This second low-pass network, R1 + R2 and
C3, has a −3 dB frequency equal to 1/(2 π (R1 + R2) (C3)). Using a
C3 value of 0.047 μF, the −3 dB signal bandwidth of this circuit is
approximately 400 Hz. The typical dc offset shift over frequency is
less than 1.5 μV and the circuit’s RF signal rejection is better than
71 dB. The 3 dB signal bandwidth of this circuit may be increased
to 900 Hz by reducing Resistors R1 and R2 to 2.2 kΩ. The
performance is similar to using 4 kΩ resistors, except that the
circuitry preceding the in-amp must drive a lower impedance load.
+V
S
I = 10mA MAX
LIM
V
V
AD623
OVER
OVER
R
OUTPUT
R
G
V
–V + 0.7V
S
R
OVER
LIM
R
=
LIM
10mA
–V
S
Figure 44. Input Protection
RF INTERFERENCE
All instrumentation amplifiers can rectify high frequency out-
of-band signals. Once rectified, these signals appear as dc offset
errors at the output. The circuit in Figure 45 provides good RFI
suppression without reducing performance within the pass band of
Table 6. RTI Error Sources
Maximum Total Input Offset Error (μV)
Maximum Total Input Offset Drift (μV/°C)
Total Input Referred Noise (nV/√Hz)
Gain AD623A
AD623B
600
350
200
150
125
110
105
100
AD623A
AD623B
AD623A and AD623B
1
2
5
10
20
50
100
1200
700
400
300
250
220
210
12
7
4
11
6
3
62
45
38
35
35
35
35
35
3
2
2.5
2.2
2.1
2
1.5
1.2
1.1
1
1000 200
Rev. D | Page 17 of 24
AD623
The circuit in Figure 45 should be built using a PC board with a
ground plane on both sides. All component leads should be as
short as possible. Resistors R1 and R2 can be common 1% metal
film units, but Capacitors C1 and C2 need to be 5% tolerance
devices to avoid degrading the circuit’s common-mode rejection.
Either the traditional 5% silver mica units or Panasonic 2%
PPS film capacitors are recommended.
ground. The REF pin should, however, be tied to a low impedance
point for optimal CMR.
The use of ground planes is recommended to minimize the
impedance of ground returns (and hence the size of dc errors).
To isolate low level analog signals from a noisy digital environment,
many data acquisition components have separate analog and
digital ground returns (see Figure 47). All ground pins from
mixed signal components, such as analog-to-digital converters
(ADCs), should be returned through the high quality analog
ground plane. Maximum isolation between analog and digital is
achieved by connecting the ground planes back at the supplies.
The digital return currents from the ADC that flow in the analog
ground plane, in general, have a negligible effect on noise
performance.
In many applications, shielded cables are used to minimize
noise; for best CMR over frequency, the shield should be properly
driven. Figure 46 shows an active guard driver that is configured
to improve ac common-mode rejection by bootstrapping the
capacitances of input cable shields, thus minimizing the capacitance
mismatch between the inputs.
+V
S
If there is only a single power supply available, it must be shared
by both digital and analog circuitry. Figure 48 shows how to
minimize interference between the digital and analog circuitry.
–IN
2
1
7
R
2
G
100Ω
AD8031
6
AD623
OUTPUT
R
G
As in the previous case, separate analog and digital ground planes
should be used (reasonably thick traces can be used as an
alternative to a digital ground plane). These ground planes
should be connected at the ground pin of the power supply.
Separate traces should be run from the power supply to the
supply pins of the digital and analog circuits. Ideally, each device
should have its own power supply trace, but these can be shared
by a number of devices, as long as a single trace is not used to
route current to both digital and analog circuitry.
5
8
3
2
REF
4
+IN
–V
S
Figure 46. Common-Mode Shield Driver
GROUNDING
Because the AD623 output voltage is developed with respect to
the potential on the reference terminal, many grounding problems
can be solved by simply tying the REF pin to the appropriate local
ANALOG POWER SUPPLY
DIGITAL POWER SUPPLY
+5V
–5V
GND
GND
+5V
0.1µF 0.1µF
0.1µF
0.1µF
7
1
6
14
2
3
V
AGND DGND
AGND
V
4
DD
DD
12
6
4
3
AD623
V
IN1
ADC
MICROPROCESSOR
AD7892-2
5
V
IN2
Figure 47. Optimal Grounding Practice for a Bipolar Supply Environment with Separate Analog and Digital Supplies
POWER SUPPLY
+5V
GND
0.1µF
0.1µF
0.1µF
7
1
6
14
2
3
V
AGND DGND
AGND
V
DD
4
DD
V
IN1
12
6
4
AD623
ADC
MICROPROCESSOR
AD7892-2
5
Figure 48. Optimal Ground Practice in a Single Supply Environment
Rev. D | Page 18 of 24
AD623
Ground Returns for Input Bias Currents
Output Buffering
Input bias currents are those dc currents that must flow to bias
the input transistors of an amplifier. These are usually transistor
base currents. When amplifying floating input sources, such as
transformers or ac-coupled sources, there must be a direct dc
path into each input in order that the bias current can flow.
Figure 49, Figure 50, and Figure 51 show how a bias current
path can be provided for the cases of transformer coupling,
thermocouple, and capacitive ac coupling. In dc-coupled resistive
bridge applications, providing this path is generally not necessary
as the bias current simply flows from the bridge supply through
the bridge into the amplifier. However, if the impedances that
the two inputs see are large and differ by a large amount (>10 kΩ),
the offset current of the input stage causes dc errors
The AD623 is designed to drive loads of 10 kΩ or greater. If
the load is less than this value, the output of the AD623 should
be buffered with a precision single-supply op amp, such as the
OP113. This op amp can swing from 0 V to 4 V on its output
while driving a load as small as 600 Ω. Table 7 summarizes the
performance of some buffer op amps.
5V
5V
0.1µF
0.1µF
V
R
G
AD623
IN
OP113
V
OUT
REFERENCE
proportional with the input offset voltage of the amplifier.
Figure 52. Output Buffering
+V
S
–IN
Table 7. Buffering Options
Op Amp Description
2
1
7
OP113
OP191
Single supply, high output current
Rail-to-rail input and output, low supply current
R
6
AD623
OUTPUT
G
5
8
3
REF
4
+IN
LOAD
–V
S
Single-Supply Data Acquisition System
TO POWER
SUPPLY
GROUND
Interfacing bipolar signals to single-supply ADCs presents a
Figure 49. Ground Returns for Bias Currents with Transformer-Coupled Inputs
challenge. The bipolar signal must be mapped into the input
range of the ADC. Figure 53 shows how this translation can be
achieved.
+V
7
S
–IN
5V
2
1
5V
5V
0.1µF
0.1µF
R
6
AD623
OTUPUT
G
5
8
3
REF
AD7776
A
IN
R
G
4
AD623
±10mV
+IN
1.02kΩ
LOAD
–V
S
REFERENCE
TO POWER
SUPPLY
GROUND
REFOUT
REFIN
Figure 50. Ground Returns for Bias Currents with Thermocouple Inputs
+V
7
S
Figure 53. A Single-Supply Data Acquisition System
–IN
2
1
The bridge circuit is excited by a 5 V supply. The full-scale output
voltage from the bridge ( 10 mV) therefore has a common-
mode level of 2.5 V. The AD623 removes the common-mode
component and amplifies the input signal by a factor of 100
(RGAIN = 1.02 kΩ). This results in an output signal of 1 V. To
prevent this signal from running into the ground rail of the
AD623, the voltage on the REF pin must be raised to at least
1 V. In this example, the 2 V reference voltage from the AD7776
ADC is used to bias the output voltage of the AD623 to 2 V 1 V.
This corresponds to the input range of the ADC.
R
6
AD623
OUTPUT
G
5
8
3
REF
4
+IN
100kΩ
LOAD
100kΩ
–V
S
TO POWER
SUPPLY
GROUND
Figure 51. Ground Returns for Bias Currents with AC-Coupled Inputs
Rev. D | Page 19 of 24
AD623
Amplifying Signals with Low Common-Mode Voltage
the previous equations, the maximum and minimum input
common-mode voltages are given by the following equations:
Because the common-mode input range of the AD623 extends
0.1 V below ground, it is possible to measure small differential
signals which have low, or no, common-mode component.
Figure 54 shows a thermocouple application where one side
of the J-type thermocouple is grounded.
5V
VCMMAX = V+ − 0.7 V − VDIFF × Gain/2
V
CMMIN = V− − 0.590 V + VDIFF × Gain/2
These equations can be rearranged to give the maximum
possible differential voltage (positive or negative) for a
particular common-mode voltage, gain, and power supply.
Because the signals on A1 and A2 can clip on either rail, the
maximum differential voltage are the lesser of the two equations.
0.1µF
R
J-TYPE
THERMOCOUPLE
G
AD623
OUTPUT
2V
1.02kΩ
|VDIFFMAX| = 2 (V+ − 0.7 V − VCM/Gain
|VDIFFMAX| = 2 (VCM − V− +0.590 V/Gain
REF
However, the range on the differential input voltage range is
also constrained by the output swing. Therefore, the range of
VDIFF may have to be lower according the following equation.
Figure 54. Amplifying Bipolar Signals with Low Common-Mode Voltage
Over a temperature range of −200°C to +200°C, the J-type thermo-
couple delivers a voltage ranging from −7.890 mV to +10.777 mV.
A programmed gain on the AD623 of 100 (RG = 1.02 kΩ) and a
voltage on the REF pin of 2 V, results in the output voltage ranging
from 1.110 V to 3.077 V relative to ground.
Input Range ≤ Available Output Swing/Gain
For a bipolar input voltage with a common-mode voltage that is
roughly half way between the rails, VDIFFMAX is half the value that
the previous equations yield because the REF pin is at midsupply.
Note that the available output swing is given for different supply
conditions in the Specifications section.
INPUT DIFFERENTIAL AND COMMON-MODE RANGE
vs. SUPPLY AND GAIN
The equations can be rearranged to give the maximum gain for
a fixed set of input conditions. Again, the maximum gain will be
the lesser of the two equations.
Figure 55 shows a simplified block diagram of the AD623. The
voltages at the outputs of Amplifier A1 and Amplifier A2 are
given by
GainMAX = 2 (V+ − 0.7 V − VCM)/VDIFF
GainMAX = 2 (VCM − V− +0.590 V)/VDIFF
VA2 = VCM + VDIFF/2 + 0.6 V + VDIFF × RF/RG
= VCM + 0.6 V + VDIFF × Gain/2
VA1 = VCM + VDIFF/2 + 0.6 V + VDIFF × RF/RG
= VCM + 0.6 V − VDIFF × Gain/2
Again, it is recommended that the resulting gain times the input
range is less than the available output swing. If this is not the
case, the maximum gain is given by
POSITIVE SUPPLY
7
GainMAX = Available Output Swing/Input Range
INVERTING
Also for bipolar inputs (that is, input range = 2 VDIFF), the
maximum gain is half the value yielded by the previous equations
because the REF pin must be at midsupply.
2
A1
R
F
4
1
8
50kΩ
50kΩ
50kΩ
50kΩ
–
+
V
DIFF
2
The maximum gain and resulting output swing for different
input conditions is given in Table 8. Output voltages are
referenced to the voltage on the REF pin.
OUTPUT
6
GAIN
R
A3
50kΩ
G
V
CM
R
F
50kΩ
REF
5
7
For the purposes of computation, it is necessary to break down the
input voltage into its differential and common-mode component.
Therefore, when one of the inputs is grounded or at a fixed
voltage, the common-mode voltage changes as the differential
voltage changes. Take the case of the thermocouple amplifier
in Figure 54. The inverting input on the AD623 is grounded;
therefore, when the input voltage is −10 mV, the voltage on the
noninverting input is −10 mV. For the purpose of the signal swing
calculations, this input voltage should be composed of a common-
mode voltage of −5 mV (that is, (+IN + −IN)/2) and a differential
input voltage of −10 mV (that is, +IN − −IN).
–
+
V
DIFF
2
A2
NONINVERTING
3
4
NEGATIVE SUPPLY
Figure 55. Simplified Block Diagram
The voltages on these internal nodes are critical in determining
whether the output voltage will be clipped. The VA1 and VA2
voltages can swing from approximately 10 mV above the negative
supply (V− or ground) to within approximately 100 mV of the
positive rail before clipping occurs. Based on this and from
Rev. D | Page 20 of 24
AD623
Table 8. Maximum Attainable Gain and Resulting Output Swing for Different Input Conditions
Closest 1% Gain
VCM (V) VDIFF (V)
REF Pin (V) Supply Voltages (V) Maximum Gain Resistor (Ω)
Resulting Gain Output Swing (V)
0
0
0
0
10 m
100 m
10 m
100 m
1
10 m
100 m
1
10 m
100 m
10 m
100 m
2.5
2.5
0
0
0
2.5
2.5
2.5
1.5
1.5
1.5
1.5
+5
+5
5
5
5
+5
+5
+5
+3
+3
+3
+3
118
11.8
490
49
866
9.31 k
205
2.1 k
26.1 k
422
4.32 k
71.5 k
715
116
11.7
488
48.61
4.83
238
24.1
2.4
141
14
116
11.74
1.2
1.1
4.8
4.8
4.8
2.3
2.4
2.4
1.4
1.4
1.1
1.1
0
4.9
2.5
2.5
2.5
1.5
1.5
0
242
24.2
2.42
142
14.2
118
11.8
7.68 k
866
9.31 k
0
Rev. D | Page 21 of 24
AD623
OUTLINE DIMENSIONS
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
8
1
5
4
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
PLANE
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 56. 8-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body (N-8)
Dimensions shown in inches and (millimeters)
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 57. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
Rev. D | Page 22 of 24
AD623
3.20
3.00
2.80
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
0.65 BSC
0.95
0.85
0.75
1.10 MAX
0.80
0.60
0.40
8°
0°
0.15
0.00
0.38
0.22
0.23
0.08
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 58. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature
Range
Package
Option
Model
Package Description
Branding
AD623AN
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
8-Lead Plastic Dual In-Line Package [PDIP]
8-Lead Plastic Dual In-Line Package [PDIP]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N], 13" Tape and Reel
8-Lead Standard Small Outline Package [SOIC_N], 7" Tape and Reel
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N], 7" Tape and Reel
8-Lead SOIC, 13" Tape and Reel
N-8
N-8
R-8
R-8
R-8
R-8
R-8
R-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
N-8
N-8
R-8
R-8
R-8
R-8
R-8
AD623ANZ1
AD623AR
AD623AR-REEL
AD623AR-REEL7
AD623ARZ1
AD623ARZ-R71
AD623ARZ-RL1
AD623ARM
AD623ARM-REEL
AD623ARM-REEL7
AD623ARMZ1
AD623ARMZ-REEL1
AD623ARMZ-REEL71
AD623BN
8-Lead Mini Small Outline Package [MSOP]
J0A
J0A
J0A
J0A
J0A
J0A
8-Lead Mini Small Outline Package [MSOP], 13" Tape and Reel
8-Lead Mini Small Outline Package [MSOP], 7" Tape and Reel
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP], 13" Tape and Reel
8-Lead Mini Small Outline Package [MSOP], 7" Tape and Reel
8-Lead Plastic Dual In-Line Package [PDIP]
AD623BNZ1
AD623BR
8-Lead Plastic Dual In-Line Package [PDIP]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N], 13" Tape and Reel
8-Lead Standard Small Outline Package [SOIC_N], 7" Tape and Reel
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N], 7" Tape and Reel
8-Lead Standard Small Outline Package [SOIC_N], 13" Tape and Reel
Evaluation Board
AD623BR-REEL
AD623BR-REEL7
AD623BRZ1
AD623BRZ-R71
AD623BRZ-RL1
EVAL-INAMP-62RZ1
R-8
1 Z = RoHS Compliant Part.
Rev. D | Page 23 of 24
AD623
NOTES
©1997–2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00788-0-7/08(D)
Rev. D | Page 24 of 24
相关型号：
©2020 ICPDF网 联系我们和版权申明