EVAL-AVB-LISTENER_技术文档

Dual Port, Xpressview,

225 MHz HDMI Receiver

ADV7612

Data Sheet

Dedicated, flexible audio output port

FEATURES

Super audio CD (SACD) with DSD output interface

HBR audio

Dolby® TrueHD

DTS-HD Master Audio™

General

Interrupt controller with two interrupt outputs

Standard Identification (STDI) circuit

Highly flexible 36-bit pixel output interface

Internal EDID RAM

Any-to-any 3 × 3 color space conversion (CSC) matrix

2-layer PCB design supported

High-Definition Multimedia Interface (HDMI®) 1.4a features

supported

All mandatory and additional 3D video formats supported

Extended colorimetry, including sYCC601, Adobe RGB,

Adobe YCC 601, xvYCC extended gamut color

CEC 1.4-compatible

HDMI receiver

225 MHz maximum TMDS clock frequency

Xpressview fast switching of HDMI ports

36-/30-bit Deep Color and 24-bit color support

High-bandwidth Digital Content Protection (HDCP) 1.4

support with internal HDCP keys

100-lead LQFP_EP, 14 mm × 14 mm package

Qualified for Automotive Applications

HDCP repeater support

Up to 127 KSVs supported

Integrated CEC controller

Programmable HDMI equalizer

5 V detect and Hot Plug assert for each HDMI port

Audio support

Audio support including high bit rate (HBR) and direct

stream digital (DSD)

S/PDIF (IEC 60958-compatible) digital audio support

Supports up to four I²S outputs

APPLICATIONS

Projectors

Automotive

Video conferencing

HDTVs

AVR, HTiB

Soundbars

Video switches

Advanced audio mute feature

FUNCTIONAL BLOCK DIAGRAM

FAST

SWITCH

HS

VS/FIELD

DE

HS/VS

HDCP

KEYS

FIELD/DE

COMPONENT

PROCESSOR

36

LLC

36-BIT

YCbCr/RGB

DATA

TMDS

DDC

HDMI1

HDMI2

4

2

I S

DEEP

COLOR

HDMI Rx

AUDIO

S/PDIF

DSD

HBR

MCLK

SCLK

LRCLK

5

OUTPUT

MCLK

SCLK

TMDS

DDC

ADV7612

NOTES

1. LRCLK IS ACCESSIBLE THROUGH THE AP5 PIN.

Figure 1.

Rev. E

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Technical Support

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ADV7612

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Power-Up Sequence ................................................................... 11

Power-Down Sequence.............................................................. 11

Functional Overview...................................................................... 12

HDMI Receiver........................................................................... 12

Component Processor ............................................................... 12

Other Features ............................................................................ 12

Pixel Input/Output Formatting .................................................... 13

Pixel Data Output Modes Features .......................................... 13

Outline Dimensions....................................................................... 17

Ordering Guide .......................................................................... 17

Automotive Products................................................................. 17

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

General Description......................................................................... 3

Detailed Functional Block Diagram .......................................... 3

Specifications..................................................................................... 4

Electrical Characteristics............................................................. 4

Data and I²C Timing Characteristics......................................... 5

Absolute Maximum Ratings............................................................ 7

Package Thermal Performance................................................... 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Power Supply Sequencing.............................................................. 11

REVISION HISTORY

1/14—Rev. D to Rev. E

6/11—Rev. B to Rev. C

Changes to PLL Supply Current Parameter, Table 1 .................... 4

Changes to Pin 96 and Pin 100, Table 4....................................... 10

Changes to Figure 7...........................................................................9

Updated Outline Dimensions....................................................... 19

6/11—Rev. A to Rev. B

5/12—Rev. C to Rev. D

Changes to Data Output Transition Time (t₁₁), Table 2 ...............5

Changes to Pin 17 and Pin 18 Description, Table 4................... 10

Changes to Pin 87 and Pin 89 Description, Table 4................... 11

Changes to Features Section............................................................ 1

Changes to General Description Section and Figure 2 ............... 3

Added Endnote 3 (Table 1) ............................................................. 4

Deleted TDM Serial Timing Parameter (Table 2)........................ 5

Changes to Figure 5.......................................................................... 6

Deleted Figure 6................................................................................ 7

Changed Pin 75 to AP1 in Figure 7 and Table 4........................... 9

Changed Pin 89 and Pin 90 Descriptions (Table 4)................... 10

Changes to HDMI Receiver and Other Features Sections........ 12

Deleted Time-Division Multiplexed (TDM) Mode Section

and Figure 9..................................................................................... 13

Added Endnote 1 in Pixel Input/Output Formatting Section and

Endnote 1 to Table 5....................................................................... 15

Changes to Ordering Guide .......................................................... 18

4/11—Rev. 0 to Rev. A

Changes to Features Section ............................................................1

Changes to Ordering Guide.......................................................... 19

Added Automotive Products Section .......................................... 19

11/10—Revision 0: Initial Version

Rev. E | Page 2 of 20

Data Sheet

ADV7612

GENERAL DESCRIPTION

The ADV7612 is offered in automotive, professional (no HDCP),

and industrial versions. The operating temperature range is

−40°C to +85°C.

Each HDMI port has dedicated 5 V detect and Hot Plug™ assert

pins. The HDMI receiver also includes an integrated program-

mable equalizer that ensures robust operation of the interface

with long cables.

The UG-216 contains critical information that must be used in

conjunction with the ADV7612.

The ADV7612 offers a flexible audio output port for audio data

extraction from the HDMI stream. HDMI audio formats,

including SACD via DSD and HBR, are supported by ADV7612.

The HDMI receiver has advanced audio functionality, such as a

mute controller that prevents audible extraneous noise in the

audio output.

The ADV7612 is a high quality Xpressview™ fast switching

HDMI®-capable receiver. It incorporates a dual input HDMI-

capable receiver that supports all mandatory 3D TV formats

defined in HDMI 1.4a specification, HDTV formats up to

1080p 36-bit Deep Color, and display resolutions up to UXGA

(1600 × 1200 at 60 Hz).

The ADV7612 contains one main component processor (CP)

that processes the video signals from the HDMI receiver. It

provides features such as contrast, brightness and saturation

adjustments, STDI detection block, free run, and synchronization

alignment controls.

It integrates a CEC controller that supports the capability

discovery and control (CDC) feature.

The ADV7612 incorporates Xpressview fast switching on both

input HDMI ports. Using Analog Devices, Inc., hardware-based

HDCP engine that minimizes software overhead, Xpressview

technology allows fast switching between both HDMI input ports

in less than 1 second.

Fabricated in an advanced CMOS process, the ADV7612 is

provided in a 14 mm × 14 mm, 100-lead surface-mount LQFP_EP,

RoHS-compliant package, and is specified over the −40°C to

+85°C temperature range.

DETAILED FUNCTIONAL BLOCK DIAGRAM

XTALP

XTALN

DPLL

12

P0 TO P11

12

P12 TO P23

SCL

SDA

12

P24 TO P25

CONTROL

INTERFACE

CS

LLC

2

I C

BACKEND

CEC

CONTROLLER

COLOR SPACE

CEC

HS

CONVERSION

CONTROL

AND DATA

VS/FIELD/ALSB

DE

RXA_5V

RXB_5V

HPA_A/INT2*

5V DETECT

AND HPD

CONTROLLER

INT1

INT2*

INTERRUPT

CONTROLLER

(INT1, INT2)

HPA_B

HDMI

PROCESSOR

DDCA_SDA

DDCA_SCL

EDID

REPEATER

CONTROLLER

COMPONENT

PROCESSOR

HDCP

EEPROM

AP1

AP2

AP3

AP4

DDCB_SDA

DDCB_SCL

A

B

C

DATA

PREPROCESOR

AND COLOR

SPACE

RXA_C±

RXB_C±

PLL

HDCP

ENGINE

CONVERSION

AP5

SCLK/INT2*

RXA_0±

RXA_1±

RXA_2±

PACKET/

INFOFRAME

MEMORY

EQUALIZER

SAMPLER

MUTE

PACKET

PROCESSOR

MCLK/INT2*

AP0

RXB_0±

RXB_1±

RXB_2±

AUDIO

PROCESSOR

ADV7612

*INT2 CAN BE ONLY OUTPUT ON ONE OF THE PINS: SCLK/INT2, MCLK/INT2, OR HPA_A/INT2.

Figure 2. Detailed Functional Block Diagram

Rev. E | Page 3 of 20

ADV7612

Data Sheet

SPECIFICATIONS

At DVDD = 1.71 V to 1.89 V, DVDDIO = 3.14 V to 3.46 V, PVDD = 1.71 V to 1.89 V, TVDD = 3.14 V to 3.46 V, CVDD = 1.71 V to 1.89 V,

Operating temperature range, unless otherwise noted.

ELECTRICAL CHARACTERISTICS

Table 1.

Parameter

DIGITAL INPUTS¹

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

Input High Voltage

V_IH

V_IL

I_IN

XTALN and XTALP

Other digital inputs

XTALN and XTALP

Other digital inputs

RESET pin

1.2

2

V

µA

pF

Input Low Voltage

Input Current

0.4

0.8

60

45

10

CS pin

60

Other digital inputs

Input Capacitance

DIGITAL INPUTS (5 V TOLERANT)^{1, 2}

Input High Voltage

Input Low Voltage

C_IN

10

V_IH

V_IL

I_IN

2.6

V

µA

0.8

+82

Input Current

−82

2.4

DIGITAL OUTPUTS¹

Output High Voltage

Output Low Voltage

V_OH

V_OL

I_LEAK

V

µA

0.4

60

High Impedance Leakage

Current

VS/FIELD/ALSB pin

35

10

HPA_A/INT2, HPA_B pin

Digital inputs other than XTALN

and XTALP

82

20

µA

Output Capacitance

POWER REQUIREMENTS^3,4

Digital Core Power Supply

Digital I/O Power Supply

PLL Power Supply

Terminator Power Supply

Comparator Power Supply

Digital Core Supply Current

Digital I/O Supply Current

PLL Supply Current

Terminator Supply Current

Comparator Supply Current

POWER-DOWN CURRENTS^3,6

Digital Core Supply Current

Digital I/O Supply Current

PLL Supply Current

Terminator Supply Current

Comparator Supply Current

Power-Up Time

C_OUT

pF

DVDD

DVDDIO

PVDD

TVDD

CVDD

I_DVDD

I_DVDDIO

I_PVDD

I_TVDD

1.71

3.14

1.71

3.14

1.71

1.8

3.3

1.8

3.3

1.8

149.5

9.9

36.9

121.4

187.0

1.89

3.46

1.89

3.46

V

1.89

V

Dual 1080p60 12 bit with BG⁵port

201.9

178.5

39.2

134.5

210.9

mA

I_CVDD

I_{DVDD_PD}

I_{DVDDIO_PD}

I_{PVDD_PD}

I_{TVDD_PD}

I_{CVDD_PD}

t_PWRUP

0.3

1.3

1.5

0.1

1.3

25

0.4

1.7

1.8

0.3

1.7

mA

ms

¹Data guaranteed by characterization.

²The following pins are 5 V tolerant: DDCA_SCL, DDCA_SDA, DDCB_SCL, DDCB_SDA, RXA_5V, and RXB_5V.

³Data recorded during lab characterization

⁴Maximum current consumption values are recorded with maximum rated voltage supply levels, MoireX video pattern, and at maximum rated temperature.

⁵BG = background.

⁶Power-Down Mode 0 (IO map, Register 0x0C = 0x62), ring oscillator powered down (HDMI map, Register 0x48 = 0x01), and DDC pads off (HDMI map, Register 0x73 = 0x03).

Rev. E | Page 4 of 20

Data Sheet

ADV7612

DATA AND I²C TIMING CHARACTERISTICS

Table 2.

Parameter

Symbol Test Conditions/Comments

Min

Typ

Max

Unit

CLOCK AND CRYSTAL

Crystal Frequency, XTALP

Crystal Frequency Stability

LLC Frequency Range

I²C PORTS

28.63636

MHz

ppm

MHz

50

170

13.5

SCL Frequency

400

kHz

ns

µs

ns

µs

SCL Minimum Pulse Width High¹

SCL Minimum Pulse Width Low¹

Start Condition Hold Time¹

Start Condition Setup Time¹

SDA Setup Time¹

t₁

t₂

t₃

t₄

t₅

t₆

t₇

t₈

600

1.3

600

100

SCL and SDA Rise Time¹

SCL and SDA Fall Time¹

Stop Condition Setup Time¹

RESET FEATURE

300

0.6

5

Reset Pulse Width

ms

CLOCK OUTPUTS

LLC Mark-Space Ratio¹

DATA AND CONTROL OUTPUTS²

Data Output Transition Time¹

t₉:t₁₀

45:55

55:45 % duty cycle

t₁₁

t₁₂

End of valid data to negative clock edge

Negative clock edge to start of valid data

1.0

0.0

2.2

0.3

ns

I²S PORT, MASTER MODE

SCLK Mark-Space Ratio¹

LRCLK Data Transition Time¹

t₁₅:t₁₆

t₁₇

t₁₈

t₁₉

t₂₀

45:55

55:45 % duty cycle

End of valid data to negative SCLK edge

Negative SCLK edge to start of valid data

End of valid data to negative SCLK edge

Negative SCLK edge to start of valid data

10

5

ns

I²S Data Transition Time¹

5

¹Data guaranteed by characterization.

²With the DLL block on output clock bypassed.

Rev. E | Page 5 of 20

ADV7612

Data Sheet

Timing Diagrams

t₃

t₅

t₃

SDA

SCL

t₆

t₁

t₂

t₇

t₄

t₈

Figure 3. I²C Timing

t₉

t₁₀

LLC

t₁₁

t₁₂

P0 TO P23, HS,

VS/FIELD/ALSB, DE

Figure 4. Pixel Port and Control SDR Output Timing

t₁₅

t₁₆

t₁₇

LRCLK

t₁₈

t₁₉

2

I S

LEFT-JUSTIFIED

MODE

MSB

MSB – 1

t₂₀

t₁₉

2

I S

2

MSB

MSB – 1

I S MODE

t₂₀

t₁₉

2

I S

RIGHT-JUSTIFIED

MODE

MSB

LSB

t₂₀

NOTES

1. LRCLK IS A SIGNAL ACCESSIBLE VIA AP5 PIN.

2

2. I S SIGNALS ARE ACCESSIBLE VIA THE AP1 TO AP4 PINS.

Figure 5. I²S Timing

Rev. E | Page 6 of 20

Data Sheet

ADV7612

ABSOLUTE MAXIMUM RATINGS

Table 3.

PACKAGE THERMAL PERFORMANCE

To reduce power consumption when using the ADV7612, the

user is advised to turn off the unused sections of the part.

Parameter

Rating

DVDD to GND

2.2 V

Due to the printed circuit board (PCB) metal variation and,

therefore, variation in PCB heat conductivity, the value of θ_JA

may differ for various PCBs.

PVDD to GND

DVDDIO to GND

CVDD to GND

2.2 V

4.0 V

2.2 V

TVDD to GND

Digital Inputs Voltage to GND

5 V Tolerant Digital Inputs to

GND¹

4.0 V

The most efficient measurement solution is obtained using the

package surface temperature to estimate the die temperature

because this eliminates the variance associated with the θ_JAvalue.

GND − 0.3 V to DVDDIO + 0.3 V

5.3 V

The maximum junction temperature (T_{J MAX}) of 125°C must not be

exceeded. The following equation calculates the junction tempera-

ture using the measured package surface temperature and applies

only when no heat sink is used on the device under test (DUT):

Digital Outputs Voltage to GND

XTALP, XTALN

SCL/SDA Data Pins to DVDDIO

GND − 0.3 V to DVDDIO + 0.3 V

−0.3 V to PVDD + 0.3 V

DVDDIO − 0.3 V to DVDDIO +

3.6 V

Maximum Junction

Temperature (T_{J MAX}

125°C

T_J= T_S+

(

Ψ _JT×W_TOTAL

)

where:

Storage Temperature Range

−60°C to +150°C

T_Sis the package surface temperature (°C).

Ψ_JT= 0.3°C/W for the 100-lead LQFP_EP.

Infrared Reflow Soldering (20 sec) 260°C

¹The following inputs are 3.3 V inputs but are 5 V tolerant: DDCA_SCL,

DDCA_SDA, DDCB_SCL, and DDCB_SDA.

W_TOTAL= ((PVDD × I_PVDD) + (0.05 × TVDD × I_TVDD) + (CVDD ×

I

_CVDD) + (DVDD × I_DVDD) + (DVDDIO × I_DVDDIO))

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

where 0.05 is 5% of the TVDD power that is dissipated on the

part itself.

ESD CAUTION

Rev. E | Page 7 of 20

ADV7612

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

1

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

AP1

CVDD

2

AP0

RXA_C–

3

VS/FIELD/ALSB

RXA_C+

4

HS

TVDD

5

DE

RXA_0–

6

DVDDIO

P0

RXA_0+

7

TVDD

8

P1

RXA_1–

9

P2

RXA_1+

10

P3

TVDD

11

P4

RXA_2–

ADV7612

TOP VIEW

(Not to Scale)

12

P5

RXA_2+

CVDD

13

14

15

16

17

18

19

20

21

22

23

24

25

P6

DVDD

P7

RXB_C–

RXB_C+

TVDD

P8

P9

RXB_0–

RXB_0+

TVDD

P10

P11

P12

P13

DVDDIO

P14

P15

P16

RXB_1–

RXB_1+

TVDD

RXB_2–

RXB_2+

CVDD

NOTES

1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.

2. CONNECT EXPOSED PAD (PIN0) TO GROUND (BOTTOM).

Figure 6. Pin Configuration

Table 4. Pin Function Descriptions

No.

Mnemonic

GND

Type

Description

0

Ground

Ground.

1

CVDD

Power

HDMI Analog Block Supply Voltage (1.8 V).

2

RXA_C−

RXA_C+

TVDD

HDMI input

Power

Digital Input Clock Complement of Port A in the HDMI Interface.

Digital Input Clock True of Port A in the HDMI Interface.

Terminator Supply Voltage (3.3 V).

3

4

5

6

7

RXA_0−

RXA_0+

TVDD

HDMI input

Power

Digital Input Channel 0 Complement of Port A in the HDMI Interface.

Digital Input Channel 0 True of Port A in the HDMI Interface.

Terminator Supply Voltage (3.3 V).

8

9

RXA_1−

RXA_1+

TVDD

HDMI input

Power

Digital Input Channel 1 Complement of Port A in the HDMI Interface.

Digital Input Channel 1 True of Port A in the HDMI Interface.

Terminator Supply Voltage (3.3 V).

10

11

12

13

14

RXA_2−

RXA_2+

CVDD

HDMI input

Power

Digital Input Channel 2 Complement of Port A in the HDMI Interface.

Digital Input Channel 2 True of Port A in the HDMI Interface.

HDMI Analog Block Supply Voltage (1.8 V).

RXB_C−

HDMI input

Digital Input Clock Complement of Port B in the HDMI Interface.

Rev. E | Page 8 of 20

Data Sheet

ADV7612

No.

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

Mnemonic

RXB_C+

TVDD

RXB_0−

RXB_0+

TVDD

RXB_1−

RXB_1+

TVDD

RXB_2−

RXB_2+

CVDD

NC

Type

Description

HDMI input

Digital Input Clock True of Port B in the HDMI Interface.

Terminator Supply Voltage (3.3 V).

Digital Input Channel 0 Complement of Port B in the HDMI Interface.

Digital Input Channel 0 True of Port B in the HDMI Interface.

Terminator Supply Voltage (3.3 V).

Digital Input Channel 1 Complement of Port B in the HDMI Interface.

Digital Input Channel 1 True of Port B in the HDMI Interface.

Terminator Supply Voltage (3.3 V).

Digital Input Channel 2 Complement of Port B in the HDMI Interface.

Digital Input Channel 2 True of Port B in the HDMI Interface.

HDMI Analog Block Supply Voltage (1.8 V).

No connect.

Power

HDMI input

Power

HDMI input

Power

HDMI input

Power

No connect

P35

Digital video output

Power

Video Pixel Output Port.

P34

Video Pixel Output Port.

DVDDIO

P33

Digital I/O Supply Voltage (3.3 V).

Video Pixel Output Port.

Digital video output

Power

P32

Video Pixel Output Port.

P31

Video Pixel Output Port.

P30

Video Pixel Output Port.

P29

Video Pixel Output Port.

P28

Video Pixel Output Port.

P27

Video Pixel Output Port.

DVDDIO

P26

Digital I/O Supply Voltage (3.3 V).

Video Pixel Output Port.

Digital video output

Power

P25

Video Pixel Output Port.

P24

Video Pixel Output Port.

DVDD

LLC

Digital Core Supply Voltage (1.8 V).

Digital video output

No connect

Line-Locked Output Clock for the Pixel Data (Range is 13.5 MHz to 170 MHz).

Video Pixel Output Port.

P23

P22

Video Pixel Output Port.

P21

Video Pixel Output Port.

P20

Video Pixel Output Port.

P19

Video Pixel Output Port.

P18

Video Pixel Output Port.

P17

Video Pixel Output Port.

NC

No connect.

P16

Digital video output

Power

Video Pixel Output Port.

P15

Video Pixel Output Port.

P14

Video Pixel Output Port.

DVDDIO

P13

Digital I/O Supply Voltage (3.3 V).

Video Pixel Output Port.

Digital video output

Power

P12

Video Pixel Output Port.

P11

Video Pixel Output Port.

P10

Video Pixel Output Port.

P9

Video Pixel Output Port.

P8

Video Pixel Output Port.

P7

Video Pixel Output Port.

DVDD

P6

Digital Core Supply Voltage (1.8 V).

Video Pixel Output Port.

Digital video output

P5

Video Pixel Output Port.

P4

Video Pixel Output Port.

Rev. E | Page 9 of 20

ADV7612

Data Sheet

No.

66

67

68

69

70

71

72

73

Mnemonic

Type

Description

P3

Digital video output

Power

Video Pixel Output Port.

P2

Video Pixel Output Port.

P1

Video Pixel Output Port.

P0

Video Pixel Output Port.

DVDDIO

DE

Digital I/O Supply Voltage (3.3 V).

DE (data enable) is a signal that indicates active pixel data.

HS is a horizontal synchronization output signal.

Miscellaneous digital

Digital video output

HS

VS/FIELD/ALSB Digital video output

VS is a vertical synchronization output signal. FIELD is a field synchronization output

signal in all interlaced video modes. VS or FIELD can be configured for this pin. ALSB

allows selection of the I²C address.

74

75

76

77

78

79

80

81

AP0

Miscellaneous digital

Miscellaneous ditial

Miscellaneous digital

Miscellaneous