EVAL-ADF4158EB1Z [ADI]
Direct Modulation/Waveform Generating, 6.1 GHz Fractional-N Frequency Synthesizer; 直接调制/波形产生6.1 GHz的分数N频率合成器
| 型号： | EVAL-ADF4158EB1Z |
| 厂家： | 
ADI |
| 描述： | Direct Modulation/Waveform Generating, 6.1 GHz Fractional-N Frequency Synthesizer |
| 文件： | 总36页 (文件大小：455K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Direct Modulation/Waveform Generating,
6.1 GHz Fractional-N Frequency Synthesizer
ADF4158
FEATURES
GENERAL DESCRIPTION
RF bandwidth to 6.1 GHz
The ADF4158 is a 6.1 GHz, fractional-N frequency synthesizer
25-bit fixed modulus allows subhertz frequency resolution
Frequency and phase modulation capability
Sawtooth and triangular waveforms in the frequency domain
Parabolic ramp
Ramp superimposed with FSK
Ramp with 2 different sweep rates
Ramp delay
Ramp frequency readback
Ramp interruption
2.7 V to 3.3 V power supply
Separate VP allows extended tuning voltage
Programmable charge pump currents
3-wire serial interface
Digital lock detect
Power-down mode
with modulation and waveform generation capability. It con-
tains a 25-bit fixed modulus, allowing subhertz resolution at
6.1 GHz. It consists of a low noise digital phase frequency
detector (PFD), a precision charge pump, and a programmable
reference divider. There is a sigma-delta (Σ-Δ) based fractional
interpolator to allow programmable fractional-N division. The
INT and FRAC registers define an overall N-divider as N = INT
+ (FRAC/225).
The ADF4158 can be used to implement frequency shift keying
(FSK) and phase shift keying (PSK) modulation. There are also
a number of frequency sweep modes available, which generate
various waveforms in the frequency domain, for example,
sawtooth and triangular waveforms. The ADF4158 features
cycle slip reduction circuitry, which leads to faster lock times,
without the need for modifications to the loop filter.
Cycle slip reduction for faster lock times
Switched bandwidth fast-lock mode
Control of all on-chip registers is via a simple 3-wire inter-
face. The device operates with a power supply ranging from
2.7 V to 3.3 V and can be powered down when not in use.
APPLICATIONS
FMCW radar
Communications test equipment
FUNCTIONAL BLOCK DIAGRAM
AV
DD
DV
DD
V
R
SET
P
ADF4158
SW2
CP
REFERENCE
5-BIT
R-COUNTER
×2
REF
IN
DOUBLER
÷2
DIVIDER
+
PHASE
CHARGE
PUMP
FREQUENCY
DETECTOR
V
DD
–
HIGH-Z
CSR
DGND
LOCK
DETECT
SW1
FL SWITCH
O
OUTPUT
MUX
MUXOUT
CE
V
DD
R
N
DIV
DIV
RF
A
B
IN
N-COUNTER
TX
DATA
RF
IN
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
CLK
MODULUS
25
2
FRACTION
REG
INTEGER
REG
32-BIT
DATA
REGISTER
DATA
LE
AGND
DGND
CPGND
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2010 Analog Devices, Inc. All rights reserved.
ADF4158
TABLE OF CONTENTS
Features .............................................................................................. 1
R-Divider Register (R2) Map.................................................... 16
Function Register (R3) Map...................................................... 18
Test Register (R4) Map .............................................................. 20
Deviation Register (R5) Map .................................................... 21
Step Register (R6) Map.............................................................. 22
Delay Register (R7) Map ........................................................... 23
Applications Information .............................................................. 24
Initialization Sequence............................................................... 24
RF Synthesizer: A Worked Example ........................................ 24
Reference Doubler and Reference Divider ............................. 24
Cycle Slip Reduction for Faster Lock Times........................... 24
Modulation.................................................................................. 25
Waveform Generation ............................................................... 25
Additional Features.................................................................... 27
Fast-Lock Timer and Register Sequences ............................... 30
Fast Lock: An Example .............................................................. 30
Fast Lock: Loop Filter Topology............................................... 30
Spur Mechanisms ....................................................................... 31
Low Frequency Applications .................................................... 31
Filter Design—ADIsimPLL....................................................... 31
PCB Design Guidelines for the Chip Scale Package.............. 31
Application of ADF4158 in FMCW Radar ................................. 32
Outline Dimensions ....................................................................... 33
Ordering Guide........................................................................... 33
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 4
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Pin Function Descriptions...................... 7
Typical Performance Characteristics ............................................. 8
Circuit Description......................................................................... 10
Reference Input Section............................................................. 10
RF Input Stage............................................................................. 10
RF INT Divider........................................................................... 10
25-Bit Fixed Modulus ................................................................ 10
INT, FRAC, and R Relationship ............................................... 10
R-Counter.................................................................................... 10
Phase Frequency Detector (PFD) and Charge Pump............ 11
MUXOUT and LOCK Detect................................................... 11
Input Shift Registers................................................................... 11
Program Modes .......................................................................... 11
Register Maps.................................................................................. 12
FRAC/INT Register (R0) Map.................................................. 14
LSB FRAC Register (R1) Map................................................... 15
REVISION HISTORY
4/10—Revision 0: Initial Version
Rev. 0 | Page 2 of 36
ADF4158
SPECIFICATIONS
AVDD = DVDD = 2.7 V to 3.3 V, VP = AVDD to 5.5 V, AGND = DGND = 0 V, TA = TMIN to TMAX, dBm referred to 50 Ω, unless
otherwise noted.
Table 1.
C Version1
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
RF CHARACTERISTICS
RF Input Frequency (RFIN)
0.5
6.1
GHz
−10 dBm min to 0 dBm max; for lower frequencies, ensure
slew rate (SR) > 400 V/μs
−15 dBm min to 0 dBm max for 2 GHz to 4 GHz RF input
frequency
REFERENCE CHARACTERISTICS
REFIN Input Frequency
10
260
MHz
For f < 10 MHz, use a dc-coupled CMOS-compatible
square wave, slew rate > 25 V/μs
16
AVDD
10
MHz
V p-p
pF
If an internal reference doubler is enabled
Biased at AVDD/22
REFIN Input Sensitivity
REFIN Input Capacitance
REFIN Input Current
PHASE DETECTOR
Phase Detector Frequency3
CHARGE PUMP
0.4
100
μA
32
MHz
ICP Sink/Source
Programmable
High Value
Low Value
Absolute Accuracy
RSET Range
ICP Three-State Leakage Current
Matching
ICP vs. VCP
ICP vs. Temperature
LOGIC INPUTS
VINH, Input High Voltage
VINL, Input Low Voltage
IINH/IINL, Input Current
CIN, Input Capacitance
LOGIC OUTPUTS
VOH, Output High Voltage
VOH, Output High Voltage
IOH, Output High Current
VOL, Output Low Voltage
POWER SUPPLIES
AVDD
5
mA
μA
%
kΩ
nA
%
With RSET = 5.1 kΩ
312.5
2.5
With RSET = 5.1 kΩ
2.7
1.4
10
1
2
2
2
Sink and source current
0.5 V < VCP < VP – 0.5 V
0.5 V < VCP < VP – 0.5 V
VCP = VP/2
%
%
V
V
μA
pF
0.6
1
10
1.4
VDD − 0.4
V
V
μA
V
Open-drain output chosen; 1 kΩ pull-up to 1.8 V
CMOS output chosen
100
0.4
IOL = 500 μA
2.7
3.3
V
DVDD
VP
IDD
AVDD
23
AVDD
5.5
32
V
mA
Rev. 0 | Page 3 of 36
ADF4158
C Version1
Typ
Parameter
Min
Max
Unit
Test Conditions/Comments
NOISE CHARACTERISTICS
Normalized Phase Noise Floor4
Phase Noise Performance5
5805 MHz Output6
−213
−93
dBc/Hz
dBc/Hz
@ VCO output
@ 5 kHz offset, 32 MHz PFD frequency
1 Operating temperature for C version: −40°C to +125°C.
2 AC-coupling ensures AVDD/2 bias.
3 Guaranteed by design. Sample tested to ensure compliance.
4 This figure can be used to calculate phase noise for any application. Use the formula –213 + 10 log(fPFD) + 20 logN to calculate in-band phase noise performance as
seen at the VCO output.
5 The phase noise is measured with the EVAL-ADF4158EB1Z and the Agilent E5052A phase noise system.
6 fREFIN = 128 MHz; fPFD = 32 MHz; offset frequency = 5 kHz; RFOUT = 5805 MHz; INT = 181; FRAC = 13631488; loop bandwidth = 100 kHz.
TIMING SPECIFICATIONS
AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = SDGND = 0 V; TA = TMIN to TMAX, dBm referred to 50 Ω,
unless otherwise noted.
Table 2. Write Timing
Parameter
Limit at TMIN to TMAX (C Version)
Unit
Test Conditions/Comments
LE setup time
DATA to CLK setup time
DATA to CLK hold time
CLK high duration
CLK low duration
t1
t2
t3
t4
t5
t6
t7
20
10
10
25
25
10
20
ns min
ns min
ns min
ns min
ns min
ns min
ns min
CLK to LE setup time
LE pulse width
Write Timing Diagram
t4
t5
CLK
t2
t3
DB2
(CONTROL BIT C3)
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
DB31 (MSB)
DB30
DATA
LE
t7
t1
t6
LE
Figure 2. Write Timing Diagram
Rev. 0 | Page 4 of 36
ADF4158
Table 3. Read Timing
Parameter
Limit at TMIN to TMAX (C Version)
Unit
Test Conditions/Comments
t1
t2
t3
t4
t5
t6
20
10
10
25
25
10
ns min
ns min
ns min
ns min
ns min
ns min
TXDATA setup time
DATA (on MUXOUT) to CLK setup time
DATA (on MUXOUT) to CLK hold time
CLK high duration
CLK low duration
CLK to LE setup time
Read Timing Diagram
TX
DATA
t1
t4
t5
CLK
t2
t3
DB2
DB1
DB36
DB35
MUXOUT
DB0
t6
LE
Figure 3. Read Timing Diagram
Rev. 0 | Page 5 of 36
ADF4158
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, GND = AGND = DGND = SDGND = 0 V,
V
DD = AVDD = DVDD = SDVDD, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 4.
Parameter
VDD to GND
VDD to VDD
VP to GND
VP to VDD
Digital I/O Voltage to GND
Analog I/O Voltage to GND
REFIN, RFIN to GND
Operating Temperature Range
Industrial (C Version)
Storage Temperature Range
Maximum Junction Temperature
Rating
−0.3 V to +4 V
−0.3 V to +0.3 V
−0.3 V to +5.8 V
−0.3 V to +5.8 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
ESD CAUTION
−40°C to +125°C
−65°C to +125°C
150°C
LFCSP θJA Thermal Impedance
(Paddle Soldered)
30.4°C/W
Reflow Soldering
Peak Temperature
Time at Peak Temperature
260°C
40 sec
Rev. 0 | Page 6 of 36
ADF4158
PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
CPGND
AGND
AGND
1
2
3
4
5
6
18 SDV
DD
17 MUXOUT
16 LE
15 DATA
14 CLK
13 CE
ADF4158
TOP VIEW
(Not to Scale)
RF
RF
B
IN
A
IN
AV
DD
NOTES
1. THE LFCSP HAS AN EXPOSED PADDLE THAT MUST BE CONNECTED TO GND.
Figure 4. LFCSP Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic Description
1
2, 3
4
CPGND
AGND
RFINB
Charge Pump Ground. This is the ground return path for the charge pump.
Analog Ground. This is the ground return path of the prescaler.
Complementary Input to the RF Prescaler. Decouple this point to the ground plane with a small bypass capacitor,
typically 100 pF.
5
RFINA
AVDD
Input to the RF Prescaler. This small-signal input is normally ac-coupled from the VCO.
Positive Power Supply for the RF Section. Place decoupling capacitors to the digital ground plane as close as possible
to this pin. AVDD must have the same voltage as DVDD.
6, 7, 8
9
REFIN
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input resistance of 100 kΩ.
It can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
10
11
12
13
14
DGND
SDGND
TXDATA
CE
Digital Ground.
Digital Σ-Δ Modulator Ground. Ground return path for the Σ-Δ modulator.
Tx Data Pin. Provide data to be transmitted in FSK or PSK mode on this pin.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-state mode.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the shift
register on the CLK rising edge. This input is a high impedance CMOS input.
CLK
15
16
17
18
19
DATA
LE
Serial Data Input. The serial data is loaded MSB first with the three LSBs being the control bits. This input is a high
impedance CMOS input.
Load Enable, CMOS Input. When LE is high, the data stored in the shift registers is loaded into one of the eight latches,
with the latch being selected using the control bits.
Multiplexer Output. This pin allows either the RF lock detect, the scaled RF, or the scaled reference frequency to be
accessed externally.
Power Supply Pin for the Digital Σ-Δ Modulator. This pin should be the same voltage as AVDD. Place decoupling
capacitors to the ground plane as close as possible to this pin.
MUXOUT
SDVDD
DVDD
Positive Power Supply for the Digital Section. Place decoupling capacitors to the digital ground plane as close as
possible to this pin. DVDD must have the same voltage as AVDD.
20 , 21
22
SW1, SW2
VP
Switches for Fast Lock.
Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V, it can be set to
5.5 V and used to drive a VCO with a tuning range of up to 5.5 V.
23
RSET
Connecting a resistor between this pin and ground sets the maximum charge pump output current. The relationship
between ICP and RSET is
25.5
RSET
ICPmax
=
where:
ICPmax = 5 mA.
RSET = 5.1 kΩ.
24
25
CP
EPAD
Charge Pump Output. When enabled, this provides ICP to the external loop filter, which in turn drives the external VCO.
Exposed Paddle. The LFCSP has an exposed paddle that must be connected to GND.
Rev. 0 | Page 7 of 36
ADF4158
TYPICAL PERFORMANCE CHARACTERISTICS
–40
5.87
5.86
5.85
5.84
5.83
5.82
5.81
5.80
5.79
5.78
5.77
5.76
–60
–80
–100
–120
–140
–160
–0.010
–0.005
0
0.005
0.010
1k
10k
100k
1M
10M
TIME (s)
FREQUENCY OFFSET (Hz)
Figure 5. Phase Noise at 5805 MHz, PFD = 32 MHz, Loop Bandwidth = 100 kHz
Figure 8. Delay Between Ramps for Sawtooth Waveform, PFD = 32 MHz,
INT = 181, FRAC = 0, DEV Offset = 4, DEV Word = 20972, Step Word = 200,
CLK DIV = 10, MOD Divider = 125, DEL Start Word = 1025
5.86
5.85
5.84
5.83
5.82
5.81
5.80
5.79
5.78
5.86
NO DELAY
5.85
DELAY
5.84
5.83
5.82
5.81
5.80
5.79
5.78
5.77
5.76
–0.025
–0.015
–0.005
0.005
0.015
0.025
0
0.005
0.010
0.015
0.020
TIME (s)
TIME (s)
Figure 6. Triangular Waveform, PFD = 32 MHz, INT = 181, FRAC = 0,
DEV Offset = 4, DEV Word = 20972, Step Word = 200, CLK DIV = 10,
MOD Divider = 125
Figure 9. Delayed Start of Triangular Burst, PFD = 32 MHz, INT = 181,
FRAC = 0, DEV Offset = 4, DEV Word = 20972, Step Word = 200,
CLK DIV = 10, MOD Divider = 125, DEL Start Word = 1000
5.810
5.808
5.806
5.804
5.802
5.800
5.798
5.796
5.794
5.792
5.790
5.87
5.85
5.83
5.81
5.79
5.77
5.75
–0.010
–0.005
0
0.005
0.010
–0.010
–0.005
0
0.005
0.010
TIME (s)
TIME (s)
Figure 7. Sawtooth Waveform, PFD = 32 MHz, INT = 181, FRAC = 0,
DEV Offset = 4, DEV Word = 20972, Step Word = 200, CLK DIV = 10,
MOD Divider = 125
Figure 10. Dual Ramp Rate Waveform, PFD = 32 MHz, INT = 181, FRAC = 0,
Ramp1: DEV Offset = 3, DEV Word = 16777, Step Word = 100,
Ramp2: DEV Offset = 3, DEV Word = 20792, Step Word = 80
Rev. 0 | Page 8 of 36
ADF4158
5.8004
5.8003
5.8002
5.8001
5.8000
5.7999
5.7998
5.7997
5.7996
5.7995
0
–5
–10
–15
–20
–25
–30
0.185 1.185 2.185 3.185 4.185 5.185 6.185 7.185
–0.010
–0.005
0
0.005
0.010
TIME (s)
FREQUENCY (GHz)
Figure 11. FSK Superimposed on Rising Edge of Triangular Waveform;
Ramp Settings: PFD = 32 MHz, INT = 181, FRAC = 0, DEV Offset = 4, DEV
Word = 20972, Step Word = 200, CLK DIV = 10, MOD Divider = 125;
FSK Settings: DEV Offset = 3, DEV Word = 4194
Figure 13. RFIN Sensitivity-Average Over Temperature and VDD
6
4
5.80010
5.80005
5.80000
5.79995
5.79990
5.79985
5.79980
5.79975
2
0
–2
–4
–6
–8
0
1
2
3
4
5
6
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
v
(V)
TIME (ms)
CP
Figure 12. FSK; Settings: Frequency Deviation = 100 kHz, Data Rate = 3 kHz
Figure 14. Charge Pump Output Characteristics
Rev. 0 | Page 9 of 36
ADF4158
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
25-BIT FIXED MODULUS
The ADF4158 has a 25-bit fixed modulus. This allows output
frequencies to be spaced with a resolution of
The reference input stage is shown in Figure 15. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on power-down.
f
RES = fPFD/225
(1)
where fPFD is the frequency of the phase frequency detector
(PFD). For example, with a PFD frequency of 10 MHz,
frequency steps of 0.298 Hz are possible.
POWER-DOWN
CONTROL
INT, FRAC, AND R RELATIONSHIP
100kΩ
SW2
NC
The INT and FRAC values, in conjunction with the R-counter,
make it possible to generate output frequencies that are spaced
by fractions of the phase frequency detector (PFD). The RF
VCO frequency (RFOUT) equation is
TO R-COUNTER
REF
IN
NC
SW1
BUFFER
SW3
NO
RFOUT = fPFD × (INT + (FRAC/225))
(2)
Figure 15. Reference Input Stage
where:
RF INPUT STAGE
RFOUT is the output frequency of external voltage controlled
oscillator (VCO).
The RF input stage is shown in Figure 16. It is followed by a
2-stage limiting amplifier to generate the current-mode logic
(CML) clock levels needed for the prescaler.
INT is the preset divide ratio of binary 12-bit counter (23 to 4095).
FRAC is the numerator of the fractional division (0 to 225 − 1).
1.6V
BIAS
f
PFD = REFIN × [(1 + D)/(R × (1 + T))]
(3)
GENERATOR
AV
DD
where:
REFIN is the reference input frequency.
D is the REFIN doubler bit.
2kΩ
2kΩ
T is the REFIN divide-by-2 bit (0 or 1).
R is the preset divide ratio of the binary, 5-bit, programmable
reference counter (1 to 32).
RF
RF
A
B
IN
RF N-DIVIDER
N = INT + FRAC/MOD
IN
FROM RF
INPUT STAGE
TO PFD
N-COUNTER
THIRD-ORDER
FRACTIONAL
AGND
INTERPOLATOR
Figure 16. RF Input Stage
INT
REG
MOD
REG
FRAC
VALUE
RF INT DIVIDER
The RF INT CMOS counter allows a division ratio in the PLL
feedback counter. Division ratios from 23 to 4095 are allowed.
Figure 17. RF N-Divider
R-COUNTER
The 5-bit R-counter allows the input reference frequency
(REFIN) to be divided down to produce the reference clock
to the PFD. Division ratios from 1 to 32 are allowed.
Rev. 0 | Page 10 of 36
ADF4158
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
INPUT SHIFT REGISTERS
The ADF4158 digital section includes a 5-bit RF R-counter,
a 12-bit RF N-counter, and a 25-bit FRAC counter. Data is
clocked into the 32-bit shift register on each rising edge of
CLK. The data is clocked in MSB first. Data is transferred
from the shift register to one of eight latches on the rising edge
of LE. The destination latch is determined by the state of the
three control bits (C3, C2, and C1) in the shift register. These
are the three LSBs—DB2, DB1, and DB0—as shown in Figure 2.
The truth table for these bits is shown in Table 6. Figure 20 and
Figure 21 show a summary of how the latches are programmed.
The PFD takes inputs from the R-counter and N-counter and
produces an output proportional to the phase and frequency
difference between them. Figure 18 shows a simplified sche-
matic of the PFD. The PFD includes a fixed delay element that
sets the width of the antibacklash pulse, which is typically 3 ns.
This pulse ensures that there is no dead zone in the PFD transfer
function and gives a consistent reference spur level.
UP
HIGH
D1
Q1
U1
CLR1
+IN
PROGRAM MODES
Table 6 and Figure 22 through Figure 29 show how to set up
the program modes in the ADF4158.
CHARGE
PUMP
CP
U3
DELAY
DOWN
Several settings in the ADF4158 are double buffered. These
include the LSB fractional value, R-counter value, reference
doubler, current setting, and RDIV2. This means that two
events must occur before the part uses a new value for any
of the double-buffered settings. First, the new value is latched
into the device by writing to the appropriate register. Second,
a new write must be performed on Register R0.
CLR2
D2 Q2
HIGH
U2
–IN
Figure 18. PFD Simplified Schematic
MUXOUT AND LOCK DETECT
For example, updating the fractional value can involve a write
to the 13 LSB bits in R1 and the 12 MSB bits in R0. R1 should
be written to first, followed by the write to R0. The frequency
change begins after the write to R0. Double buffering ensures
that the bits written to in R1 do not take effect until after
the write to R0.
The output multiplexer on the ADF4158 allows the user
to access various internal points on the chip. The state of
MUXOUT is controlled by the M4, M3, M2, and M1 bits
(see Figure 22). Figure 19 shows the MUXOUT section in
block diagram form.
Table 6. C3, C2, and C1 Truth Table
DV
DD
THREE-STATE OUTPUT
DV
Control Bits
DD
C3
0
C2
0
C1
0
Register
R0
DGND
R-DIVIDER OUTPUT
N-DIVIDER OUTPUT
DIGITAL LOCK DETECT
SERIAL DATA OUTPUT
CLK DIVIDER OUTPUT
R-DIVIDER/2
0
0
1
R1
0
1
0
R2
MUX
CONTROL
MUXOUT
0
1
1
R3
1
0
0
R4
1
0
1
R5
1
1
0
R6
1
1
1
R7
N-DIVIDER/2
DGND
Figure 19. MUXOUT Schematic
Rev. 0 | Page 11 of 36
ADF4158
REGISTER MAPS
FRAC/INT REGISTER (R0)
MUXOUT
CONTROL
12-BIT MSB FRACTIONAL VALUE
(FRAC)
CONTROL
BITS
12-BIT INTEGER VALUE (INT)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
R1 M4 M3 M2 M1 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 C3(0) C2(0) C1(0)
LSB FRAC REGISTER (R1)
13-BIT LSB FRACTIONAL VALUE
(FRAC) (DBB)
CONTROL
BITS
RESERVED
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
F13 F12 F11 F10 F9
F8
F7
F6
F5
F4
F3
F2
F1
0
0
0
0
0
0
0
0
0
0
0
0
C3(0) C2(0) C1(1)
R-DIVIDER REGISTER (R2)
DBB
DBB
CP
CURRENT
SETTING
CONTROL
BITS
5-BIT R-COUNTER
12-BIT MOD DIVIDER
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
CR1 CPI4 CPI3 CPI2 CPI1
0
P1
U2
U1
R5
R4
R3
R2
R1 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1 C3(0) C2(1) C1(0)
FUNCTION REGISTER (R3)
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
NS1 U12 RM2 RM1 PE1 FE1 U11 U10 U9 U8 U7 C3(0) C2(1) C1(1)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NOTES
1. DBB = DOUBLE-BUFFERED BIT(S).
Figure 20. Register Summary 1
Rev. 0 | Page 12 of 36
ADF4158
TEST REGISTER (R4)
READ-
BACK
TO
CLK
DIV
MODE
CONTROL
BITS
RESERVED
12-BIT CLOCK DIVIDER VALUE
RESERVED
MUXOUT
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
LS1
0
0
0
0
0
0
0
0
R2
R1 CK2 CK1 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
0
0
0
C3(1) C2(0) C1(0)
0
DEVIATION REGISTER (R5)
CONTROL
BITS
16-BIT DEVIATION WORD
4-BIT DEV OFFSET
WORD
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
TR1 PR1
I2
I1 FRE1 R2E1 DS1 DO4 DO3 DO2 DO1 D16 D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D2
D1 C3(1) C2(0) C1(1)
D3
STEP REGISTER (R6)
CONTROL
BITS
20-BIT STEP WORD
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
0
SSE1 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9
S8
S7
S6
S5
S4
S3
S2
S1 C3(1) C2(1) C1(0)
DELAY REGISTER (R7)
CONTROL
BITS
RESERVED
12-BIT DELAY START DIVIDER
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
0
0
0
0
0
0
RDF1 RD1 DC1 DSE1 DS12 DS11 DS10 DS9 DS8 DS7 DS6 DS5 DS4 DS3 DS2 DS1 C3(1) C2(1) C1(1)
NOTES
1. DBB = DOUBLE-BUFFERED BIT(S).
Figure 21. Register Summary 2
Rev. 0 | Page 13 of 36
ADF4158
12-Bit MSB Fractional Value (FRAC)
FRAC/INT REGISTER (R0) MAP
These 12 bits, along with Bits DB[27:15] in the LSB FRAC
register (Register R1), control what is loaded as the FRAC value
into the fractional interpolator. This is part of what determines
the overall feedback division factor. It is also used in Equation 2.
These 12 bits are the most significant bits (MSB) of the 25-bit
FRAC value, and Bits DB[27:15] in the LSB FRAC register
(Register R1) are the least significant bits (LSB). See the RF
Synthesizer: A Worked Example section for more information.
With Register R0 DB[2:0] set to [0, 0, 0], the on-chip
FRAC/INT register is programmed as shown in Figure 22.
Ramp On
Setting DB31 to 1 enables the ramp, setting DB31 to 0 disables
the ramp.
MUXOUT Control
The on-chip multiplexer is controlled by DB[30:27] on the
ADF4158. See Figure 22 for the truth table.
12-Bit Integer Value (INT)
These 12 bits control what is loaded as the INT value. This is
used to determine the overall feedback division factor. It is used
in Equation 2. See the INT, FRAC, and R Relationship section
for more information.
MUXOUT
12-BIT MSB FRACTIONAL VALUE
(FRAC)
CONTROL
BITS
12-BIT INTEGER VALUE (INT)
CONTROL
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
R1 M4 M3 M2 M1 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 C3(0) C2(0) C1(0)
MSB FRACTIONAL VALUE
F15 F14 (FRAC)*
R1 RAMP ON
M4 M3 M2 M1
OUTPUT
THREE-STATE OUTPUT
DV
F25
0
0
0
0
.
F24
0
0
0
0
.
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
0
1
RAMP DISABLED
RAMP ENABLED
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
.
0
1
0
1
.
0
DD
1
DGND
2
R-DIVIDER OUTPUT
N-DIVIDER OUTPUT
RESERVED
3
.
.
.
.
.
.
DIGITAL LOCK DETECT
SERIAL DATA OUTPUT
RESERVED
.
.
.
.
.
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
4092
4093
4094
4095
RESERVED
CLK DIVIDER OUTPUT
RESERVED
*THE FRAC VALUE IS MADE UP OF THE 12-BIT MSB STORED IN
FAST-LOCK SWITCH
R-DIVIDER/2
REGISTER R0, AND THE 13-BIT LSB REGISTER STORED IN
13
REGISTER R1. FRAC VALUE = 13-BIT LSB + 12-BIT MSB × 2
.
N-DIVIDER/2
READBACK TO MUXOUT
INTEGER VALUE
N12
N11
N10
N9
0
0
0
0
.
N8
0
0
0
0
.
N7
0
0
0
0
.
N6
N5
1
1
1
1
.
N4
0
1
1
1
.
N3
1
0
0
0
.
N2
1
0
0
1
.
N1
1
0
1
0
.
(INT)
0
0
0
0
.
0
0
0
0
.
0
0
0
0
.
0
0
0
0
.
23
24
25
26
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
4093
4094
4095
Figure 22. FRAC/INT Register (R0) Map
Rev. 0 | Page 14 of 36
ADF4158
LSB FRAC REGISTER (R1) MAP
With Register R1 DB[2:0] set to [0, 0, 1], the on-chip LSB FRAC
register is programmed as shown in Figure 23.
These 13 bits are the least significant bits (LSB) of the 25-bit
FRAC value, and Bits DB[14:3] in the INT/FRAC register are
the most significant bits (MSB). See the RF Synthesizer: A
Worked Example section for more information.
13-Bit LSB FRAC Value
These 13 bits, along with Bits DB[14:3] in the FRAC/INT
register (Register R0), control what is loaded as the FRAC value
into the fractional interpolator. This is part of what determines
the overall feedback division factor. It is also used in Equation 2.
Reserved Bits
All reserved bits should be set to 0 for normal operation.
13-BIT LSB FRACTIONAL VALUE
CONTROL
RESERVED
RESERVED
BITS
(FRAC) (DBB)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
F13 F12 F11 F10 F9
F8
F7
F6
F5
F4
F3
F2
F1
0
0
0
0
0
0
0
0
0
0
0
0
C3(0) C2(0) C1(1)
LSB FRACTIONAL VALUE
(FRAC)*
F13
0
0
0
0
.
F12
0
0
0
0
.
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
F2
F1
0
0
0
0
1
1
.
1
0
1
.
1
2
3
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
8188
8189
8190
8191
*THE FRAC VALUE IS MADE UP OF THE 12-BIT MSB STORED IN
REGISTER R0, AND THE 13-BIT LSB REGISTER STORED IN
13
REGISTER R1. FRAC VALUE = 13-BIT LSB + 12-BIT MSB × 2
.
NOTES
1. DBB = DOUBLE-BUFFERED BITS.
Figure 23. LSB FRAC Register (R1) Map
Rev. 0 | Page 15 of 36
ADF4158
RDIV2
R-DIVIDER REGISTER (R2) MAP
Setting DB21 to 1 inserts a divide-by-2 toggle flip-flop between
the R-counter and the PFD. This can be used to provide a 50%
duty cycle signal at the PFD for use with cycle slip reduction.
With Register R2 DB[2:0] set to [0, 1, 0], the on-chip R-divider
register is programmed as shown in Figure 24.
Reserved Bits
Reference Doubler
All reserved bits should be set to 0 for normal operation.
Setting DB20 to 0 feeds the REFIN signal directly to the 5-bit RF
R-counter, disabling the doubler. Setting this bit to 1 multiplies
the REFIN frequency by a factor of 2 before feeding the signal
into the 5-bit R-counter. When the doubler is disabled, the
REFIN falling edge is the active edge at the PFD input to the
fractional synthesizer. When the doubler is enabled, both the
rising edge and falling edge of REFIN become active edges at the
PFD input.
CSR Enable
Setting this bit to 1 enables cycle slip reduction. This is a
method for improving lock times. Note that the signal at the PFD
must have a 50% duty cycle in order for cycle slip reduction to
work. In addition, the charge pump current setting must be set
to a minimum. See the Cycle Slip Reduction for Faster Lock
Times section for more information.
The maximum allowed REFIN frequency when the doubler is
enabled is 30 MHz.
Also note that the cycle slip reduction feature can only be
operated when the phase detector polarity setting is positive
(DB6 in Register R3). It cannot be used if the phase detector
polarity is set to negative.
5-Bit R-Counter
The 5-bit R-counter allows the input reference frequency
(REFIN) to be divided down to produce the reference clock
to the phase frequency detector (PFD). Division ratios from
1 to 32 are allowed.
Charge Pump Current Setting
DB[27:24] set the charge pump current setting (see Figure 24).
Set these bits to the charge pump current that the loop filter is
designed with.
12-Bit MOD Divider
Prescaler (P/P + 1)
Bits DB[14:3] are used to program the MOD divider, which
determines the duration of the time step in ramp mode.
The dual-modulus prescaler (P/P + 1), along with the INT,
FRAC, and MOD counters, determines the overall division
ratio from the RFIN to the PFD input.
Operating at CML levels, it takes the clock from the RF input
stage and divides it down for the counters. It is based on
a synchronous 4/5 core. When set to 4/5, the maximum RF
frequency allowed is 3 GHz. Therefore, when operating
the ADF4158 above 3 GHz, the prescaler must be set to 8/9.
The prescaler limits the INT value.
With P = 4/5, NMIN = 23.
With P = 8/9, NMIN = 75.
Rev. 0 | Page 16 of 36
ADF4158
DBB
DBB
5-BIT R COUNTER
CP
CURRENT
SETTING
CONTROL
BITS
12-BIT MOD DIVIDER
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
CR1 CPI4 CPI3 CPI2 CPI1
0
P1
U2
U1
R5
R4
R3
R2
R1 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1 C3(0) C2(1) C1(0)
CYCLE SLIP
CR1 REDUCTION
REFERENCE
DOUBLER
U1
D12 D11
.......... D2
D1
12-BIT MOD DIVIDER VALUE
0
1
DISABLED
ENABLED
0
1
DISABLED
ENABLED
0
0
0
0
.
0
0
0
0
.
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
0
0
1
1
0
1
0
1
0
1
2
3
U2
0
R DIVIDER
DISABLED
ENABLED
.
.
.
.
.
.
.
.
.
.
1
.
.
.
1
1
1
1
1
1
1
1
0
0
4092
4093
4094
4095
0
1
1
1
0
1
P1
0
PRESCALER
4/5
8/9
1
I
(mA)
CP
CPI4
CPI3
CPI2
CPI1
5.1kΩ
R5
0
0
0
0
.
R4
0
0
0
0
.
R3
0
0
0
1
.
R2
0
1
1
0
.
R1
1
0
1
0
.
R-COUNTER DIVIDE RATIO
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0.31
0.63
0.94
1.25
1.57
1.88
2.19
2.5
1
2
3
4
.
.
.
.
.
.
.
.
.
.
1
1
1
0
1
1
1
0
1
1
1
0
0
1
1
0
1
.
29
30
31
32
2.81
3.13
3.44
3.75
4.06
4.38
4.69
5
1
0
NOTES
1. DBB = DOUBLE-BUFFERED BITS.
Figure 24. R-Divider Register (R2) Map
Rev. 0 | Page 17 of 36
ADF4158
Phase Detector (PD) Polarity
FUNCTION REGISTER (R3) MAP
DB6 sets the phase detector polarity. When the VCO
characteristics are positive, set this bit to 1. When the
VCO characteristics are negative, set this bit to 0.
With Register R3 DB[2:0] set to [0, 1, 1], the on-chip function
register is programmed as shown in Figure 25.
Reserved Bits
Power-Down
All reserved bits should be set to 0 for normal operation.
DB5 provides the programmable power-down mode. Setting
this bit to 1 performs a power-down. Setting this bit to 0 returns
the synthesizer to normal operation. While in software power-
down mode, the part retains all information in its registers.
Only when supplies are removed are the register contents lost.
N SEL
This setting is used to circumvent the issue of pipeline delay
between an update of the integer and fractional values in the
N-counter. Typically, the INT value is loaded first, followed by
the FRAC value. This can cause the N-counter value to be at an
incorrect value for a brief period of time equal to the pipeline
delay (about four PFD cycles). This has no effect if the INT
value has not been updated. However, if the INT value has been
changed, this can cause the PLL to overshoot in frequency while
it tries to lock to the temporarily incorrect N value. After the
correct fractional value is loaded, the PLL quickly locks to the
correct frequency. Introducing an additional delay to the load-
ing of the INT value using the N SEL bit causes the INT and
FRAC values to be loaded at the same time, preventing frequency
overshoot. The delay is turned on by setting Bit DB15 to 1.
When a power-down is activated, the following events occur:
1. All active dc current paths are removed.
2. The synthesizer counters are forced to their load state
conditions.
3. The charge pump is forced into three-state mode.
4. The digital lock-detect circuitry is reset.
5. The RFIN input is debiased.
6. The input register remains active and capable of loading
and latching data.
Charge Pump Three-State
SD Reset
DB4 puts the charge pump into three-state mode when
For most applications, DB14 should be set to 0. When DB14 is
set to 0, the Σ-Δ modulator is reset on each write to Register R0.
If it is not required that the Σ-Δ modulator be reset on each
Register R0 write, set this bit to 1.
programmed to 1. It should be set to 0 for normal operation.
Counter Reset
DB3 is the RF counter reset bit. When this bit is set to 1, the RF
synthesizer counters are held in reset. For normal operation, set
this bit to 0.
Ramp Mode
DB[11:10] determine the type of generated waveform.
PSK Enable
When DB9 is set to 1, PSK modulation is enabled. When set to
0, PSK modulation is disabled.
FSK Enable
When DB8 is set to 1, FSK modulation is enabled. When set to
0, FSK modulation is disabled.
Lock Detect Precision (LDP)
When DB7 is programmed to 0, 24 consecutive PFD cycles of
15 ns must occur before digital lock detect is set. When this bit
is programmed to 1, 40 consecutive reference cycles of 15 ns
must occur before digital lock detect is set.
Rev. 0 | Page 18 of 36
ADF4158
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NS1 U12
0
0
RM2 RM1 PE1 FE1 U11 U10 U9
U8
U7 C3(0) C2(1) C1(1)
COUNTER
NS1
0
N SEL
U7
RESET
N WORD LOAD ON SDCLK
N WORD LOAD DELAYED 4 CYCLES
0
1
DISABLED
ENABLED
1
U11
0
LDP
24 PFD CYCLES
40 PFD CYCLES
U12 Σ-Δ RESET
1
0
1
ENABLED
DISABLED
CP
FE1 FSK ENABLE
U10
0
PD POLARITY
U8
THREE-STATE
0
1
DISABLED
ENABLED
NEGATIVE
POSITIVE
0
1
DISABLED
ENABLED
1
RM2 RM1 RAMP MODE
0
1
1
1
0
1
1
1
CONTINUOUS SAWTOOTH
CONTINUOUS TRIANGULAR
SINGLE SAWTOOTH
PE1 PSK ENABLE
U9
0
POWER-DOWN
DISABLED
0
1
DISABLED
ENABLED
SINGLE TRIANGULAR
1
ENABLED
Figure 25. Function Register (R3) Map
Rev. 0 | Page 19 of 36
ADF4158
CLK DIV Mode
TEST REGISTER (R4) MAP
Depending on the settings of DB[20:19], the 12-bit clock
divider may be a counter for the switched R fast-lock ramp
(CLK2), or it may be turned off.
With Register R4 DB[2:0] set to [1, 0, 0], the on-chip test
register (R4) is programmed as shown in Figure 26.
LE SEL
12-Bit Clock Divider Value
In some applications, it is necessary to synchronize LE
with the reference signal. To do this, DB31 should be set
to 1. Synchronization is done internally on the part.
DB[18:7] are used to program the clock divider, which
determines how long the loop remains in wideband mode
while the switched R fast-lock technique is used. See the
Fast Lock: Loop Filter Topology section for more details.
Reserved Bits
All reserved bits should be set to 0 for normal operation.
Readback to MUXOUT
DB[22:21] enable or disable the readback to MUXOUT
function. This function allows reading back the synthesizer’s
frequency at the moment of interrupt.
READ-
CLK
CONTROL
BITS
BACK
DIV
RESERVED
12-BIT CLOCK DIVIDER VALUE
RESERVED
TO
MUXOUT
MODE
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
LS1 R2 R1 CK2 CK1 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 C3(1) C2(0) C1(0)
0
0
0
0
0
0
0
0
0
0
0
0
LS1
LE SEL
LE FROM PIN
LE SYNC WITH REF
R1
R2
READBACK TO MUXOUT
0
1
D12 D11 .......... D2
D1
CLOCK DIVIDER VALUE
0
1
0
0
DISABLED
ENABLED
0
0
0
0
.
0
0
0
0
.
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
0
0
1
1
.
0
1
0
1
.
0
1
2
3
.
.
.
.
.
.
.
.
.
.
.
CK2 CK1 CLOCK DIVIDER MODE
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
4092
4093
4094
4095
0
0
1
1
0
1
0
1
CLOCK DIVIDER OFF
FAST-LOCK DIVIDER
RESERVED
RAMP DIVIDER
Figure 26. Test Register (R4) Map
Rev. 0 | Page 20 of 36
ADF4158
FSK Ramp Enable
DEVIATION REGISTER (R5) MAP
Setting DB25 to 1 enables the FSK ramp. Setting DB25 to 0
disables the FSK ramp.
With Register R5 DB[2:0] set to [1, 0, 1], the on-chip deviation
register is programmed as shown in Figure 27.
Ramp 2 Enable
Reserved Bits
Setting DB24 to 1 enables the second ramp. Setting DB24 to 0
disables the second ramp.
All reserved bits should be set to 0 for normal operation.
Tx Ramp CLK
Deviation Select
Setting DB29 to 0 uses the clock divider clock for clocking the
ramp. Setting DB29 to 1 uses the Tx data clock for clocking
the ramp.
Setting DB23 to 0 chooses the first deviation word. Setting
DB23 to 1, chooses the second deviation word.
4-Bit Deviation Offset Word
PAR Ramp
DB[22:19] determine the deviation offset. The deviation offset
affects the deviation resolution.
Setting DB28 to 1 enables the parabolic ramp. Setting DB28 to 0
disables the parabolic ramp.
16-Bit Deviation Word
Interrupt
DB[18:3] determine the signed deviation word. The deviation
word defines the deviation step.
DB[27:26] determine which type of interrupt is used. This
feature is used for reading back the INT and FARC value of a
ramp at a given moment in time (rising edge on the TXDATA
pin triggers the interrupt). From these bits, frequency can be
obtained. After readback, the sweep might continue or stop
at the readback frequency.
CONTROL
4-BIT DEV OFFSET
WORD
16-BIT DEVIATION WORD
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
TR1 PR1
I2
I1 FRE1 R2E1 DS1 DO4 DO3 DO2 DO1 D16 D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5 D4
D3
C3(1) C2(0) C1(1)
D2
D1
FRE1 FSK RAMP ENABLE
DS1
0
DEV SEL
PR1 PAR RAMP
TR1 TX RAMP CLK
0
1
DISABLED
ENABLED
DEV WORD 1
DEV WORD 2
0
1
CLK DIV
TX DATA
0
1
DISABLED
ENABLED
1
D16 D14 .......... D2
D1
16-BIT DEVIATION WORD
0
.
1
.
..........
..........
..........
..........
1
.
1
.
32,767
.
0
0
0
0
1
1
1
0
3
2
R2E1 RAMP 2 ENABLE
I2
0
I1
0
INTERRUPT
INTERRUPT OFF
0
1
DISABLED
ENABLED
0
0
0
0
..........
..........
0
0
1
0
1
0
LOAD CHANNEL CONTINUE SWEEP
NOT USED
0
1
1
0
1
1
1
.
1
1
1
.
..........
..........
..........
..........
..........
1
1
0
.
1
0
1
.
–1
–2
–3
.
LOAD CHANNEL STOP SWEEP
1
1
DO4 DO3 DO2 DO1
4-BIT DEV OFFSET WORD
0
0
0
0
.
0
0
0
0
.
0
0
1
1
.
0
1
0
1
.
0
1
2
3
1
0
0
0
–32,768
.
.
.
.
.
.
.
.
1
1
1
1
1
1
0
1
1
1
13
14
15
0
1
Figure 27. Deviation Register (R5) Map
Rev. 0 | Page 21 of 36
ADF4158
Step SEL
STEP REGISTER (R6) MAP
Setting DB23 to 0 chooses Step Word 1. Setting DB23 to 1
chooses Step Word 2.
With Register R6 DB[2:0] set to [1, 1, 0], the on-chip step
register is programmed as shown in Figure 28.
20-Bit Step Word
Reserved Bits
DB[22:3] determine the step word. Step word is a number of
steps in the ramp.
All reserved bits should be set to 0 for normal operation.
CONTROL
RESERVED
12-BIT DELAY START WORD
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
0
0
0
0
0
0
RDF1 RD1 DC1 DSE1 DS12 DS11 DS10 DS9 DS8 DS7 DS6 DS5 DS4 DS3
C3(1) C2(1) C1(1)
DS2 DS1
RDF1 RAMP DELAY FAST LOCK
DSE1 DEL START ENABLE
DS12 DS11 .......... DS2 DS1
12-BIT DELAY START WORD
0
1
DISABLED
ENABLED
0
1
DISABLE
ENABLE
0
0
0
0
.
0
0
0
0
.
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
0
0
1
1
0
1
0
1
.
0
1
2
DC1 DEL CLK SEL
RD1 RAMP DELAY
3
0
1
PFD CLK
0
1
DISABLED
ENABLED
.
.
.
.
PFD × MOD_DIV CLK
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
4092
4093
4094
4095
Figure 28. Step Register (R6) Map
Rev. 0 | Page 22 of 36
ADF4158
Delay Clock Select
DELAY REGISTER (R7) MAP
Setting DB16 to 0 selects the PFD clock as the delay clock.
Setting DB16 to 1 selects PFD × MOD_DIV (MOD_DIV
set by DB[14:3] in Register R2) as delay clock.
With Register R7 DB[2:0] set to [1, 1, 1], the on-chip delay
register is programmed as shown in Figure 29.
Reserved Bits
Delayed Start Enable
All reserved bits should be set to 0 for normal operation.
Ramp Delay Fast Lock
Setting DB15 to 1 enables delayed start. Setting DB15 to 0
disables delayed start.
Setting DB18 to 1 enables the ramp delay fast-lock function.
Setting DB18 to 0 disables this function.
12-Bit Delayed Start Word
DB[14:3] determine the delay start word. The delay start word
affects the duration of the ramp start delay.
Ramp Delay
Setting DB17 to 1 enables the ramp delay function. Setting
DB17 to 0 disables this function.
CONTROL
RESERVED
12-BIT DELAY START WORD
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
0
0
0
0
0
0
RDF1 RD1 DC1 DSE1 DS12 DS11 DS10 DS9 DS8 DS7 DS6 DS5 DS4 DS3
C3(1) C2(1) C1(1)
DS2 DS1
RDF1 RAMP DELAY FAST LOCK
DSE1 DEL START ENABLE
DS12 DS11 .......... DS2 DS1
12-BIT DELAY START WORD
0
1
OFF
ON
0
1
DISABLE
ENABLE
0
0
0
0
.
0
0
0
0
.
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
0
0
1
1
0
1
0
1
.
0
1
2
DC1 DEL CLK SEL
RD1 RAMP DELAY
3
0
1
PFD CLK
0
1
OFF
ON
.
.
.
.
PFD × MOD_DIV CLK
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
4092
4093
4094
4095
Figure 29. Delay Register (R7) Map
Rev. 0 | Page 23 of 36
ADF4158
APPLICATIONS INFORMATION
INITIALIZATION SEQUENCE
REFERENCE DOUBLER AND REFERENCE DIVIDER
After powering up the part, administer the following
programming sequence:
The reference doubler on chip allows the input reference signal
to be doubled. This is useful for increasing the PFD comparison
frequency. Making the PFD frequency higher improves the noise
performance of the system. Doubling the PFD frequency
usually improves noise performance by 3 dB.
1. Delay register (R7)
2. Step register (R6)—load the step register (R6) twice, first
with STEP SEL = 0 and then with STEP SEL = 1
3. Deviation register (R5)—load the deviation register (R5)
twice, first with DEV SEL = 0 and then with DEV SEL = 1
4. Test register (R4)
It is important to note that the PFD cannot be operated above
32 MHz due to a limitation in the speed of the Σ-Δ circuit of the
N-divider.
5. Function register (R3)
6. R-divider register (R2)
CYCLE SLIP REDUCTION FOR FASTER LOCK TIMES
In fast-locking applications, a wide loop filter bandwidth is
required for fast frequency acquisition, resulting in increased
integrated phase noise and reduced spur attenuation. Using
cycle slip reduction, the loop bandwidth can be kept narrow
to reduce integrated phase noise and attenuate spurs while
still realizing fast lock times.
7. LSB FRAC register (R1)
8. FRAC/INT register (R0)
RF SYNTHESIZER: A WORKED EXAMPLE
The following equation governs how the synthesizer should be
programmed:
RFOUT = [N + (FRAC/225)] × [fPFD
]
(4)
Cycle Slips
Cycle slips occur in integer-N/fractional-N synthesizers when
the loop bandwidth is narrow compared with the PFD frequency.
The phase error at the PFD inputs accumulates too fast for the PLL
to correct, and the charge pump temporarily pumps in the wrong
direction, slowing down the lock time dramatically. The ADF4158
contains a cycle slip reduction circuit to extend the linear range
of the PFD, allowing faster lock times without loop filter changes.
where:
RFOUT is the RF frequency output.
N is the integer division factor.
FRAC is the fractionality.
f
PFD = REFIN × [(1 + D)/(R × (1 + T))]
(5)
where:
REFIN is the reference frequency input.
D is the RF REFIN doubler bit.
R is the RF reference division factor.
T is the reference divide-by-2 bit (0 or 1).
When the ADF4158 detects that a cycle slip is about to occur, it
turns on an extra charge pump current cell. This outputs a constant
current to the loop filter or removes a constant current from the
loop filter (depending on whether the VCO tuning voltage needs
to increase or decrease to acquire the new frequency). The effect is
that the linear range of the PFD is increased. Stability is main-
tained because the current is constant and is not a pulsed current.
For example, in a system where a 5.8002 GHz RF frequency
output (RFOUT) is required and a 10 MHz reference frequency
input (REFIN) is available, the frequency resolution is
f
f
RES = REFIN/225
RES = 10 MHz/225
= 0.298 Hz
(6)
If the phase error increases again to a point where another cycle
slip is likely, the ADF4158 turns on another charge pump cell.
This continues until the ADF4158 detects that the VCO fre-
quency has gone past the desired frequency. It then begins to
turn off the extra charge pump cells one by one until they are
all turned off and the frequency is settled.
From Equation 5,
f
PFD = [10 MHz × (1 + 0)/1] = 10 MHz
5.8002 GHz = 10 MHz × (N + FRAC/225)
Up to seven extra charge pump cells can be turned on. In most
applications, it is enough to eliminate cycle slips altogether,
giving much faster lock times.
Calculating N and FRAC values,
N = int(RFOUT/fPFD) = 580
FRAC = FMSB × 213 + FLSB
F
MSB = int(((RFOUT/fPFD) − N) × 212) = 81
F
LSB = int(((((RFOUT/fPFD) − N) × 212) − FMSB) × 213) = 7537
where:
FMSB is the 12-bit MSB FRAC value in Register R0.
FLSB is the 13-bit LSB FRAC value in Register R1.
int() makes an integer of the argument in parentheses.
Rev. 0 | Page 24 of 36
ADF4158
Setting Bit DB28 in the R-divider register (Register R2) to 1
enables cycle slip reduction. Note that a 45% to 55% duty cycle
is needed on the signal at the PFD in order for CSR to operate
correctly. The reference divide-by-2 flip-flop can help to
provide a 50% duty cycle at the PFD. For example, if a 100 MHz
reference frequency is available and the user wants to run the
PFD at 10 MHz, setting the R-divide factor to 10 results in a
10 MHz PFD signal that is not 50% duty cycle. By setting the
R-divide factor to 5 and enabling the reference divide-by-2 bit,
a 50% duty cycle 10 MHz signal can be achieved.
WAVEFORM GENERATION
The ADF4158 is capable of generating four types of waveforms
in the frequency domain: single ramp burst, single sawtooth
burst, sawtooth ramp, and triangular ramp. Figure 30 through
Figure 33 show the types of waveforms available.
Note that the cycle slip reduction feature can only be operated
when the phase detector polarity setting is positive (DB6 in
Register R3). It cannot be used if the phase detector polarity is
negative.
TIME
Figure 30. Single Ramp Burst
MODULATION
The ADF4158 can operate in frequency shift keying (FSK) or
phase shift keying (PSK) mode.
Frequency Shift Keying (FSK)
FSK is implemented by setting the ADF4158 N-divider up for
the center frequency and then toggling the TXDATA pin. The
deviation from the center frequency is set by
TIME
DEV = (fPFD/225) × (DEV × 2DEV_OFFSET
)
(7)
Figure 31. Single Sawtooth Burst
f
where:
DEV is a 16-bit word.
DEV_OFFSET is a 4-bit word.
f
PFD is the PFD frequency.
The ADF4158 implements this by incrementing or decre-
menting the set N-divide value by DEV × 2DEV_OFFSET
.
Phase Shift Keying (PSK)
TIME
When the ADF4158 is set up in PSK mode, it is possible to
toggle the output phase of the ADF4158 between 0° and 180°.
The TXDATA pin controls the phase.
Figure 32. Sawtooth Ramp
FSK Settings Worked Example
For example, take an FSK system operating at 5.8 GHz, with
a 25 MHz PFD, 250 kHz deviation and DEV_OFFSET = 4.
Rearrange Equation 4 as follows
fDEV
DEV =
(8)
fPFD
×2DEV _ OFFSET
TIME
225
Figure 33. Triangular Ramp
250 kHz
DEV =
= 20,971.52
25 MHz
× 24
225
The DEV value is rounded to 20,972. Toggling the TXDATA pin
causes the frequency to hop between 250 kHz frequencies
from the programmed center frequency.
Rev. 0 | Page 25 of 36
ADF4158
Waveform Deviations and Timing
Single Sawtooth Burst
Figure 34 shows a version of a burst or ramp. The key
parameters that define a burst or ramp are
In the single sawtooth burst, the N-divide value is reset to its
initial value on the next timeout interval after the number of
steps has taken place. The ADF4158 retains this N-divide value.
•
•
•
Frequency deviation
Timeout interval
Number of steps
Sawtooth Ramp
The sawtooth ramp is a repeated version of the single sawtooth
burst. The waveform repeats until the ramp is disabled.
TIMER
Triangular Ramp
The triangular ramp is similar to the single ramp burst. However,
when the steps have been completed, the ADF4158 begins to
decrement the N-divide value by DEV × 2DEV_OFFSET on each
timeout interval. When the number of steps has again been
completed, it reverts to incrementing the N-divide value.
Repeating this creates a triangular waveform. The waveform
repeats until the ramp is disabled.
fDEV
TIME
Figure 34. Waveform Timing
FMCW Radar Ramp Settings Worked Example
Frequency Deviation
The frequency deviation for each frequency hop is set by
DEV = (fPFD/225) × (DEV × 2DEV_OFFSET
Take as an example, an FMCW radar system requiring the
RF LO to sawtooth ramp over a 50 MHz range every 2 ms.
The PFD frequency is 25 MHz, and the RF output range is
5800 MHz to 5850 MHz.
f
)
(9)
where:
DEV is a 16-bit word.
DEV_OFFSET is a 4-bit word.
The frequency deviation for each hop in the ramp is set to
~250 kHz.
Timeout Interval
The frequency resolution of ADF4158 is calculated as follows:
The time between each frequency hop is set by
Timer = CLK1 × CLK2 × (1/fPFD
where:
CLK1 and CLK2 are 12-bit clock values (12-bit MOD divider in
R2, 12-bit clock divider in R4—CLK DIV set as RAMP DIV).
f
RES = fPFD/225
Numerically:
RES = 25 MHz/225 = 0.745 Hz
The DEV_OFFSET is calculated after rearranging Equation 9:
(11)
)
(10)
f
DEV_OFFSET = log2(fDEV/(fRES × DEVMAX))
(12)
f
PFD is the PFD frequency.
Expressed in log10(x), Equation 10 can be transformed into the
following equation:
Number of Steps
A 20-bit step value defines the number of frequency hops that
take place. The INT value cannot be incremented by more than
28 from its starting value.
DEV_OFFSET = log10(fDEV/(fRES × DEVMAX))/log10(2)
where:
DEVMAX = 215 − Maximum of the Deviation Word.
DEV = frequency deviation.
(13)
Single Ramp Burst
f
The most basic waveform is the single ramp burst. All other
waveforms are slight variations on this.
DEV_OFFSET = a 4-bit word.
Using Equation 13, DEV_OFFSET is calculated as follows
DEV_OFFSET = log10(250 kHz/(0.745 Hz × 215))/log10(2) = 3.356
After rounding, DEV_OFFSET = 4.
In the single ramp burst, the ADF4158 is locked to the fre-
quency defined in the FRAC/INT register. When the ramp
mode is enabled, the ADF4158 increments the N-divide value
by DEV × 2DEV_OFSET, causing a frequency shift, fDEV, on each
timer interval. This happens until the set number of steps has
taken place. The ADF4158 then retains the final N-divide value.
From DEV_OFFSET, the resolution of frequency deviation can
be calculated as follows
f
f
DEV_RES = fRES × 2DEV_OFFSET
DEV_RES = 0.745 Hz × 24 = 11.92 Hz
(14)
Rev. 0 | Page 26 of 36
ADF4158
To calculate the DEV word, use Equation 12.
The resulting ramp with two various rates is shown in
Figure 35. Eventually, the ramp must be activated as
described in Activating the Ramp section.
SWEEP RATE SET BY OTHER REGISTER
DEV = fDEV/(fRES × 2DEV_OFFSET
)
(15)
250 kH z
DEV =
= 20,971.52
25 MHz
225
×24
Rounding this to 20,972 and recalculating using Equation 9
to get the actual deviation frequency, fDEV, thus produces the
following:
SWEEP RATE SET BY ONE REGISTER
DEV = (25 MHz/225) × (20,972 × 24) = 249.986 kHz
TIME
f
Figure 35. Dual Sweep Rate
The number of fDEV steps required to cover the 50 MHz range
is 50 MHz/249.986 kHz = 200. To cover the 50 MHz range in
2 ms, the ADF4158 must hop every 2 ms/200 = 10 μs.
Ramp Mode with FSK Signal on Ramp
In traditional approaches a FMCW radars used either linear
frequency modulation (LFM) or FSK modulation. These
modulations used separately introduce ambiguity between
measured distance and velocity, especially in multitarget
situations. To overcome this issue and enable unambiguous
(range − velocity) multitarget detection, use a ramp with
FSK on it.
Rearrange Equation 10 to set the timer value (and fix CLK2 to 1):
CLK1 = Timer × fPFD/CLK2 = 10 μs × 25 MHz /1 = 250
To summarize the settings: DEV = 20,972, number of steps =
200, CLK1 = 250, CLK2 = 1. Using these settings, program the
ADF4158 to a center frequency of 5800 MHz, and enable the
sawtooth ramp to produce the required waveform. If a triangu-
lar ramp was used with the same settings, the ADF4158 would
sweep from 5800 MHz to 5850 MHz and back down again. The
entire sweep would take 4 ms.
Example
For example, if
•
•
PLL is locked to 5790 MHz.
There are 100 steps each of which lasts 10 μs and has a
deviation of 100 kHz.
Activating the Ramp
After setting all of the previous parameters, the ramp must be
activated. It is achieved by choosing the desired type of ramp
(DB[11:10] in Register R3) and starting the ramp (DB31 = 1
in Register R0).
•
The FSK signal is 25 kHz.
Then,
1. Program the ramp as described in the FMCW Radar Ramp
Settings Worked Example section. While doing that DB23
in Register R5 and DB23 in Register R6 should be set to 0.
2. Set the bits in Register R5 as follows to program FSK on
ramp to 25 kHz:
ADDITIONAL FEATURES
Two Ramp Rates
This feature allows for two ramps with different step and devia-
tion settings. It also allows the ramp rate to be reprogrammed
while another ramp is running.
DB[18:3] = 4194 (deviation word), DB[22:19] = 3
(deviation offset), DB23 = 1 (deviation select for FSK on
ramp), and DB25 = 1 (ramp with FSK enabled).
Example
For example, if
An example of ramp with FSK on the top of it is shown in
Figure 36. Eventually, the ramp must be activated as described
in Activating the Ramp section.
•
•
PLL is locked to 5790 MHz.
Ramp 1 jumps 100 steps, each of which lasts 10 μs and has
a frequency deviation of 100 kHz.
•
Ramp 2 jumps 80 steps, each of which lasts 10 μs and has a
frequency deviation of 125 kHz.
Then,
1. DB24 in Register R5 should be set to 1, which activates
Ramp 2 rates mode.
LFM
STEP = FREQUENCY
FSK
SWEEP/(N – 1)
SHIFT
2. Program Ramp 1 and Ramp 2 as follows to get two ramp
rates:
0
RAMP END
Ramp 1: Register R5 DB[18:3] = 16,777, DB[22:19] = 3
with DB23 = 0; Register R6 DB[22:3] = 100, DB23 = 0.
Ramp 2: Register R5 DB[18:3] = 20,972, DB[22:19] = 3
with DB23 = 1; Register R6 DB[22:3] = 80, DB23 = 1.
TIME
Figure 36. Combined FSK and LFM Waveform (N Corresponds to the Number
of LFM Steps)
Rev. 0 | Page 27 of 36
ADF4158
Delayed Start
Example
A delayed start can be used with two different parts to control
the start time. The idea of delayed start is shown in Figure 37.
For example, to add a delay between bursts in a ramp,
1. Set DB17 in Register R7 to 1 to enable delay between
ramps option.
RAMP WITHOUT
DELAYED START
2. Set Bit DB16 in Register R7 to 0 and the 12-bit delay start
word (DB[14:3] in Register R7) to 125 to delay the ramp
by 5 μs. The delay is calculated as follows:
Delay = tPFD × Delay Start Word
= 40 ns × 125 = 5 μs
RAMP WITH
DELAYED START
If a longer delay is needed, for example, 125 μs, Bit DB16
in Register R7 should be set to 1 and the 12-bit delay start
word (DB[14:3] in Register R7) should be set to 125. The
delay is calculated as follows
TIME
Figure 37. Delayed Start of Sawtooth Ramp
Example
For example, to program a delayed start with two different parts
to control the start time,
Delay = tPFD × MOD × Delay Start Word
= 40 ns × 25 × 125 = 125 μs
1. Set DB15 in Register R7 to 1 to enable the delayed start of
ramp option.
2. Set Bit DB16 in Register R7 to 0 and the 12-bit delay start
word (DB[14:3] in Register R7) to 125 to delay the ramp on
the first part is delayed by 5 μs. The delay is calculated as
follows:
There is also a possibility to activate fast-lock operation for
the first period of delay. This is done by setting Bit DB18 in
Register R7 to 1. This feature is useful for sawtooth ramps to
mitigate the frequency overshoot on the transition from one
sawtooth to the next. Eventually, the ramp must be activated
as described in Activating the Ramp section.
Delay = TPFD × Delay Start Word
Nonlinear Ramp Mode
= 40 ns × 125 = 5 μs
The ADF4158 is capable of generating a parabolic ramp. The
output frequency is generated according to the following
equation:
3. Set Bit DB16 in Register R7 to 1 and the 12-bit delay start
word (DB[14:3] in Register R7) to 125 to delay the ramp
on the second part is delayed by 125 μs. Use the following
formula for calculating the delay:
f
OUT(n + 1) = fOUT(n) + n × fDEV
(16)
where:
Delay = tPFD × MOD × Delay Start Word
f
f
OUT is output frequency.
DEV is frequency deviation.
= 40 ns × 25 × 125 = 125 μs
n is step number.
Eventually, the ramp must be activated as described in
Activating the Ramp section.
Delay Between Ramps
This feature adds a delay between bursts in ramp. Figure 38
shows a delay between ramps in sawtooth mode.
DELAY
TIME
Figure 39. Parabolic Ramp
TIME
Figure 38. Delay Between Ramps for Sawtooth Mode
Rev. 0 | Page 28 of 36
ADF4158
The following example explains how to set up and use this
function.
Table 7. Interrupt Modes
Mode
Action
DB[27:26] = 00
DB[27:26] = 01
DB[27:26] = 11
Interrupt is off
Interrupt on TXDATA, sweep continues
Interrupt on TXDATA, sweep stops
Example
fOUT = 5790 MHz
f
DEV = 100 kHz
When an interrupt takes place, the data consisting of the INT
and FRAC values can be read back via MUXOUT. The data is
made up of 37 bits, 12 of which represent the INT value and 25
the FRAC value.
Number of steps = 50
Duration of a single step = 10 μs
Ramp mode must be either triangular (Register R3, DB[11:10]
= 01) or single triangular (Register R3, DB[11:10] = 11).
The idea of frequency readback is shown in Figure 40.
In the first case, the generated frequency range is calculated as
follows:
FREQUENCY AT WHICH INTERRUPT TOOK PLACE
1
2
Δf = fDEV × (Number of Steps + 2) × (Number of Steps + 1)/2
= 132.6 MHz
In the second case, the generated frequency range is calculated
as follows:
TIME
TIME OF INTERRUPT
Δf = fDEV × (Number of Steps + 1) × Number of Steps/2
1. SWEEP CONTINUES MODE
2. SWEEP STOPS MODE
= 127.5 MHz
The timer is set in the same way as for its linear ramps
described in the Waveform Generation section.
INTERRUPT SIGNAL
Activation of the parabolic ramp is achieved by setting Bit DB28
in Register R5 to 1.
LOGIC HIGH
LOGIC LOW
Next the counter reset (DB3 in Register R3) should be set first
to 1 and then to 0.
Eventually, the ramp must be activated as described in the
Activating the Ramp section.
TIME
Figure 40. Interrupt and Frequency Readback
Interrupt Modes and Frequency Readback
Note that DB[22:21] in Register R4 should be set to 2 and
DB[30:27] in Register R0 (MUXOUT control) should be
set to 15 (1111).
Interrupt modes are triggered from the rising edge of TXDATA
Depending on the settings of DB[27:26] in Register R5, the
modes in Table 7 are activated.
.
The mechanism of how single bits are read back is shown in
Figure 41.
DATA CLOCKED OUT ON POSITIVE EDGE OF CLK AND READ ON NEGATIVE EDGE OF CLK
READBACK WORD (37 BITS)
0 0001 1100 1111 0110 0010 0011 1010 0111 1000 (HEX01CF623A78)
TX
DATA
LE
CLK
MUXOUT
MSB
LSB
25-BIT FRAC WORD
1 0110 0010 0011 1010 0111 1000
1623A78
12-BIT INT WORD
0000 1110 0111
0E7
23214712
231
25
RF = fPFD × (231 + 23214712/2 ) = 1.7922963GHz = 1.846V V
TUNE
Figure 41. Reading Back Single Bits to Determine the Output Frequency at the Moment of Interrupt
Rev. 0 | Page 29 of 36
ADF4158
TX
DATA
32 CLK
PULSES
37 CLK
PULSES
32 CLK
PULSES
37 CLK
PULSES
32 CLK
PULSES
37 CLK
PULSES
CLK
FREQUENCY
READBACK
FREQUENCY
READBACK
FREQUENCY
READBACK
MUXOUT
R0 WRITE
R4 WRITE
R4 WRITE
DATA
LE
Figure 42. Continuous Frequency Readback
For continuous frequency readback the following sequence
should be used:
In addition, note that the fast-lock feature doesn’t work in
ramp mode.
•
•
•
•
Register 0 write
LE high
Pulse on TXDATA
Frequency readback (as described at the beginning of the
Interrupt Modes and Frequency Readback section and
Figure 41)
Pulse on TXDATA
Register R4 write
FAST LOCK: AN EXAMPLE
If a PLL has a reference frequency of 13 MHz, that is, fPFD
13 MHz, as well as MOD = 10 (12-bit MOD divider in Register
R2) and a required lock time of 50 μs, the PLL is set to wide
bandwidth for 40 μs.
=
If the time period set for the wide bandwidth is 40 μs, then
Fast-Lock Timer Value = Time in Wide Bandwidth × fPFD/MOD
Fast-Lock Timer Value = 40 μs × 13 MHz /10 = 52.
•
•
•
Frequency readback (as described at the beginning of the
Interrupt Modes and Frequency Readback section and
Therefore, 52 must be loaded into the clock divider value in
Register R4 in Step 1 of the sequence described in the Fast-Lock
Timer and Register Sequences section.
Figure 41)
Pulse on TXDATA
…
•
•
FAST LOCK: LOOP FILTER TOPOLOGY
The sequence is also shown in Figure 42.
To use fast-lock mode, an extra connection from the PLL to the
loop filter is needed. The damping resistor in the loop filter
must be reduced to ¼ of its value while in wide bandwidth
mode. This is required because the charge pump current is
increased by 16 while in wide bandwidth mode, and stability
must be ensured. To further enhance stability and mitigate
frequency overshoot while frequency change (in wide band-
width mode), Register R3 is connected. During fast lock, the
SW1 pin is shorted to ground and SW2 is connected to CP (it
is done by setting Bits DB[20:19] in Register R4 to 01—fast lock
divider). The following two topologies can be used:
FAST-LOCK TIMER AND REGISTER SEQUENCES
If the fast-lock mode is used, a timer value needs to be
loaded into the PLL to determine the time spent in wide
bandwidth mode.
When the DB[20:19] bits in Register 4 (R4) are set to 01 (fast-
lock divider), the timer value is loaded via the 12-bit clock
divider value. To use fast lock, the PLL must be written to in
the following sequence:
1. Initialization sequence (see the Initialization Sequence
section). This should only be performed once after
powering up the part.
2. Load Register R4 DB[16:15] = 01 and the chosen fast-lock
timer value (DB[18:7]).
3. Load Register R2 with the chosen MOD divider value
(DB[14:3]) if longer time in wide loop bandwidth is
required.
•
Divide the damping resistor (R1) into two values (R1 and
R1A) that have a ratio of 1:3 (see Figure 43).
•
Connect an extra resistor (R1A) directly from SW1, as shown
in Figure 44. The extra resistor must be chosen such that
the parallel combination of an extra resistor and the damping
resistor (R1) is reduced to ¼ of the original value of R1.
For both of the topologies, the ratio R3:R2 should equal 1:4.
Note that the duration that the PLL remains in wide bandwidth
is equal to the MOD × fast-lock timer/fPFD, where MOD is the
12-bit MOD divider in Register R2.
Rev. 0 | Page 30 of 36
ADF4158
Reference Spurs
ADF4158
R3
R2
SW2
Reference spurs are generally not a problem in fractional-N
synthesizers because the reference offset is far outside the loop
bandwidth. However, any reference feedthrough mechanism
that bypasses the loop can cause a problem. One such mechan-
ism is the feedthrough of low levels of on-chip reference switching
noise out through the RFIN pins back to the VCO, resulting in
reference spur levels as high as −90 dBc. Take care in the PCB
layout to ensure that the VCO is well separated from the input
reference to avoid a possible feedthrough path on the board.
CP
VCO
C1
C2
C3
R1
SW1
R1A
Figure 43. Fast-Lock Loop Filter Topology—Topology 1
LOW FREQUENCY APPLICATIONS
ADF4158
R3
SW2
The specification on the RF input is 0.5 GHz minimum; however,
RF frequencies lower than this can be used if the minimum slew
rate specification of 400 V/μs is met. An appropriate LVDS driver
can be used to square up the RF signal before it is fed back to the
ADF4158 RF input. The FIN1001 from Fairchild Semiconductor
is one such LVDS driver.
R2
CP
VCO
C1
C2
C3
R1
R1A
SW1
FILTER DESIGN—ADIsimPLL
Figure 44. Fast-Lock Loop Filter Topology—Topology 2
A filter design and analysis program is available to help the
user implement PLL design. Visit www.analog.com/pll for a
free download of the ADIsimPLL™ software. This software
designs, simulates, and analyzes the entire PLL frequency
domain and time domain response. Various passive and
active filter architectures are allowed.
SPUR MECHANISMS
The fractional interpolator in the ADF4158 is a third-order Σ-Δ
modulator (SDM) with a 25-bit fixed modulus (MOD). The SDM
is clocked at the PFD reference rate (fPFD) that allows PLL output
frequencies to be synthesized at a channel step resolution of
fPFD/MOD. The various spur mechanisms possible with
fractional-N synthesizers and how they affect the ADF4158
are discussed in this section.
PCB DESIGN GUIDELINES FOR THE CHIP SCALE
PACKAGE
The lands on the chip scale package (CP-24) are rectangular.
The printed circuit board (PCB) pad for these should be 0.1 mm
longer than the package land length and 0.05 mm wider than
the package land width. Center the land on the pad. This ensures
that the solder joint size is maximized.
Fractional Spurs
In most fractional synthesizers, fractional spurs can appear at
the set channel spacing of the synthesizer. In the ADF4158,
these spurs do not appear. The high value of the fixed modulus
in the ADF4158 makes the SDM quantization error spectrum
look like broadband noise, effectively spreading the fractional
spurs into noise.
The bottom of the chip scale package has a central thermal pad.
The thermal pad on the PCB should be at least as large as this
exposed pad. On the PCB, there should be a clearance of at least
0.25 mm between the thermal pad and the inner edges of the
pad pattern. This ensures that shorting is avoided.
Integer Boundary Spurs
Interactions between the RF VCO frequency and the PFD
frequency can lead to spurs known as integer boundary spurs.
When these frequencies are not integer related (which is
the purpose of the fractional-N synthesizer), spur sidebands
appear on the VCO output spectrum at an offset frequency that
corresponds to the beat note or difference frequency between
an integer multiple of the PFD and the VCO frequency.
Thermal vias can be used on the PCB thermal pad to improve
the thermal performance of the package. If vias are used, they
should be incorporated into the thermal pad at 1.2 mm pitch
grid. The via diameter should be between 0.3 mm and 0.33 mm,
and the via barrel should be plated with 1 ounce of copper to
plug the via. Connect the PCB thermal pad to AGND.
These spurs are named integer boundary spurs because they are
more noticeable on channels close to integer multiples of the PFD
where the difference frequency can be inside the loop band-
width. These spurs are attenuated by the loop filter.
Rev. 0 | Page 31 of 36
ADF4158
APPLICATION OF ADF4158 IN FMCW RADAR
The application of ADF4158 in FMCW radar is shown in
Figure 45.
The ADF4158 in FMCW radar is used for generating ramps
(sawtooth or triangle) that are necessary for this type of radar
to operate. Traditionally, the PLL was driven directly by a direct
digital synthesizer (DDS) to generate the required type of wave-
form. Due to the implemented waveform generating mechanism
on the ADF4158, a DDS is no longer needed, which reduces cost.
In addition, the PLL solution has advantages over another
method (the DAC driving the VCO directly) for generating
FMCW ramps, which suffered from VCO tuning characteristics
nonlinearities requiring compensation. The PLL method
gives highly linear ramps without the need for calibration.
NO DDS REQUIRED
WITH ADF4158
5.1GHz
TO
5.1333GHz
76.5GHz
TO
77.0GHz
LINEAR
REFERENCE
OSCILLATOR
FREQUENCY
SWEEP
26MHz
ADF4158
PLL
×5 ×3
PA
VCO
MULTIPLY
×15
Tx
ANTENNA
AD9288
AD9235
ADSP-BF531
DSP
BASEBAND
MIXER
MICRO-
CONTROLLER
ADC
MUX
HPF
RANGE
COMPENSATION
16B
10B
TO
12B
BUS
CAN/FLEXRAY
Rx
ANTENNAS
Figure 45. FMCW Radar with ADF4158
Rev. 0 | Page 32 of 36
ADF4158
OUTLINE DIMENSIONS
4.10
4.00 SQ
3.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
19
18
24
0.50
BSC
1
2.65
2.50 SQ
2.45
EXPOSED
PAD
13
12
BOTTOM VIEW
6
7
0.50
0.40
0.30
0.25 MIN
TOP VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD.
Figure 46. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-24-7)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADF4158CCPZ
ADF4158CCPZ-RL7
EVAL-ADF4158EB1Z
Temperature Range
−40°C to +125°C
−40°C to +125°C
Package Description
Package Option
CP-24-7
CP-24-7
24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Evaluation Board
1 Z = RoHS Compliant Part.
Rev. 0 | Page 33 of 36
ADF4158
NOTES
Rev. 0 | Page 34 of 36
ADF4158
NOTES
Rev. 0 | Page 35 of 36
ADF4158
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08728-0-4/10(0)
Rev. 0 | Page 36 of 36
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