EVAL-ADAU1381Z_技术文档

Low Noise Stereo Codec with Enhanced

Recording and Playback Processing

ADAU1381

FEATURES

GENERAL DESCRIPTION

24-bit stereo audio ADC and DAC

The ADAU1381 is a low power, 24-bit stereo audio codec. The

low noise DAC and ADC support sample rates from 8 kHz to

96 kHz. Low current draw and power saving modes make the

ADAU1381 ideal for battery-powered audio applications.

400 mW speaker amplifier (into 8 Ω load)

Built-in sound engine for audio processing

Wind noise detection and autofiltering

Enhanced stereo capture (ESC)

A configurable sound engine provides enhanced record and

playback processing to improve overall audio quality.

Dual-band automatic level control (ALC)

6-band equalizer, including notch filter

Sampling rates from 8 kHz to 96 kHz

Stereo pseudo differential microphone input

Optional stereo digital microphone input pulse-density

modulation (PDM)

Stereo line output

PLL supporting a range of input clock rates

Analog and digital I/O 1.8 V to 3.3 V

Software control via SigmaStudio graphical user interface

Software-controllable, clickless mute

Software register and hardware pin standby mode

32-lead, 5 mm × 5 mm LFCSP or 30-ball, 6 × 5 bump WLCSP

The record path includes two digital stereo microphone inputs

and an analog stereo input path. The analog inputs can be

configured for either a pseudo differential or a single-ended

stereo source. A dedicated analog beep input signal can be

mixed into any output path. The ADAU1381 includes a stereo

line output and speaker driver, which makes the device capable of

supporting dynamic speakers.

The serial control bus supports the I²C® or SPI protocols, and

the serial audio bus is programmable for I²S, left-justified, right-

justified, or TDM mode. A programmable PLL supports flexible

clock generation for all standard rates and available master clocks

from 11 MHz to 20 MHz.

APPLICATIONS

Digital still cameras

Digital video cameras

FUNCTIONAL BLOCK DIAGRAM

ADAU1381

REGULATOR

BEEP

PGA

SOUND ENGINE

AOUTL

AOUTR

LMIC/LMICN/

MICD1

DECIMATION

FILTERS

LEFT

PGA

ADC

DAC

WIND NOISE

NOTCH FILTER

EQUALIZER

LMICP

OUTPUT

MIXER

RMIC/RMICN/

MICD2

SPP

SPN

DIGITAL VOLUME

CONTROL

RIGHT

DAC

PGA

ADC

RMICP

PDN

AUTOMATIC LEVEL

CONTROL

2

SERIAL DATA

INPUT/OUTPUT PORTS

I C/SPI

CONTROL PORT

MICROPHONE

BIAS

MICBIAS

PLL

Figure 1.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADAU1381

TABLE OF CONTENTS

Features .............................................................................................. 1

Input Signal Path ........................................................................ 30

Analog-to-Digital Converters................................................... 31

Digital Dual-Band Automatic Level Control (ALC) ............. 31

Playback Signal Path ...................................................................... 32

Output Signal Paths ................................................................... 32

Digital-to-Analog Converters................................................... 32

Line Outputs ............................................................................... 32

Speaker Output........................................................................... 32

Control Ports................................................................................... 33

I²C Port ........................................................................................ 33

SPI Port........................................................................................ 36

Memory and Register Access.................................................... 36

Serial Data Input/Output Ports .................................................... 38

TDM Modes................................................................................ 38

General-Purpose Input/Outputs.................................................. 40

Sound Engine.................................................................................. 41

Signal Processing........................................................................ 41

Processing Flow.......................................................................... 41

Programming.............................................................................. 41

Parameter Memory .................................................................... 41

Applications Information.............................................................. 42

Power Supply Bypass Capacitors.............................................. 42

GSM Noise Filter........................................................................ 42

Grounding................................................................................... 42

Speaker Driver Supply Trace (AVDD2) .................................. 42

Exposed Pad PCB Design ......................................................... 42

Control Register Map..................................................................... 43

Clock Management, Internal Regulator, and PLL Control... 44

Record Path Configuration....................................................... 48

Serial Port Configuration.......................................................... 53

Audio Converter Configuration............................................... 58

Playback Path Configuration.................................................... 63

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

Specifications..................................................................................... 4

Record Side Performance Specifications................................... 4

Output Side Performance Specifications................................... 6

Power Supply Specifications........................................................ 8

Typical Power Management Measurements ............................. 9

Digital Filters................................................................................. 9

Digital Input/Output Specifications......................................... 10

Digital Timing Specifications ................................................... 11

Absolute Maximum Ratings.......................................................... 14

Thermal Resistance .................................................................... 14

ESD Caution................................................................................ 14

Pin Configuration and Function Descriptions........................... 15

Typical Performance Characteristics ........................................... 17

System Block Diagrams ................................................................. 20

Theory of Operation ...................................................................... 24

Startup, Initialization, and Power................................................. 25

Power-Up Sequence ................................................................... 25

Clock Generation and Management........................................ 26

Enabling Digital Power to Functional Subsystems ................ 26

Setting Up the Sound Engine.................................................... 26

Power Reduction Modes............................................................ 26

Power-Down Sequence.............................................................. 26

Clocking and Sampling Rates ....................................................... 27

Core Clock................................................................................... 27

Sampling Rates............................................................................ 27

PLL ............................................................................................... 28

Record Signal Path.......................................................................... 30

Rev. 0 | Page 2 of 84

ADAU1381

Pad Configuration.......................................................................70

Digital Subsystem Configuration..............................................76

Outline Dimensions........................................................................83

Ordering Guide ...........................................................................83

REVISION HISTORY

10/09—Revision 0: Initial Version

Rev. 0 | Page 3 of 84

ADAU1381

SPECIFICATIONS

Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications.

Supply voltages AVDD = AVDD1 = AVDD2 = I/O supply = 3.3 V, digital supply = 1.5 V, unless otherwise noted; temperature = 25°C;

master clock (MCLK) = 12.288 MHz (f_S= 48 kHz, 256 × f_Smode); input sample rate = 48 kHz; measurement bandwidth = 20 Hz to 20 kHz;

word width = 24 bits; load capacitance (digital output) = 20 pF; load current (digital output) = 2 mA; high level input voltage = 0.7 × IOVDD;

and low level input voltage = 0.3 × IOVDD. All power management registers are set to their default states.

RECORD SIDE PERFORMANCE SPECIFICATIONS

Specifications guaranteed at 25°C (ambient).

Table 1.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

ANALOG-TO-DIGITAL CONVERTERS

ADC Resolution

Digital Attenuation Step

Digital Attenuation Range

INPUT RESISTANCE

All ADCs

24

0.375

95

Bits

dB

Noninverting Inputs PGA

(LMICP, RMICP)

All gain settings

500

kΩ

Inverting Inputs PGA (LMICN, RMICN)

0 dB gain

6 dB gain

10 dB gain

14 dB gain

17 dB gain

20 dB gain

26 dB gain

32 dB gain

0 dB

6 dB

10 dB

14 dB

−23 dB

62

32

22

14

10

8

5

4

20

9

6

3.5

50

2

kΩ

Beep Input PGA

20 dB

26 dB

32 dB

SINGLE-ENDED MICROPHONE INPUT

TO ADC PATH

Full-Scale Input Voltage (0 dB)

Scales linearly with AVDD

AVDD = 1.8 V

AVDD = 3.3 V

−60 dB input

AVDD = 1.8 V

AVDD = 3.3 V

AVDD = 1.8 V

AVDD = 3.3 V

−3 dBFS

AVDD/3.3

0.55 (1.56)

1.0 (2.83)

V rms

V rms (V p-p)

Dynamic Range

With A-Weighted Filter (RMS)

96

99.2

92

dB

94

92

No Filter (RMS)

96.5

Total Harmonic Distortion + Noise

AVDD = 1.8 V

AVDD = 3.3 V

−88

−90

dB

Signal-to-Noise Ratio

With A-Weighted Filter (RMS)

AVDD = 1.8 V

AVDD = 3.3 V

AVDD = 1.8 V

AVDD = 3.3 V

96

100

92

dB

No Filter (RMS)

97

Rev. 0 | Page 4 of 84

ADAU1381

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

Left/Right Microphone PGA Gain

Range

AVDD = 3.3 V

0

32

dB

Left/Right Microphone PGA Mute

Attenuation

AVDD = 3.3 V; mute set by Register

0x400E, Bit 1, and Register 0x400F, Bit 1

−98

dB

Interchannel Gain Mismatch

Offset Error

Gain Error

AVDD = 3.3 V

50

0.25

−1

mdB

mV

%

Interchannel Isolation

Power Supply Rejection Ratio

AVDD = 3.3 V

−98

dB

CM capacitor = 10 μF

AVDD = 3.3 V, 100 mV p-p at 217 Hz

AVDD = 3.3 V, 100 mV p-p at 1 kHz

−55

dB

DIFFERENTIAL MICROPHONE INPUT TO

ADC PATH

Full-Scale Input Voltage (0 dB)

Scales linearly with AVDD

AVDD = 1.8 V

AVDD = 3.3 V

−60 dB input

AVDD = 1.8 V

AVDD = 3.3 V

AVDD = 1.8 V

AVDD = 3.3 V

−3 dBFS

AVDD/3.3

0.55 (1.56)

1.0 (2.83)

V rms

V rms (V p-p)

Dynamic Range

With A-Weighted Filter (RMS)

96

99.2

92

dB

94

92

No Filter (RMS)

96.5

Total Harmonic Distortion + Noise

AVDD = 1.8 V

AVDD = 3.3 V

−84

−85

dB

Signal-to-Noise Ratio

With A-Weighted Filter (RMS)

AVDD = 1.8 V

AVDD = 3.3 V

AVDD = 1.8 V

AVDD = 3.3 V

AVDD = 3.3 V; mute set by Register

0x400E, Bit 1, and Register 0x400F, Bit 1

96

100

92

97

−98

dB

No Filter (RMS)

Left/Right Microphone PGA Mute

Attenuation

Interchannel Gain Mismatch

Offset Error

Gain Error

AVDD = 3.3 V

50

0.25

−1

mdB

mV

%

Interchannel Isolation

Common-Mode Rejection Ratio

AVDD = 3.3 V

AVDD = 3.3 V, 100 mV rms, 1 kHz

AVDD = 3.3 V, 100 mV rms, 20 kHz

−85

−60

−45

dB

BEEP TO LINE OUTPUT PATH

Full-Scale Input Voltage (0 dB)

Scales linearly with AVDD

AVDD = 1.8 V

AVDD = 3.3 V

AVDD/3.3

0.55 (1.56)

1.0 (2.83)

V rms

V rms (V p-p)

Total Harmonic Distortion + Noise

−3 dBFS input, measured at AOUTL pin,

beep gain set to 0 dB

AVDD = 1.8 V

AVDD = 3.3 V

−88

dB

Signal-to-Noise Ratio

With A-Weighted Filter (RMS)

AVDD = 1.8 V

AVDD = 3.3 V

AVDD = 1.8 V

AVDD = 3.3 V

99

105

96

dB

No Filter (RMS)

102

Rev. 0| Page 5 of 84

ADAU1381

Parameter

Test Conditions/Comments

−60 dB input

Min

Typ

Max

Unit

Dynamic Range

With A-Weighted Filter (RMS)

AVDD = 1.8 V

AVDD = 3.3 V

AVDD = 1.8 V

AVDD = 3.3 V

AVDD = 3.3 V; mute set by

Register 0x4008, Bit 3

99

105

96

102

−90

dB

No Filter (RMS)

Beep Input Mute Attenuation

Offset Error

Gain Error

Interchannel Gain Mismatch

Beep Input PGA Gain Range

Beep Playback Mixer Gain Range

Power Supply Rejection Ratio

AVDD = 3.3 V

10

−0.3

30

mV

dB

mdB

dB

AVDD = 3.3 V

CM capacitor = 10 μF

−23

−15

+32

+6

dB

AVDD = 3.3 V, 100 mV p-p at 217 Hz

AVDD = 3.3 V, 100 mV p-p at 1 kHz

Microphone bias enabled

−58

−72

dB

MICROPHONE BIAS

Bias Voltage

0.65 × AVDD

AVDD = 1.8 V, low bias

AVDD = 3.3 V, low bias

AVDD = 1.8 V, high bias

AVDD = 3.3 V, high bias

1.17

2.145

1.62

2.97

V

0.90 × AVDD

Bias Current Source

AVDD = 3.3 V, high bias, high

performance

5

mA

Noise in the Signal Bandwidth

AVDD = 3.3 V, 20 Hz to 20 kHz

High bias, high performance

High bias, low performance

Low bias, high performance

Low bias, low performance

AVDD = 1.8 V, 20 Hz to 20 kHz

High bias, high performance

High bias, low performance

Low bias, high performance

Low bias, low performance

39

78

25

35

nV√Hz

35

45

23

nV√Hz

OUTPUT SIDE PERFORMANCE SPECIFICATIONS

Specifications guaranteed at 25°C (ambient).

Table 2.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

DIGITAL-TO-ANALOG CONVERTERS

DAC Resolution

Digital Attenuation Step

Digital Attenuation Range

DAC TO LINE OUTPUT PATH

Full-Scale Output Voltage (0 dB)

All DACs

24

0.375

95

Bits

dB

Scales linearly with AVDD

AVDD = 1.8 V

AVDD = 3.3 V

AVDD = 3.3 V; mute set by Register

0x401C, Bit 5, and Register 0x401E, Bit 6

AVDD/3.3

0.55 (1.56)

1.0 (2.83)

−85

V rms

V rms (V p-p)

dB

Line Output Mute Attenuation,

DAC to Mixer Path Muted

Line Output Mute Attenuation,

Line Output Muted

AVDD = 3.3 V; mute set by Register

0x4025, Bit 1, and Register 0x4026, Bit 1

−85

dB

Rev. 0 | Page 6 of 84

ADAU1381

Parameter

Test Conditions/Comments

−60 dB input

AVDD = 1.8 V

AVDD = 3.3 V

AVDD = 1.8 V

AVDD = 3.3 V

−3 dBFS

Min

Typ

Max

Unit

Dynamic Range

With A-Weighted Filter (RMS)

99

103

97

dB

94

92

No Filter (RMS)

100

Total Harmonic Distortion + Noise

AVDD = 1.8 V

AVDD = 3.3 V

−88

Signal-to-Noise Ratio

With A-Weighted Filter (RMS)

AVDD = 1.8 V

AVDD = 3.3 V

AVDD = 1.8 V

AVDD = 3.3 V

99

103

97

dB

No Filter (RMS)

100

Power Supply Rejection Ratio

CM capacitor = 10 μF

AVDD = 3.3 V, 100 mV p-p at 217 Hz

AVDD = 3.3 V, 100 mV p-p at 1 kHz

AVDD = 3.3 V

−55

−63

−1

dB

Gain Error

Interchannel Gain Mismatch

Offset Error

AVDD = 3.3 V

50

10

mdB

mV

DAC TO SPEAKER OUTPUT PATH

P_O= output power

Differential Full-Scale Output Voltage Scales linearly with AVDD

(0 dB)

AVDD/1.65

V rms

AVDD = 1.8 V

AVDD = 3.3 V

1.1 (3.12)

2.0 (5.66)

V rms (V p-p)

Total Harmonic Distortion + Noise

4 Ω Load

AVDD = 1.8 V, P_O= 50 mW

AVDD = 3.3 V, P_O= 175 mW

AVDD = 1.8 V, P_O= 50 mW

AVDD = 3.3 V, P_O= 175 mW

AVDD = 3.3 V, P_O= 330 mW

AVDD = 3.3 V, P_O= 440 mW

−60 dB input

−60

−16

dB

8 Ω Load

Dynamic Range

With A-Weighted Filter (RMS)

AVDD = 1.8 V

AVDD = 3.3 V

AVDD = 1.8 V

AVDD = 3.3 V

100

105

98

dB

94

92

No Filter (RMS)

103

Signal-to-Noise Ratio

With A-Weighted Filter (RMS)

AVDD = 1.8 V

AVDD = 3.3 V

AVDD = 1.8 V

AVDD = 3.3 V

100

105

98

dB

No Filter (RMS)

103

Power Supply Rejection Ratio

CM capacitor = 10 μF

AVDD = 3.3 V,100 mV p-p at 217 Hz

AVDD = 3.3 V, 100 mV p-p at 1 kHz

AVDD = 3.3 V

−55

2

dB

mV

dB

Differential Offset Error

Mono Mixer Mute Attenuation,

DAC to Mixer Path Muted

Mute set by Register 0x401F, Bit 0

−90

BEEP TO SPEAKER OUTPUT PATH

P_O= output power

Differential Full-Scale Output Voltage Scales linearly with AVDD

(0 dB)

AVDD/1.65

V rms

AVDD = 1.8 V

AVDD = 3.3 V

1.1 (3.12)

2.0 (5.66)

V rms (V p-p)

Rev. 0| Page 7 of 84

ADAU1381

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

Total Harmonic Distortion + Noise

8 Ω, 1 nF load, AVDD = 1.8 V, P_O= 50 mW

AVDD = 3.3 V, P_O= 175 mW

−60 dB input

−60

dB

Dynamic Range

With A-Weighted Filter (RMS)

AVDD = 1.8 V

AVDD = 3.3 V

AVDD = 1.8 V

AVDD = 3.3 V

97

103

94

dB

No Filter (RMS)

100

Signal-to-Noise Ratio

With A-Weighted Filter (RMS)

AVDD = 1.8 V

AVDD = 3.3 V

AVDD = 1.8 V

AVDD = 3.3 V

98

103

96

dB

No Filter (RMS)

101

Power Supply Rejection Ratio

CM capacitor = 10 μF

100 mV p-p at 217 Hz

100 mV p-p at 1 kHz

−57

−60

2

dB

mV

dB

Differential Offset Error

Mono Mixer Mute Attenuation,

Beep to Mixer Path Muted

Mute set by Register 0x401F, Bit 0

−90

REFERENCE (CM PIN)

Common-Mode Reference Output

AVDD/2

V

POWER SUPPLY SPECIFICATIONS

AVDD1 and AVDD2 must always be equal. Power supply measurements are taken with the sound engine processing path enabled.

Table 3.

Parameter

Test Conditions/Comments

Min

1.8

Typ

3.3

Max

3.65

Unit

V

AVDD1, AVDD2

IOVDD

1.63

3.3

V

Digital I/O Current (IOVDD = 3.3 V)

Slave Mode, Analog I/O,

20 pF capacitive load on all digital pins

f_S= 48 kHz

0.20

mA

12.288 MHz External MCLK Input

f_S= 96 kHz

f_S= 8 kHz

f_S= 48 kHz

f_S= 96 kHz

0.35

0.04

1.25

2.50

0.22

mA

Master Mode, MCKO Disabled

f_S= 8 kHz

Digital I/O Current (IOVDD = 1.8 V)

Slave Mode, Analog I/O,

20 pF capacitive load on all digital pins

f_S= 48 kHz

0.10

mA

12.288 MHz External MCLK Input

f_S= 96 kHz

f_S= 8 kHz

f_S= 48 kHz

f_S= 96 kHz

f_S= 8 kHz

See Table 4

0.18

0.02

0.68

1.33

0.12

mA

Master Mode, MCKO Disabled

Analog Current (AVDD)

Rev. 0 | Page 8 of 84

ADAU1381

TYPICAL POWER MANAGEMENT MEASUREMENTS

Master clock = 12.288 MHz, PLL is active in integer mode at a 256 × f_Sinput rate for f_S= 48 kHz, analog and digital input tones are

−1 dBFS with a frequency of 1 kHz. Analog input and output are simultaneously active. Pseudo differential stereo input is routed to

ADCs, and DACs are routed to stereo line output with a 16 kΩ load. ADC input at −1 dBFS, DAC input at 0 dBFS. The speaker output is

disabled. The serial port is configured in slave mode. The beep path is disabled. The sound engine processing path is enabled. Current

measurements are given in units of mA rms.

Table 4. Mixer Boost and Power Management Conditions

Typical AVDD Current Typical ADC

Typical Line Output

THD + N (dB)

Operating Voltage

AVDD = IOVDD = 3.3 V Normal (default)

Power Management Mode¹

Mixer Boost Mode²

Normal operation

Boost Level 1

Boost Level 2

Boost Level 3

Normal operation

Boost Level 1

Boost Level 2

Boost Level 3

Normal operation

Boost Level 1

Boost Level 2

Boost Level 3

Normal operation

Boost Level 1

Boost Level 2

Boost Level 3

Normal operation

Boost Level 1

Boost Level 2

Boost Level 3

Normal operation

Boost Level 1

Boost Level 2

Boost Level 3

Normal operation

Boost Level 1

Boost Level 2

Boost Level 3

Normal operation

Boost Level 1

Boost Level 2

Boost Level 3

Consumption (mA)

16.84

16.88

16.92

17.00

15.66

15.68

15.70

15.75

17.43

17.50

17.53

17.63

16.25

16.28

16.31

16.38

15.15

15.19

15.23

15.30

14.03

14.05

14.07

14.12

15.71

15.76

15.81

15.89

14.59

14.62

14.65

14.71

THD + N (dB)

88.5

88.0

88.5

89.0

88.5

86.5

88.5

88.0

93.0

87.5

94.5

90.5

89.5

85.5

90.5

88.0

Extreme power saving

Enhanced performance

Power saving

AVDD = IOVDD = 1.8 V Normal (default)

Extreme power saving

Enhanced performance

Power saving

¹Set by Register 0x4009, Bits[4:1], and Register 0x4029, Bits[5:2].

²Set by Register 0x4009, Bits[6:5].

DIGITAL FILTERS

Table 5.

Parameter

Mode

All modes, typ value is for 48 kHz

Factor

Min

Typ

Max

Unit

ADC DECIMATION FILTER

Pass Band

Pass-Band Ripple

Transition Band

Stop Band

0.4375 × f_S

21

0.015

24

27

kHz

dB

kHz

dB

0.5 × f_S

0.5625 × f_S

Stop-Band Attenuation

Group Delay

70

22.9844/f_S

479

ꢀs

Rev. 0| Page 9 of 84

ADAU1381

Parameter

Mode

Factor

Min

Typ

Max

Unit

DAC INTERPOLATION FILTER

Pass Band

48 kHz mode, typ value is for 48 kHz

96 kHz mode, typ value is for 96 kHz

48 kHz mode, typ value is for 48 kHz

96 kHz mode, typ value is for 96 kHz

48 kHz mode, typ value is for 48 kHz

96 kHz mode, typ value is for 96 kHz

48 kHz mode, typ value is for 48 kHz

96 kHz mode, typ value is for 96 kHz

48 kHz mode, typ value is for 48 kHz

96 kHz mode, typ value is for 96 kHz

48 kHz mode, typ value is for 48 kHz

96 kHz mode, typ value is for 96 kHz

0.4535 × f_S

0.3646 × f_S

22

69

kHz

dB

35

Pass-Band Ripple

Transition Band

Stop Band

0.01

0.05

dB

0.5 × f_S

0.5465 × f_S

0.6354 × f_S

24

48

26

61

kHz

dB

ꢀs

Stop-Band Attenuation

Group Delay

70

25/f_S

11/f_S

521

115

DIGITAL INPUT/OUTPUT SPECIFICATIONS

−25°C < T_A< +85°C, IOVDD = 1.62 V to 3.63 V, unless otherwise specified.

Table 6.

Parameter

Conditions/Comments

Min

0.7 × IOVDD

Typ

Max

Unit

HIGH LEVEL INPUT VOLTAGE (V_IH)

LOW LEVEL INPUT VOLTAGE (V_IL)

V

IOVDD ≥ 2.97 V

1.8 V ≤ IOVDD ≤ 2.97 V

IOVDD < 1.8 V

0.3 × IOVDD

0.2 × IOVDD

0.1 × IOVDD

V

INPUT LEAKAGE

I_IHat V_IH= 2.4 V

I_ILat V_IL= 0.8 V

I_ILof MCKI

I_IHwith internal pull-up

I_ILwith internal pull-down

I_IHwith internal pull-up

I_ILwith internal pull-down

0.17

−7

0.7

−7

ꢀA

V

5

0.18

HIGH LEVEL OUTPUT VOLTAGE (V_OH)

LOW LEVEL OUTPUT VOLTAGE (V_OL)

INPUT CAPACITANCE

For low drive strength, I_OH= 2 mA and I_OL= 2 mA

at IOVDD = 3.3 V, I_OH= 0.6 mA and I_OL= 0.6 mA at

IOVDD = 1.8 V; for high drive strength, I_OH= 3 mA

and I_OL= 3 mA at IOVDD = 3.3 V, I_OH= 0.9 mA and

IOVDD − 0.4

I

_OL= 0.9 mA at IOVDD = 1.8 V

For low drive strength, I_OH= 2 mA and I_OL= 2 mA

at IOVDD = 3.3 V, I_OH= 0.6 mA and I_OL= 0.6 mA at

IOVDD = 1.8 V; for high drive strength, I_OH= 3 mA

and I_OL= 3 mA at IOVDD = 3.3 V, I_OH= 0.9 mA and

0.4

5

V

I

_OL= 0.9 mA at IOVDD = 1.8 V

pF

Rev. 0 | Page 10 of 84

ADAU1381

DIGITAL TIMING SPECIFICATIONS

−25°C < T_A< +85°C, IOVDD = 1.62 V to 3.63 V, unless otherwise specified.

Table 7. Digital Timing

Limit

Parameter

t_MIN

t_MAX

Unit

Description

MASTER CLOCK

t_MP

Duty Cycle

SERIAL PORT

t_BIL

t_BIH

t_LIS

t_LIH

t_SIS

t_SIH

t_SODM

SPI PORT

f_CCLK,R

f_CCLK,W

t_CCPL

50

30

90.9

70

ns

%

Master clock (MCLK) period (that is, period of the signal input to MCKI).

10

5

ns

BCLK pulse width low.

BCLK pulse width high.

LRCLK setup. Time to BCLK rising.

LRCLK hold. Time from BCLK rising.

DAC_SDATA setup. Time to BCLK rising.

DAC_SDATA hold. Time from BCLK rising.

ADC_SDATA delay. Time from BCLK falling in master mode.

5

70

5

MHz

ns

CCLK frequency, read operation, IOVDD = 1.8 V 10%.

CCLK frequency, read operation, IOVDD = 3.3 V 10%.

CCLK frequency, write operation, IOVDD = 1.8 V 10%.

CCLK frequency, write operation, IOVDD = 3.3 V 10%.

CCLK pulse width low.

10

25

10

5

t_CCPH

t_CLS

ns

CCLK pulse width high.

CLATCH setup. Time to CCLK rising.

t_CLH

ns

CLATCH hold. Time from CCLK rising.

t_CLPH

10

5

ns

CLATCH pulse width high.

t_CDS

ns

CDATA setup. Time to CCLK rising.

t_CDH

5

ns

CDATA hold. Time from CCLK rising.

t_COD

70

40

COUT delay from CCLK edge to valid data, IOVDD = 1.8 V 10%.

COUT delay from CCLK edge to valid data, IOVDD = 3.3 V 10%.

ns

I²C PORT

f_SCL

t_SCLH

t_SCLL

t_SCS

t_SCH

t_DS

t_SCR

t_SCF

400

kHz

ꢀs

ns

ꢀs

SCL frequency.

SCL high.

SCL low.

Setup time; relevant for repeated start condition.

Hold time. After this period, the first clock is generated.

Data setup time.

SCL rise time.

SCL fall time.

SDA rise time.

SDA fall time.

Bus-free time. Time between stop and start.

R_L= 1 MΩ, C_L= 14 pF.

0.6

1.3

0.6

100

300

t_SDR

t_SDF

t_BFT

0.6

DIGITAL MICROPHONE

t_DCF

t_DCR

t_DDV

t_DDH

10

30

12

ns

Digital microphone clock fall time.

Digital microphone clock rise time.

Digital microphone delay time for valid data.

Digital microphone delay time for data three-stated.

22

0

Rev. 0| Page 11 of 84

ADAU1381

Digital Timing Diagrams

t_LIH

t_BIH

BCLK

t_BIL

t_LIS

LRCLK

t_SIS

DAC_SDATA

LEFT-JUSTIFIED

MODE

MSB

MSB – 1

t_SIH

t_SIS

DAC_SDATA

I S MODE

2

MSB

t_SIH

t_SIS

DAC_SDATA

RIGHT-JUSTIFIED

MODE

LSB

MSB

t_SIH

8-BIT CLOCKS

(24-BIT DATA)

12-BIT CLOCKS

(20-BIT DATA)

14-BIT CLOCKS

(18-BIT DATA)

16-BIT CLOCKS

(16-BIT DATA)

Figure 2. Serial Input Port Timing

t_BIH

BCLK

t_BIL

LRCLK

t_SODM

MSB

ADC_SDATA

LEFT-JUSTIFIED

MODE

MSB – 1

t_SODM

MSB

ADC_SDATA

I S MODE

2

t_SODM

ADC_SDATA

RIGHT-JUSTIFIED

MODE

LSB

MSB

8-BIT CLOCKS

(24-BIT DATA)

12-BIT CLOCKS

(20-BIT DATA)

14-BIT CLOCKS

(18-BIT DATA)

16-BIT CLOCKS

(16-BIT DATA)

Figure 3. Serial Output Port Timing

Rev. 0 | Page 12 of 84

ADAU1381

t_CLS

t_CLH

t_CLPH

t_CCPL

t_CCPH

CLATCH

CCLK

CDATA

t_CDH

t_CDS

COUT

t_COD

Figure 4. SPI Port Timing

t_SDR

t_SCH

t_DS

t_SCH

SDA

SCL

t_SDF

t_SCR

t_SCLH

t_SCS

t_BFT

t_SCLLt_SCF

Figure 5. I²C Port Timing

t_DCF

t_DCR

CLK

t_DDH

t_DDV

DATA1/

DATA2

DATA1

DATA2

DATA1

DATA2

Figure 6. Digital Microphone Timing

Rev. 0| Page 13 of 84

ADAU1381

ABSOLUTE MAXIMUM RATINGS

Table 8.

THERMAL RESISTANCE

In Table 9, θ_JAis the junction-to-ambient thermal resistance, θ_JBis

the junction-to-board thermal resistance, θ_JCis the junction-to-case

thermal resistance, ψ_JBis the in-use junction-to-top of package ther-

mal resistance, and ψ_JTis the in-use junction-to-board thermal

resistance. All characteristics are for a 4-layer board.

Parameter

Rating

Power Supply (AVDD1 = AVDD2)

Input Current (Except Supply Pins)

Analog Input Voltage (Signal Pins)

Digital Input Voltage (Signal Pins)

−0.3 V to +3.9 V

20 mA

–0.3 V to VDD + 0.3 V

−0.3 V to VDD + 0.3 V

Operating Temperature Range (Case) −25°C to +85°C

Storage Temperature Range −65°C to +150°C

Table 9. Thermal Resistance

Package Type

32-Lead LFCSP

30-Ball WLCSP

θ_JA

35

39

θ_JB

19

7

θ_JC

2.5

0.5

ψ_JB

ψ_JT

Unit

°C/W

18

0.3

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

ESD CAUTION

Rev. 0 | Page 14 of 84

ADAU1381

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

CM

PDN

AGND1

AVDD1

DVDDOUT

DGND

1

2

3

4

5

6

7

8

24 NC

23 AGND2

22 SPP

PIN 1

INDICATOR

21 NC

ADAU1381

TOP VIEW

(Not to Scale)

20 SPN

19 AVDD2

18 MCKO

17 MCKI

GPIO

SCL/CCLK

NOTES

1. NC = NO CONNECT.

2. THE EXPOSED PAD IS CONNECTED INTERNALLY TO THE

ADAU1381 GROUNDS. FOR INCREASED RELIABILITY OF THE

SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS

RECOMMENDED THAT THE PAD BE SOLDERED TO THE

GROUND PLANE.

Figure 7. 32-Lead LFCSP Pin Configuration

1

2

3

4

5

6

LMIC/

LIMICN/

MICD1

AGND2

AOUTL

RMICP

MICBIAS

CM

A

RMIC/

RMICN/

MICD2

SPP

SPN

AOUTR

LMICP

BEEP

PDN

AGND1

AVDD1

B

C

D

E

LRCLK/

GPIO3

ADDR0/

CDATA

SCL/

CCLK

ADC_

SDATA/

GPIO1

ADDR1/

CLATCH

AVDD2

MCKI

MCKO

GPIO

DVDDOUT

DGND

DAC_

SDATA/

GPIO0

BCLK/

GPIO2

SDA/

COUT

IOVDD

TOP VIEW

(BALL SIDE DOWN)

Not to Scale

Figure 8. 30-Ball, 6 × 5 WLCSP Pin Configuration (Bottom View)

Rev. 0| Page 15 of 84

ADAU1381

Table 10. Pin Function Descriptions

Pin No.

LFCSP WLCSP Mnemonic

Type¹

Description

1

A6

CM

A_OUT VDD/2 V Common-Mode Reference. A 10 μF to 47 μF decoupling capacitor should be

connected between this pin and ground to reduce crosstalk between the ADCs and

DACs. The material of the capacitors is not critical. This pin can be used to bias external

analog circuits, as long as they are not drawing current from CM (for example, the

noninverting input of an op amp).

2

3

4

5

C5

B6

C6

D6

PDN

A_IN

PWR

Power-Down. Setting this pin to 0 powers down the chip. Resides in AVDD1 domain.

Analog Ground.

Analog Power Supply. Should be equivalent to AVDD2.

Digital Core Supply Decoupling Point. The digital supply is generated from an on-

board regulator and does not require an external supply. DVDDOUT should be

decoupled to DGND with a 100 nF capacitor.

AGND1

AVDD1

DVDDOUT

6

7

8

9

10

11

12

E6

D5

C4

E5

C3

D4

E4

DGND

GPIO

PWR

D_IO

D_IN

D_IO

D_IN

PWR

Digital Ground.

Dedicated General-Purpose Input/Output.

I²C Clock/SPI Clock.

I²C Data/SPI Data Output.

I²C Address 0/SPI Data Input.

I²C Address 1/SPI Latch Signal.

SCL/CCLK

SDA/COUT

ADDR0/CDATA

ADDR1/CLATCH

IOVDD

Supply for Digital Input and Output Pins. The digital output pins are supplied from

IOVDD, which sets the highest allowed input voltage for the digital input pins. The

current draw of this pin is variable because it is dependent on the loads of the digital

outputs. IOVDD should be decoupled to DGND with a 100 nF capacitor.

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

E3

D3

E2

C2

E1

D2

D1

C1

N/A

B1

A1

N/A

B2

A2

B3

DAC_SDATA/GPIO0

ADC_SDATA/GPIO1

BCLK/GPIO2

LRCLK/GPIO3

MCKI

MCKO

AVDD2

SPN

NC

SPP

AGND2

NC

AOUTR

D_IO

D_IN

DAC Serial Input Data/General-Purpose Input and Output.

ADC Serial Output Data/General-Purpose Input and Output.

Serial Data Port Bit Clock/General-Purpose Input and Output.

Serial Data Port Frame Clock/General-Purpose Input and Output.

Master Clock Input.

D_OUT Master Clock Output.

PWR

A_OUT Speaker Amplifier Negative Signal Output.

No Connect.

A_OUT Speaker Amplifier Positive Signal Output.

Analog Power Supply. Should be equivalent to AVDD1.

PWR

Speaker Amplifier Ground.

No Connect.

A_OUT Line Output Amplifier, Right Channel.

A_OUT Line Output Amplifier, Left Channel.

AOUTL

RMIC/RMICN/MICD2 A_IN

Right Channel Input from Single-Ended Source/Right Channel Input from Negative

Pseudo Differential Source/Digital Microphone Input 2.

28

29

30

A3

B4

A4

RMICP

LMICP

A_IN

Right Channel Input from Positive Pseudo Differential Source.

Left Channel Input from Positive Pseudo Differential Source.

Left Channel Input from Single-Ended Source/Left Channel Input from Negative

Pseudo Differential Source/Digital Microphone Input 1.

LMIC/LMICN/MICD1 A_IN

31

32

B5

A5

BEEP

MICBIAS

A_IN

PWR

Beep Signal Input.

Microphone Bias.

THERM_PAD

(Exposed Pad)

Exposed Pad. The exposed pad is connected internally to the ADAU1381 grounds. For

increased reliability of the solder joints and maximum thermal capability, it is

recommended that the pad be soldered to the ground plane.

¹A_OUT = analog output, A_IN = analog input, PWR = power, D_IO = digital input/output, D_OUT = digital output, and D_IN = digital input.

Rev. 0 | Page 16 of 84

ADAU1381

TYPICAL PERFORMANCE CHARACTERISTICS

0

0.10

0.08

0.06

0.04

0.02

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–0.02

–0.04

–0.06

–0.08

–0.10

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

0

0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50

FREQUENCY (NORMALIZED TO f_S

)

Figure 9. ADC Decimation Filter, 64× Oversampling,

Normalized to f_S

Figure 12. ADC Decimation Filter Pass-Band Ripple, 128× Oversampling,

Normalized to f_S

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0.04

0.02

0

–0.02

–0.04

–0.06

0

0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40

FREQUENCY (NORMALIZED TO f_S

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

)

FREQUENCY (NORMALIZED TO f_S

)

Figure 13. ADC Decimation Filter, Double-Rate Mode,

Normalized to f_S

Figure 10. ADC Decimation Filter Pass-Band Ripple, 64× Oversampling,

Normalized to f_S

0

0.04

0.02

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–0.02

–0.04

–0.06

0

0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40

FREQUENCY (NORMALIZED TO f_S

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

)

FREQUENCY (NORMALIZED TO f_S

)

Figure 14. ADC Decimation Filter Pass-Band Ripple, Double-Rate Mode,

Normalized to f_S

Figure 11. ADC Decimation Filter, 128× Oversampling,

Normalized to f_S

Rev. 0| Page 17 of 84

ADAU1381

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0.05

0.04

0.03

0.02

0.01

0

–0.01

–0.02

–0.03

–0.04

–0.05

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

0

0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50

FREQUENCY (NORMALIZED TO f_S

)

Figure 15. DAC Interpolation Filter, 64× Oversampling,

Normalized to f_S

Figure 18. DAC Interpolation Filter Pass-Band Ripple, 128× Oversampling,

Normalized to f_S

0.20

0.15

0.10

0.05

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–0.05

–0.10

–0.15

–0.20

0

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

FREQUENCY (NORMALIZED TO f_S

)

FREQUENCY (NORMALIZED TO f_S

)

Figure 16. DAC Interpolation Filter Pass-Band Ripple, 64× Oversampling,

Normalized to f_S

Figure 19. DAC Interpolation Filter, Double-Rate Mode,

Normalized to f_S

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0.20

0.15

0.10

0.05

0

–0.05

–0.10

–0.15

–0.20

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

0

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

FREQUENCY (NORMALIZED TO f_S

)

FREQUENCY (NORMALIZED TO f_S

)

Figure 17. DAC Interpolation Filter, 128× Oversampling,

Normalized to f_S

Figure 20. DAC Interpolation Filter Pass-Band Ripple, Double-Rate Mode,

Normalized to f_S

Rev. 0 | Page 18 of 84

ADAU1381

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

–20

–40

–60

–80

–100

1

10

100

600

1

10

100

SPEAKER OUTPUT POWER (mW)

Figure 21. THD + N vs. Speaker Output Power, 8 Ω Load, 3.3 V Supply

Figure 22. THD + N vs. Speaker Output Power, 8 Ω Load, 1.8 V Supply

Rev. 0| Page 19 of 84

ADAU1381

SYSTEM BLOCK DIAGRAMS

IOVDD

10µF

AVDD1

10µF

AVDD2

47µF

0.1µF

MICBIAS

–

+

8Ω

SPEAKER

OUT

0.1µF

DIFFERENTIAL INPUT

(LEFT)

100pF

10µF

LMIC/LMICN/MICD1

LMICP

SPN

SPP

STEREO SINGLE-ENDED

HEADPHONE OUTPUT

49.9kΩ

10kΩ

LEFT_OUT

220µF

AOUTL

AOUTR

10Ω

49.9kΩ

10kΩ

ADAU1381

100pF

DIFFERENTIAL INPUT

(RIGHT)

10µF

10kΩ

RMIC/RMICN/MICD2

RMICP

10kΩ

49.9kΩ

220µF

10Ω

CM

10µF

RIGHT_OUT

+

STEREO

HEADPHONE

AMPLIFIER

100nF

10µF

GPIO

BEEP

MCKI

DAC_SDATA/GPIO0

ADC_SDATA/GPIO1

BCLK/GPIO2

EXTERNAL

BEEP INPUT

49.9kΩ

SERIAL

DATA

LRCLK/GPIO3

EXTERNAL

MCLK SOURCE

49.9kΩ

ADDR1/CLATCH

ADDR0/CDATA

SDA/COUT

2.2pF

SYSTEM

CONTROLLER

MCKO

PDN

49.9kΩ

SCL/CCLK

MCKO

PDN

Figure 23. System Block Diagram with Differential Inputs

Rev. 0 | Page 20 of 84

ADAU1381

IOVDD

10µF

AVDD1

10µF

AVDD2

47µF

0.1µF

MICBIAS

0.1µF

–

+

8Ω

SPEAKER

OUT

0.1µF

MICBIAS

0.1µF

100pF

SPN

SPP

STEREO SINGLE-ENDED

HEADPHONE OUTPUT

2kΩ

10kΩ

ANALOG

MIC 1

LMIC/LMICN/MICD1

LMICP

10kΩ

LEFT_OUT

220µF

AOUTL

AOUTR

10Ω

10µF

49.9kΩ

10kΩ

ADAU1381

100pF

MICBIAS

0.1µF

10kΩ

2kΩ

10kΩ

220µF

10Ω

ANALOG

MIC 2

RMIC/RMICN/MICD2

RMICP

CM

10µF

49.9kΩ

RIGHT_OUT

+

STEREO

HEADPHONE

AMPLIFIER

100nF

10µF

GPIO

10µF

GPIO

BEEP

MCKI

DAC_SDATA/GPIO0

ADC_SDATA/GPIO1

BCLK/GPIO2

EXTERNAL

BEEP INPUT

49.9kΩ

SERIAL

DATA

LRCLK/GPIO3

EXTERNAL

MCLK SOURCE

49.9kΩ

ADDR1/CLATCH

ADDR0/CDATA

SDA/COUT

2.2pF

SYSTEM

CONTROLLER

MCKO

49.9kΩ

SCL/CCLK

MCKO

PDN

Figure 24. System Block Diagram with Analog Microphone Inputs

Rev. 0| Page 21 of 84

ADAU1381

IOVDD

10µF

AVDD1

10µF

AVDD2

47µF

0.1µF

MICBIAS

0.1µF

–

+

8Ω

SPEAKER

OUT

0.1µF

100pF

SPN

SPP

STEREO SINGLE-ENDED

HEADPHONE OUTPUT

SINGLE-ENDED

STEREO INPUT

10kΩ

10µF

1kΩ

LEFT_OUT

220µF

AOUTL

AOUTR

10Ω

LMIC/LMICN/MICD1

LMICP

49.9kΩ

10µF

10kΩ

ADAU1381

100pF

1kΩ

RMIC/RMICN/MICD2

RMICP

10kΩ

49.9kΩ

10kΩ

220µF

10Ω

10µF

CM

RIGHT_OUT

+

STEREO

HEADPHONE

AMPLIFIER

100nF

10µF

GPIO

10µF

GPIO

BEEP

MCKI

DAC_SDATA/GPIO0

ADC_SDATA/GPIO1

BCLK/GPIO2

EXTERNAL

BEEP INPUT

49.9kΩ

SERIAL

DATA

LRCLK/GPIO3

EXTERNAL

MCLK SOURCE

49.9kΩ

ADDR1/CLATCH

ADDR0/CDATA

SDA/COUT

2.2pF

SYSTEM

CONTROLLER

MCKO

PDN

49.9kΩ

SCL/CCLK

MCKO

PDN

Figure 25. System Block Diagram with Single-Ended Stereo Line Inputs

Rev. 0 | Page 22 of 84

ADAU1381

IOVDD

10µF

AVDD1

10µF

AVDD2

47µF

0.1µF

MICBIAS

0.1µF

–

+

8Ω

SPEAKER

OUT

0.1µF

100pF

SPN

SPP

STEREO SINGLE-ENDED

HEADPHONE OUTPUT

10kΩ

LEFT_OUT

220µF

AOUTL

AOUTR

STEREO DIGITAL

10Ω

LMIC/LMICN/MICD1

LMICP

MIC INPUT

10µF

10kΩ

ADAU1381

100pF

RMIC/RMICN/MICD2

RMICP

10kΩ

R52

10kΩ

220µF

10Ω

10µF

CM

RIGHT_OUT

+

STEREO

HEADPHONE

AMPLIFIER

100nF

10µF

GPIO

10µF

GPIO

BEEP

MCKI

DAC_SDATA/GPIO0

ADC_SDATA/GPIO1

BCLK/GPIO2

EXTERNAL

BEEP INPUT

49.9kΩ

SERIAL

DATA

LRCLK/GPIO3

EXTERNAL

MCLK SOURCE

49.9kΩ

ADDR1/CLATCH

ADDR0/CDATA

SDA/COUT

2.2pF

SYSTEM

CONTROLLER

MCKO

49.9kΩ

SCL/CCLK

MCKO

PDN

Figure 26. System Block Diagram with Stereo Digital Microphone Inputs

Rev. 0| Page 23 of 84

ADAU1381

THEORY OF OPERATION

The ADAU1381 is a low power audio codec with an integrated,

fixed-function audio processing sound engine. It is an all-in-one

package that offers high quality audio, low power, small size, and

many advanced features. The stereo ADC and stereo DAC each

have a dynamic range (DNR) performance of at least 96.5 dB and

a total harmonic distortion plus noise (THD + N) performance

of at least −90 dB. The serial data port is compatible with I²S, left-

justified, right-justified, and TDM modes for interfacing to digital

audio data. The operating voltage range is 1.8 V to 3.65 V, with

an on-board regulator generating the internal digital supply voltage.

The playback path allows input signals and DAC outputs to be

mixed into speaker and/or line outputs. The speaker driver is

capable of driving 400 mW into an 8 ꢀ load.

The fixed-function sound engine contains a digital audio

processing flow optimized for digital still camera stereo audio

processing. However, the flexibility offered by the built-in

sound engine allows this codec to be used for a wide variety of

low power applications. Signal processing blocks included in the

sound engine include the following:

•

Wind noise detection and autofiltering

Dual-band compression with programmable crossover,

compression curves, and timing

Programmable multiband equalizer

Configurable notch filter

Enhanced stereo capture algorithm

Automatic level control

Digital volume control

The record path includes very flexible input configurations that

can accept differential or single-ended analog microphone inputs

as well as two stereo digital microphone inputs. There is also a

beep input pin (BEEP) dedicated to analog beep signals that are

common in digital still camera applications. A microphone bias

pin that can power electrets-type microphones is also available.

Each input signal has its own programmable gain amplifier (PGA)

for input volume adjustment. An automatic level control (ALC)

is built into the sound engine to maintain a constant input re-

cording volume.

•

Multiplexers for signal routing

The ADAU1381 can generate its internal clocks from a wide

range of input clocks by using the on-board fractional PLL.

The PLL accepts inputs from 11 MHz to 20 MHz.

The ADCs and DACs are high quality, 24-bit Σ-Δ converters

that operate at selectable 64× or 128× oversampling rates. The

base sampling rate of the converters is set by the input clock rate

and can be further scaled with the converter control register

settings. The converters can operate at sampling frequencies

from 8 kHz to 96 kHz. The ADCs and DACs also include very

fine-step digital volume controls.

The ADAU1381 is provided in a small, 32-lead, 5 mm × 5 mm

lead frame chip scale package (LFCSP) with an exposed bottom

pad, or a 30-ball (6 × 5 bump), 3.4 mm × 2.64 mm wafer level

chip scale package (WLCSP).

Rev. 0 | Page 24 of 84

ADAU1381

STARTUP, INITIALIZATION, AND POWER

POWER-UP SEQUENCE

This section details the procedure for setting up the ADAU1381

properly. Figure 27 provides an overview of how to initialize the IC.

If AVDD1 and AVDD2 are from the same supply, they can

power up simultaneously. If AVDD1 and AVDD2 are from

separate supplies, then AVDD1 should be powered up first.

IOVDD should be applied simultaneously with AVDD1, if

possible.

START

YES

NO

ARE AVDD1 AND AVDD2

SUPPLIED SEPARATELY?

CAN AVDD1 AND AVDD2

BE SIMULTANEOUSLY

SUPPLIED?

The ADAU1381 uses a power-on reset (POR) circuit to reset the

registers upon power-up. The POR monitors the DVDDOUT

pin and generates a reset signal whenever power is applied to

the chip. During the reset, the ADAU1381 is set to the default

values documented in the register map (see the Control Register

Map section).

NO

YES

SUPPLY POWER

TO AVDD1

SUPPLY POWER TO AVDD1/AVDD2

PINS SIMULTANEOUSLY

SUPPLY POWER

TO AVDD2

The POR is also used to prevent clicks and pops on the speaker

driver output. The power-up sequencing and timing involved is

described in Figure 28 in this section, and in Figure 36

and Figure 37 of the Speaker Output section.

SUPPLY POWER TO IOVDD

WAIT 14ms FOR POWER-ON RESET

AND INITIALIZATION ROM BOOT

CONFIGURE CLOCK GENERATION

REGISTER 16384 (0x4000)

A self-boot ROM initializes the memories after the POR has

completed. When the self-boot sequence is complete, the control

registers are accessible via the I²C/SPI control port and should

then be configured as required for the application. Typically,

with a 10 μF capacitor on AVDD1, the power supply ramp-up,

POR, and self-boot combined take approximately 14 ms.

AND REGISTER 16386 (0x4002)

WAIT FOR PLL LOCK

(2.4ms TO 3.5ms)

ENABLE DIGITAL POWER TO

FUNCTIONAL SUBSYSTEMS

REGISTER 16512 (0x4080)

AND REGISTER 16513 (0x4081)

SET UP SOUND ENGINE REGISTERS

FOR CUSTOMIZED SIGNAL PATH

(INCLUDING VOLUME, SAMPLE RATES,

FILTER COEFFICIENTS)

INITIALIZATION

COMPLETE

Figure 27. Initialization Sequence

MAIN SUPPLY ENABLED

MAIN SUPPLY DISABLED

AVDD1

AVDD2

1.5V

DVDDOUT

1.35V

0.95V

POR

ACTIVE

POWER-UP

(INTERNAL

SIGNAL)

POR ACTIVATES

POR COMPLETE/SELF-BOOT INITIATES

SELF-BOOT COMPLETE/MEMORY

IS ACCESSIBLE

IOVDD

14ms

INTERNAL MCLK

(NOT TO SCALE)

INPUT/OUTPUT

PINS

HIGH-Z

ACTIVE

HIGH-Z

Figure 28. Power-Up and Power-Down Sequence Timing Diagram

Rev. 0| Page 25 of 84

ADAU1381

CLOCK GENERATION AND MANAGEMENT

ENABLING DIGITAL POWER TO FUNCTIONAL

SUBSYSTEMS

The ADAU1381 uses a flexible clocking scheme that enables the

use of many different input clock rates. The PLL can be bypassed

or used, resulting in two different approaches to clock manage-

ment. For more information about clocking schemes, PLL

configuration, and sampling rates, see the Clocking and

Sampling Rates section.

To power subsystems in the device, they must be enabled using

Register 16512 (0x4080), Digital Power-Down 0, and Register

16513 (0x4081), Digital Power-Down 1. The exact settings depend

on the application. However, to proceed with the initialization

sequence and access the RAMs and registers of the ADAU1381,

Register 16512 (0x4080), Digital Power-Down 0, Bit 6, memory

controller, and Bit 0, sound engine, must be enabled.

Case 1: PLL Is Bypassed

If the PLL is bypassed, the core clock is derived directly from

the master clock (MCLK) input. The rate of this clock must be

set properly in Register 16384 (0x4000), clock control, Bits[2:1],

input master clock frequency. When the PLL is bypassed,

supported external clock rates are 256 × f_S, 512 × f_S, 768 × f_S,

and 1024 × f_S, where f_Sis the base sampling rate. The core clock

of the chip is off until Register 16384 (0x4000), clock control,

Bit 0, core clock enable, is set to 1.

SETTING UP THE SOUND ENGINE

After the PLL has locked, the ADAU1381 is in an operational

state, and the control port can be used to configure the sound

engine. For more information, see the Sound Engine section.

POWER REDUCTION MODES

Sections of the ADAU1381 chip can be turned on and off as

needed to reduce power consumption. These include the ADCs,

the DACs, and the PLL.

Case 2: PLL Is Used

The core clock to the entire chip is off during the PLL lock

acquisition period. The user can poll the lock bit to determine

when the PLL has locked. After lock is acquired, the ADAU1381

can be started by setting Register 16384 (0x4000), clock control,

Bit 0, core clock enable, to 1.This bit enables the core clock to all

the internal functional blocks of the ADAU1381.

In addition, some functions can be set in the registers to operate

in power saving, normal, or enhanced performance operation.

See the respective portions of the General-Purpose Input/Outputs

section for more information.

Each digital filter of the ADCs and DACs can be set to a 64× or

128× (default) oversampling ratio. Setting the oversampling ratio

to 64× lowers power consumption with a minimal impact on

performance. See the Typical Performance Characteristics section

and the Typical Power Management Measurements section for

specifications and graphs of the filters.

PLL Lock Acquisition

During the lock acquisition period, only Register 16384 (0x4000),

clock control, and Register 16386 (0x4002), PLL control, are

accessible through the control port. Reading from or writing to

any other address is prohibited until Register 16384 (0x4000),

clock control, Bit 0, core clock enable, and Register 16386 (0x4002),

PLL control, Bit 1, PLL lock, are set to 1.

Detailed information regarding individual power reduction control

registers can be found in the Control Register Map section of this

document.

Register 16386 (0x4002), PLL control, is a 48-bit register for which

all bits must be written with a single continuous write to the

control port.

PDN

Power-Down Pin (

)

The power-down pin provides a simple hardware-based method

for initiating low power mode without requiring access via the

PDN

The PLL lock time is dependent on the MCLK rate. Typical lock

times are provided in Table 11.

control port. When the

pin is raised to the same potential as

AVDD1, the internal digital regulator is disabled and the device

ceases to function, with power consumption dropping to a very

low level. The common-mode voltage sinks, and all internal

Table 11. PLL Lock Time

PLL Mode

Fractional

Integer

Fractional

MCLK Frequency

Lock Time (Typical)

3.0 ms

2.96 ms

2.4 ms

2.98 ms

PDN

memories and registers lose their contents. When the

pin is

12 MHz

12.288 MHz

13 MHz

lowered back to ground, the device reinitializes in its default state,

as described in the Power-Up Sequence section.

14.4 MHz

POWER-DOWN SEQUENCE

19.2 MHz

When powering down the device, the IOVDD, AVDD1, and

AVDD2 supplies should be disabled at the same time, if possible,

but only after the analog and speaker outputs have been muted. If

the supplies cannot be disabled simultaneously, the preferred

sequence is IOVDD first, AVDD2 second, and AVDD1 last.

19.68 MHz

19.8 MHz

Rev. 0 | Page 26 of 84

ADAU1381

CLOCKING AND SAMPLING RATES

SOUND ENGINE

FRAME RATE

f_S/

SOUND

ENGINE

0.5, 1, 1.5, 2, 3, 4, 6

PLL CONTROL

CLOCK CONTROL

CONVERTER

SAMPLING RATE

ADCs

DACs

f/X

f × (R + N/M)

INTEGER, NUMERATOR,

DENOMINATOR

INPUT MASTER

CORE

CLOCK

CLOCK FREQUENCY

MCKI

INPUT DIVIDE

1, 2, 3, 4

f_S/

256 × f_S, 512 × f_S,

768 × f_S, 1024 × f_S

0.5, 1, 1.5, 2, 3, 4, 6

SERIAL PORT

SAMPLING RATE

AUTOMATICALLY SET TO 1024 × f_S

WHEN PLL CLOCK SOURCE SELECTED

SERIAL DATA

INPUT/OUTPUT

PORTS

f_S/

0.5, 1, 1.5, 2, 3, 4, 6

Figure 29. Clock Routing Diagram

For example, if the input to Bit 3 = 49.152 MHz (from PLL),

then Bits[2:1] = 1024 × f_S; therefore,

CORE CLOCK

The core clock divider generates a core clock either from the

PLL or directly from MCLK and can be set in Register 16384

(0x4000), clock control.

f_S= 49.152 MHz/1024 = 48 kHz

Table 13. Clock Control Register (Register 16384, 0x4000)

The core clock is always in 256 × f_Smode. Direct MCLK fre-

quencies must correspond to a value listed in Table 12, where f_S

is the base sampling frequency. PLL outputs are always in 1024

× f_Smode, and the clock control register automatically sets the

core clock divider to f/4 when using the PLL.

Bits

Bit Name

Settings

3

Clock source select

0: direct from MCKI pin (default)

1: PLL clock

[2:1]

0

Input master clock 00: 256 × f_S(default)

frequency

01: 512 × f_S

10: 768 × f_S

11: 1024 × f_S

Table 12. Core Clock Frequency Dividers

Core clock enable

0: core clock disabled (default)

1: core clock enabled

Input Clock Rate

256 × f_S

Core Clock Divider

Core Clock

f/1

f/2

f/3

f/4

256 × f_S

512 × f_S

SAMPLING RATES

768 × f_S

1024 × f_S

The ADCs, DACs, and serial port share a common sampling

rate that is set in Register 16407 (0x4017), Converter Control 0.

Bits[2:0], converter sampling rate, set the sampling rate as a ratio of

the base sampling frequency. The sound engine sampling rate is

set in Register 16619 (0x40EB), sound engine frame rate, Bits[3:0],

sound engine frame rate, and the serial port sampling rate is set

in Register 16632 (0x40F8), serial port sampling rate, Bits[2:0],

serial port control sampling rate.

Clocks for the converters, the serial ports, and the sound engine are

derived from the core clock. The core clock can be derived directly

from MCLK, or it can be generated by the PLL. Register 16384

(0x4000), clock control, Bit 3, clock source select, determines

the clock source.

Bits[2:1], input master clock frequency, should be set according

to the expected input clock rate selected by Bit 3, clock source

select. The clock source select value also determines the core

clock rate and the base sampling frequency, f_S.

It is strongly recommended that the sampling rates for the

converters, serial ports, and sound engine be set to the same

value, unless appropriate compensation filtering is done within

the sound engine.

Rev. 0| Page 27 of 84

ADAU1381

Table 14 and Table 15 list the sampling rate divisions for

common base sampling rates.

Fractional Mode

Fractional mode is used when the MCLK is a fractional

(R + (N/M)) multiple of the PLL output.

Table 14. Base Sampling Rate Divisions for f_S= 48 kHz

For example, if MCLK = 12 MHz and f_S= 48 kHz, then

PLL Required Output = 1024 × 48 kHz = 49.152 MHz

R + (N/M) = 49.152 MHz/12 MHz = 4 + (12/125)

Base Sampling

Frequency

Sampling Rate Scaling Sampling Rate

f_S= 48 kHz

f_S/1

48 kHz

8 kHz

f_S/6

f_S/4

f_S/3

f_S/2

f_S/1.5

f_S/0.5

12 kHz

16 kHz

24 kHz

32 kHz

96 kHz

Common fractional PLL parameter settings for 44.1 kHz and

48 kHz sampling rates can be found in Table 16 and Table 17.

Table 16. Fractional PLL Parameter Settings for f_S= 44.1 kHz¹

MCLK

Input

(MHz)

Input

Divider Integer Denominator

(X)

Numerator

(N)

(R)

(M)

Table 15. Base Sampling Rate Divisions for f_S= 44.1 kHz

12

1

3

625

477

3849

34

Base Sampling

Frequency

13

1

3

8125

125

Sampling Rate Scaling Sampling Rate

14.4

19.2

19.68

19.8

2

6

f_S= 44.1 kHz

f_S/1

f_S/6

f_S/4

f_S/3

f_S/2

f_S/1.5

f_S/0.5

44.1 kHz

7.35 kHz

11.025 kHz

14.7 kHz

22.05 kHz

29.4 kHz

88.2 kHz

2

4

125

88

2

4

1025

1375

604

772

2

4

¹Desired core clock = 11.2896 MHz, PLL output = 45.1584 MHz.

Table 17. Fractional PLL Parameter Settings for f_S= 48 kHz¹

MCLK

Input

(MHz)

Input

PLL

Divider Integer Denominator

(X)

Numerator

(N)

(R)

(M)

125

1625

75

The PLL uses the MCLK as a reference to generate the core

clock. PLL settings are set in Register 16386 (0x4002), PLL

control. Depending on the MCLK frequency, the PLL must be

set for either integer or fractional mode. The PLL can accept

input frequencies in the range of 11 MHz to 20 MHz.

12

1

4

12

13

1

3

1269

62

14.4

19.2

19.68

19.8

2

6

2

5

25

3

2

4

205

825

204

796

All six bytes in the PLL control register must be written with a

single continuous write to the control port.

2

4

¹Desired core clock = 12.288 MHz, PLL output = 49.152 MHz.

TO PLL

CLOCK DIVIDER

÷ X

MCKI

× (R + N/M)

The PLL outputs a clock in the range of 41 MHz to 54 MHz,

which should be taken into account when calculating PLL

values and MCLK frequencies.

Figure 30. PLL Block Diagram

Integer Mode

Integer mode is used when the MCLK is an integer (R) multiple

of the PLL output (1024 × f_S).

For example, if MCLK = 12.288 MHz and f_S= 48 kHz, then

PLL Required Output = 1024 × 48 kHz = 49.152 MHz

R = 49.152 MHz/12.288 MHz = 4

In integer mode, the values set for N and M are ignored.

Rev. 0 | Page 28 of 84

ADAU1381

The ADC and DAC sampling rate can be set in Register 16407

(0x4017), Converter Control 0, Bits[2:0], converter sampling

rate. The sound engine sampling rate and serial port sampling

rate are similarly set in Register 16619 (0x40EB), sound engine

frame rate, Bits[3:0], sound engine frame rate, and Register

16632 (0x40F8), serial port sampling rate, Bits[2:0], serial port

control sampling rate, respectively.

Table 18. Sampling Rates for 256 × 48 kHz Core Clock

Core Clock

Sampling Rate Divider

Sampling Rate

12.288 MHz

(1 × 256)

48 kHz

(6 × 256)

8 kHz

(4 × 256)

12 kHz

(3 × 256)

16 kHz

(2 × 256)

24 kHz

(1.5 × 256)

(0.5 × 256)

32 kHz

96 kHz

Table 18 and Table 19 depict example sampling rate settings.

The (1 × 256) case is the base sampling rate.

Table 19. Sampling Rates for 256 × 44.1 kHz Core Clock

Core Clock

Sampling Rate Divider

Sampling Rate

11.2896 MHz

(1 × 256)

44.1 kHz

(6 × 256)

7.35 kHz

(4 × 256)

(3 × 256)

11.025 kHz

14.7 kHz

(2 × 256)

(1.5 × 256)

(0.5 × 256)

22.05 kHz

29.4 kHz

88.2 kHz

Rev. 0| Page 29 of 84

ADAU1381

RECORD SIGNAL PATH

BEEP

Analog Beep Input

PGA

The BEEP pin is used for mono single-ended signals, such as a

beep warning. This signal bypasses the ADCs and the sound

engine and is mixed directly into any of the analog outputs.

LMIC/LMICN/

MICD1

A BEEP pin input can also be amplified or muted by a PGA, up

to 32 dB in Register 16392 (0x4008), digital microphone and analog

beep control. The beep input must be enabled in Register 16400

(0x4010), microphone bias control and beep enable.

LEFT

ADC

PGA

LMICP

DECIMATORS

CM

RMIC/RMICN/

MICD2

Microphone Bias

The MICBIAS pin provides a voltage reference for electret

microphones. Register 16400 (0x4010), microphone bias

control and beep enable, sets the operation mode of this pin.

RIGHT

ADC

PGA

RMICP

CM

Example Configurations

Figure 31. Record Signal Path Diagram

TO DECIMATORS

LMIC/LMICN/

MICD1

INPUT SIGNAL PATH

The ADAU1381 can be configured for three types of microphone

inputs: single-ended, differential, or digital. The LMIC/LMICN/

MICD1 and RMIC/RMICN/MICD2 pins encompass all of these

configurations. LMICP and RMICP are used only during

differential configurations (see Figure 31, the record signal path

diagram).

PGA

LMICP

CM

TO DECIMATORS

RMIC/RMICN/

MICD2

Each analog input has individual gain controls (boost or cut). These

signals are routed to their respective right or left channel ADC.

PGA

RMICP

CM

Analog Microphone Inputs

Figure 32. Stereo Digital Microphone Input Configuration

For differential inputs, RMICN and RMICP denote the negative

and positive input for the right channel, respectively. LMICN

and LMICP denote the negative and positive input for the left

channel, respectively.

LMIC/LMICN/

MICD1

TO LEFT

ADC

PGA

LMICP

LMIC and RMIC inputs are single-ended line inputs. Together,

they can be used as a stereo single-ended input.

CM

RMIC/RMICN/

MICD2

Digital Microphone Inputs

When a digital PDM microphone connected to the MICD1 or

MICD2 pin is used, Register 16392 (0x4008), digital microphone

and analog beep control, must be set appropriately to enable the

microphone input of choice. The MCKO output clock provides

the clock for the microphone and must be set accordingly in

Register 16384 (0x4000), clock control, depending on the

streaming PDM rate of the microphone.

TO RIGHT

ADC

PGA

RMICP

CM

Figure 33. Single-Ended Input Configuration

The digital microphone signal bypasses the ADCs and is routed

directly into the decimation filters. The digital microphone and

ADCs share these decimation filters; therefore, both cannot be

used simultaneously.

Rev. 0 | Page 30 of 84

ADAU1381

LMIC/LMICN/

MICD1

Digital ADC Volume Control

The ADC output (digital input) volume can be adjusted in

Register 16410 (0x401A), left ADC attenuator, Bits[7:0], left ADC

digital attenuator, for the left channel digital volume control and

in Register 16411 (0x401B), right ADC attenuator, Bits[7:0], right

ADC digital attenuator, for right channel digital volume control.

TO LEFT

ADC

PGA

LMICP

CM

RMIC/RMICN/

MICD2

High-Pass Filter

TO RIGHT

ADC

A high-pass filter is used in the ADC path to remove dc offsets

and can be selected in Register 16409 (0x4019), ADC control,

Bit 5, high-pass filter select, where it can be enabled or disabled.

PGA

RMICP

CM

Figure 34. Differential Input Configuration

DIGITAL DUAL-BAND AUTOMATIC LEVEL

CONTROL (ALC)

ANALOG-TO-DIGITAL CONVERTERS

The ADAU1381 includes an automatic level control (ALC). The

ALC adjusts the input gain continuously for a varying input signal

as dictated by the user-defined ALC settings. This allows the input

recording level to remain constant. Although this functionality

relates mainly to the record signal path, it is implemented digitally

in the sound engine.

The ADAU1381 uses two 24-bit Σ-Δ analog-to-digital converters

(ADCs) with selectable oversampling rates of either 64× or 128×.

The full-scale input to the ADCs depends on AVDD1. At 3.3 V,

the full-scale input level is 1.0 V rms. Inputs greater than the

full-scale value result in clipping and distortion.

Rev. 0| Page 31 of 84

ADAU1381

PLAYBACK SIGNAL PATH

LEFT PLAYBACK

LINE OUT

AMPLIFIER

beep signal. The mixer can be controlled in Register 16415

(0x401F), playback mono mixer control.

MIXER

LEFT

DAC

AOUTL

LEFT

The drivers are low noise, Class AB mono amplifiers designed to

drive 8 Ω, 400 mW speakers. The output is differential and does

not require external capacitors. The gain settings for the speaker

drivers can be set in Register 16423 (0x4027), playback speaker

output control. In this register, the drivers can be set for any of

the four gain settings: 0 dB, 2 dB, 4 dB, or 6 dB. Additionally,

the speaker driver can be muted or powered down completely.

PLAYBACK

BEEP GAIN

MONO

PLAYBACK

BEEP GAIN

MONO

OUTPUT

MONO

PLAYBACK

MIXER

GAIN

BEEP FROM

RECORD PGA

SPP

SPN

RIGHT

PLAYBACK

BEEP GAIN

–1

MONO OUTPUT

INVERTER

For pop and click suppression, an internal precharge sequence with

output gating/enabling occurs after the mono driver is enabled.

The sequence lasts for 8 ms, and then the internal mute signal

rising edge occurs (see Figure 36 for the power-up sequence

timing diagram).

RIGHT

DAC

AOUTR

RIGHT PLAYBACK

MIXER

LINE OUT

AMPLIFIER

Figure 35. Playback Signal Path Diagram

OUTPUT SIGNAL PATHS

The power-down sequence is essentially the reverse of the start-

up sequence, as depicted in Figure 37.

The outputs of the ADAU1381 include a left and right line output

and speaker driver. The beep input signal can be mixed into any

of these outputs, with separate gain control for each path.

SPEAKER

OUTPUT

ENABLE

DIGITAL-TO-ANALOG CONVERTERS

4ms

MONO

OUTPUT

MUTE

The ADAU1381 uses two 24-bit Σ-Δ digital-to-analog converters

(DACs) with selectable oversampling rates of 64× or 128×. The

full-scale output of the DACs depends on AVDD1. At 3.3 V, the

full-scale output level is 1.0 V rms.

V

CM

SPP

SPN

HIGH-Z

<1µA

Digital DAC Volume Control

2.3mA + SIGNAL

CURRENT

The DAC output (digital output) volume can be adjusted in

Register 16427 (0x402B), left DAC attenuator, for the left channel

digital volume control and in Register 16428 (0x402C), right

DAC attenuator, for the right channel digital volume control.

I

1.1mA

2.3mA

AVDD2

DAC

DAC VOLUME

INCREASES

DAC VOLUME MUTED

BEEP VOLUME

INCREASES

BEEP

BEEP VOLUME MUTED

De-Emphasis Filter

Figure 36. Speaker Driver Power-Up Sequence

A de-emphasis filter is used in the DAC path to remove high

frequency noise in an FM system. This filter can be enabled or

disabled in Register 16426 (0x402A), DAC control.

SPEAKER

OUTPUT

ENABLE

4ms

MONO

OUTPUT

MUTE

LINE OUTPUTS

The AOUTL and AOUTR pins are the left and right line outputs,

respectively. Both outputs have a line output amplifier that can

be set in the control registers.

V

CM

SPP

SPN

HIGH-Z

CM

HIGH-Z

<1µA

The left playback mixer is dedicated to the AOUTL output. This

mixer mixes the left DAC and the beep signal.

2.3mA + SIGNAL

CURRENT

I

2.3mA

1.1mA

AVDD2

DAC

Similarly, the right playback mixer mixes the right DAC and the

beep input and is dedicated to the AOUTR output.

DAC VOLUME

DECREASES

DAC VOLUME MUTED

SPEAKER OUTPUT

BEEP VOLUME

DECREASES

BEEP

BEEP VOLUME MUTED

The SPP and SPN pins are the positive and negative speaker

outputs, respectively. Each output has a speaker driver.

Figure 37. Speaker Driver Power-Down Sequence

The speaker outputs are derived from the mono playback mixer,

which sums the right and left DAC outputs and mixes with the

Rev. 0 | Page 32 of 84

ADAU1381

CONTROL PORTS

The ADAU1381 can operate in one of two control modes: I²C

control or SPI control.

Burst mode addressing, where the subaddresses are automati-

cally incremented at word boundaries, can be used for writing

large amounts of data to contiguous memory locations. This

increment happens automatically after a single-word write unless a

stop condition is encountered. The registers in the ADAU1381

range in width from one to six bytes; therefore, the auto-increment

feature knows the mapping between subaddresses and the word

length of the destination register. A data transfer is always

terminated by a stop condition.

The ADAU1381 has both a 4-wire SPI control port and a 2-wire

I²C bus control port. Each can be used to set the registers. The

part defaults to I²C mode but can be put into SPI control mode

CLATCH

by pulling the

pin low three times.

The control port is capable of full read/write operation for all

addressable registers. Most sound engine processing parameters

are controlled by writing new values to the sound engine parameter

register using the control port. Other functions, such as mute,

input/output mode control, and analog signal paths, can be

programmed by writing to the appropriate registers.

Both SDA and SCL should have 2.0 kꢀ pull-up resistors on the

lines connected to them. The voltage on these signal lines should

not be more than AVDD1.

Table 21. I²C Address Byte Format

Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5

All addresses can be accessed in either a single-address mode or

a burst mode. The first byte (Byte 0) of a control port write contains

Bit 6

Bit 7

0

1

0

ADDR1 ADDR0 R/W

W

the 7-bit chip address plus the R/ bit. The next two bytes (Byte 1

and Byte 2) together form the subaddress of the register location

within the ADAU1381. All subsequent bytes (starting with Byte 3)

contain the data, such as control port data, register data, or sound

engine parameter data. The number of bytes per word depends

on the type of data that is being written. The exact formats for

specific types of writes and reads are shown in Figure 40

to Figure 43.

Table 22. I²C Addresses

R/W

ADDR1

ADDR0

Slave Address

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0x70

0x71

0x72

0x73

0x74

0x75

0x76

0x77

The ADAU1381 has several mechanisms for updating sound

engine parameters in real time without causing pops or clicks.

The control port pins are multifunctional, depending on the

mode in which the part is operating. Table 20 details these

multiple functions.

Addressing

Table 20. Control Port Pin Functions

Initially, each device on the I²C bus is in an idle state and

monitoring the SDA and SCL lines for a start condition and

the proper address. The I²C master initiates a data transfer by

establishing a start condition, defined by a high-to-low transition

on SDA while SCL remains high. This indicates that an address or

an address and data stream follow. All devices on the bus respond

to the start condition and shift the next eight bits (the 7-bit

I²C Mode

SPI Mode

SCL/CCLK

SDA/COUT

SCL—input

SDA—open-collector output

ADDR1/CLATCH I²C Address Bit 1—input

CCLK—input

COUT—output

CLATCH—input

CDATA—input

ADDR0/CDATA

I²C Address Bit 0—input

I²C PORT

W

address plus the R/ bit), MSB first. The device that recognizes

The ADAU1381 supports a 2-wire serial (I²C-compatible)

microprocessor bus driving multiple peripherals. Two pins,

serial data (SDA) and serial clock (SCL), carry information

between the ADAU1381 and the system I²C master controller.

In I²C mode, the ADAU1381 is always a slave on the bus, meaning

it cannot initiate a data transfer. Each slave device is recognized by

a unique address. The address byte format is shown in Table 21.

The address resides in the first seven bits of the I²C write. The

LSB of this byte sets either a read or write operation. Logic 1

corresponds to a read operation, and Logic 0 corresponds to a

write operation. The full byte addresses, including the pin settings

the transmitted address responds by pulling the data line low

during the ninth clock pulse. This ninth bit is known as an

acknowledge bit. All other devices withdraw from the bus at

this point and return to the idle condition.

W

The R/ bit determines the direction of the data. A Logic 0 on the

LSB of the first byte means the master writes information to the

peripheral, whereas a Logic 1 means the master reads information

from the peripheral after writing the subaddress and repeating

the start address. A data transfer takes place until a stop condition

is encountered. A stop condition occurs when SDA transitions

from low to high while SCL is held high. Figure 38 shows the

timing of an I²C write, and Figure 39 shows an I²C read.

W

and R/ bit, are shown in Table 22.

Rev. 0| Page 33 of 84

ADAU1381

Stop and start conditions can be detected at any stage during

the data transfer. If these conditions are asserted out of sequence

with normal read and write operations, the ADAU1381

immediately jumps to the idle condition. During a given SCL

high period, the user should issue only one start condition, one

stop condition, or a single stop condition followed by a single

start condition. If an invalid subaddress is issued by the user,

the ADAU1381 does not issue an acknowledge and returns to

the idle condition. If the user exceeds the highest subaddress while

in auto-increment mode, one of two actions is taken. In read mode,

the ADAU1381 outputs the highest subaddress register contents

until the master device issues a no acknowledge, indicating the

end of a read. A no-acknowledge condition is where the SDA

line is not pulled low on the ninth clock pulse on SCL. If the

highest subaddress location is reached while in write mode, the

data for the invalid byte is not loaded into any subaddress register,

a no acknowledge is issued by the ADAU1381, and the part returns

to the idle condition.

SCL

0

1

SDA

R/W

0

ADDR1 ADDR0

START BY

MASTER

ACKNOWLEDGE

BY ADAU1381

ACKNOWLEDGE

BY ADAU1381

FRAME 1

CHIP ADDRESS BYTE

FRAME 2

SUBADDRESS BYTE 1

SCL

(CONTINUED)

SDA

(CONTINUED)

ACKNOWLEDGE

BY ADAU1381

ACKNOWLEDGE STOP BY

BY ADAU1381 MASTER

FRAME 3

SUBADDRESS BYTE 2

FRAME 4

DATA BYTE 1

Figure 38. I²C Write to ADAU1381 Clocking

SCL

0

1

0

R/W

SDA

START BY

ADDR1 ADDR0

ACKNOWLEDGE

BY ADAU1381

ACKNOWLEDGE

BY ADAU1381

MASTER

FRAME 1

CHIP ADDRESS BYTE

FRAME 2

SUBADDRESS BYTE 1

SCL

(CONTINUED)

SDA

(CONTINUED)

0

1

R/W

0

ADDR1 ADDR0

ACKNOWLEDGE

BY ADAU1381

REPEATED

START BY MASTER

ACKNOWLEDGE

BY ADAU1381

FRAME 3

SUBADDRESS BYTE 2

FRAME 4

CHIP ADDRESS BYTE

SCL

(CONTINUED)

SDA

(CONTINUED)

ACKNOWLEDGE

BY ADAU1381

ACKNOWLEDGE STOP BY

BY MASTER MASTER

FRAME 5

READ DATA BYTE 1

FRAME 6

READ DATA BYTE 2

Figure 39. I²C Read from ADAU1381 Clocking

Rev. 0 | Page 34 of 84

ADAU1381

I²C Read and Write Operations

of the subaddress, the master must issue a repeated start command

W

followed by the chip address byte with the R/ bit set to 1 (read).

Figure 40 shows the timing of a single-word write operation.

Every ninth clock pulse, the ADAU1381 issues an acknowledge

by pulling SDA low.

This causes the ADAU1381 SDA to reverse and begin driving

data back to the master. The master then responds every ninth

pulse with an acknowledge pulse to the ADAU1381.

Figure 41 shows the timing of a burst mode write sequence.

This figure shows an example where the target destination

registers are two bytes. The ADAU1381 knows to increment its

subaddress register every two bytes because the requested

subaddress corresponds to a register or memory area with a

2-byte word length.

Figure 43 shows the timing of a burst mode read sequence. This

figure shows an example where the target read registers are two

bytes. The ADAU1381 increments its subaddress every two bytes

because the requested subaddress corresponds to a register or

memory area with word lengths of two bytes. Other address

ranges may have a variety of word lengths ranging from one to

five bytes. The ADAU1381 always decodes the subaddress and

sets the auto-increment circuit so that the address increments

after the appropriate number of bytes.

The timing of a single-word read operation is shown in Figure 42.

W

Note that the first R/ bit is 0, indicating a write operation. This is

because the subaddress still needs to be written to set up the

internal address. After the ADAU1381 acknowledges the receipt

CHIP ADDRESS,

SUBADDRESS,

HIGH BYTE

SUBADDRESS,

LOW BYTE

DATA

BYTE 1

DATA

BYTE 2

DATA

BYTE N

AS

...

AS

P

S

R/W = 0

S = START BIT, P = STOP BIT, AS = ACKNOWLEDGE BY SLAVE.

SHOWS A ONE-WORD WRITE, WHERE EACH WORD HAS N BYTES.

Figure 40. Single-Word I²C Write Sequence

CHIP

ADDRESS,

R/W = 0

SUBADDRESS,

HIGH BYTE

SUBADDRESS,

LOW BYTE

...

P

S

AS

DATA-WORD 1, DATA-WORD 1, DATA-WORD 2, DATA-WORD 2,

BYTE 1 BYTE 2 BYTE 1 BYTE 2

DATA-WORD N, DATA-WORD N,

BYTE 1 BYTE 2

S = START BIT, P = STOP BIT, AS = ACKNOWLEDGE BY SLAVE.

SHOWS AN N-WORD WRITE, WHERE EACH WORD HAS TWO BYTES. (OTHER WORD LENGTHS ARE POSSIBLE, RANGING FROM ONE TO FIVE BYTES.)

Figure 41. Burst Mode I²C Write Sequence

CHIP ADDRESS,

R/W = 0

SUBADDRESS,

HIGH BYTE

SUBADDRESS,

LOW BYTE

CHIP ADDRESS,

R/W = 1

DATA

BYTE 1

DATA

BYTE 2

DATA

BYTE N

...

AS

S

AS

AM

P

S

S = START BIT, P = STOP BIT, AM = ACKNOWLEDGE BY MASTER, AS = ACKNOWLEDGE BY SLAVE.

SHOWS A ONE-WORD READ, WHERE EACH WORD HAS N BYTES.

Figure 42. Single-Word I²C Read Sequence

CHIP

ADDRESS,

R/W = 0

CHIP

ADDRESS,

R/W = 1

SUBADDRESS,

HIGH BYTE

SUBADDRESS,

LOW BYTE

...

P

S

AS

AM

DATA-WORD 1,

BYTE 1

DATA-WORD 1,

BYTE 2

DATA-WORD N, DATA-WORD N,

BYTE 1 BYTE 2

S = START BIT, P = STOP BIT, AM = ACKNOWLEDGE BY MASTER, AS = ACKNOWLEDGE BY SLAVE.

SHOWS AN N-WORD READ, WHERE EACH WORD HAS TWO BYTES. (OTHER WORD LENGTHS ARE POSSIBLE, RANGING FROM ONE TO FIVE BYTES.)

Figure 43. Burst Mode I²C Read Sequence

Rev. 0| Page 35 of 84

ADAU1381

Data Bytes

SPI PORT

The number of data bytes varies according to the register being

accessed. During a burst mode write, an initial subaddress is

written followed by a continuous sequence of data for consecutive

register locations. A sample timing diagram for a single-write

SPI operation to the parameter memory is shown in Figure 44.

A sample timing diagram of a single-read SPI operation is shown

in Figure 45. The COUT pin goes from three-state to being driven

at the beginning of Byte 3. In this example, Byte 0 to Byte 2

By default, the ADAU1381 is in I²C mode, but can be put into SPI

CLATCH

control mode by pulling

uses a 4-wire interface, consisting of

and COUT signals, and is always a slave port. The

low three times. The SPI port

CLATCH

, CCLK, CDATA,

CLATCH

signal

goes low at the beginning of a transaction and high at the end of

a transaction. The CCLK signal latches CDATA on a low-to-high

transition. COUT data is shifted out of the ADAU1381 on the

falling edge of CCLK and should be clocked into a receiving

device, such as a microcontroller, on the CCLK rising edge. The

CDATA signal carries the serial input data, and the COUT signal is

the serial output data. The COUT signal remains three-stated until

a read operation is requested. This allows other SPI-compatible

peripherals to share the same readback line. All SPI transactions

have the same basic format shown in Table 24. A timing diagram

is shown in Figure 4. All data should be written MSB first. The

ADAU1381 can be taken out of SPI mode only by a full reset.

contain the addresses and R/ bit, and subsequent bytes carry

W

the data.

SPI Read/Write Clock Frequency (CCLK)

The SPI port of the ADAU1381 has asymmetrical read and

write clock frequencies. It is possible to write data into the

device at higher data rates than reading data out of the device.

More detailed information is available in the Digital Timing

Specifications section.

W

Chip Address R/

MEMORY AND REGISTER ACCESS

The first byte of an SPI transaction includes the 7-bit chip address

and an R/ bit. The chip address is always 0x38. The LSB of

this first byte determines whether the SPI transaction is a read

(Logic 1) or a write (Logic 0).

Several conditions must be true to have full access to all memory

and registers via the control port:

W

•

The ADAU1381 must have finished its initialization,

including power-on reset, PLL lock, and self-boot.

The core clock must be enabled (Register 16384 (0x4000),

clock control, Bit 0, core clock enable, set to 1).

The memory controller must be powered (Register 16512

(0x4080), Digital Power-Down 0, Bit 6, memory controller, set

to 1).

Table 23. SPI Address Byte Format

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

0

1

0

R/W

Subaddress

•

The sound engine must be powered (Register 16512 (0x4080),

Digital Power-Down 0, Bit 0, sound engine, set to 1).

The 12-bit subaddress word is decoded into a location in one of

the registers. This subaddress is the location of the appropriate

register. The MSBs of the subaddress are zero-padded to bring the

word to a full 2-byte length.

Table 24. Generic Control Word Format

Byte 0

Byte 1

Byte 2

Byte 3

Byte 4¹

CHIP_ADR[6:0], R/W

SUBADR[15:8]

SUBADR[7:0]

Data

¹Continues to end of data.

Rev. 0 | Page 36 of 84

ADAU1381

CLATCH

CCLK

CDATA

BYTE 0

BYTE 1

BYTE 2

BYTE 3

Figure 44. SPI Write to ADAU1381 Clocking (Single-Write Mode)

CLATCH

CCLK

CDATA

COUT

BYTE 1

BYTE 3

BYTE 0

HIGH-Z

DATA

Figure 45. SPI Read from ADAU1381 Clocking (Single-Read Mode)

Rev. 0| Page 37 of 84

ADAU1381

SERIAL DATA INPUT/OUTPUT PORTS

TDM MODES

The flexible serial data input and output ports of the ADAU1381

can be set to accept or transmit data in 2-channel format or in a

4-channel or 8-channel TDM stream to interface to external ADCs

or DACs. Data is processed by default in twos complement, MSB

first format, unless otherwise configured in the control registers.

By default, the left channel data field precedes the right channel

data field in 2-channel streams. In TDM 4 mode, Slot 0 and Slot 1

are in the first half of the audio frame, and Slot 2 and Slot 3 are

in the second half of the audio frame. In TDM 8 mode, Slot 0 to

Slot 3 are in the first half of the audio frame, and Slot 4 to Slot 7

are in the second half of the frame. The serial modes and the

position of the data in the frame are set in Register 16405 (0x4015),

Serial Port Control 0; Register 16406 (0x4016), Serial Port Control 1;

Register 16407 (0x4017), Converter Control 0; and Register 16408

(0x4018), Converter Control 1.

The LRCLK in TDM mode can be input to the ADAU1381

either as a 50% duty cycle clock or as a bit-wide pulse.

When the LRCLK is set as a pulse, a 47 pF capacitor should be

connected between the LRCLK pin and ground, as shown

in Figure 46. This is necessary in both master and slave modes

to properly align the LRCLK signal to the serial data stream.

ADAU1381

LRCLK

47pF

BCLK

Figure 46. TDM Pulse Mode LRCLK Capacitor Alignment

The serial data clocks must be synchronous with the ADAU1381

master clock input. The LRCLK and BCLK pins are used to clock

both the serial input and output ports. The ADAU1381 can be

set as the master or the slave in a system. Because there is only

one set of serial data clocks, the input and output ports must

always be both master or both slave.

The ADAU1381 TDM implementation is a TDM audio stream.

Unlike a true TDM bus, its output does not become high imped-

ance during periods when it is not transmitting data.

In TDM 8 mode, the ADAU1381 can be a master for f_Sup to

48 kHz. Table 25 lists the modes in which the serial output port

can function.

Register 16405 (0x4015), Serial Port Control 0, and Register

16406 (0x4016), Serial Port Control 1, allow control of clock

polarity and data input modes. The valid data formats are I²S,

left-justified, right-justified (24-/20-/18-/16-bit), and TDM. In

all modes except for the right-justified modes, the serial port

inputs an arbitrary number of audio data bits, up to a limit of 24.

Extra bits do not cause an error, but they are truncated internally.

The serial port can operate with an arbitrary number of BCLK

transitions in each LRCLK frame.

Table 25. Serial Output Port Master/Slave Mode Capabilities

2-Channel Modes (I²S, Left-

f_S

Justified, Right-Justified)

8-Channel TDM

Master and slave

Slave

48 kHz

96 kHz

Master and slave

Table 26 describes the proper configurations for standard audio

data formats. Right-justified modes must be configured manually

using Register 16406 (0x4016), Serial Port Control 1, Bits[7:5],

number of bit clock cycles per frame, and Bits[1:0], data delay

from LRCLK edge.

Table 26. Data Format Configurations

BCLK Cycles/

Audio Frame

Data Delay from

LRCLK Edge

Format

LRCLK Polarity

LRCLK Mode

BCLK Polarity

I²S (see Figure 47) Frame begins on falling edge 50% duty cycle Data changes

on falling edge

64

Delayed from LRCLK edge

by 1 BCLK

Aligned with LRCLK edge

Left-Justified

(see Figure 48)

Right-Justified

(see Figure 49)

Frame begins on rising edge

50% duty cycle Data changes

on falling edge

50% duty cycle Data changes

on falling edge

Frame begins on rising edge

Delayed from LRCLK edge

by 8, 12, or 16 BCLKs to

align LSB with right edge

of frame.

TDM with Clock

(see Figure 50)

TDM with Pulse

(see Figure 51)

Frame begins on falling edge 50% duty cycle Data changes

on falling edge

64 to 256

Delayed from start of word

clock by 1 BCLK

Delayed from start of word

clock by 1 BCLK

Frame begins on rising edge

Pulse

Data changes

on falling edge

Rev. 0 | Page 38 of 84

ADAU1381

LEFT CHANNEL

LRCLK

BCLK

RIGHT CHANNEL

MSB

LSB

SDATA

MSB

LSB

1/f_S

Figure 47. I²S Mode—16 Bits to 24 Bits per Channel

RIGHT CHANNEL

LEFT CHANNEL

LRCLK

BCLK

MSB

LSB

MSB

LSB

SDATA

1/f_S

Figure 48. Left-Justified Mode—16 Bits to 24 Bits per Channel

RIGHT CHANNEL

LEFT CHANNEL

LRCLK

BCLK

SDATA

MSB

LSB

1/f_S

MSB

LSB

Figure 49. Right-Justified Mode—16 Bits to 24 Bits per Channel

LRCLK

256 BCLKs

BCLK

DATA

32 BCLKs

SLOT 1

SLOT 2

SLOT 3

SLOT 4

SLOT 5

SLOT 6

SLOT 7

SLOT 8

LRCLK

BCLK

DATA

MSB

MSB – 1

MSB – 2

Figure 50. TDM Mode

LRCLK

BCLK

MSB TDM

CH

0

SDATA

8TH

CH

SLOT 0

SLOT 1

SLOT 2

SLOT 3

SLOT 4

SLOT 5

SLOT 6

SLOT 7

32

BCLKs

Figure 51. TDM Mode with Pulse Word Clock

Rev. 0| Page 39 of 84

ADAU1381

GENERAL-PURPOSE INPUT/OUTPUTS

from a GPIO output with an external transistor or buffer. Because

of issues that may arise from simultaneously driving or sinking a

large current on many pins, care should be taken in the application

design to avoid connecting high efficiency LEDs directly to many

or all of the GPIO pins. If many LEDs are required, use an external

driver. When the GPIO pins are set as open-collector outputs,

they should be pulled up to a maximum voltage of what is set

on IOVDD.

The serial data input/output pins are shared with the general-

purpose input/output function. Each of these four pins can be

set to only one function. The function of these pins is set in

Register 16628 (0x40F4), serial data/GPIO pin configuration.

The GPIO pins can be used as either inputs or outputs. These pins

are readable and can be set either through the control interface

or directly by the sound engine. When set as inputs, these pins

can be used with push-button switches or rotary encoders to

control sound engine program settings. Digital outputs can be

used to drive LEDs or external logic to indicate the status of

internal signals and control other devices. Examples of this use

include indicating signal overload, signal present, and button

press confirmation.

The configuration of the GPIO functions is set up in Register 16582

to Register 16586 (0x40C6 to 0x40CA), GPIO pin control.

GPIOs Set from Control Port

The GPIO pins can also be set to be directly controlled from the

I²C/SPI control port. When the pins are set into this mode, five

memory locations are enabled for the GPIO pin settings

(see Table 68). The physical settings on the GPIO pins mirror

the settings of the LSB of these 4-byte-wide memory locations.

When set as an output, each pin can typically drive 2 mA. This

is enough current to directly drive some high efficiency LEDs.

Standard LEDs require about 20 mA of current and can be driven

Rev. 0 | Page 40 of 84

ADAU1381

SOUND ENGINE

communications interface board (see the AD1940 product page

for ordering information).

SIGNAL PROCESSING

The ADAU1381 is designed to provide a fixed-function signal

processing flow specifically catered to digital still cameras and other

low power applications.

SigmaStudio is also capable of one-click generation of C-compatible

data and header files, which can then be integrated directly into

a system’s host processor.

PROCESSING FLOW

PARAMETER MEMORY

The processing flow is outlined in Figure 52.

The sound engine makes use of a parameter memory to store

signal processing parameter values, such as filter coefficients.

This memory space is mapped to addresses starting at 0x0000

and is accessible via the control port. The parameter memory

allows the user to modify signal processing parameters in real

time during operation of the sound engine.

PROGRAMMING

Although the sound engine’s audio processing flow is fixed-

function, processing parameters and signal paths can be

modified by the user.

Real-time tuning and parameter generation is made possible by

SigmaStudio™, a graphical user interface that can communicate

with the ADAU1381 control port via the EVAL-ADUSB2EBZ

LINE INPUT

ADC

MONO

DAC

MIX

ADC

DIGITAL MIC

LINE OUTPUT

BEEP

STEREO

ADAU1381 SOUND ENGINE

STEREO

RECORD

STEREO DIGITAL

OUTPUT

RECORD

MUTE

WIND

ENHANCED

STEREO

ROUTING

DUAL-BAND

DYNAMIC

NOISE

SIX-BAND

LOGIC

REDUCTION

CAPTURE

ROUTING

DUAL-BAND

EQUALIZER

SIX BAND

PROCESSOR

LOGIC

DYNAMIC

ROUTING

DUAL-BAND

EQUALIZER

SIX BAND

LOGIC

PROCESSOR

DYNAMIC

EQUALIZER

PROCESSOR

PLAYBACK

DIGITAL STEREO

INPUT

PLAYBACK

STEREO

ROUTING

LOGIC

FLAG

Figure 52. Sound Engine Signal Processing Flow

Rev. 0| Page 41 of 84

ADAU1381

APPLICATIONS INFORMATION

POWER SUPPLY BYPASS CAPACITORS

GROUNDING

Each analog and digital power supply pin should be bypassed to

its nearest appropriate ground pin with a single 100 nF capacitor.

The connections to each side of the capacitor should be as short

as possible, and the trace should stay on a single layer with no

vias. For maximum effectiveness, locate the capacitor equidistant

from the power and ground pins or, when equidistant placement

is not possible, slightly closer to the power pin. Thermal connec-

tions to the ground planes should be made on the far side of the

capacitor.

A single ground plane should be used in the application layout.

Components in an analog signal path should be placed away

from digital signals.

SPEAKER DRIVER SUPPLY TRACE (AVDD2)

The trace supplying power to the AVDD2 pin has higher current

requirements than the AVDD1 pin (up to 300 mA). An appro-

priately thick trace is recommended.

EXPOSED PAD PCB DESIGN

Each supply signal on the board should also be bypassed with a

single bulk capacitor (10 μF to 47 μF).

The ADAU1381 LFCSP package has an exposed pad on the

underside. This pad is used to couple the package to the PCB

for heat dissipation when using the outputs to drive earpiece or

headphone loads. When designing a board for the ADAU1381,

special consideration should be given to the following:

VDD GND

•

A copper layer equal in size to the exposed pad should be

on all layers of the board, from top to bottom, and should

connect somewhere to a dedicated copper board layer

(see Figure 55).

CAPACITOR

TO VDD

•

Vias should be placed to connect all layers of copper,

allowing for efficient heat and energy conductivity. For an

example, see Figure 56, which has nine vias arranged in a

3 inch × 3 inch grid in the pad area.

TO GND

Figure 53. Recommended Power Supply Bypass Capacitor Layout

GSM NOISE FILTER

TOP

In mobile applications, excessive 217 Hz GSM noise on the

analog supply pins can degrade the quality of the audio signal.

To avoid this problem, it is recommended that an LC filter be

used in series with the bypass capacitors for the AVDD pins.

This filter should consist of a 1.2 nH inductor and a 9.1 pF

capacitor in series between AVDDx and ground, as shown

in Figure 54.

GROUND

POWER

BOTTOM

VIAS

COPPER SQUARES

Figure 55. Exposed Pad Layout Example, Side View

10µF

+

0.1µF

1.2nH 9.1pF

AVDD1 AVDD2

Figure 54. GSM Filter on the Analog Supply Pins

Figure 56. Exposed Pad Layout Example, Top View

Rev. 0 | Page 42 of 84

ADAU1381

CONTROL REGISTER MAP

All registers except the PLL control register are 1-byte write and read registers.

Table 27.

Address

Hex

Decimal

16384

16385

16386

16392

16393

16398

16399

16400

16405

16406

16407

16408

16409

16410

16411

16412

16414

16415

16416

16421

16422

16423

16424

16425

16426

16427

16428

16429

16430

16431

16432

16433

Name

0x4000

0x4001

0x4002

0x4008

0x4009

0x400E

0x400F

0x4010

0x4015

0x4016

0x4017

0x4018

0x4019

0x401A

0x401B

0x401C

0x401E

Clock control

Regulator control

PLL control (48-bit register)

Digital microphone and analog beep control

Record power management

Record gain left PGA

Record gain right PGA

Microphone bias control and beep enable

Serial Port Control 0

Serial Port Control 1

Converter Control 0

Converter Control 1

ADC control

Left ADC attenuator

Right ADC attenuator

Playback mixer left control

Playback mixer right control

Playback mono mixer control

Playback clamp amplifier control

Left line output mute

Right line output mute

Playback speaker output control

Beep zero-crossing detector control

Playback power management

DAC control

0x401F

0x4020

0x4025

0x4026

0x4027

0x4028

0x4029

0x402A

0x402B

0x402C

0x402D

0x402E

0x402F

0x4030

0x4031

0x4080

0x4081

0x40C6 to 0x40CA

0x03E8 to 0x03EC

0x40E9 to 0x40EA

0x40EB

0x40F2

Left DAC attenuator

Right DAC attenuator

Serial Port Pad Control 0

Serial Port Pad Control 1

Communication Port Pad Control 0

Communication Port Pad Control 1

MCKO control

Digital Power-Down 0

Digital Power-Down 1

GPIO pin control

16512

16513

16582 to 16586

1000 to 1004

16617 to 16618

16619

16626

16627

16628

16630

GPIO pin value registers

Nonmodulo registers

Sound engine frame rate

Serial input route control

Serial output route control

Serial data/GPIO pin configuration

Sound engine run

0x40F3

0x40F4

0x40F6

0x40F8

16632

Serial port sampling rate

Rev. 0| Page 43 of 84

ADAU1381

the PLL is always 1024 × f_S, and Bits[2:1] should be set to 11.

PLL parameters can be set in the PLL control register. Inputs

directly from MCKI require an exact clock rate as described in

the Bits[2:1], Input Master Clock Frequency section.

CLOCK MANAGEMENT, INTERNAL REGULATOR,

AND PLL CONTROL

Register 16384 (0x4000), Clock Control

The clock control register sets the clocking scheme for the

ADAU1381. The system clock can be generated from either the

PLL or directly from the MCKI (master clock input) pin. Addi-

tionally, the MCKO (master clock output) pin can be configured.

Bits[2:1], Input Master Clock Frequency

The maximum clock speed allowed is 1024 × 48 kHz. These bits set

the expected input master clock frequency for proper clock divider

values in order to output a constant system clock of 256 × f_S. When

using the PLL, these bits must always be set to 1024 × f_S. When

bypassing the PLL, the external clock frequency on the MCKI pin

must be 256 × f_S, 512 × f_S, 768 × f_S, or 1024 × f_S. Table 29

and Table 30 show the relationship between the system clock and

the internal master clock for base sampling frequencies of 44.1

kHz and 48 kHz.

Bits[6:5], MCKO Frequency

These bits set the frequency to be output on MCKO as a multiple

of the base sampling frequency (32×, 64×, 128×, or 256×). The

MCKO pin can be used to provide digital microphones with a clock.

Bit 4, MCKO Enable

This bit enables or disables the MCKO pin.

Bit 0, Core Clock Enable

Bit 3, Clock Source Select

This bit enables the internal master clock to start the IC.

The clock source select bit either routes the MCLK input through

the PLL or bypasses the PLL. When using the PLL, the output of

Table 28. Clock Control Register

Bits

Description

Default

7

Reserved

[6:5]

MCKO frequency

00: 32 × f_S

00

01: 64 × f_S

10: 128 × f_S

11: 256 × f_S

4

MCKO enable

0: disabled

0

1: enabled

3

Clock source select

0: direct from MCKI pin

1: PLL clock

0

[2:1]

Input master clock frequency

00: 256 × f_S

00

01: 512 × f_S

10: 768 × f_S

11: 1024 × f_S

0

Core clock enable

0: core clock disabled

1: core clock enabled

0

Table 29. Core Clock Output for f_S= 44.1 kHz

MCLK Input Setting

MCLK Input Value

MCLK Input Divider

Core Clock

256 × f_S

11.2896 MHz

22.5792 MHz

33.8688 MHz

45.1584 MHz

1

2

3

4

11.2896 MHz

512 × f_S

768 × f_S

1024 × f_S

Table 30. Core Clock Output for f_S= 48 kHz

MCLK Input Setting

MCLK Input Value

MCLK Input Divider

Core Clock

12.288 MHz

256 × f_S

12.288 MHz

24.576 MHz

36.864 MHz

49.152 MHz

1

2

3

4

512 × f_S

768 × f_S

1024 × f_S

Rev. 0 | Page 44 of 84

ADAU1381

Register 16385 (0x4001), Regulator Control

Bits[10:9], Input Divider

Bits[2:1], Regulator Output Level

The input divider (X) divides the input clock to offer a wider

range of input clocks.

These bits set the regulated voltage output for the digital core,

DVDDOUT. After the initialization sequence has completed,

the regulator output is set to 1.4 V. The recommended regulator

output level when the device begins to process audio is 1.5 V.

Therefore, this register should be set to 1.5 V when the sound

engine is being configured.

Bit 8, PLL Type

This selects the type of PLL operation, fractional or integer-N.

Fractional Type PLL

Fractional type MCLK inputs are scaled to the corresponding

desired core clock input using the parameters outlined in Table 33

and Table 34 as examples of typical base sampling frequencies

(44.1 kHz and 48 kHz). A numerical-controlled oscillator is

used to divide the PLL_CLK by a mixed number given by the

addition of the integer part (R) and fractional part (N/M).

Register 16386 (0x4002), PLL Control

This is a 48-bit register that must be written to in a single burst

write. PLL operating parameters are used to scale the MCLK

input to the desired clock core in order to obtain an appropriate

PLL clock (PLL output frequency). The PLL can be configured

for either fractional or integer-N type MCLK inputs.

For example, if the MCLK is 12 MHz, the required clock is

12.288 MHz, and f_Sis 48 kHz, then the PLL clock is 49.152 MHz

because PLL clock is always 1024 × f_S; therefore,

Bits[47:40], Denominator MSB

Byte 1, M[15:8] of the denominator (M) for fractional part of feed-

back divider. This is concatenated with Denominator LSB, M[7:0].

PLL Clock/MCLK = 4.096 = 4 + (12/125) = R + (N/M)

In this case, the input divider is X = 1.

Bits[39:32], Denominator LSB

Byte 0, M[7:0] of the denominator (M) for fractional part of feed-

back divider. This is concatenated with Denominator MSB, M[15:8].

This allows the MCLK input to emulate the desired required clock

and output a 49.152 MHz PLL clock. Figure 30 shows how the PLL

uses the parameters to emulate the required 12.288 MHz clock.

Bits[31:24], Numerator MSB

Integer-N Type PLL

Byte 1, N[15:8] of the numerator (N) for fractional part of the feed-

back divider. This is concatenated with Numerator LSB, N[7:0].

Integer-N type MCLK inputs are any integer multiple of the

desired core clock. The fractional part (N/M) is 0; however, the

PLL type bit must be set for integer-N.

Bits[23:16], Numerator LSB

Byte 0, N[7:0] of the numerator (N) for fractional part of the feed-

back divider. This is concatenated with Numerator MSB, N[15:8].

Bit 1, PLL Lock

The PLL lock bit is a read-only bit. Reading a 1 from this bit

indicates that the PLL has locked to the input master clock.

Bits[14:11], Integer

Integer (R) parameter used in both integer-N and fractional

PLL operation. This value must be between 2 and 8.

Bit 0, PLL Enable

This bit enables the PLL.

Table 31. Regulator Control Register

Bits

[7:3]

[2:1]

Description

Reserved

Default

Regulator output level

00: 1.5 V

01

01: 1.4 V

10: 1.6 V

11: 1.7 V

0

Reserved

Rev. 0| Page 45 of 84

ADAU1381

Table 32. PLL Control Register

Bits

Description

Default

[47:40]

Denominator MSB

00000111

00000000 and 00000000: M[15:8] and M[7:0] = 0

…

00000000 and 11111101: M[15:8] and M[7:0] = 125

…

11111111 and 11111111: M[15:8] and M[7:0] = 65,535

[39:32]

[31:24]

[23:16]

Denominator LSB

00000000 and 00000000: M[15:8] and M[7:0] = 0

…

00000000 and 11111101: M[15:8] and M[7:0] = 125

…

11111111 and 11111111: M[15:8] and M[7:0] = 65,535

01010011

00000010

10000111

Numerator MSB

00000000 and 00000000: N[15:8] and N[7:0] = 0

…

00000000 and 00001100: N[15:8] and N[7:0] = 12

…

11111111 and 11111111: N[15:8] and N[7:0] = 65,535

Numerator LSB

00000000 and 00000000: N[15:8] and N[7:0] = 0

…

00000000 and 00001100: N[15:8] and N[7:0] = 12

…

11111111 and 11111111: N[15:8] and N[7:0] = 65,535

Reserved

15

[14:11]

Integer

0011

0010: R = 2

0011: R = 3

0100: R = 4

0101: R = 5

0110: R = 6

0111: R = 7

1000: R = 8

[10:9]

Input divider

00: no division

01: divide by X = 2

10: divide by X = 3

11: divide by X = 4

PLL type

00

1

8

0: integer-N

1: fractional

[7:2]

1

Reserved

PLL lock (read only)

0: unlocked

1: locked (sticky bit)

PLL enable

1

0

0: disabled

1: enabled

Rev. 0 | Page 46 of 84

ADAU1381

Table 33. Fractional PLL Parameter Settings for f_S= 44.1 kHz (f_S= 44.1 kHz, Core Clock = 256 × 44.1 kHz, PLL Clock = 45.1584 MHz)

MCLK Input (MHz)

Input Divider (X)

Integer (R)

Denominator (M)

Numerator (N)

12

13

14.4

19.2

19.68

19.8

1

3

2

625

8125

125

2035

1375

477

3849

17

44

302

386

Table 34. Fractional PLL Parameter Settings for f_S= 48 kHz (f_S= 48 kHz, Core Clock = 256 × 48 kHz, PLL Clock = 49.152 MHz)

MCLK Input (MHz)

Input Divider (X)

Integer (R)

Denominator (M)

Numerator (N)

12

13

14.4

19.2

19.68

19.8

1

4

3

2

125

1625

75

25

205

825

12

1269

31

14

102

398

Rev. 0| Page 47 of 84

ADAU1381

Bit 3, Beep Input Mute

RECORD PATH CONFIGURATION

This bit mutes the beep input.

Register 16392 (0x4008), Digital Microphone and

Analog Beep Control

Bits[2:0], Beep Input Gain

This register controls the digital microphone settings and the

analog beep input gain.

This bit controls the gain setting for the analog beep input; it

defaults at 0 dB and can be set as high as 32 dB. The beep signal

must be enabled in Register 16400 (0x4010), microphone bias

control and beep enable.

Bits[5:4], Digital Microphone Enable

These bits control the enable function for the stereo digital

microphones. The analog front end is powered down when

using a digital microphone.

Table 35. Digital Microphone and Analog Beep Control Register

Bits

[7:6]

[5:4]

Description

Default

Reserved

Digital microphone enable

00: disabled

00

01: MICD1 enabled

10: MICD2 enabled

11: reserved

3

Beep input mute

0: muted

0

1: unmuted

[2:0]

Beep input gain. Note that Setting 100 sets the input beep gain to −23 dB.

000

000: 0 dB

001: +6 dB

010: +10 dB

011: +14 dB

100: −23 dB

101: +20 dB

110: +26 dB

111: +32 dB

Rev. 0 | Page 48 of 84

ADAU1381

Bits[6:5], Mixer Amplifier Boost

Register 16393 (0x4009), Record Power Management

These bits set the power mode of operation for the front-end

mixer boost. With higher AVDD1 levels, distortion may become

an issue affecting performance. Each boost level enhances the

THD + N performance at 3.3 V AVDD1.

This register manages the power consumption for the record

path. In particular, the current distribution for the mixer boosts,

ADC, front-end mixer, and PGAs can be set in one of four

modes. The four modes of operation available that affect the

performance of the device are normal operation, power saving,

enhanced performance, and extreme power saving. Normal

operation has a base current of 2.5 μA, enhanced performance

has a base current of 3 μA, power saving has a base current of

a 2 μA, and extreme power saving has a base current of 1.5 μA.

Enhanced performance offers the highest performance, but

with the trade-off of higher power consumption.

Bits[4:3], ADC Bias Control

These bits set the bias current for the ADCs based on the mode

of operation selected.

Bits[2:1], Front-End Bias Control

These bits set the bias current for the PGAs and mixers in the

front-end record path.

Table 36. Record Power Management Register

Bits

Description

Default

7

Reserved

[6:5]

Mixer amplifier boost

00: normal operation

01: Boost Level 1

00

10: Boost Level 2

11: Boost Level 3

[4:3]

[2:1]

0

ADC bias control

00

00: normal operation

01: extreme power saving

10: power saving

11: enhanced performance

Front-end bias control

00: normal operation

01: extreme power saving

10: power saving

11: enhanced performance

Reserved

Rev. 0| Page 49 of 84

ADAU1381

input pin (LMICP) is disabled, and the complementary input of

the PGA is switched to common mode.

Register 16398 (0x400E), Record Gain Left PGA

The record gain left PGA control register controls the left channel

input PGA. This register configures the input for either differ-

ential or single-ended signals and sets the left channel input

recording volume.

Bit 1, Record Path Left Mute

This bit mutes the left channel input PGA.

Bit 0, Left PGA Enable

Bits[7:5], Left Input Gain

This bit enables the left channel input PGA

These bits set the left channel analog microphone input PGA gain.

Bit 2, Single-Ended Left Input Enable

If this bit is high (enabled), a single-ended input can be input on

the LMIC pin and gained by the PGA. The positive differential

Table 37. Record Gain Left PGA Register

Bits

Description

Left input gain

000: 0 dB

Default

[7:5]

000

001: 6 dB

010: 10 dB

011: 14 dB

100: 17 dB

101: 20 dB

110: 26 dB

111: 32 dB

[4:3]

2

Reserved

Single-ended left input enable

0: disabled

1: enabled

0

1

0

Record path left mute

0: muted

1: unmuted

Left PGA enable

0: disabled

1: enabled

Rev. 0 | Page 50 of 84

ADAU1381

input pin (RMICP) is disabled, and the complementary input of

the PGA is switched to common mode.

Register 16399 (0x400F), Record Gain Right PGA

The record gain right PGA control register controls the right

channel input PGA. This register configures the input for either

differential or single-ended signals and sets the right channel

input recording volume.

Bit 1, Record Path Right Mute

This bit mutes the entire right channel input PGA.

Bit 0, Right PGA Enable

Bits[7:5], Right Input Gain

This bit enables the right channel PGA.

These bits set the right channel analog microphone input PGA gain.

Bit 2, Single-Ended Right Input Enable

If this bit is high (enabled), a single-ended input can be input on

the RMIC pin and gained by the PGA. The positive differential

Table 38. Record Gain Right PGA Register

Bits

Description

Right input gain

000: 0 dB

Default

[7:5]

000

001: 6 dB

010: 10 dB

011: 14 dB

100: 17 dB

101: 20 dB

110: 26 dB

111: 32 dB

[4:3]

2

Reserved

Single-ended right input enable

0: disabled

1: enabled

0

1

0

Record path right mute

0: muted

1: unmuted

Right PGA enable

0: disabled

1: enabled

Rev. 0| Page 51 of 84

ADAU1381

Bit 2, Microphone Gain

Register 16400 (0x4010), Microphone Bias Control and

Beep Enable

Provides two voltage bias options, 0.65 × AVDD1 and 0.90 ×

AVDD1. A higher bias contributes to a higher microphone gain.

The maximum current that can be drawn from MICBIAS is 5 mA.

Bit 4, Beep Input Enable

This bit enables the beep signal, which is input to the BEEP pin.

Setting this bit to 0 mutes the beep signal for all output paths.

Bit 0, Microphone Bias Enable

This bit enables the MICBIAS output.

Bit 3, Microphone High Performance

This bit puts the microphone bias into high performance mode,

by offering more current to the microphone.

Table 39. Microphone Bias Control and Beep Enable Register

Bits

[7:5]

4

Description

Default

Reserved

Beep input enable

0: disabled

0

1: enabled

3

2

Microphone high performance

0: high power

1: low performance

Microphone gain

0: enabled

0

1: disabled

1

0

Reserved

Microphone bias enable

0: disabled

0

1: enabled

Rev. 0 | Page 52 of 84

ADAU1381

Bits[2:1], Channels per Frame

SERIAL PORT CONFIGURATION

Register 16405 (0x4015), Serial Port Control 0

Bit 5, LRCLK Mode

These bits set the number of channels contained in the data stream

(see Figure 59). The possible choices are stereo (used in standard

I²S signals), TDM 4 (a 4-channel time division multiplexed stream),

or TDM 8 (an 8-channel time division multiplexed stream). The

TDM output modes are simply multichannel data streams, and

the data pin does not become high impedance during periods

when it is not outputting data.

This bit sets the serial port frame clock (LRCLK) as either a

50% duty cycle waveform or a pulse synchronization waveform.

When in slave mode, the pulse should be at least 1 BCLK cycle

wide to guarantee proper data transfer.

Bit 4, BCLK Polarity

Within a TDM stream, channels are grouped by pair, as shown

in Figure 60.

This bit sets the polarity of the bit clock (BCLK) signal. This

setting determines whether the data and frame clock signals

change on a rising (+) or falling (−) edge of the BCLK signal

(see Figure 57). Standard I²S signals use negative BCLK polarity.

Bit 0, Serial Data Port Mode

This bit sets the clock pins as either master or slave. Both

LRCLK and BCLK are the bus master of the serial port when

master mode is enabled.

Bit 3, LRCLK Polarity

The polarity of LRCLK determines whether the left stereo channel

is initiated on a rising (+) or falling (−) edge of the LRCLK signal

(see Figure 58). Standard I²S signals use negative LRCLK polarity.

Table 40. Serial Port Control 0 Register

Bits

[7:6]

5

Description

Default

Reserved

LRCLK mode

0

0: 50% duty cycle clock

1: pulse mode; pulse should be at least 1 BCLK wide

BCLK polarity

4

0

0: data changes on falling (−) edge

1: data changes on rising (+) edge

LRCLK polarity

3

0

0: left frame starts on falling (−) edge

1: left frame starts on rising (+) edge

Channels per frame

[2:1]

00

00: stereo (two channels)

01: TDM 4 (four channels)

10: TDM 8 (eight channels)

11: reserved

0

Serial data port mode

0: slave

0

1: master

Rev. 0| Page 53 of 84

ADAU1381

BCLK POLARITY

LRCLK

BCLK

SDATA

LRCLK

BCLK

SDATA

Figure 57. Serial Port BCLK Polarity

LRCLK POLARITY

LRCLK

L

R

L

R

L

R

LRCLK

Figure 58. Serial Port LRCLK Polarity

1/f_LRCLK

LRCLK

STEREO CHANNELS

TDM 4 CHANNELS

TDM 8 CHANNELS

1

2

1

2

3

4

1

2

3

4

5

6

7

8

Figure 59. Channels per Frame

1/f_LRCLK

LRCLK

TDM 4 CHANNELS

TDM 8 CHANNELS

FIRST PAIR

SECOND PAIR

1

2

3

4

FIRST PAIR

1

SECOND PAIR

THIRD PAIR

FOURTH PAIR

2

3

4

5

6

7

8

Figure 60. TDM Channel Pairs

Rev. 0 | Page 54 of 84

ADAU1381

Bit 2, MSB Position

Register 16406 (0x4016), Serial Port Control 1

This bit sets the bit-level endianness (or bit order) of the data

stream. A setting of 0 results in a big-endian order, with the MSB

coming first in the stream and the LSB coming last. A setting of 1

results in a little-endian order, with the LSB coming first in the

stream and the MSB coming last. Figure 65 shows examples of

the two settings with a 24-bit audio stream in an MSB delay-by-0

configuration. In Figure 65, M stands for MSB, and L stands for LSB.

Bits[7:5], Number of Bit Clock Cycles per Frame

These bits set the number of BCLK cycles contained in one

LRCLK period. The frequency of BCLK is calculated as the

number of bit clock cycles per frame times the sample rate of

the serial port in hertz. Figure 61 and Figure 62 show examples

of different settings for these bits.

Bit 4, ADC Channel Position in TDM

Bits[1:0], Data Delay from LRCLK Edge

This register sets the order of the ADC channels when output on

the serial output port. A setting of 0 puts the left channel first in its

respective TDM channel pair. A setting of 1 puts the right channel

first in its respective TDM channel pair. This bit should be set in

conjunction with Register 16408 (0x4018), Converter Control 1,

Bits[1:0], on-chip ADC data selection in TDM mode, to select

where the data should appear in the TDM stream. Figure 63 shows

a setting of 0, and Figure 64 shows a setting of 1.

These bits set the delay between the LRCLK edge and the first

data bit in the stream. The I²S standard is a delay of one BCLK

cycle. Examples of different data delay settings are shown

in Figure 66, with a 64 BCLK cycle per frame, 24-bit audio data,

big-endian bit order configuration. In Figure 66, M represents

the most significant bit of the audio channel’s data, and L represents

the least significant bit.

The first example setting (delay by 0) in Figure 66 represents a left-

justified mode because the least significant bit aligns with the

beginning of the audio frame. The third example setting (delay

by 8) represents a right-justified mode because the least significant

bit aligns with the end of the audio frame. A delay-by-16 setting

would not be valid in this mode because the audio data would

exceed the boundaries of the frame clock period.

Bit 3, DAC Channel Position in TDM

This register sets the order of the DAC channels when output on

the serial output port. A setting of 0 puts the left channel first in its

respective TDM channel pair. A setting of 1 puts the right channel

first in its respective TDM channel pair. This bit should be set in

conjunction with Register 16407 (0x4017), Converter Control 0,

Bits[6:5], on-chip DAC data selection in TDM mode, to select

where the data should appear in the TDM stream. Figure 63

shows a setting of 0, and Figure 64 shows a setting of 1.

Figure 67 shows an example of delay by 16 for a 16-bit audio

stream with 64 BCLK cycles per frame.

Table 41. Serial Port Control 1 Register

Bits

Description

Default

[7:5]

Number of bit clock cycles per frame

000: 64

000

001: 32

010: 48

011: 128

100: 256

101: reserved

110: reserved

111: reserved

4

ADC channel position in TDM

0: left first

0

1: right first

3

DAC channel position in TDM

0: left first

0

1: right first

2

MSB position

0

0: MSB first

1: MSB last

[1:0]

Data delay from LRCLK edge

00: 1 BCLK cycle

01: 0 BCLK cycles

10: 8 BCLK cycles

11: 16 BCLK cycles

00

Rev. 0| Page 55 of 84

ADAU1381

1/f_LRCLK

LRCLK

BCLK

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Figure 61. Example: 32 BCLK Cycles per Frame

1/f_LRCLK

LRCLK

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

BCLK

Figure 62. Example: 48 BCLK Cycles per Frame

1/f_LRCLK

LRCLK

FIRST PAIR

SECOND PAIR

LEFT

RIGHT

LEFT

RIGHT

TDM 4 CHANNELS

TDM 8 CHANNELS

FIRST PAIR

SECOND PAIR

THIRD PAIR

FOURTH PAIR

LEFT RIGHT

LEFT

RIGHT

LEFT

RIGHT

LEFT

RIGHT

Figure 63. Left First Channel Selection in TDM

1/f_LRCLK

LRCLK

TDM 4 CHANNELS

TDM 8 CHANNELS

FIRST PAIR

SECOND PAIR

RIGHT

LEFT

RIGHT

LEFT

FIRST PAIR

SECOND PAIR

THIRD PAIR

RIGHT LEFT

FOURTH PAIR

RIGHT

LEFT

RIGHT

LEFT

RIGHT

LEFT

Figure 64. Right First Channel Selection in TDM

BCLK

1

M

L

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

MSB FIRST

L

LSB FIRST

M

Figure 65. MSB Position Settings

Rev. 0 | Page 56 of 84

ADAU1381

1/f_LRCLK

LRCLK

BCLK

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

SERIAL DATA

(DELAY BY 0)

M

L

M

L

SERIAL DATA

(DELAY BY 1)

M

L

M

L

SERIAL DATA

(DELAY BY 8)

M

L

M

L

Figure 66. Serial Audio Data Delay Example Settings

1/f_LRCLK

LRCLK

BCLK

1

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

SERIAL DATA

(DELAY BY 16)

M

L

M

L

Figure 67. Serial Audio Data Delay by 16 Example

Rev. 0| Page 57 of 84

ADAU1381

Bit 4, DAC Oversampling Ratio

AUDIO CONVERTER CONFIGURATION

This bit sets the oversampling ratio of the DAC relative to the

audio sample rate. The higher rate yields slightly better audio

quality but increases power consumption.

Register 16407 (0x4017), Converter Control 0

Bits[6:5], On-Chip DAC Data Selection in TDM Mode

These bits set the position of the DAC input channels on a TDM

stream. In TDM 4 mode, valid settings are first pair or second

pair. In TDM 8 mode, valid settings are first pair, second pair,

third pair, or fourth pair. These bits should be set in conjunction

with Register 16406 (0x4016), Serial Port Control 1, Bit 3, DAC

channel position in TDM, to select where the data should appear

in the TDM stream.

Bit 3, ADC Oversampling Ratio

This bit sets the oversampling ratio of the ADC relative to the

audio sample rate. The higher rate yields slightly better audio

quality but increases power consumption.

Bits[2:0], Converter Sampling Rate

These bits set the sampling rate of the audio ADCs and DACs

relative to the sound engine’s audio sample rate.

Figure 68, Figure 69, and Figure 70 show examples of different

TDM settings.

Table 42. Converter Control 0 Register

Bits

Description

Default

7

Reserved

[6:5]

On-chip DAC data selection in TDM mode

00

00: first pair

01: second pair

10: third pair

11: fourth pair

DAC oversampling ratio

0: 128

4

0

1: 64

3

ADC oversampling ratio

0: 128

1: 64

[2:0]

Converter sampling rate; the numbers in parentheses are example values for a base sample rate of 48 kHz

000

000: f_S(48 kHz)

001: f_S/6 (8 kHz)

010: f_S/4 (12 kHz)

011: f_S/3 (16 kHz)

100: f_S/2 (24 kHz)

101: f_S/1.5 (32 kHz)

110: f_S× 2 (96 kHz)

111: reserved

Rev. 0 | Page 58 of 84

ADAU1381

1/f_LRCLK

LRCLK

TDM 4 CHANNELS

TDM 8 CHANNELS

FIRST PAIR

SECOND PAIR

LEFT

RIGHT

FIRST PAIR

SECOND PAIR

THIRD PAIR

FOURTH PAIR

LEFT

RIGHT

Figure 68. Example of Left Channel First, First Pair TDM Setting

1/f_LRCLK

LRCLK

TDM 4 CHANNELS

TDM 8 CHANNELS

FIRST PAIR

SECOND PAIR

RIGHT

LEFT

FIRST PAIR

SECOND PAIR

RIGHT LEFT

THIRD PAIR

FOURTH PAIR

Figure 69. Example of Right Channel First, Second Pair TDM Setting

1/f_LRCLK

LRCLK

FIRST PAIR

SECOND PAIR

THIRD PAIR

FOURTH PAIR

LEFT

RIGHT

TDM 8 CHANNELS

Figure 70. Example of Left Channel First, Fourth Pair TDM Setting

Rev. 0| Page 59 of 84

ADAU1381

with Register 16406 (0x4016), Serial Port Control 1, Bit 4, ADC

channel position in TDM, to select where the data should appear

in the TDM stream.

Register 16408 (0x4018), Converter Control 1

Bits[1:0], On-Chip ADC Data Selection in TDM Mode

These bits set the position of the ADC output channels on a TDM

stream. In TDM 4 mode, valid settings are first pair or second

pair. In TDM 8 mode, valid settings are first pair, second pair,

third pair, or fourth pair. These bits should be set in conjunction

Figure 68, Figure 69, and Figure 70 show examples of different

TDM settings.

Table 43. Converter Control 1 Register

Bits

[7:2]

[1:0]

Description

Default

Reserved

On-chip ADC data selection in TDM mode

00: first pair

00

01: second pair

10: third pair

11: fourth pair

Rev. 0 | Page 60 of 84

ADAU1381

Bit 3, Digital Microphone Channel Swap

Register 16409 (0x4019), ADC Control

This bit allows the left and right channels of the digital microphone

input to swap. Standard mode is the left channel on the rising

edge and the right channel on the falling edge. Swapped mode is

the right channel on the rising edge and the left channel on the

falling edge.

Bit 6, Invert Input Polarity

This bit enables an optional polarity inverter in the ADC path,

which is an amplifier with a gain of −1, representing a 180°

phase shift.

Bit 5, High-Pass Filter Select

Bit 2, Digital Microphone Input Select

This bit enables an optional high-pass filter in the ADC path,

with a cutoff frequency of 2 Hz when f_S= 48 kHz. The cutoff

frequency scales linearly with f_S.

This bit must be enabled in order to use the digital microphone

inputs. When this bit is asserted, the on-chip ADCs are off, BCLK

is the master at 128 × f_S, and ADC_SDATA is expected to have

the left and right channels interleaved. This bit must be disabled

to use the ADCs.

Bit 4, Digital Microphone Data Polarity Swap

This bit inverts the polarity of valid data states for the digital

microphone data stream. A typical PDM microphone can drive

its data output pin either high or low, not both. This bit must be

configured accordingly to recognize a valid output state of the

microphone. The default is negative, meaning that a digital

logic low signal is recognized by the ADAU1381 as a pulse in

the PDM signal.

Bits[1:0], ADC Enable

These bits must be configured to use the ADCs. ADC channels

can be enabled or disabled individually.

Table 44. ADC Control Register

Bits

Description

Default

7

Reserved

6

Invert input polarity

0: normal

0

1: inverted

5

High-pass filter select

0: disabled

0

1: enabled

4

Digital microphone data polarity swap

0: negative

0

1: positive

3

Digital microphone channel swap

0: standard mode

1: swapped mode

Digital microphone input select

0: digital microphone input off

1: select digital microphone input, ADCs off

ADC enable

0

2

0

[1:0]

00

00: both off

01: left on

10: right on

11: both on

Rev. 0| Page 61 of 84

ADAU1381

Register 16411 (0x401B), Right ADC Attenuator

Register 16410 (0x401A), Left ADC Attenuator

Bits[7:0], Right ADC Digital Attenuator

Bits[7:0], Left ADC Digital Attenuator

These bits control a 256-step, logarithmically spaced volume

control from 0 dB to −95.625 dB, in increments of 0.375 dB.

When a new value is entered into this register, the volume control

slews gradually to the new value, avoiding pops and clicks in the

process. The slew ramp is logarithmic, incrementing 0.375 dB

per audio frame.

These bits control a 256-step, logarithmically spaced volume

control from 0 dB to −95.625 dB, in increments of 0.375 dB.

When a new value is entered into this register, the volume control

slews gradually to the new value, avoiding pops and clicks in the

process. The slew ramp is logarithmic, incrementing 0.375 dB

per audio frame.

Table 45. Left ADC Attenuator Register

Bits

Description

Default

[7:0]

Left ADC digital attenuator; attenuation is in increments of 0.375 dB with each step of slewing

00000000

00000000: 0 dB

00000001: −0.375 dB

00000010: −0.75 dB

…

11111110: −95.25 dB

11111111: −95.625 dB

Table 46. Right ADC Attenuator Register

Bits

Description

Default

[7:0]

Right ADC digital attenuator; attenuation is in increments of 0.375 dB with each step of slewing

00000000

00000000: 0 dB

00000001: −0.375 dB

00000010: −0.75 dB

…

11111110: −95.25 dB

11111111: −95.625 dB

Rev. 0 | Page 62 of 84

ADAU1381

Register 16414 (0x401E), Playback Mixer Right Control

PLAYBACK PATH CONFIGURATION

Register 16412 (0x401C), Playback Mixer Left Control

Bit 5, Left DAC Mute

Bit 6, Right DAC Mute

This bit mutes the right DAC output. It does not have any slew

and is updated immediately when the register write has been

completed. This results in an abrupt cutoff of the audio output

and should therefore be preceded by a soft mute in the sound

engine or a slew mute using the DAC attenuator.

This bit mutes the left DAC output. It does not have any slew

and is updated immediately when the register write has been

completed. This results in an abrupt cutoff of the audio output

and should therefore be preceded by a soft mute in the sound

engine or a slew mute using the DAC attenuator.

Bits[4:1], Right Playback Beep Gain

These bits set the gain of the beep signal in the right playback

path. If the zero-crossing detector is activated, the change in

gain is applied on the next detected zero crossing or when the

timeout period expires, whichever comes first. The gain control

is in 3 dB increments and should not be incremented more than

3 dB at a time in order to avoid audible artifacts on the output.

Bits[4:1], Left Playback Beep Gain

These bits set the gain of the beep signal in the left playback

path. If the zero-crossing detector is activated, the change in

gain is applied on the next detected zero crossing or when the

timeout period expires, whichever comes first. The gain control

is in 3 dB increments and should not be incremented more than

3 dB at a time in order to avoid audible artifacts on the output.

Table 47. Playback Mixer Left Control Register

Bits

[7:6]

5

Description

Default

Reserved

Left DAC mute

0: muted

0

1: unmuted

Left playback beep gain

0000: muted

0001: −15 dB

0010: −12 dB

0011: −9 dB

0100: −6 dB

0101: −3 dB

0110: 0 dB

[4:1]

0000

0111: +3 dB

1000: +6 dB

Reserved

0

Table 48. Playback Mixer Right Control Register

Bits

Description

Default

7

Reserved

6

Right DAC mute

0: muted

0

1: unmuted

Reserved

5

[4:1]

Right playback beep gain

0000: muted

0001: −15 dB

...

0000

1000: +6 dB

Reserved

0

Rev. 0| Page 63 of 84

ADAU1381

Register 16416 (0x4020), Playback Clamp Amp Control

Register 16415 (0x401F), Playback Mono Mixer Control

The playback clamp amp is an amplifier on the line output path.

If the line outputs are muted using Register 16421 (0x4025), left

line output mute, or Register 16422 (0x4026), right line output

mute, this amplifier serves to maintain a common-mode voltage

on the line output pins. This helps to avoid a pop or click when

the line outputs are reenabled.

Bit 7, Left DAC Mute

This bit mutes the left DAC output, but does not power down

the DAC. Use of this bit does not result in power savings.

Bit 6, Right DAC Mute

This bit mutes the right DAC output, but does not power down

the DAC. Use of this bit does not result in power savings.

Bit 1, Clamp Amplifier Power Saving Mode

The clamp amplifier has two operating modes: high power

mode and low power mode. The high power mode has more

current available to maintain a stable common-mode voltage on

the output pins. The low power mode may be slightly less stable,

depending on operating conditions, but saves several microamps.

Bits[5:2], Mono Playback Beep Gain

These bits set the gain of the beep output signal in mono mode.

If the zero-crossing detector is active, then the gain change

takes place on the next zero crossing in the beep signal or when

the timeout occurs, whichever comes first.

Bit 0, Clamp Amplifier Control

Bit 0, Mono Output Mute

This bit enables or disables the clamp amp. It is enabled by default.

The clamp amp should usually be enabled in systems where the

line outputs are used.

This bit mutes the mono line output.

Table 49. Playback Mono Mixer Control Register

Bits

Description

Left DAC mute

0: muted

Default

7

0

1: unmuted

6

Right DAC mute

0: muted

0

1: unmuted

[5:2]

Mono playback beep gain

0000: muted

0001: −15 dB

0010: −12 dB

0011: −9 dB

0000

0100: −6 dB

0101: −3 dB

0110: 0 dB

0111: +3 dB

1000: +6 dB

1

0

Reserved

Mono output mute (active low)

0: muted

0

1: unmuted

Table 50. Playback Clamp Amplifier Control Register

Bits

[7:2]

1

Description

Default

Reserved

Clamp amplifier power saving mode

0: high power

1

1: low power

0

Clamp amplifier control

0: enabled

0

1: disabled

Rev. 0 | Page 64 of 84

ADAU1381

Register 16422 (0x4026), Right Line Output Mute

Register 16421 (0x4025), Left Line Output Mute

Bit 1, Right Line Output Mute

Bit 1, Left Line Output Mute

This bit mutes the right line output. It does not have any effect

on the speaker outputs.

This bit mutes the left line output. It does not have any effect on

the speaker outputs.

Table 51. Left Line Output Mute Register

Bits

[7:2]

1

Description

Default

Reserved

Left line output mute (active low)

0: muted

0

1: unmuted

0

Reserved

Table 52. Right Line Output Mute Register

Bits

[7:2]

1

Description

Default

Reserved

Right line output mute (active low)

0: muted

0

1: unmuted

0

Reserved

Rev. 0| Page 65 of 84

ADAU1381

Register 16424 (0x4028), Beep Zero-Crossing Detector

Control

Register 16423 (0x4027), Playback Speaker Output

Control

Bits[4:3], Detector Timeout

Bits[7:6], Speaker Output Gain Control

The timeout detector waits the specified amount of time for a

beep zero crossing before forcing the mute or unmute in the

playback path beep gains (that is, the left playback beep gain,

right playback beep gain, and mono playback beep gain).

These bits control the gain of the speaker output. In general, this

parameter should be tuned at a system level, set once during system

initialization and not altered during operation of the system.

Bit 0, Speaker Output Enable

Bit 0, Zero-Crossing Detector Enable

This bit enables the speaker output. It initiates the speaker power-

up and power-down sequences shown in Figure 36 and Figure 37.

This bit enables the zero-crossing detector. Disabling the beep

zero-crossing detector may cause clicks and pops on the output

when using the beep path.

Table 53. Playback Speaker Output Control Register

Bits

Description

Speaker output gain control

00: 0 dB

Default

[7:6]

00

01: 2 dB

10: 4 dB

11: 6 dB

[5:1]

0

Reserved

Speaker output enable

0: disabled

0

1: enabled

Table 54. Beep Zero-Crossing Detector Control Register

Bits

[7:5]

[4:3]

Description

Default

Reserved

Detector timeout

00: 20 ms

11

01: 10 ms

10: 5 ms

11: 2.5 ms

[2:1]

0

Reserved

Zero-crossing detector enable

0: disabled

1

1: enabled

Rev. 0 | Page 66 of 84

ADAU1381

Bits[5:4], DAC Bias Control

Register 16425 (0x4029), Playback Power Management

These bits control the amount of unity bias current allotted to

the DAC.

This register controls the unity current supplied to each functional

block described. Within the functional blocks, the current can

be multiplied. Normal operation has a base current of 2.5 μA,

enhanced performance has a base current of 3 μA, power saving

has a base current of 2 μA, and extreme power saving has a base

current of 1.5 μA. Enhanced performance mode offers the best

audio quality but also uses the most current.

Bits[3:2], Back-End Bias Control

These bits control the amount of unity bias current allotted to

the playback mixers and amplifiers.

Bit 1, Back-End Right Enable

Bit [7:6], Speaker Amplifier Bias Control

This bit enables the playback mixers and amplifiers.

These bits control the amount of unity bias current allotted to

the speaker amplifier.

Bit 0, Back-End Left Enable

This bit enables the playback mixers and amplifiers.

Table 55. Playback Power Management Register

Bits

Description

Default

[7:6]

Speaker amplifier bias control

00: normal operation

01: power saving

00

10: enhanced performance

00: reserved

[5:4]

[3:2]

DAC bias control

00

00: normal operation

01: extreme power saving

10: power saving

00: enhanced performance

Back-end bias control

00: normal operation

01: extreme power saving

10: power saving

00: enhanced performance

Back-end right enable

0: disabled

1

0

1: enabled

Back-end left enable

0: disabled

1: enabled

Rev. 0| Page 67 of 84

ADAU1381

Bit 5, Invert Input Polarity

Register 16426 (0x402A), DAC Control

This bit applies a gain of −1, or a 180° phase shift, to the DAC

output signal.

Bits[7:6], Mono Mode

These bits control the output mode of the DAC. Setting these

bits to 00 outputs two distinct channels, left and right. Setting

these bits to 01 outputs the left input channel on both the left

and right outputs, and the right input channel is lost. Setting

these bits to 10 outputs the right input channel on both the left

and right outputs, and the left input channel is lost. Setting these

bits to 11 mixes the left and right input channels and outputs

the mixed mono signal on both the left and right outputs.

Bit 2, DAC De-Emphasis Filter Enable

This bit enables a de-emphasis filter and should be used when a

preemphasized signal is input to the DACs.

Bits[1:0], DAC Enable

These bits allow the DACs to be individually enabled or disabled.

Disabling unused DACs can result in significant power savings.

Table 56. DAC Control Register

Bits

Description

Default

[7:6]

Mono mode

00

00: stereo output

01: both output left channel

10: both output right channel

11: both output left/right mix

Invert input polarity

0: normal

5

0

1: inverted

[4:3]

2

Reserved

DAC de-emphasis filter enable

0: disabled

0

1: enabled

[1:0]

DAC enable

00

00: both off

01: left on

10: right on

11: both on

Rev. 0 | Page 68 of 84

ADAU1381

Register 16428 (0x402C), Right DAC Attenuator

Register 16427 (0x402B), Left DAC Attenuator

Bits[7:0], Right DAC Digital Attenuator

Bits[7:0], Left DAC Digital Attenuator

These bits control a 256-step, logarithmically spaced volume

control from 0 dB to −95.625 dB, in increments of 0.375 dB.

When a new value is entered into this register, the volume control

slews gradually to the new value, avoiding pops and clicks in the

process. The slew ramp is logarithmic, incrementing 0.375 dB

per audio frame.

These bits control a 256-step, logarithmically spaced volume

control from 0 dB to −95.625 dB, in increments of 0.375 dB.

When a new value is entered into this register, the volume control

slews gradually to the new value, avoiding pops and clicks in the

process. The slew ramp is logarithmic, incrementing 0.375 dB

per audio frame.

Table 57. Left DAC Attenuator Register

Bits

Description

Default

[7:0]

Left DAC digital attenuator, in increments of 0.375 dB with each step of slewing

00000000

00000000: 0 dB

00000001: −0.375 dB

00000010: −0.75 dB

…

11111110: −95. 25

11111111: −95.625 dB

Table 58. Right DAC Attenuator Register

Bits

Description

Default

[7:0]

Right DAC digital attenuator, in increments of 0.375 dB with each step of slewing

00000000

00000000: 0 dB

00000001: −0.375 dB

00000010: −0.75 dB

…

11111110: −95. 25

11111111: −95.625 dB

Rev. 0| Page 69 of 84

ADAU1381

PAD CONFIGURATION

Figure 71 shows a block diagram of the pad design for the GPIO/serial port and communications port pins.

DIGITAL

I/O

SUPPLY SUPPLY

DATA OUT

LEVEL

SHIFTER

OUTPUT ENABLE

OUTPUT

CONTROL

LOGIC

OUTPUT PULL-UP ENABLE

(CONTROLS PMOS)

DEBOUNCE

ENABLE

INPUT

ENABLE

PULL-UP

ENABLE

6×

LEVEL

SHIFTER

INPUT

ESD

DATA IN

DEBOUNCE

PAD

12×

PULL-DOWN

ENABLE

WEAK PULL-UP/PULL-DOWN

240kΩ NOMINAL

WEAK PULL-UP ENABLE

LEVEL

SHIFTER

190kΩ WORST CASE

WEAK PULL-DOWN ENABLE

DRIVE STRENGTH

(CONTROLS NUMBER OF PARALLEL TRANSISTOR PAIRS)

IOVDD = 3.3V; LOW = 2.0mA, HIGH = 4.0mA

IOVDD = 1.8V; LOW = 0.75mA, HIGH = 1.5mA

Figure 71. Pad Configuration, Internal Design

Rev. 0 | Page 70 of 84

ADAU1381

Bits[3:2], LRCLK Pad Pull-Up/Pull-Down

Register 16429 (0x402D), Serial Port Pad Control 0

These bits enable or disable a weak pull-up or pull-down device

on the pad. The effective resistance of the pull-up or pull-down

is nominally 240 kꢀ.

Bits[7:6], ADC_SDATA Pad Pull-Up/Pull-Down

These bits enable or disable a weak pull-up or pull-down device

on the pad. The effective resistance of the pull-up or pull-down

is nominally 240 kꢀ.

Bits[1:0], BCLK Pad Pull-Up/Pull-Down

These bits enable or disable a weak pull-up or pull-down device

on the pad. The effective resistance of the pull-up or pull-down

is nominally 240 kꢀ.

Bits[5:4], DAC_SDATA Pad Pull-Up/Pull-Down

These bits enable or disable a weak pull-up or pull-down device

on the pad. The effective resistance of the pull-up or pull-down

is nominally 240 kꢀ.

Table 59. Serial Port Pad Control 0 Register

Bits

Description

Default

[7:6]

ADC_SDATA pad pull-up/pull-down

00: pull-up

11

01: reserved

10: none (default)

11: pull-down

[5:4]

[3:2]

[1:0]

DAC_SDATA pad pull-up/pull-down

00: pull-up

01: reserved

10: none (default)

11: pull-down

11

LRCLK pad pull-up/pull-down

00: pull-up

01: reserved

10: none (default)

11: pull-down

BCLK pad pull-up/pull-down

00: pull-up

01: reserved

10: none (default)

11: pull-down

Rev. 0| Page 71 of 84

ADAU1381

Bit 1, LRCLK Pin Drive Strength

Register 16430 (0x402E), Serial Port Pad Control 1

This bit sets the drive strength of the LRCLK pin. Low mode yields

2 mA when IOVDD = 3.3 V, or 0.75 mA when IOVDD = 1.8 V.

High mode yields 4 mA when IOVDD = 3.3 V, or 1.5 mA when

IOVDD = 1.8 V.

Bit 3, ADC_SDATA Pin Drive Strength

This bit sets the drive strength of the ADC_SDATA pin. Low mode

yields 2 mA when IOVDD = 3.3 V, or 0.75 mA when IOVDD =

1.8 V. High mode yields 4 mA when IOVDD = 3.3 V, or 1.5 mA

when IOVDD = 1.8 V.

Bit 0, BCLK Pin Drive Strength

This bit sets the drive strength of the BCLK pin. Low mode yields

2 mA when IOVDD = 3.3 V, or 0.75 mA when IOVDD = 1.8 V.

High mode yields 4 mA when IOVDD = 3.3 V, or 1.5 mA when

IOVDD = 1.8 V.

Bit 2, DAC_SDATA Pin Drive Strength

This bit sets the drive strength of the DAC_SDATA pin. Low mode

yields 2 mA when IOVDD = 3.3 V, or 0.75 mA when IOVDD =

1.8 V. High mode yields 4 mA when IOVDD = 3.3 V, or 1.5 mA

when IOVDD = 1.8 V.

Table 60. Serial Port Pad Control 1 Register

Bits

[7:4]

3

Description

Default

Reserved

ADC_SDATA pin drive strength

0

0: low

1: high

2

1

0

DAC_SDATA pin drive strength

0: low

1: high

0

LRCLK pin drive strength

0: low

1: high

BCLK pin drive strength

0: low

1: high

Rev. 0 | Page 72 of 84

ADAU1381

Bits[3:2], SCL/CCLK Pad Pull-Up/Pull-Down

Register 16431 (0x402F), Communication Port Pad

Control 0

These bits enable or disable a weak pull-up or pull-down device

on the pad. The effective resistance of the pull-up or pull-down

is nominally 240 kꢀ.

Bits[7:6], CDATA Pad Pull-Up/Pull-Down

These bits enable or disable a weak pull-up or pull-down device

on the pad. The effective resistance of the pull-up or pull-down

is nominally 240 kꢀ.

Bits[1:0], SDA/COUT Pad Pull-Up/Pull-Down

These bits enable or disable a weak pull-up or pull-down device

on the pad. The effective resistance of the pull-up or pull-down

is nominally 240 kꢀ.

CLATCH

Bits[5:4],

Pad Pull-Up/Pull-Down

These bits enable or disable a weak pull-up or pull-down device

on the pad. The effective resistance of the pull-up or pull-down

is nominally 240 kꢀ.

Table 61. Communication Port Pad Control 0 Register

Bits

Description

Default

[7:6]

CDATA pad pull-up/pull-down

00: pull-up

11

01: reserved

10: none (default)

11: pull-down

[5:4]

[3:2]

[1:0]

CLATCH pad pull-up/pull-down

00: pull-up

01: reserved

10: none (default)

11: pull-down

00

11

SCL/CCLK pad pull-up/pull-down

00: pull-up

01: reserved

10: none (default)

11: pull-down

SDA/COUT pad pull-up/pull-down

00: pull-up

01: reserved

10: none (default)

11: pull-down

Rev. 0| Page 73 of 84

ADAU1381

Bit 1, SCL/CCLK Pin Drive Strength

Register 16432 (0x4030), Communication Port Pad

Control 1

This bit sets the drive strength of the SCL/CCLK pin. Low mode

yields 2 mA when IOVDD = 3.3 V, or 0.75 mA when IOVDD =

1.8 V. High mode yields 4 mA when IOVDD = 3.3 V, or 1.5 mA

when IOVDD = 1.8 V.

Bit 3, CDATA Pin Drive Strength

This bit sets the drive strength of the CDATA pin. Low mode yields

2 mA when IOVDD = 3.3 V, or 0.75 mA when IOVDD = 1.8 V.

High mode yields 4 mA when IOVDD = 3.3 V, or 1.5 mA when

IOVDD = 1.8 V.

Bit 0, SDA/COUT Pin Drive Strength

This bit sets the drive strength of the SDA/COUT pin. Low mode

yields 2 mA when IOVDD = 3.3 V, or 0.75 mA when IOVDD =

1.8 V. High mode yields 4 mA when IOVDD = 3.3 V, or 1.5 mA

when IOVDD = 1.8 V.

CLATCH

Bit 2,

Pin Drive Strength

CLATCH

This bit sets the drive strength of the

pin. Low mode

yields 2 mA when IOVDD = 3.3 V, or 0.75 mA when IOVDD =

1.8 V. High mode yields 4 mA when IOVDD = 3.3 V, or 1.5 mA

when IOVDD = 1.8 V.

Table 62. Communication Port Pad Control 1 Register

Bits

[7:4]

3

Description

Default

Reserved

CDATA pin drive strength

0

0: low

1: high

2

1

0

CLATCH pin drive strength

0

0: low

1: high

SCL/CCLK pin drive strength

0: low

1: high

SDA/COUT pin drive strength

0: low

1: high

Rev. 0 | Page 74 of 84

ADAU1381

Bit 1, MCKO Pull-Up Enable

Register 16433 (0x4031), MCKO Control

This bit enables or disables a weak pull-up device on the pad.

The effective resistance of the pull-up is nominally 240 kꢀ.

Bit 2, MCKO Pin Drive Strength

This bit sets the drive strength of the MCKO pin. Low mode yields

2 mA when IOVDD = 3.3 V, or 0.75 mA when IOVDD = 1.8 V.

High mode yields 4 mA when IOVDD = 3.3 V, or 1.5 mA when

IOVDD = 1.8 V.

Bit 0, MCKO Pull-Down Enable

This bit enables or disables a weak pull-down device on the pad.

The effective resistance of the pull-down is nominally 240 kꢀ.

Table 63. MCKO Control Register

Bits

[7:3]

2

Description

Default

Reserved

MCKO pin drive strength

0: low

0

1: high

1

0

MCKO pull-up enable (active low)

0: pull-down disabled

1: pull-down enabled

MCKO pull-down enable

0: pull-down disabled

1: pull-down enabled

0

1

Rev. 0| Page 75 of 84

ADAU1381

Bit 3, Serial Output Routing

DIGITAL SUBSYSTEM CONFIGURATION

Register 16512 (0x4080), Digital Power-Down 0

Bit 7, ADC Engine

Setting this bit to 0 disables the routing paths for the record signal

path, which goes from the sound engine to the serial port output.

Bit 2, Serial Input Routing

Setting this bit to 0 disables the ADCs and the digital micro-

phone inputs.

Setting this bit to 0 disables the routing paths for the play-

back signal path, which goes from the serial input ports to the

sound engine.

Bit 6, Memory Controller

Setting this bit to 0 disables all memory access, which disables

the sound engine, ADCs, and DACs, as well as prohibits memory

access via the control port.

Bit 1, Serial Port, ADC, DAC, and Frame Pulse Clock

Generator

Setting this bit to 0 disables the internal clock generator, which

generates all master clocks for the serial ports, sound engine,

ADCs, and DACs. This bit must be enabled if audio is being

passed through the ADAU1381.

Bit 5, Clock Domain Transfer

Setting this bit to 0—in conjunction with Bit 4, serial ports—

disables the serial ports.

Bit 4, Serial Ports

Bit 0, Sound Engine

Setting this bit to 0—in conjunction with Bit 5, clock domain

transfer—disables the serial ports.

Setting this bit to 0 disables the sound engine and makes the

memory inaccessible. This bit must be enabled in order to

process audio and change parameter values.

Table 64. Digital Power-Down 0 Register

Bit

Description

Default

7

ADC engine

0

0: disabled

1: enabled

6

5

4

3

2

1

0

Memory controller

0: disabled

1: enabled

0

Clock domain transfer (when using the serial ports)

0: disabled

1: enabled

Serial ports

0: disabled

1: enabled

Serial output routing

0: disabled

1: enabled

Serial input routing

0: disabled

1: enabled

Serial port, ADC, DAC, and frame pulse clock generator

0: disabled

1: enabled

Sound engine

0: disabled

1: enabled

Rev. 0 | Page 76 of 84

ADAU1381

Bit 1, Digital Microphone

Register 16513 (0x4081), Digital Power-Down 1

Setting this bit to 0 disables the digital microphone input.

Bit 3, Output Precharge

The output precharge system allows the outputs to be biased before

they are enabled and prevents pops or clicks from appearing on

the output. This bit should be set to 1 at all times.

Bit 0, DAC Engine

Setting this bit to 0 disables the DACs.

Bit 2, Zero-Crossing Detector

Setting this bit to 0 disables the zero-crossing detector for beep

playback.

Table 65. Digital Power-Down 1 Register

Bits

[7:4]

3

Description

Default

Reserved

Output precharge

0: disabled

1

1: enabled

2

1

0

Zero-crossing detector

0: disabled

1: enabled

1

0

Digital microphone

0: disabled

1: enabled

DAC engine

0: disabled

1: enabled

Rev. 0| Page 77 of 84

ADAU1381

The GPIO pin can be set directly by the sound engine and therefore

should be set as 1011 or 1100 (outputs set by the sound engine).

In order for GPIO0 through GPIO3 to be used, they should be

configured as 1001 or 1010 (outputs set by the I²C/SPI port).

Register 16582 to Register 16586 (0x40C6 to 0x40CA),

GPIO Pin Control

Bits[3:0], GPIO Pin Function

The GPIO pin control register sets the functionality of each

GPIO pin as depicted in Table 67. GPIO0 to GPIO3 use the

same pins as the serial port and must be enabled in Register

16628 (0x40F4), serial data/GPIO pin configuration. Pin 7 is

a dedicated GPIO.

There are five GPIO pin value registers that allow the input/output

data value of the GPIO pin to be written to or read directly from

the control port. The corresponding addresses are listed in Table 68.

Each value register contains four bytes and can store only one of

two values: logic high or logic low. Logic high is stored as 0x00,

0x80, 0x00, 0x00. Logic low is stored as 0x00, 0x00, 0x00, 0x00.

Table 66. GPIO Pin Control Register

Address

Decimal

Hex

Register

Bits

[7:4]

[3:0]

[7:4]

[3:0]

[7:4]

[3:0]

[7:4]

[3:0]

[7:4]

[3:0]

Description

Default

1100

16582

0x40C6

GPIO pin control

Reserved

Dedicated GPIO (Pin 7) function (see Table 67)

Reserved

GPIO0 pin function (see Table 67)

Reserved

GPIO1 pin function (see Table 67)

Reserved

GPIO2 pin function (see Table 67)

Reserved

16583

16584

16585

16586

0x40C7

0x40C8

0x40C9

0x40CA

GPIO0 control

GPIO1 control

GPIO2 control

GPIO3 control

1100

GPIO3 pin function (see Table 67)

1100

Table 67. GPIO Pin Functions

GPIO Bits[3:0]

GPIO Pin Function

0000

Input without debounce

0001

0010

0011

0100

0101

0110

0111

Input with debounce (0.3 ms)

Input with debounce (0.6 ms)

Input with debounce (0.9 ms)

Input with debounce (5 ms)

Input with debounce (10 ms)

Input with debounce (20 ms)

Input with debounce (40 ms)

1000

1001

1010

1011

1100

1101

Input controlled by I²C/SPI port

Output set by I²C/SPI port with pull-up

Output set by I²C/SPI port without pull-up

Output set by engine with pull-up

Output set by engine without pull-up

Reserved

1110

Output CRC error (sticky)

1111

Output watchdog error (sticky)

Register 1000 to Register 1004 (0x03E8 to 0x03EC), GPIO Pin Value

Table 68. Addresses of GPIO Pin Value Registers

Address

Decimal

1000

1001

1002

1003

Hex

Register

0x03E8

0x03E9

0x03EA

0x03EB

0x03EC

GPIO pin value, GPIO

GPIO pin value, GPIO0

GPIO pin value, GPIO1

GPIO pin value, GPIO2

GPIO pin value, GPIO3

1004

Rev. 0 | Page 78 of 84

ADAU1381

Register 16619 (0x40EB), Sound Engine Frame Rate

Register 16617 and Register 16618 (0x40E9 and 0x40EA),

Nonmodulo

Bits[3:0], Sound Engine Frame Rate

These registers set the boundary for the nonmodulo RAM space

used by the sound engine. An appropriate value is automatically

loaded to this register during initialization. It should not be

modified for any reason.

These bits set the frequency of the frame start pulse, which is

delivered to the sound engine to begin processing on each audio

frame. It effectively determines the sample rate of audio in the

sound engine. This register should always be set to none at least

one frame prior to disabling Register 16630 (0x40F6), sound

engine run, Bit 0, sound engine run, to allow the sound engine

to finish processing the current frame before halting.

Table 69. Nonmodulo Registers

Bits

Description

[31:0]

Reserved

Table 70. Sound Engine Frame Rate Register

Bits

[7:4]

[3:0]

Description

Default

Reserved

Sound engine frame rate

0000: f_S× 2 (96 kHz)

0001: f_S(48 kHz)

0010: f_S/1.5 (32 kHz)

0011: f_S/2 (24 kHz)

0100: f_S/3 (16 kHz)

0101: f_S/4 (12 kHz)

0110: f_S/6 (8 kHz)

0111: serial data input rate

1000: serial data output rate

1001: f_S× 4 (192 kHz)

1010: none

0000

…

1111: none

Rev. 0| Page 79 of 84

ADAU1381

Register 16626 (0x40F2), Serial Input Route Control

Bits[3:0], Input Routing

These bits select which serial data input channels are routed to the DACs (see Figure 72).

Table 71. Serial Input Route Control Register

Bits

[7:4]

[3:0]

Description

Default

Reserved

Input routing

0000

0000: serial input to sound engine to DACs

0001: serial input [L0, R0]¹to DACs [L, R]

0010: reserved

0011: serial input [L1, R1]¹to DACs [L, R]

0100: reserved

0101: serial input [L2, R2]¹to DACs [L, R]

0110: reserved

0111: serial input [L3, R3]¹to DACs [L, R]

1000: reserved

1001: serial input [R0, L0]¹to DACs [L, R]

1010: reserved

1011: serial input [R1, L1]¹to DACs [L, R]

1100: reserved

1101: serial input [R2, L2]¹to DACs [L, R]

1110: reserved

1111: serial input [R3, L3]¹to DACs [L, R]

¹Lx = left side of Channel x; Rx = right side of Channel x.

Rev. 0 | Page 80 of 84

ADAU1381

Register 16627 (0x40F3), Serial Output Route Control

Bits[3:0], Output Routing

These bits select where the ADC outputs are routed in the serial data stream (see Figure 72).

Table 72. Serial Output Route Control Register

Bits Description

Default

[7:4] Reserved

[3:0] Output routing

0000

0000: ADCs to sound engine to serial outputs

0001: ADCs [L, R] to serial output [L0, R0]¹

0010: reserved

0011: ADCs [L, R] to serial output [L1, R1]¹

0100: reserved

0101: ADCs [L, R] to serial output [L2, R2]¹

0110: reserved

0111: ADCs [L, R] to serial output [L3, R3]¹

1000: reserved

1001: ADCs [L, R] to serial output [R0, L0]¹

1010: reserved

1011: ADCs [L, R] to serial output [R1, L1]¹

1100: reserved

1101: ADCs [L, R] to serial output [R2, L2]¹

1110: reserved

1111: ADCs [L, R] to serial output [R3, L3]¹

¹Lx = left side of Channel x; Rx = right side of Channel x.

1/f_LRCLK

LRCLK

L0

R0

STEREO CHANNELS

TDM 4 CHANNELS

TDM 8 CHANNELS

L0

R0

L1

R1

L0

R0

L1

R1

L2

R2

L3

R3

Figure 72. Serial Port Routing Control

Rev. 0| Page 81 of 84

ADAU1381

Register 16628 (0x40F4), Serial Data/GPIO Pin

Configuration

Before going into standby mode, the following sequence must

be performed:

Bits[3:0], GPIO[0:3]

1. Set the sound engine frame rate in Register 16619 to

0x7F (none).

2. Wait 3 ms.

The serial data/GPIO pin configuration register controls the

functionality of the serial data port pins. If the bits in this

register are set to 1, then the GPIO[0:3] pins become GPIO

interfaces to the sound engine. If these bits are set to 0, they

remain LRCLK, BCLK, or serial port data pins, respectively.

3. Set the sound engine run bit in Register 16630 to 0x00.

When reenabling the sound engine run bit, the following

sequence must be followed:

Register 16630 (0x40F6), Sound Engine Run

1. Set the sound engine frame rate in Register 16619 to an

appropriate value.

2. Set the sound engine run bit in Register 16630 to 0x01.

Bit 0, Sound Engine Run

This bit, in conjunction with the sound engine frame rate, initiates

audio processing in the sound engine. When this bit is enabled,

the program counter begins to increment when a new frame of

audio data is input to the sound engine. When this bit is disabled,

the sound engine goes into standby mode.

Register 16632 (0x40F8), Serial Port Sampling Rate

Bits[2:0], Serial Port Control Sampling Rate

These bits set the serial port sampling rate as a function of the

audio sampling rate, f_S. In most applications, the serial port

sampling rate, sound engine sampling rate, and ADC and DAC

sampling rates should be equal.

Table 73. Serial Data/GPIO Pin Configuration Register

Bits

[7:4]

3

Description

Default

Reserved

GPIO0

0

0: LRCLK

1: GPIO enabled

GPIO1

2

1

0

0: BCLK

1: GPIO enabled

GPIO2

0: serial data output

1: GPIO enabled

GPIO3

0: serial data input

1: GPIO enabled

Table 74. Sound Engine Run Register

Bits

[7:1]

0

Description

Default

Reserved

Sound engine run

0: sound engine standby

1: run the sound engine

0

Table 75. Serial Port Sampling Rate Register

Bits

[7:3]

[2:0]

Description

Default

Reserved

Serial port control sampling rate

000: f_S/1 (48 kHz)

001: f_S/6 (8 kHz)

010: f_S/4 (12 kHz)

011: f_S/3 (16 kHz)

100: f_S/2 (24 kHz)

101: f_S/1.5 (32 kHz)

110: f_S/0.5 (96 kHz)

111: reserved

000

Rev. 0 | Page 82 of 84

ADAU1381

OUTLINE DIMENSIONS

5.00

BSC SQ

0.60 MAX

PIN 1

INDICATOR

25

24

32

1

PIN 1

INDICATOR

0.50

BSC

EXPOSED

PAD

(BOTTOM VIEW)

3.65

3.50 SQ

3.35

TOP

VIEW

4.75

BSC SQ

0.50

0.40

0.30

17

16

8

9

0.25 MIN

0.80 MAX

0.65 TYP

3.50 REF

12° MAX

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

1.00

0.85

0.80

0.30

0.23

0.18

COPLANARITY

0.08

SECTION OF THIS DATA SHEET.

0.20 REF

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2

Figure 73. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

5 mm × 5 mm Body, Very Thin Quad

(CP-32-4)

Dimensions shown in millimeters

0.650

0.595

0.540

3.44

3.40

3.36

SEATING

PLANE

3

2

1

6

5

4

A

B

C

D

E

BALL A1

IDENTIFIER

2.68

2.64

2.60

2.00

REF

0.34

0.32

0.30

0.50

BALL PITCH

TOP VIEW

(BALL SIDE DOWN)

BOTTOM VIEW

(BALL SIDE UP)

0.27

0.24

0.21

2.50 REF

Figure 74. 30-Ball Wafer Level Chip Scale Package [WLCSP]

(CB-30-2)

Dimensions shown in millimeters

ORDERING GUIDE

Model

Temperature Range

Package Description

32-Lead LFCSP_VQ

32-Lead LFCSP_VQ, Reel

32-Lead LFCSP_VQ, 7”Reel

30-Ball WLCSP, Reel

Package Option

CP-32-4

CB-30-2

ADAU1381BCPZ¹

ADAU1381BCPZ-RL¹

ADAU1381BCPZ-RL7¹

ADAU1381BCBZ-RL¹

ADAU1381BCBZ-RL7¹

EVAL-ADAU1381Z¹

−25°C to +85°C

30-Ball WLCSP, 7”Reel

Evaluation Board

CB-30-2

¹Z = RoHS Compliant Part.

Rev. 0| Page 83 of 84

ADAU1381

NOTES

Purchase of licensed I²C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I²C Patent

Rights to use these components in an I²C system, provided that the system conforms to the I²C Standard Specification as defined by Philips.

registered trademarks are the property of their respective owners.

D08313-0-10/09(0)

Rev. 0 | Page 84 of 84


型号：	EVAL-ADAU1381Z
厂家：	ADI
描述：	Low Noise Stereo Codec with Enhanced Recording and Playback Processing 低噪声立体声编解码器增强录音和回放处理解码器编解码器
文件：	总84页 (文件大小：1244K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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